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[Script] update SDF generation script

This commit is contained in:
tangxifan 2020-11-23 16:24:26 -07:00
parent 973fe1acc8
commit 73de63d41c
1 changed files with 13 additions and 7 deletions
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20
SNPS_PT/SCRIPT/generate_sdf.tcl
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@ -6,20 +6,21 @@
################################## ##################################
# Define environment variables # Define environment variables
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
set FPGA_NETLIST_HOME "../../FPGA1212_FC_HD_SKY_PNR/fpga_core"; #set FPGA_NETLIST_HOME "../../FPGA1212_FC_HD_SKY_PNR/fpga_top";
set FPGA_NETLIST_HOME "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top";
set SDF_HOME "../../SDF" set SDF_HOME "../../SDF"
# #
# Enable reporting ALL the timing paths even those are NOT constrained # Enable reporting ALL the timing paths even those are NOT constrained
set_app_var svr_enable_vpp true set_app_var svr_enable_vpp true
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/results/lib/skywater130_fd_sc_hd/db_nldm" set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/results/lib/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
# Top-level module name # Top-level module name
set DESIGN_NAME fpga_core; set DESIGN_NAME fpga_top;
set FPGA_NETLIST_FILES "fpga_core_icv_in_design.pt.v" set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
################################## ##################################
# Read timing libraries # Read timing libraries
@ -30,15 +31,20 @@ read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/results/lib/sky130_fd_sc_hd/db_nld
read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
link_design ${DESIGN_NAME} link_design ${DESIGN_NAME}
#########################################
# Setup constraints to break combinational loops
set_disable_timing [get_pins */*/*chan*]
set_disable_timing [get_pins */*/*grid_pin*]
################################## ##################################
# Read post-PnR parasitics # Read post-PnR parasitics
read_parasitics ${FPGA_NETLIST_HOME}/fpga_core_icv_in_design.nominal_25.spef read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
################################## ##################################
# Write sdf file # Write sdf file
write_sdf -version 3.0 ${SDF_HOME}/FPGA1212_FC_HD_SKY_PNR/fpga_core_icv_in_design.pt.sdf write_sdf -version 3.0 ${SDF_HOME}/FPGA1212_FC_HD_SKY_PNR/fpga_top_icv_in_design.pt.sdf
################################## ##################################
# Finish and quit # Finish and quit
# Comment it out if you want to debug # Comment it out if you want to debug
#exit exit