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[Arch] Patch openfpga arch for new syntax on I/O

This commit is contained in:
tangxifan 2020-11-05 10:37:37 -07:00
parent bbdd13ac16
commit 6b474ce422
8 changed files with 12 additions and 12 deletions
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2
ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
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@ -186,7 +186,7 @@
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrbp_1" default_val="1"/>
<port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/>

2
ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml
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@ -186,7 +186,7 @@
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__inv_1"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hs__dfrbp_1" default_val="1"/>
<port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/>

2
ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml
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@ -186,7 +186,7 @@
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__inv_1"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hvl__dfrbp_1" default_val="1"/>
<port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/>

2
ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml
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@ -186,7 +186,7 @@
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__inv_1"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_ls__dfrbp_1" default_val="1"/>
<port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/>

2
ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml
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@ -186,7 +186,7 @@
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__inv_1"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_ms__dfrbp_1" default_val="1"/>
<port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/>

2
ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml
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@ -185,7 +185,7 @@
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
<output_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="scs8ms_dfrbp_1" default_val="1"/>
<port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/>

4
ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -187,14 +187,14 @@
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="inout" prefix="PAD" lib_name="A" size="1" is_global="true" is_io="true" />
<port type="inout" prefix="PAD" lib_name="A" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model>
<circuit_model type="iopad" name="GPOUT" prefix="GPOUT" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io_hd.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="inout" prefix="PAD" lib_name="Y" size="1" is_global="true" is_io="true" />
<port type="inout" prefix="PAD" lib_name="Y" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="input" prefix="outpad" lib_name="A" size="1"/>
</circuit_model>
</circuit_library>

8
ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
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@ -188,11 +188,11 @@
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="inout" prefix="Y" lib_name="Y" size="1" is_global="true" is_io="true" />
<port type="output" prefix="A" lib_name="A" size="1" is_global="true" is_io="true" />
<port type="inout" prefix="Y" lib_name="Y" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="A" lib_name="A" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" lib_name="mem_out" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" default_val="1"/>
<port type="output" prefix="IE" lib_name="IE" size="1" is_global="true" is_io="true" />
<port type="output" prefix="OE" lib_name="OE" size="1" is_global="true" is_io="true" />
<port type="output" prefix="IE" lib_name="IE" size="1" is_global="true" is_io="true"/>
<port type="output" prefix="OE" lib_name="OE" size="1" is_global="true" is_io="true"/>
<port type="input" prefix="outpad" lib_name="in" size="1"/>
<port type="output" prefix="inpad" lib_name="out" size="1"/>
</circuit_model>