From 6b474ce422dac070aa55bdeefbbd7d2ca61b7f16 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 5 Nov 2020 10:37:37 -0700
Subject: [PATCH] [Arch] Patch openfpga arch for new syntax on I/O

---
 ...register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml | 2 +-
 ...register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml | 2 +-
 ...egister_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml | 2 +-
 ...register_scan_chain_skywater130nm_fdls_cc_openfpga.xml | 2 +-
 ...register_scan_chain_skywater130nm_fdms_cc_openfpga.xml | 2 +-
 ...ister_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml | 2 +-
 ...n_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml | 4 ++--
 ...register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml | 8 ++++----
 8 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
index e6d1b24..be0309b 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
@@ -186,7 +186,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
       <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrbp_1" default_val="1"/>
       <port type="input" prefix="outpad" lib_name="A" size="1"/>
       <port type="output" prefix="inpad" lib_name="Y" size="1"/>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml
index 9880c7a..bce7666 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml
@@ -186,7 +186,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__inv_1"/>
-      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
       <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hs__dfrbp_1" default_val="1"/>
       <port type="input" prefix="outpad" lib_name="A" size="1"/>
       <port type="output" prefix="inpad" lib_name="Y" size="1"/>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml
index a5efd99..915e1b7 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml
@@ -186,7 +186,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__inv_1"/>
-      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
       <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hvl__dfrbp_1" default_val="1"/>
       <port type="input" prefix="outpad" lib_name="A" size="1"/>
       <port type="output" prefix="inpad" lib_name="Y" size="1"/>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml
index 1ebbe06..c7485a1 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml
@@ -186,7 +186,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__inv_1"/>
-      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
       <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_ls__dfrbp_1" default_val="1"/>
       <port type="input" prefix="outpad" lib_name="A" size="1"/>
       <port type="output" prefix="inpad" lib_name="Y" size="1"/>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml
index 1bbf6d7..57ca9fa 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml
@@ -186,7 +186,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__inv_1"/>
-      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
       <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_ms__dfrbp_1" default_val="1"/>
       <port type="input" prefix="outpad" lib_name="A" size="1"/>
       <port type="output" prefix="inpad" lib_name="Y" size="1"/>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml
index a47ab93..1f341b1 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml
@@ -185,7 +185,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
       <output_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
-      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
       <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="scs8ms_dfrbp_1" default_val="1"/>
       <port type="input" prefix="outpad" lib_name="A" size="1"/>
       <port type="output" prefix="inpad" lib_name="Y" size="1"/>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
index 186a4d1..ee61144 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -187,14 +187,14 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <port type="inout" prefix="PAD" lib_name="A" size="1" is_global="true" is_io="true" />
+      <port type="inout" prefix="PAD" lib_name="A" size="1" is_global="true" is_io="true" is_data_io="true"/>
       <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
     <circuit_model type="iopad" name="GPOUT" prefix="GPOUT" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io_hd.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <port type="inout" prefix="PAD" lib_name="Y" size="1" is_global="true" is_io="true" />
+      <port type="inout" prefix="PAD" lib_name="Y" size="1" is_global="true" is_io="true" is_data_io="true"/>
       <port type="input" prefix="outpad" lib_name="A" size="1"/>
     </circuit_model>
   </circuit_library>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
index 6242733..c372a49 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
@@ -188,11 +188,11 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <port type="inout" prefix="Y" lib_name="Y" size="1" is_global="true" is_io="true" />
-      <port type="output" prefix="A" lib_name="A" size="1" is_global="true" is_io="true" />
+      <port type="inout" prefix="Y" lib_name="Y" size="1" is_global="true" is_io="true" is_data_io="true"/>
+      <port type="output" prefix="A" lib_name="A" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" lib_name="mem_out" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" default_val="1"/>
-      <port type="output" prefix="IE" lib_name="IE" size="1" is_global="true" is_io="true" />
-      <port type="output" prefix="OE" lib_name="OE" size="1" is_global="true" is_io="true" />
+      <port type="output" prefix="IE" lib_name="IE" size="1" is_global="true" is_io="true"/>
+      <port type="output" prefix="OE" lib_name="OE" size="1" is_global="true" is_io="true"/>
       <port type="input" prefix="outpad" lib_name="in" size="1"/>
       <port type="output" prefix="inpad" lib_name="out" size="1"/>
     </circuit_model>