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[Doc] Update to latest architecture definition and device information

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tangxifan 2020-11-12 21:59:14 -07:00
parent 3108ba6283
commit 67763c3464
4 changed files with 35 additions and 62 deletions
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8
DOC/source/arch/clb.rst
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Configurable Logic Block User Guide Configurable Logic Block User Guide
----------------------------------- -----------------------------------
FROG's Configurable Logic Block (CLB) consists of 10 logic elements as shown in :numref:`fig_le_arch` and a 50% depopulated crossbar which tightly interconnects the logic elements. Each Configurable Logic Block (CLB) consists of 8 logic elements as shown in :numref:`fig_fle_arch`.
.. _fig_le_arch: .. _fig_fle_arch:
.. figure:: ./figures/le_arch.png .. figure:: ./figures/fle_arch.png
:scale: 100% :scale: 100%
:alt: Logic element schematic :alt: Logic element schematic
Logic Element Schematic of a logic element
.. _fig_clb_arch: .. _fig_clb_arch:

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DOC/source/arch/figures/le_arch.png
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DOC/source/dc_ac_character.rst
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DC and AC Characteristics DC and AC Characteristics
------------------------- -------------------------
FROG contains 196 I/O pins, whose details are summarized in the following tables. Each FPGA device contains 37 I/O pins, whose details are summarized in the following tables.
I/O usage and port information I/O usage and port information
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@ -11,24 +11,12 @@ I/O usage and port information
+-----------+------------------------------------------------------------------------+-------------+ +-----------+------------------------------------------------------------------------+-------------+
| I/O Type | Description | No. of Pins | | I/O Type | Description | No. of Pins |
+===========+========================================================================+=============+ +===========+========================================================================+=============+
| Data I/O | Datapath I/Os of FPGA fabric | 80 | | Data I/O | Datapath I/Os of FPGA fabric | 30 |
+-----------+------------------------------------------------------------------------+-------------+
| VDD_core | VDD supply for FPGA core | 28 |
+-----------+------------------------------------------------------------------------+-------------+
| VSS_core | VSS supply for FPGA core | 28 |
+-----------+------------------------------------------------------------------------+-------------+
| VDD_io | VDD supply for FPGA I/Os | 16 |
+-----------+------------------------------------------------------------------------+-------------+
| VSS_io | VSS supply for FPGA I/Os | 16 |
+-----------+------------------------------------------------------------------------+-------------+ +-----------+------------------------------------------------------------------------+-------------+
| Clk | Operating clock of FPGA core | 1 | | Clk | Operating clock of FPGA core | 1 |
+-----------+------------------------------------------------------------------------+-------------+ +-----------+------------------------------------------------------------------------+-------------+
| Reset | Reset flip-flop contents to logic '0' | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| ProgClk | Clock used by configuration protocol to program FPGA fabric | 1 | | ProgClk | Clock used by configuration protocol to program FPGA fabric | 1 |
+-----------+------------------------------------------------------------------------+-------------+ +-----------+------------------------------------------------------------------------+-------------+
| ProgReset | Reset configurable memories to logic '0' | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| CCin | Input of configuation protocol to load bitstream | 1 | | CCin | Input of configuation protocol to load bitstream | 1 |
+-----------+------------------------------------------------------------------------+-------------+ +-----------+------------------------------------------------------------------------+-------------+
| CCout | Output of configuration protocol to read back bitstream | 1 | | CCout | Output of configuration protocol to read back bitstream | 1 |
@ -39,9 +27,7 @@ I/O usage and port information
+-----------+------------------------------------------------------------------------+-------------+ +-----------+------------------------------------------------------------------------+-------------+
| SCout | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 | | SCout | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 |
+-----------+------------------------------------------------------------------------+-------------+ +-----------+------------------------------------------------------------------------+-------------+
| Spypad | Spypads for debugging. See details in spypad section | 14 | | Total | | 37 |
+-----------+------------------------------------------------------------------------+-------------+
| Total | | 191 |
+-----------+------------------------------------------------------------------------+-------------+ +-----------+------------------------------------------------------------------------+-------------+
Recommended Operating Conditions Recommended Operating Conditions
@ -52,15 +38,15 @@ Recommended Operating Conditions
+----------+------------------------------+------+------+-------+ +----------+------------------------------+------+------+-------+
| Symbol | Description | Min | Max | Units | | Symbol | Description | Min | Max | Units |
+==========+==============================+======+======+=======+ +==========+==============================+======+======+=======+
| VDD_io | Supply voltage for I/Os | 1.26 | 2.34 | V | | VDD_io | Supply voltage for I/Os | TBD | TBD | V |
+----------+------------------------------+------+------+-------+ +----------+------------------------------+------+------+-------+
| VDD_core | Supply voltage for FPGA core | 0.56 | 1.04 | V | | VDD_core | Supply voltage for FPGA core | TBD | TBD | V |
+----------+------------------------------+------+------+-------+ +----------+------------------------------+------+------+-------+
| V_in | Input voltage for other I/Os | 0.56 | 1.04 | V | | V_in | Input voltage for other I/Os | TBD | TBD | V |
+----------+------------------------------+------+------+-------+ +----------+------------------------------+------+------+-------+
| I_in | Maximum current through pins | N/A | 4 | mA | | I_in | Maximum current through pins | N/A | TBD | mA |
+----------+------------------------------+------+------+-------+ +----------+------------------------------+------+------+-------+
| f_max | Maximum frequency of I/Os | N/A | 70 | MHz | | f_max | Maximum frequency of I/Os | N/A | TBD | MHz |
+----------+------------------------------+------+------+-------+ +----------+------------------------------+------+------+-------+
Typical AC Characteristics Typical AC Characteristics
@ -71,11 +57,11 @@ Typical AC Characteristics
+-----------------+-------------------------------------------+------+------+-------+ +-----------------+-------------------------------------------+------+------+-------+
| Symbol | Description | Min | Max | Units | | Symbol | Description | Min | Max | Units |
+=================+===========================================+======+======+=======+ +=================+===========================================+======+======+=======+
| V_in Overshoot | Maximum allowed overshoot voltage for Vin | 2.34 | 2.34 | V | | V_in Overshoot | Maximum allowed overshoot voltage for Vin | TBD | TBD | V |
+-----------------+-------------------------------------------+------+------+-------+ +-----------------+-------------------------------------------+------+------+-------+
| V_in Undershoot | Minimum allowed overshoot voltage for Vin | 1.26 | 1.26 | V | | V_in Undershoot | Minimum allowed overshoot voltage for Vin | TBD | TBD | V |
+-----------------+-------------------------------------------+------+------+-------+ +-----------------+-------------------------------------------+------+------+-------+
| I_VDD_core | Quiescent VDD_core supply current | 5000 | 5000 | mA | | I_VDD_core | Quiescent VDD_core supply current | TBD | TBD | mA |
+-----------------+-------------------------------------------+------+------+-------+ +-----------------+-------------------------------------------+------+------+-------+
| I_VDD_io | Quiescent VDD_io supply current | TBD | TBD | mA | | I_VDD_io | Quiescent VDD_io supply current | TBD | TBD | mA |
+-----------------+-------------------------------------------+------+------+-------+ +-----------------+-------------------------------------------+------+------+-------+

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DOC/source/technical_highlights.rst
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Highlights Device Overview
---------- ---------------
FROG is the FiRst Open-source fpGa, which is designed through a no-human-in-the-loop automate flow. Built on a state-of-the-art 14nm FinFET technology, FROG aims to empower embedded applications with its low-cost design approach but high-performance architecture. All the FPGA devices in this project are fully open-source, from the architecture description to the physical design outputs, e.g., GDSII.
All the devices are designed through the OpenFPGA framework and the Skywater 130nm PDK.
- Multi-mode 6-input Look-Up Table (LUT) technology, which operate as dual-output 5-input LUTs, as well as four-output 4-input LUTs. The devices are embedded FPGA IPs, which are designed to interface the caravel SoC interface.
We aims to empower embedded applications with its low-cost design approach but high-density architecture.
- Native support on up-to 600-bit shift registers as well as ripple-carry adders
- 512Kb dual-port block RAM populated in 16 independent on-chip memory banks
- Operating temperature ranging from -40 :math:`^\circ C` to 85 :math:`^\circ C`
- Packaged by wire-bonded BGA
.. table:: Logic capacity of FROG - Native support on shift registers
- Operating temperature ranging from 0 :math:`^\circ C` to 85 :math:`^\circ C`
.. table:: Logic capacity of High Density (HD) FPGA IP
+--------------------------+------------+ +--------------------------+------------+
| Resource Type | Capacity | | Resource Type | Capacity |
+==========================+============+ +==========================+============+
| Look-Up Tables [1]_ | 9.92k | | Look-Up Tables [1]_ | 1152 |
+--------------------------+------------+ +--------------------------+------------+
| Arithmetic Units [2]_ | 19.84k | | Flip-flops | 2204 |
+--------------------------+------------+ +--------------------------+------------+
| Flip-flops | 19.84k | | Max. Configuration Speed | TBD |
+--------------------------+------------+ +--------------------------+------------+
| Block RAM [3]_ | 512kb | | Max. Operating Speed | TBD |
+--------------------------+------------+ +--------------------------+------------+
| Max. Configuration Speed | TBD | | User I/O Pins | 30 |
+--------------------------+------------+ +--------------------------+------------+
| Max. Operating Speed | 150MHz | | Max. I/O Speed | TBD |
+--------------------------+------------+ +--------------------------+------------+
| User I/O Pins | 124 | | Core Voltage | 1.8V |
+--------------------------+------------+
| Max. I/O Speed | 70MHz |
+--------------------------+------------+
| I/O Voltage | 1.8V |
+--------------------------+------------+
| Core Voltage | 0.8V |
+--------------------------+------------+ +--------------------------+------------+
.. [1] counted by 6-input fracturable LUTs .. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT.
.. [2] Counted by 1-bit full adders
.. [3] Include sixteen 32kb memory blocks