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[Doc] Update I/O arrangement to avoid congestion in backend

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tangxifan 2020-11-18 19:11:35 -07:00
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DOC/source/arch/io_resource.rst
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@ -37,7 +37,7 @@ Accelerator Mode
When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor. When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor.
:numref:`fig_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations. :numref:`fig_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations.
.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[122:131] are not connected. .. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:30] are not connected.
.. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator. .. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator.