diff --git a/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.png b/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.png index f234225..640de11 100644 Binary files a/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.png and b/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.png differ diff --git a/DOC/source/arch/figures/fpga_io_map_wishbone_mode.png b/DOC/source/arch/figures/fpga_io_map_wishbone_mode.png index ac02459..635f25d 100644 Binary files a/DOC/source/arch/figures/fpga_io_map_wishbone_mode.png and b/DOC/source/arch/figures/fpga_io_map_wishbone_mode.png differ diff --git a/DOC/source/arch/io_resource.rst b/DOC/source/arch/io_resource.rst index 3666d0f..394f588 100644 --- a/DOC/source/arch/io_resource.rst +++ b/DOC/source/arch/io_resource.rst @@ -37,7 +37,7 @@ Accelerator Mode When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor. :numref:`fig_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations. -.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[122:131] are not connected. +.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:30] are not connected. .. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator.