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[Testbench] Caravel SCFF testbench is working but see problems in verification

This commit is contained in:
tangxifan 2020-12-16 15:22:22 -07:00
parent f5d78fc0fa
commit 5ffdce9ce0
4 changed files with 79 additions and 6 deletions
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36
TESTBENCH/caravel_dv/scff_test/scff_test_caravel.c
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@ -50,6 +50,42 @@ void main() {
*/ */
// By default all the I/Os are in input mode // By default all the I/Os are in input mode
reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_2 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_4 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_6 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_7 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_8 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_9 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_12 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_13 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_14 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_15 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_16 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_17 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_18 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_19 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_20 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_21 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_22 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_23 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_25 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_27 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_28 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_29 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_30 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_31 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_36 = GPIO_MODE_USER_STD_INPUT_NOPULL;
reg_mprj_io_37 = GPIO_MODE_USER_STD_INPUT_NOPULL;
// Only specify those should be in output mode // Only specify those should be in output mode
reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT; reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT; reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;

42
TESTBENCH/caravel_dv/scff_test/scff_test_caravel.hex
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@ -6,7 +6,7 @@
13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00 13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00
13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00 13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00
13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00
13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 85 11 13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 05 31
93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1 93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1
11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00 11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00
63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 71 28 63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 71 28
@ -20,7 +20,39 @@ F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F
23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC 23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC
FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08 FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08
A3 81 62 00 82 80 01 00 00 00 41 11 22 C6 00 08 A3 81 62 00 82 80 01 00 00 00 41 11 22 C6 00 08
B7 07 00 26 93 87 C7 04 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 07 02 13 07 20 40 98 C3 B7 07
B7 07 00 26 93 87 C7 0A 09 67 13 07 87 80 98 C3 00 26 93 87 47 02 13 07 20 40 98 C3 B7 07 00 26
B7 07 00 26 05 47 98 C3 01 00 B7 07 00 26 98 43 93 87 87 02 13 07 20 40 98 C3 B7 07 00 26 93 87
85 47 E3 0C F7 FE 01 00 32 44 41 01 82 80 00 00 C7 02 13 07 20 40 98 C3 B7 07 00 26 93 87 07 03
13 07 20 40 98 C3 B7 07 00 26 93 87 47 03 13 07
20 40 98 C3 B7 07 00 26 93 87 87 03 13 07 20 40
98 C3 B7 07 00 26 93 87 C7 03 13 07 20 40 98 C3
B7 07 00 26 93 87 07 04 13 07 20 40 98 C3 B7 07
00 26 93 87 47 04 13 07 20 40 98 C3 B7 07 00 26
93 87 87 04 13 07 20 40 98 C3 B7 07 00 26 93 87
07 05 13 07 20 40 98 C3 B7 07 00 26 93 87 47 05
13 07 20 40 98 C3 B7 07 00 26 93 87 87 05 13 07
20 40 98 C3 B7 07 00 26 93 87 C7 05 13 07 20 40
98 C3 B7 07 00 26 93 87 07 06 13 07 20 40 98 C3
B7 07 00 26 93 87 47 06 13 07 20 40 98 C3 B7 07
00 26 93 87 87 06 13 07 20 40 98 C3 B7 07 00 26
93 87 C7 06 13 07 20 40 98 C3 B7 07 00 26 93 87
07 07 13 07 20 40 98 C3 B7 07 00 26 93 87 47 07
13 07 20 40 98 C3 B7 07 00 26 93 87 87 07 13 07
20 40 98 C3 B7 07 00 26 93 87 C7 07 13 07 20 40
98 C3 B7 07 00 26 93 87 07 08 13 07 20 40 98 C3
B7 07 00 26 93 87 47 08 13 07 20 40 98 C3 B7 07
00 26 93 87 87 08 13 07 20 40 98 C3 B7 07 00 26
93 87 C7 08 13 07 20 40 98 C3 B7 07 00 26 93 87
07 09 13 07 20 40 98 C3 B7 07 00 26 93 87 47 09
13 07 20 40 98 C3 B7 07 00 26 93 87 87 09 13 07
20 40 98 C3 B7 07 00 26 93 87 C7 09 13 07 20 40
98 C3 B7 07 00 26 93 87 07 0A 13 07 20 40 98 C3
B7 07 00 26 93 87 47 0A 13 07 20 40 98 C3 B7 07
00 26 93 87 87 0A 13 07 20 40 98 C3 B7 07 00 26
93 87 07 0B 13 07 20 40 98 C3 B7 07 00 26 93 87
47 0B 13 07 20 40 98 C3 B7 07 00 26 93 87 C7 04
09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 C7 0A
09 67 13 07 87 80 98 C3 B7 07 00 26 05 47 98 C3
01 00 B7 07 00 26 98 43 85 47 E3 0C F7 FE 01 00
32 44 41 01 82 80 00 00

2
TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v
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@ -18,10 +18,12 @@ module scff_test_caravel;
wire [0:0] pReset; wire [0:0] pReset;
reg [0:0] prog_clock_reg; reg [0:0] prog_clock_reg;
wire [0:0] prog_clk; wire [0:0] prog_clk;
wire [0:0] prog_clock;
wire [0:0] Test_en; wire [0:0] Test_en;
wire [0:0] Reset; wire [0:0] Reset;
reg [0:0] op_clock_reg; reg [0:0] op_clock_reg;
wire [0:0] op_clk; wire [0:0] op_clk;
wire [0:0] op_clock;
reg [0:0] prog_reset; reg [0:0] prog_reset;
reg [0:0] greset; reg [0:0] greset;

5
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_caravel_include_netlists.v
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@ -5,9 +5,12 @@
//----- Time scale ----- //----- Time scale -----
`timescale 1ns / 1ps `timescale 1ns / 1ps
// Design parameter for FPGA bitstream sizes
`define FPGA_SCANCHAIN_SIZE 2304
// Include caravel gate-level netlists // Include caravel gate-level netlists
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_qlsofa_hd_rtl_include_netlists.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_qlsofa_hd_rtl_include_netlists.v"
// Include testbench files // Include testbench files
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v"
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/spiflash.v" `include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/spiflash.v"