mirror of https://github.com/lnis-uofu/SOFA.git
Merge pull request #31 from LNIS-Projects/xt_dev
Testbench improvements
This commit is contained in:
Laboratory for Nano Integrated Systems (LNIS)
GitHub
commit
4d0f50470e
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@ -2,4 +2,5 @@
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This directory contains the testbenches for FPGA fabrics that are automatically generated by OpenFPGA or tuned for a specific FPGA fabric.
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Please keep this directory clean and organize as follows:
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- Each testbench should be placed in a separated directory
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- **common**: include commonly used testbench template for post-PnR verification mainly
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- READMD is the only file allowed in the directory, others should be sub-directories.
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@ -0,0 +1,11 @@
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# Skywater PDK
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This directory contains the commonly used testbench template for FPGA verificatio
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* **post\_pnr\_fpga\_cells.v**: The netlist that includes all the standard cells used by the post-PnRed FPGA fabric
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* Pre-PnR testbenches
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- **pre\_pnr\_ccff\_test.v**: The template testbench for post-PnR verification on the configuration chain
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* Post-PnR testbenches
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- **post\_pnr\_ccff\_test.v**: The template testbench for post-PnR verification on the configuration chain
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- **post\_pnr\_scff\_test.v**: The template testbench for post-PnR verification on the scan chain
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@ -54,6 +54,7 @@ wire [0:0] IO_ISOL_N;
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// ----- Counters for error checking -----
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integer num_prog_cycles = 0;
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integer num_errors = 0;
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integer num_checked_points = 0;
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// Indicate when configuration should be finished
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reg config_done = 0;
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@ -134,9 +135,9 @@ initial
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.prog_clk(prog_clk[0]),
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.Test_en(Test_en[0]),
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.clk(clk[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:`FPGA_IO_SIZE - 1]),
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.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:`FPGA_IO_SIZE - 1]),
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.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:`FPGA_IO_SIZE - 1]),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:`FPGA_IO_SIZE - 1]),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:`FPGA_IO_SIZE - 1]),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:`FPGA_IO_SIZE - 1]),
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.ccff_head(ccff_head[0]),
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.ccff_tail(ccff_tail[0]),
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.sc_head(sc_head[0]),
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@ -168,11 +169,24 @@ initial
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// Check the ccff_tail when configuration is done
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if (1'b1 == config_done) begin
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if (sc_tail != 1'b1) begin
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$display("Error: sc_tail = %b", sc_tail);
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num_errors = num_errors + 1;
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// The tail should spit a pulse after configuration is done
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// So it should be at logic '1' and then pulled down to logic '0'
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if (0 == num_checked_points) begin
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if (ccff_tail !== 1'b1) begin
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$display("Error: ccff_tail = %b", sc_tail);
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num_errors = num_errors + 1;
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end
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end
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if (1 <= num_checked_points) begin
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if (ccff_tail !== 1'b0) begin
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$display("Error: ccff_tail = %b", sc_tail);
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num_errors = num_errors + 1;
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end
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end
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num_checked_points = num_checked_points + 1;
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end
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if (2 < num_checked_points) begin
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$display("Simulation finish with %d errors", num_errors);
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// End simulation
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@ -0,0 +1,48 @@
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// Include Skywater cell netlists that are used in post PnRed FPGA netlists
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// Cells already used pre-PnR
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
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// Cells added due to their use in PnR
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_4.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b_1.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_4.v"
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@ -54,6 +54,7 @@ wire [0:0] IO_ISOL_N;
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// ----- Counters for error checking -----
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integer num_clock_cycles = 0;
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integer num_errors = 0;
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integer num_checked_points = 0;
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// Indicate when configuration should be finished
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reg scan_done = 0;
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@ -130,14 +131,14 @@ initial
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.prog_clk(prog_clk[0]),
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.Test_en(Test_en[0]),
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.clk(clk[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1]),
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.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1]),
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.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:`FPGA_IO_SIZE - 1]),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1]),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1]),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:`FPGA_IO_SIZE - 1]),
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.ccff_head(ccff_head[0]),
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.ccff_tail(ccff_tail[0]),
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.sc_head(sc_head[0]),
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.sc_tail(sc_tail[0])
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//.IO_ISOL_N(IO_ISOL_N)
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.sc_tail(sc_tail[0]),
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.IO_ISOL_N(IO_ISOL_N)
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);
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// ----- Force constant '0' to FPGA I/O as this testbench only check
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@ -164,11 +165,24 @@ initial
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// Check the tail of scan-chain when configuration is done
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if (1'b1 == scan_done) begin
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if (sc_tail != 1'b1) begin
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$display("Error: sc_tail = %b", sc_tail);
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num_errors = num_errors + 1;
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// The tail should spit a pulse after configuration is done
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// So it should be at logic '1' and then pulled down to logic '0'
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if (0 == num_checked_points) begin
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if (sc_tail !== 1'b1) begin
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$display("Error: sc_tail = %b", sc_tail);
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num_errors = num_errors + 1;
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end
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end
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if (1 <= num_checked_points) begin
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if (sc_tail !== 1'b0) begin
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$display("Error: sc_tail = %b", sc_tail);
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num_errors = num_errors + 1;
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end
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end
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num_checked_points = num_checked_points + 1;
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end
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if (2 < num_checked_points) begin
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$display("Simulation finish with %d errors", num_errors);
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// End simulation
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@ -3,7 +3,7 @@
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// Description: FPGA Verilog Testbench for Top-level netlist of Design: and2_latch
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// Author: Xifan TANG
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// Organization: University of Utah
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// Date: Tue Nov 17 15:03:02 2020
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// Date: Tue Nov 17 19:54:57 2020
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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@ -12,14 +12,15 @@ module and2_latch_autocheck_top_tb;
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// ----- Local wires for global ports of FPGA fabric -----
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wire [0:0] prog_clk;
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wire [0:0] Test_en;
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wire [0:0] IO_ISOL_N;
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wire [0:0] clk;
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// ----- Local wires for I/Os of FPGA fabric -----
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wire [0:143] gfpga_pad_EMBEDDED_IO_SOC_IN;
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wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
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wire [0:143] gfpga_pad_EMBEDDED_IO_SOC_OUT;
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wire [0:143] gfpga_pad_EMBEDDED_IO_SOC_DIR;
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wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
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wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
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reg [0:0] config_done;
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wire [0:0] prog_clock;
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@ -141,321 +142,325 @@ initial
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assign prog_clk[0] = prog_clock[0];
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assign clk[0] = op_clock[0];
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assign Test_en[0] = 1'b0;
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assign IO_ISOL_N[0] = 1'b1;
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assign sc_head[0] = 1'b0;
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// ----- End connecting global ports of FPGA fabric to stimuli -----
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// ----- FPGA top-level module to be capsulated -----
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fpga_core FPGA_DUT (
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.prog_clk(prog_clk[0]),
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.Test_en(Test_en[0]),
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.IO_ISOL_N(IO_ISOL_N[0]),
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.clk(clk[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:143]),
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.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:143]),
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.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:143]),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:143]),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:143]),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:143]),
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.ccff_head(ccff_head[0]),
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.ccff_tail(ccff_tail[0]),
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.sc_head(sc_head[0]),
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.sc_tail(sc_tail[0])
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);
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// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
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// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_IN[11] -----
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[11] = a[0];
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// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] -----
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assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = a[0];
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// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_IN[12] -----
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[12] = b[0];
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||||
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] -----
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = b[0];
|
||||
|
||||
// ----- Blif Benchmark input clk is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_IN[42] -----
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[42] = clk[0];
|
||||
// ----- Blif Benchmark input clk is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] -----
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = clk[0];
|
||||
|
||||
// ----- Blif Benchmark output out_c is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_OUT[13] -----
|
||||
assign out_c_fpga[0] = gfpga_pad_EMBEDDED_IO_SOC_OUT[13];
|
||||
// ----- Blif Benchmark output out_c is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] -----
|
||||
assign out_c_fpga[0] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13];
|
||||
|
||||
// ----- Blif Benchmark output out_d is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_OUT[10] -----
|
||||
assign out_d_fpga[0] = gfpga_pad_EMBEDDED_IO_SOC_OUT[10];
|
||||
// ----- Blif Benchmark output out_d is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] -----
|
||||
assign out_d_fpga[0] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10];
|
||||
|
||||
// ----- Wire unused FPGA I/Os to constants -----
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[1] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[2] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[3] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[4] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[5] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[6] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[7] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[8] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[9] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[10] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[13] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[14] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[15] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[16] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[17] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[18] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[19] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[20] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[21] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[22] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[23] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[24] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[25] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[26] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[27] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[28] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[29] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[30] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[31] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[32] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[33] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[34] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[35] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[36] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[37] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[38] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[39] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[40] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[41] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[43] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[44] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[45] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[46] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[47] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[48] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[49] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[50] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[51] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[52] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[53] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[54] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[55] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[56] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[57] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[58] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[59] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[60] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[61] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[62] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[63] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[64] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[65] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[66] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[67] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[68] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[69] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[70] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[71] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[72] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[73] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[74] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[75] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[76] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[77] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[78] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[79] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[80] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[81] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[82] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[83] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[84] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[85] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[86] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[87] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[88] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[89] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[90] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[91] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[92] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[93] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[94] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[95] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[96] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[97] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[98] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[99] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[100] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[101] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[102] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[103] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[104] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[105] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[106] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[107] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[108] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[109] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[110] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[111] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[112] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[113] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[114] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[115] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[116] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[117] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[118] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[119] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[120] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[121] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[122] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[123] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[124] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[125] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[126] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[127] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[128] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[129] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[130] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[131] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[132] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[133] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[134] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[135] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[136] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[137] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[138] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[139] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[140] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[141] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[142] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[143] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = 1'b0;
|
||||
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[0] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[1] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[2] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[3] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[4] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[5] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[6] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[7] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[8] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[9] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[11] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[12] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[14] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[15] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[16] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[17] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[18] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[19] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[20] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[21] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[22] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[23] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[24] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[25] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[26] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[27] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[28] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[29] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[30] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[31] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[32] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[33] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[34] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[35] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[36] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[37] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[38] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[39] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[40] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[41] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[42] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[43] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[44] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[45] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[46] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[47] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[48] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[49] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[50] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[51] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[52] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[53] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[54] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[55] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[56] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[57] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[58] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[59] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[60] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[61] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[62] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[63] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[64] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[65] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[66] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[67] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[68] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[69] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[70] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[71] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[72] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[73] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[74] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[75] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[76] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[77] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[78] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[79] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[80] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[81] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[82] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[83] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[84] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[85] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[86] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[87] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[88] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[89] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[90] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[91] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[92] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[93] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[94] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[95] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[96] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[97] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[98] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[99] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[100] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[101] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[102] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[103] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[104] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[105] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[106] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[107] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[108] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[109] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[110] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[111] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[112] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[113] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[114] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[115] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[116] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[117] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[118] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[119] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[120] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[121] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[122] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[123] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[124] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[125] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[126] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[127] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[128] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[129] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[130] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[131] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[132] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[133] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[134] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[135] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[136] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[137] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[138] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[139] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[140] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[141] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[142] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[143] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] = 1'b0;
|
||||
|
||||
`ifdef AUTOCHECKED_SIMULATION
|
||||
// ----- Reference Benchmark Instanication -------
|
||||
|
|
|
|||
|
|
@ -14,51 +14,11 @@
|
|||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
|
||||
|
||||
// ------ Include Skywater cell netlists -----
|
||||
// Cells already used pre-PnR
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
|
||||
|
||||
// Cells added due to their use in PnR
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
|
||||
|
||||
// ------ Include fabric top-level netlists -----
|
||||
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
|
||||
|
||||
`ifdef AUTOCHECKED_SIMULATION
|
||||
`include "and2_latch_output_verilog.v"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -14,51 +14,11 @@
|
|||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
|
||||
|
||||
// ------ Include Skywater cell netlists -----
|
||||
// Cells already used pre-PnR
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
|
||||
|
||||
// Cells added due to their use in PnR
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
|
||||
|
||||
// ------ Include fabric top-level netlists -----
|
||||
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
|
||||
|
||||
`ifdef AUTOCHECKED_SIMULATION
|
||||
`include "and2_output_verilog.v"
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
`timescale 1ns / 1ps
|
||||
|
||||
// Design parameter for FPGA I/O sizes
|
||||
`define FPGA_IO_SIZE 108
|
||||
`define FPGA_IO_SIZE 144
|
||||
|
||||
// Design parameter for FPGA bitstream sizes
|
||||
`define FPGA_BITSTREAM_SIZE 65656
|
||||
|
|
@ -20,50 +20,10 @@
|
|||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
|
||||
|
||||
// ------ Include Skywater cell netlists -----
|
||||
// Cells already used pre-PnR
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
|
||||
|
||||
// Cells added due to their use in PnR
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
|
||||
|
||||
// ------ Include fabric top-level netlists -----
|
||||
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
|
||||
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_ccff_test.v"
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
`timescale 1ns / 1ps
|
||||
|
||||
// Design parameter for FPGA I/O sizes
|
||||
`define FPGA_IO_SIZE 108
|
||||
`define FPGA_IO_SIZE 144
|
||||
|
||||
// Design parameter for FPGA bitstream sizes
|
||||
`define FPGA_SCANCHAIN_SIZE 2304
|
||||
|
|
@ -20,50 +20,10 @@
|
|||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
|
||||
|
||||
// ------ Include Skywater cell netlists -----
|
||||
// Cells already used pre-PnR
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
|
||||
|
||||
// Cells added due to their use in PnR
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
|
||||
|
||||
// ------ Include fabric top-level netlists -----
|
||||
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
|
||||
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_scff_test.v"
|
||||
|
|
|
|||
Loading…
Reference in New Issue