From e58fc97794a962939f8f5005be3a6efe033ff5ca Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Nov 2020 10:55:59 -0700 Subject: [PATCH 1/6] [Testbench] Update post-pnr test for latest PnRed netlist --- .../and2_post_pnr_autocheck_top_tb.v | 845 ++++++++++++------ .../and2_post_pnr_include_netlists.v | 5 +- 2 files changed, 584 insertions(+), 266 deletions(-) diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v index 9a2af5d..40d830b 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v @@ -3,7 +3,7 @@ // Description: FPGA Verilog Testbench for Top-level netlist of Design: and2 // Author: Xifan TANG // Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 +// Date: Tue Nov 17 19:54:57 2020 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps @@ -12,14 +12,15 @@ module and2_autocheck_top_tb; // ----- Local wires for global ports of FPGA fabric ----- wire [0:0] prog_clk; wire [0:0] Test_en; +wire [0:0] IO_ISOL_N; wire [0:0] clk; // ----- Local wires for I/Os of FPGA fabric ----- -wire [0:107] gfpga_pad_EMBEDDED_IO_SOC_IN; +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; -wire [0:107] gfpga_pad_EMBEDDED_IO_SOC_OUT; -wire [0:107] gfpga_pad_EMBEDDED_IO_SOC_DIR; +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; reg [0:0] config_done; wire [0:0] prog_clock; @@ -59,7 +60,7 @@ wire [0:0] sc_tail; // ----- Error counter: Deposit an error for config_done signal is not raised at the beginning ----- integer nb_error= 1; -// ----- Number of clock cycles in configuration phase: 65417 ----- +// ----- Number of clock cycles in configuration phase: 65657 ----- // ----- Begin configuration done signal generation ----- initial begin @@ -75,7 +76,7 @@ initial end always begin - #5 prog_clock_reg[0] = ~prog_clock_reg[0]; + #10 prog_clock_reg[0] = ~prog_clock_reg[0]; end // ----- End raw programming clock signal generation ----- @@ -90,7 +91,7 @@ initial end always wait(~greset) begin - #0.4159859717 op_clock_reg[0] = ~op_clock_reg[0]; + #10 op_clock_reg[0] = ~op_clock_reg[0]; end // ----- End raw operating clock signal generation ----- @@ -101,7 +102,7 @@ always wait(~greset) initial begin prog_reset[0] = 1'b1; - #10 prog_reset[0] = 1'b0; + #20 prog_reset[0] = 1'b0; end // ----- End programming reset signal generation ----- @@ -110,7 +111,7 @@ initial initial begin prog_set[0] = 1'b1; - #10 prog_set[0] = 1'b0; + #20 prog_set[0] = 1'b0; end // ----- End programming set signal generation ----- @@ -121,8 +122,8 @@ initial begin greset[0] = 1'b1; wait(config_done) - #0.8319719434 greset[0] = 1'b1; - #1.663943887 greset[0] = 1'b0; + #20 greset[0] = 1'b1; + #40 greset[0] = 1'b0; end // ----- End operating reset signal generation ----- @@ -135,19 +136,21 @@ initial // ----- End operating set signal generation: always disabled ----- // ----- Begin connecting global ports of FPGA fabric to stimuli ----- - assign clk[0] = op_clock[0]; assign prog_clk[0] = prog_clock[0]; + assign clk[0] = op_clock[0]; assign Test_en[0] = 1'b0; + assign IO_ISOL_N[0] = 1'b1; assign sc_head[0] = 1'b0; // ----- End connecting global ports of FPGA fabric to stimuli ----- // ----- FPGA top-level module to be capsulated ----- fpga_core FPGA_DUT ( .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), + .IO_ISOL_N(IO_ISOL_N[0]), .clk(clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:107]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:107]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:107]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:143]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:143]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:143]), .ccff_head(ccff_head[0]), .ccff_tail(ccff_tail[0]), .sc_head(sc_head[0]), @@ -155,230 +158,302 @@ initial ); // ----- Link BLIF Benchmark I/Os to FPGA I/Os ----- -// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_IN[57] ----- - assign gfpga_pad_EMBEDDED_IO_SOC_IN[57] = a[0]; +// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] ----- + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = a[0]; -// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_IN[55] ----- - assign gfpga_pad_EMBEDDED_IO_SOC_IN[55] = b[0]; +// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] ----- + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = b[0]; -// ----- Blif Benchmark output out_c is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_OUT[58] ----- - assign out_c_fpga[0] = gfpga_pad_EMBEDDED_IO_SOC_OUT[58]; +// ----- Blif Benchmark output out_c is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ----- + assign out_c_fpga[0] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]; // ----- Wire unused FPGA I/Os to constants ----- - assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[1] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[2] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[3] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[4] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[5] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[6] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[7] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[8] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[9] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[10] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[11] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[12] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[13] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[14] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[15] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[16] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[17] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[18] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[19] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[20] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[21] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[22] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[23] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[24] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[25] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[26] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[27] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[28] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[29] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[30] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[31] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[32] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[33] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[34] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[35] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[36] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[37] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[38] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[39] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[40] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[41] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[42] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[43] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[44] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[45] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[46] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[47] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[48] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[49] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[50] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[51] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[52] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[53] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[54] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[56] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[58] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[59] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[60] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[61] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[62] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[63] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[64] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[65] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[66] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[67] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[68] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[69] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[70] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[71] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[72] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[73] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[74] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[75] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[76] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[77] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[78] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[79] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[80] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[81] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[82] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[83] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[84] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[85] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[86] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[87] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[88] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[89] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[90] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[91] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[92] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[93] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[94] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[95] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[96] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[97] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[98] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[99] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[100] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[101] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[102] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[103] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[104] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[105] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[106] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[107] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[0] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[1] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[2] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[3] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[4] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[5] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[6] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[7] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[8] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[9] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[10] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[11] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[12] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[13] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[14] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[15] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[16] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[17] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[18] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[19] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[20] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[21] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[22] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[23] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[24] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[25] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[26] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[27] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[28] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[29] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[30] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[31] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[32] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[33] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[34] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[35] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[36] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[37] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[38] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[39] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[40] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[41] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[42] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[43] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[44] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[45] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[46] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[47] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[48] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[49] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[50] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[51] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[52] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[53] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[54] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[55] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[56] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[57] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[59] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[60] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[61] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[62] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[63] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[64] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[65] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[66] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[67] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[68] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[69] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[70] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[71] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[72] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[73] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[74] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[75] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[76] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[77] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[78] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[79] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[80] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[81] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[82] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[83] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[84] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[85] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[86] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[87] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[88] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[89] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[90] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[91] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[92] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[93] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[94] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[95] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[96] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[97] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[98] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[99] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[100] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[101] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[102] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[103] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[104] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[105] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[106] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[107] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] = 1'b0; `ifdef AUTOCHECKED_SIMULATION // ----- Reference Benchmark Instanication ------- @@ -449,12 +524,31 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -560,12 +654,31 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -671,12 +784,31 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -782,12 +914,30 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -893,6 +1043,18 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); @@ -946,7 +1108,6 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -958,10 +1119,7 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1004,8 +1162,31 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); @@ -1014,9 +1195,6 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1053,10 +1231,6 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1087,7 +1261,6 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1113,7 +1286,31 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b1); prog_cycle_task(1'b1); @@ -1121,6 +1318,16 @@ initial prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1181,6 +1388,15 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1232,6 +1448,11 @@ initial prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1312,6 +1533,11 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1337,12 +1563,26 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b1); + prog_cycle_task(1'b0); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); + prog_cycle_task(1'b0); prog_cycle_task(1'b1); prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1353,6 +1593,9 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1388,6 +1631,8 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1447,6 +1692,15 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b1); prog_cycle_task(1'b1); @@ -1454,6 +1708,24 @@ initial prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1559,12 +1831,31 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1670,6 +1961,10 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); @@ -1768,7 +2063,6 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1789,6 +2083,7 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -2589,11 +2884,18 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -2644,17 +2946,21 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -3361,7 +3667,6 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -3369,10 +3674,6 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -3423,21 +3724,17 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -4941,7 +5238,6 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -4960,6 +5256,7 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -6031,9 +6328,6 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -6410,7 +6704,9 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -6579,6 +6875,7 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -7130,7 +7427,6 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -7149,6 +7445,7 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -10303,7 +10600,6 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -10322,6 +10618,7 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -11577,6 +11874,15 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -11888,6 +12194,15 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -65886,7 +66201,7 @@ initial begin $timeformat(-9, 2, "ns", 20); $display("Simulation start"); // ----- Can be changed by the user for his/her need ------- - #654195 + #1313320 if(nb_error == 0) begin $display("Simulation Succeed"); end else begin diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v index 668a0a9..f9310c2 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -55,10 +55,13 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v" // ------ Include fabric top-level netlists ----- //`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" `ifdef AUTOCHECKED_SIMULATION `include "and2_output_verilog.v" From ae82946052af93f08f9157a00857cce53bb09899 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Nov 2020 11:15:01 -0700 Subject: [PATCH 2/6] [Testbench] Update and2_latch post-pnr testbench --- .../and2_latch_post_pnr_autocheck_top_tb.v | 605 +++++++++--------- .../and2_latch_post_pnr_include_netlists.v | 5 +- 2 files changed, 309 insertions(+), 301 deletions(-) diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v index 8ff6c4e..2a059ad 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v @@ -3,7 +3,7 @@ // Description: FPGA Verilog Testbench for Top-level netlist of Design: and2_latch // Author: Xifan TANG // Organization: University of Utah -// Date: Tue Nov 17 15:03:02 2020 +// Date: Tue Nov 17 19:54:57 2020 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps @@ -12,14 +12,15 @@ module and2_latch_autocheck_top_tb; // ----- Local wires for global ports of FPGA fabric ----- wire [0:0] prog_clk; wire [0:0] Test_en; +wire [0:0] IO_ISOL_N; wire [0:0] clk; // ----- Local wires for I/Os of FPGA fabric ----- -wire [0:143] gfpga_pad_EMBEDDED_IO_SOC_IN; +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; -wire [0:143] gfpga_pad_EMBEDDED_IO_SOC_OUT; -wire [0:143] gfpga_pad_EMBEDDED_IO_SOC_DIR; +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; reg [0:0] config_done; wire [0:0] prog_clock; @@ -141,321 +142,325 @@ initial assign prog_clk[0] = prog_clock[0]; assign clk[0] = op_clock[0]; assign Test_en[0] = 1'b0; + assign IO_ISOL_N[0] = 1'b1; assign sc_head[0] = 1'b0; // ----- End connecting global ports of FPGA fabric to stimuli ----- // ----- FPGA top-level module to be capsulated ----- fpga_core FPGA_DUT ( .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), + .IO_ISOL_N(IO_ISOL_N[0]), .clk(clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:143]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:143]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:143]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:143]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:143]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:143]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail[0]), .sc_head(sc_head[0]), .sc_tail(sc_tail[0]) ); // ----- Link BLIF Benchmark I/Os to FPGA I/Os ----- -// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_IN[11] ----- - assign gfpga_pad_EMBEDDED_IO_SOC_IN[11] = a[0]; +// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] ----- + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = a[0]; -// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_IN[12] ----- - assign gfpga_pad_EMBEDDED_IO_SOC_IN[12] = b[0]; +// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] ----- + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = b[0]; -// ----- Blif Benchmark input clk is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_IN[42] ----- - assign gfpga_pad_EMBEDDED_IO_SOC_IN[42] = clk[0]; +// ----- Blif Benchmark input clk is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] ----- + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = clk[0]; -// ----- Blif Benchmark output out_c is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_OUT[13] ----- - assign out_c_fpga[0] = gfpga_pad_EMBEDDED_IO_SOC_OUT[13]; +// ----- Blif Benchmark output out_c is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] ----- + assign out_c_fpga[0] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13]; -// ----- Blif Benchmark output out_d is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_OUT[10] ----- - assign out_d_fpga[0] = gfpga_pad_EMBEDDED_IO_SOC_OUT[10]; +// ----- Blif Benchmark output out_d is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] ----- + assign out_d_fpga[0] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10]; // ----- Wire unused FPGA I/Os to constants ----- - assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[1] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[2] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[3] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[4] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[5] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[6] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[7] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[8] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[9] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[10] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[13] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[14] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[15] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[16] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[17] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[18] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[19] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[20] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[21] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[22] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[23] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[24] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[25] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[26] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[27] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[28] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[29] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[30] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[31] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[32] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[33] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[34] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[35] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[36] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[37] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[38] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[39] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[40] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[41] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[43] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[44] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[45] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[46] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[47] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[48] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[49] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[50] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[51] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[52] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[53] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[54] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[55] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[56] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[57] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[58] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[59] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[60] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[61] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[62] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[63] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[64] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[65] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[66] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[67] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[68] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[69] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[70] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[71] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[72] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[73] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[74] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[75] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[76] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[77] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[78] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[79] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[80] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[81] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[82] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[83] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[84] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[85] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[86] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[87] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[88] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[89] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[90] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[91] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[92] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[93] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[94] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[95] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[96] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[97] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[98] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[99] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[100] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[101] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[102] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[103] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[104] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[105] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[106] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[107] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[108] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[109] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[110] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[111] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[112] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[113] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[114] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[115] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[116] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[117] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[118] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[119] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[120] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[121] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[122] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[123] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[124] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[125] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[126] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[127] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[128] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[129] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[130] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[131] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[132] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[133] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[134] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[135] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[136] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[137] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[138] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[139] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[140] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[141] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[142] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[143] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[0] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[1] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[2] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[3] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[4] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[5] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[6] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[7] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[8] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[9] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[11] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[12] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[14] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[15] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[16] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[17] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[18] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[19] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[20] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[21] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[22] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[23] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[24] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[25] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[26] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[27] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[28] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[29] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[30] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[31] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[32] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[33] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[34] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[35] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[36] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[37] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[38] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[39] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[40] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[41] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[42] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[43] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[44] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[45] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[46] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[47] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[48] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[49] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[50] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[51] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[52] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[53] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[54] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[55] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[56] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[57] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[58] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[59] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[60] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[61] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[62] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[63] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[64] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[65] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[66] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[67] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[68] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[69] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[70] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[71] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[72] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[73] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[74] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[75] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[76] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[77] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[78] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[79] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[80] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[81] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[82] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[83] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[84] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[85] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[86] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[87] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[88] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[89] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[90] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[91] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[92] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[93] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[94] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[95] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[96] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[97] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[98] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[99] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[100] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[101] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[102] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[103] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[104] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[105] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[106] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[107] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[108] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[109] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[110] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[111] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[112] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[113] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[114] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[115] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[116] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[117] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[118] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[119] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[120] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[121] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[122] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[123] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[124] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[125] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[126] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[127] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[128] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[129] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[130] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[131] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[132] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[133] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[134] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[135] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[136] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[137] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[138] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[139] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[140] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[141] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[142] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[143] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] = 1'b0; `ifdef AUTOCHECKED_SIMULATION // ----- Reference Benchmark Instanication ------- diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v index 6f55c69..4ad7663 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v @@ -55,10 +55,13 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v" // ------ Include fabric top-level netlists ----- //`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" `ifdef AUTOCHECKED_SIMULATION `include "and2_latch_output_verilog.v" From 40eccfa0ba81e5448bc75dc8b13bb78aad6b3d1b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Nov 2020 11:45:51 -0700 Subject: [PATCH 3/6] [Testbench] Update post-PnR testbenches for configuration chain and scan-chain and enhance checking codes --- TESTBENCH/common/post_pnr_ccff_test.v | 26 ++++++++++++---- TESTBENCH/common/post_pnr_scff_test.v | 30 ++++++++++++++----- .../ccff_test_post_pnr_include_netlists.v | 7 +++-- .../scff_test_post_pnr_include_netlists.v | 7 +++-- 4 files changed, 52 insertions(+), 18 deletions(-) diff --git a/TESTBENCH/common/post_pnr_ccff_test.v b/TESTBENCH/common/post_pnr_ccff_test.v index 53f9a1d..4ed9cb3 100644 --- a/TESTBENCH/common/post_pnr_ccff_test.v +++ b/TESTBENCH/common/post_pnr_ccff_test.v @@ -54,6 +54,7 @@ wire [0:0] IO_ISOL_N; // ----- Counters for error checking ----- integer num_prog_cycles = 0; integer num_errors = 0; +integer num_checked_points = 0; // Indicate when configuration should be finished reg config_done = 0; @@ -134,9 +135,9 @@ initial .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:`FPGA_IO_SIZE - 1]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:`FPGA_IO_SIZE - 1]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:`FPGA_IO_SIZE - 1]), .ccff_head(ccff_head[0]), .ccff_tail(ccff_tail[0]), .sc_head(sc_head[0]), @@ -168,11 +169,24 @@ initial // Check the ccff_tail when configuration is done if (1'b1 == config_done) begin - if (sc_tail != 1'b1) begin - $display("Error: sc_tail = %b", sc_tail); - num_errors = num_errors + 1; + // The tail should spit a pulse after configuration is done + // So it should be at logic '1' and then pulled down to logic '0' + if (0 == num_checked_points) begin + if (sc_tail != 1'b1) begin + $display("Error: sc_tail = %b", sc_tail); + num_errors = num_errors + 1; + end end + if (1 <= num_checked_points) begin + if (sc_tail != 1'b0) begin + $display("Error: sc_tail = %b", sc_tail); + num_errors = num_errors + 1; + end + end + num_checked_points = num_checked_points + 1; + end + if (2 < num_checked_points) begin $display("Simulation finish with %d errors", num_errors); // End simulation diff --git a/TESTBENCH/common/post_pnr_scff_test.v b/TESTBENCH/common/post_pnr_scff_test.v index 4b6c15b..85a3eb9 100644 --- a/TESTBENCH/common/post_pnr_scff_test.v +++ b/TESTBENCH/common/post_pnr_scff_test.v @@ -54,6 +54,7 @@ wire [0:0] IO_ISOL_N; // ----- Counters for error checking ----- integer num_clock_cycles = 0; integer num_errors = 0; +integer num_checked_points = 0; // Indicate when configuration should be finished reg scan_done = 0; @@ -130,14 +131,14 @@ initial .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:`FPGA_IO_SIZE - 1]), .ccff_head(ccff_head[0]), .ccff_tail(ccff_tail[0]), .sc_head(sc_head[0]), - .sc_tail(sc_tail[0]) - //.IO_ISOL_N(IO_ISOL_N) + .sc_tail(sc_tail[0]), + .IO_ISOL_N(IO_ISOL_N) ); // ----- Force constant '0' to FPGA I/O as this testbench only check @@ -164,11 +165,24 @@ initial // Check the tail of scan-chain when configuration is done if (1'b1 == scan_done) begin - if (sc_tail != 1'b1) begin - $display("Error: sc_tail = %b", sc_tail); - num_errors = num_errors + 1; + // The tail should spit a pulse after configuration is done + // So it should be at logic '1' and then pulled down to logic '0' + if (0 == num_checked_points) begin + if (sc_tail != 1'b1) begin + $display("Error: sc_tail = %b", sc_tail); + num_errors = num_errors + 1; + end end + if (1 <= num_checked_points) begin + if (sc_tail != 1'b0) begin + $display("Error: sc_tail = %b", sc_tail); + num_errors = num_errors + 1; + end + end + num_checked_points = num_checked_points + 1; + end + if (2 < num_checked_points) begin $display("Simulation finish with %d errors", num_errors); // End simulation diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v index ec47dbe..d736108 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -9,7 +9,7 @@ `timescale 1ns / 1ps // Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 108 +`define FPGA_IO_SIZE 144 // Design parameter for FPGA bitstream sizes `define FPGA_BITSTREAM_SIZE 65656 @@ -61,9 +61,12 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v" // ------ Include fabric top-level netlists ----- //`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_ccff_test.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index 6734773..28c7f6d 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -9,7 +9,7 @@ `timescale 1ns / 1ps // Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 108 +`define FPGA_IO_SIZE 144 // Design parameter for FPGA bitstream sizes `define FPGA_SCANCHAIN_SIZE 2304 @@ -61,9 +61,12 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v" // ------ Include fabric top-level netlists ----- //`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_scff_test.v" From 5a2f1e7607e91547f61bcbcfe82bb111097763c9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Nov 2020 13:33:13 -0700 Subject: [PATCH 4/6] [TESTBENCH] Place the include lines for post-PnR skywater cell netlists in a separated netlist, so that it can be shared among post-PnRed testbenches --- TESTBENCH/common/post_pnr_fpga_cells.v | 45 +++++++++++++++++++ .../and2_latch_post_pnr_include_netlists.v | 45 +------------------ .../and2_post_pnr_include_netlists.v | 45 +------------------ .../ccff_test_post_pnr_include_netlists.v | 45 +------------------ .../scff_test_post_pnr_include_netlists.v | 45 +------------------ 5 files changed, 49 insertions(+), 176 deletions(-) create mode 100644 TESTBENCH/common/post_pnr_fpga_cells.v diff --git a/TESTBENCH/common/post_pnr_fpga_cells.v b/TESTBENCH/common/post_pnr_fpga_cells.v new file mode 100644 index 0000000..410177e --- /dev/null +++ b/TESTBENCH/common/post_pnr_fpga_cells.v @@ -0,0 +1,45 @@ +// Include Skywater cell netlists that are used in post PnRed FPGA netlists +// Cells already used pre-PnR +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v" + +// Cells added due to their use in PnR +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v index 4ad7663..c1b7265 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v @@ -14,50 +14,7 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" // ------ Include Skywater cell netlists ----- -// Cells already used pre-PnR -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v" - -// Cells added due to their use in PnR -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" // ------ Include fabric top-level netlists ----- //`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v index f9310c2..24d1f7b 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -14,50 +14,7 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" // ------ Include Skywater cell netlists ----- -// Cells already used pre-PnR -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v" - -// Cells added due to their use in PnR -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" // ------ Include fabric top-level netlists ----- //`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v index d736108..ad70cd7 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -20,50 +20,7 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" // ------ Include Skywater cell netlists ----- -// Cells already used pre-PnR -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v" - -// Cells added due to their use in PnR -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" // ------ Include fabric top-level netlists ----- //`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index 28c7f6d..7d8c45b 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -20,50 +20,7 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" // ------ Include Skywater cell netlists ----- -// Cells already used pre-PnR -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v" - -// Cells added due to their use in PnR -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" // ------ Include fabric top-level netlists ----- //`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" From 3756c25572e0b83ee02957841c29614ef5c4872e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Nov 2020 13:51:26 -0700 Subject: [PATCH 5/6] [Testbench] Enhance checking codes. Now 'X' or 'Z' signal will fail in self-checking --- TESTBENCH/common/post_pnr_ccff_test.v | 8 ++++---- TESTBENCH/common/post_pnr_fpga_cells.v | 3 +++ TESTBENCH/common/post_pnr_scff_test.v | 4 ++-- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/TESTBENCH/common/post_pnr_ccff_test.v b/TESTBENCH/common/post_pnr_ccff_test.v index 4ed9cb3..a8e44df 100644 --- a/TESTBENCH/common/post_pnr_ccff_test.v +++ b/TESTBENCH/common/post_pnr_ccff_test.v @@ -172,14 +172,14 @@ initial // The tail should spit a pulse after configuration is done // So it should be at logic '1' and then pulled down to logic '0' if (0 == num_checked_points) begin - if (sc_tail != 1'b1) begin - $display("Error: sc_tail = %b", sc_tail); + if (ccff_tail !== 1'b1) begin + $display("Error: ccff_tail = %b", sc_tail); num_errors = num_errors + 1; end end if (1 <= num_checked_points) begin - if (sc_tail != 1'b0) begin - $display("Error: sc_tail = %b", sc_tail); + if (ccff_tail !== 1'b0) begin + $display("Error: ccff_tail = %b", sc_tail); num_errors = num_errors + 1; end end diff --git a/TESTBENCH/common/post_pnr_fpga_cells.v b/TESTBENCH/common/post_pnr_fpga_cells.v index 410177e..0c7cda0 100644 --- a/TESTBENCH/common/post_pnr_fpga_cells.v +++ b/TESTBENCH/common/post_pnr_fpga_cells.v @@ -34,6 +34,7 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_4.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v" @@ -43,3 +44,5 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_4.v" diff --git a/TESTBENCH/common/post_pnr_scff_test.v b/TESTBENCH/common/post_pnr_scff_test.v index 85a3eb9..c049745 100644 --- a/TESTBENCH/common/post_pnr_scff_test.v +++ b/TESTBENCH/common/post_pnr_scff_test.v @@ -168,13 +168,13 @@ initial // The tail should spit a pulse after configuration is done // So it should be at logic '1' and then pulled down to logic '0' if (0 == num_checked_points) begin - if (sc_tail != 1'b1) begin + if (sc_tail !== 1'b1) begin $display("Error: sc_tail = %b", sc_tail); num_errors = num_errors + 1; end end if (1 <= num_checked_points) begin - if (sc_tail != 1'b0) begin + if (sc_tail !== 1'b0) begin $display("Error: sc_tail = %b", sc_tail); num_errors = num_errors + 1; end From 7145f7ccd47af077804562dbfea15947e3935480 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Nov 2020 13:59:15 -0700 Subject: [PATCH 6/6] [Doc] Add documentation about the testbenches --- TESTBENCH/README.md | 1 + TESTBENCH/common/README.md | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 TESTBENCH/common/README.md diff --git a/TESTBENCH/README.md b/TESTBENCH/README.md index 5b27814..7a2dbc3 100644 --- a/TESTBENCH/README.md +++ b/TESTBENCH/README.md @@ -2,4 +2,5 @@ This directory contains the testbenches for FPGA fabrics that are automatically generated by OpenFPGA or tuned for a specific FPGA fabric. Please keep this directory clean and organize as follows: - Each testbench should be placed in a separated directory +- **common**: include commonly used testbench template for post-PnR verification mainly - READMD is the only file allowed in the directory, others should be sub-directories. diff --git a/TESTBENCH/common/README.md b/TESTBENCH/common/README.md new file mode 100644 index 0000000..040e1de --- /dev/null +++ b/TESTBENCH/common/README.md @@ -0,0 +1,11 @@ +# Skywater PDK +This directory contains the commonly used testbench template for FPGA verificatio + +* **post\_pnr\_fpga\_cells.v**: The netlist that includes all the standard cells used by the post-PnRed FPGA fabric + +* Pre-PnR testbenches + - **pre\_pnr\_ccff\_test.v**: The template testbench for post-PnR verification on the configuration chain + +* Post-PnR testbenches + - **post\_pnr\_ccff\_test.v**: The template testbench for post-PnR verification on the configuration chain + - **post\_pnr\_scff\_test.v**: The template testbench for post-PnR verification on the scan chain