Added SOFA-A project

.gitignore

@@ -16,3 +16,4 @@
 **/*_task/run**
 **/*_task/config/task.conf
 .vscode/
+LoadTools.sh

SOFA_A/.gitignore

@@ -0,0 +1,24 @@
+# Ignore all
+*
+# Unignore all with extensions
+!*.*
+# Unignore all dirs
+!*/
+# Unignore makefiles
+!Makefile*
+# Ignore directories starting with . in from root directory
+/.*/
+# All files starting underscroll
+_*.*
+# All directories starting underscroll
+_*
+# Unignore python init_file
+!__init__.py
+
+
+# OpenFPGA Task ignore files
+task.conf
+!*_pnr/*_task/**
+**/*_task/latest
+**/*_task/run*
+**/release/pickle/

SOFA_A/CommonFiles/render_sofa_a.py

@@ -0,0 +1,126 @@
+"""
+This file redners the fabric before the netlist generation
+"""
+import logging
+import os
+import pickle
+from glob import glob
+from pathlib import Path
+
+from spydrnet_physical.util import FPGAGridGen
+
+logger = logging.getLogger("spydrnet_logs")
+
+PROJ_NAME = os.environ["PROJ_NAME"]
+RELEASE_DIR = os.environ["RELEASE_DIRECTORY"]
+LAYOUT = os.environ["LAYOUT"]
+TASK_DIR_NAME = os.environ["TASK_DIR_NAME"]
+SVG_DIR = f"{RELEASE_DIR}/svg"
+XML_DIR = f"{RELEASE_DIR}/xml"
+PICKLE_DIR = f"{RELEASE_DIR}/pickle"
+
+def main():
+    """
+    Main flow
+    """
+    try:
+        VPR_ARCH_FILE = glob((f"{TASK_DIR_NAME}/arch/*vpr*"))[0]
+    except IndexError:
+        logger.exception(
+            "Architecture file not found ['%s/arch/*vpr*']", TASK_DIR_NAME)
+        exit(1)
+    logger.info("Reading architeture file %s", VPR_ARCH_FILE)
+    # Demonstrates how to modify the structure
+    fpga = FPGAGridGen(
+        design_name=PROJ_NAME,
+        arch_file=VPR_ARCH_FILE,
+        release_root=RELEASE_DIR,
+        layout=LAYOUT,
+    )
+    logger.info("Loading Layout %s", LAYOUT)
+    fpga.enumerate_grid()
+    fpga.default_parameters["cbx"][0] = 10  # uncomment to force square plan
+    fpga.default_parameters["cby"][1] = 10  # uncomment to force square plan
+    Path(SVG_DIR).mkdir(parents=True, exist_ok=True)
+    Path(PICKLE_DIR).mkdir(parents=True, exist_ok=True)
+
+    dwg = fpga.render_layout(
+        filename=f"{SVG_DIR}/{PROJ_NAME}_render.svg", grid_io=True)
+
+    dwg.save(pretty=True, indent=4)
+    pickle.dump(dwg, open(f"{PICKLE_DIR}/{PROJ_NAME}_render.pickle", "wb"))
+    logger.info("Saving file %s/%s_render.svg", SVG_DIR, PROJ_NAME)
+
+    # ============ Modify your floorplan here ============
+    # Adding stylesheet
+    fpga.add_style("symbol[id*='sides_merged'] * { fill:green; opacity:0.5 }")
+    fpga.add_style("symbol[id*='corner'] * { fill:#28f7c7; opacity:0.5 }")
+    fpga.add_style("symbol[id*='main_tile'] * { fill:#F0A35E; opacity:0.5 }")
+    fpga.add_style("symbol[id*='merged'] * { stroke:white; stroke-width:1px;}")
+
+    # Extract width and height
+    w = fpga.get_width()
+    h = fpga.get_height()
+
+    for y in range(2, h):
+        x = 0
+        instances = [f"cby_{x}__{y}_", f"sb_{x}__{y}_",
+                     f"cbx_{x+1}__{y}_", f"clb_{x+1}__{y}_",
+                     f"cby_{x+1}__{y}_", f"sb_{x+1}__{y}_"]
+        fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}")
+        x = w
+        instances = [f"cby_{x}__{y}_", f"sb_{x}__{y}_",
+                     f"cbx_{x}__{y}_", f"clb_{x}__{y}_"]
+        fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}")
+
+    for x in range(2, w):
+        y = 0
+        instances = [f"cbx_{x}__{y}_", f"sb_{x}__{y}_",
+                     f"cby_{x}__{y+1}_", f"clb_{x}__{y+1}_",
+                     f"cbx_{x}__{y+1}_", f"sb_{x}__{y+1}_"]
+        fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}")
+        y = h
+        instances = [f"cbx_{x}__{y}_", f"sb_{x}__{y}_",
+                     f"cby_{x}__{y}_", f"clb_{x}__{y}_"]
+        fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}")
+
+    # Main tile
+    for x in range(2, w):
+        for y in  range(2, h):
+            fpga.merge_symbol(
+                [ f"clb_{x}__{y}_", f"sb_{x}__{y}_",
+                    f"cbx_{x}__{y}_", f"cby_{x}__{y}_"],
+                    f"main_tile_merged_{x}_{y}")
+
+    # Corner Tiles
+    fpga.merge_symbol(
+        [f"cby_0__{h}_", f"sb_0__{h}_", f"cbx_1__{h}_",
+         f"cby_1__{h}_", f"sb_1__{h}_"], "corner_merged_ltop")
+    fpga.merge_symbol(
+        [f"cbx_{w}__{h}_", f"cby_{w}__{h}_",
+         f"clb_{w}__{h}_", f"sb_{w}__{h}_"], "corner_merged_rtop")
+    fpga.merge_symbol(
+        [f"cbx_{w}__0_", f"cbx_{w}__1_",
+         f"sb_{w}__0_", f"sb_{w}__1_",
+         f"cby_{w}__1_", f"clb_{w}__1_"], "corner_merged_rbottom")
+    fpga.merge_symbol(
+        ["cbx_1__0_", "cbx_1__1_",
+         "sb_0__0_", "sb_0__1_",
+         "sb_1__0_", "sb_1__1_",
+         "cby_1__1_", "clb_1__1_"], "corner_merged_lbottom")
+
+    # ====================== END =========================
+
+    dwg.saveas(
+        filename=f"{SVG_DIR}/{PROJ_NAME}_restruct_render.svg", pretty=True, indent=4
+    )
+    pickle.dump(
+        dwg, open(f"{PICKLE_DIR}/{PROJ_NAME}_restruct_render.pickle", "wb"))
+    pickle.dump(fpga, open(
+        f"{PICKLE_DIR}/{PROJ_NAME}_fpgagridgen.pickle", "wb"))
+    logger.info("Saving file %s/%s_restruct_render.svg", SVG_DIR, PROJ_NAME)
+    return dwg
+
+
+if __name__ == "__main__":
+    main()

SOFA_A/CommonFiles/render_sofa_a_fabric_key.py

@@ -0,0 +1,84 @@
+# ##############################################################################
+# Tool: OpenFPGA-Physical
+# Script: generate_fabric_key.py
+# Description : This script cretes a fabric_key.xml file for give size of FPGA
+#       Currently this script generate pattern which routes configuration chain
+#       from right top corner to left bottom corner by traversing horizontally
+#       in every row of the FPGA grid
+################################################################################
+"""
+File Title
+"""
+
+
+import logging
+import os
+from glob import glob
+import pickle
+from copy import deepcopy
+from pathlib import Path
+
+from spydrnet_physical.util import FabricKeyGenCCFF
+
+logger = logging.getLogger("spydrnet_logs")
+
+
+PROJ_NAME = os.environ["PROJ_NAME"]
+RELEASE_DIR = os.environ["RELEASE_DIRECTORY"]
+FPGA_WIDTH = int(os.environ.get("FPGA_SIZE_X"))
+FPGA_HEIGHT = int(os.environ.get("FPGA_SIZE_Y"))
+FABRIC_KEY_PATTERN = os.environ["FABRIC_KEY_PATTERN"]
+TASK_DIR_NAME = os.environ.get("TASK_DIR_NAME")
+LAYOUT = os.environ["LAYOUT"]
+TASK_DIR_NAME = os.environ["TASK_DIR_NAME"]
+VERILOG_PROJ_DIR = os.environ["VERILOG_PROJ_DIR"]
+SVG_DIR = f"{RELEASE_DIR}/svg"
+XML_DIR = f"{RELEASE_DIR}/xml"
+PICKLE_DIR = f"{RELEASE_DIR}/pickle"
+
+
+
+class CustomFabricKey(FabricKeyGenCCFF):
+    """
+    Extending `FabricKeyGenCCFF`
+    """
+
+    def create_fabric_key(self, pattern=None):
+        """
+        Create fabric key command
+        """
+        super().create_fabric_key(pattern)
+
+
+def main():
+    """
+    Main method to execute function
+    """
+    with open(f"{PICKLE_DIR}/{PROJ_NAME}_fpgagridgen.pickle", "rb") as file_ptr:
+        fpga = pickle.load(file_ptr)
+    fabric_key = CustomFabricKey(fpga)
+
+    fabric_key.create_fabric_key(FABRIC_KEY_PATTERN)
+    filename = os.path.join(SVG_DIR, f"{PROJ_NAME}_CCFF_Chain.svg")
+    fabric_key.render_svg(filename=filename)
+
+    fabric_filename = os.path.join(TASK_DIR_NAME, "flow_inputs", "fabric_key.xml")
+    fabric_key.save_fabric_key(filename=fabric_filename)
+
+    try:
+        bitstream_dist_file = glob(f"{RELEASE_DIR}/*_verilog/XML/*_distribution.xml")[0]
+        fabric_key.read_bistream_distribution(bitstream_dist_file)
+        fabric_key.validate_key(
+            skip_missing_checks=False, skip_extra_instance_checks=False
+        )
+        bit_stat = fabric_key.bitstream_stats()
+        max_bits = max(bit_stat.values())
+        for region, bitstream in bit_stat.items():
+            print(f"{region:10s}  ", end="")
+            print("█" * round(100 * (bitstream / max_bits)), end="")
+            print(f"  {bitstream/max_bits:.1%} [{bitstream:>6d}]")
+    except IndexError:
+        logger.warning("bitstream_dist_file not found skipping validation")
+
+if __name__ == "__main__":
+    main()

SOFA_A/CommonFiles/restructure_fabric_sofa_a.py

@@ -0,0 +1,308 @@
+"""
+Restructuring for castor
+Template : restructure_fabric.py [openfpga-physical]
+Author: Ganesh Gore
+
+Stages for tiling
+
+- *_raw_floorplan
+- *_original_floorplan
+- *_pre_tile floorplan
+- *_final_floorplan
+
+"""
+import gzip
+import json
+import logging
+import os
+import pickle
+import re
+import shutil
+import sys
+import time
+import xml.etree.ElementTree as ET
+from collections import OrderedDict
+from copy import deepcopy
+from fnmatch import fnmatch
+from glob import glob
+from itertools import chain
+from pathlib import Path
+
+import spydrnet as sdn
+import yaml
+from spydrnet_physical.util import (
+    ConnectPointList,
+    FloorPlanViz,
+    FPGAGridGen,
+    OpenFPGA,
+    Tile02,
+    get_names,
+    initial_hetero_placement,
+)
+from spydrnet_physical.util.shell import launch_shell
+from svgwrite.container import Group
+
+logger = logging.getLogger("spydrnet_logs")
+sdn.enable_file_logging(LOG_LEVEL="INFO", filename="restructuring")
+
+
+# Constants Decalartion Section
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+PROP = "VERILOG.InlineConstraints"
+
+LAYOUT = os.environ.get("LAYOUT")
+PROJ_NAME = os.environ.get("PROJ_NAME")
+TASK_DIR_NAME = os.environ.get("TASK_DIR_NAME")
+VERILOG_DIRECTORY = os.environ.get("VERILOG_PROJ_DIR")
+FPGA_WIDTH = int(os.environ.get("FPGA_SIZE_X"))
+FPGA_HEIGHT = int(os.environ.get("FPGA_SIZE_Y"))
+RELEASE_DIR = os.environ["RELEASE_DIRECTORY"]
+SVG_DIR = f"{RELEASE_DIR}/svg/"
+PICKLE_DIR = f"{RELEASE_DIR}/pickle/"
+XML_DIR = f"{RELEASE_DIR}/xml"
+
+CBX_COLOR = "#d9d9f3"
+CBY_COLOR = "#a8d0db"
+SB_COLOR = "#ceefe4"
+GRID_COLOR = "#ddd0b1"
+
+GLOBAL_SCALE = 1000
+SC_HEIGHT = 480
+CPP = 96
+SC_GRID = SC_HEIGHT * CPP
+
+ADDITIONAL_STYLES = ""
+STYLE_SHEET = """
+    symbol {mix-blend-mode: difference;}
+    symbol[id*='grid_dsp'] * {fill:#70AE98;}
+    symbol[id*='grid_io'] * {fill:#e6a210;}
+    symbol[id*='grid_bram'] * {fill:#BC85C3;}
+    .over_util {fill:#b22222 !important}
+    text{font-family: Lato; font-style: italic; font-size: 3500px;}
+    rect.highlight_box { fill:none; stroke-width:40; stroke:green;}
+    text.highlight_box { font-size:500px; font-weight:800; fill:red}
+    line {stroke-width:20px !important;}
+"""
+
+mapping = {}
+script_start_time = time.time()
+
+# %%
+# Main method to perform restructuring
+#
+
+
+def main():
+    """
+    Main method
+    """
+    global ADDITIONAL_STYLES
+
+    Path(f"{RELEASE_DIR}/post_synth").mkdir(parents=True, exist_ok=True)
+    Path(f"{RELEASE_DIR}/rpts/pre_pnr").mkdir(parents=True, exist_ok=True)
+    try:
+        VPR_ARCH_FILE = glob((f"{TASK_DIR_NAME}/arch/*vpr*.xml"))[0]
+    except IndexError:
+        logger.exception(
+            "Arch file not found  ['%s/arch/*vpr*.xml']", TASK_DIR_NAME)
+        sys.exit()
+    source_files = glob(f"{VERILOG_DIRECTORY}/SRCSynth/*.v")
+    source_files += glob(f"{VERILOG_DIRECTORY}/SRCSynth/*/*.v")
+
+    for file in source_files:
+        logger.debug("Reading file: %s", file)
+    fpga = OpenFPGA(grid=(FPGA_WIDTH, FPGA_HEIGHT), verilog_files=source_files)
+    fpga.netlist.name = PROJ_NAME
+    print_time_elpased("Finished netlist parsing")
+
+    # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+    Path(SVG_DIR).mkdir(parents=True, exist_ok=True)
+    Path(PICKLE_DIR).mkdir(parents=True, exist_ok=True)
+
+    # Read eaternal area information
+    filename = f"{RELEASE_DIR}/post_synth/fpga_top_module_area.rpt"
+    if os.path.isfile(filename):
+        fpga.annotate_area_information(filename, skipline=1)
+
+    # sump top level port information
+    filename = f"{RELEASE_DIR}/post_synth/top_instances_ports.txt"
+    dump_top_definition_ports(fpga, rpt_file=filename)
+
+    # Visualize Floorplan
+    fpga_grid = FPGAGridGen(
+        design_name=PROJ_NAME, layout=LAYOUT, arch_file=VPR_ARCH_FILE, release_root=None
+    )
+    fpga_grid.enumerate_grid()
+    fpga.load_grid(fpga_grid)
+
+    fpga.register_placement_creator(
+        initial_hetero_placement,
+        areaFile={},
+    )
+    fpga.merge_all_grid_ios()
+    fpga.remove_direct_interc()
+
+    fpga.placement_creator.CPP = CPP
+    fpga.placement_creator.SC_HEIGHT = SC_HEIGHT
+    fpga.placement_creator.SC_GRID = CPP * SC_HEIGHT
+    top = fpga.top_module
+
+    WSmall, HSmall = fpga.fpga_size
+    W, H = fpga.fpga_size
+
+    # ==========================================================================
+    with open(r'shapes.yaml', 'r', encoding="UTF-8") as file:
+        m = yaml.safe_load(file)
+    # ==========================================================================
+    fpga.placement_creator.update_shaping_param(m)
+    fpga.placement_creator.derive_sb_paramters()
+    auto_shaped_modules = fpga.placement_creator.create_shapes(
+        w_override=WSmall, h_override=HSmall, shape_all=True)
+    shapes = fpga.placement_creator.module_shapes
+
+    print(auto_shaped_modules)
+    for each in auto_shaped_modules:
+        if "cbx" in each:
+            if "__0_" in each:
+                shapes[each] = deepcopy(shapes["cbx_1__0_"])
+            elif f"__{HSmall}_" in each:
+                shapes[each] = deepcopy(shapes[f"cbx_1__{HSmall}_"])
+            else:
+                shapes[each] = deepcopy(shapes["cbx_1__1_"])
+        if "cby" in each:
+            if "_0__" in each:
+                shapes[each] = deepcopy(shapes["cby_0__1_"])
+            elif f"_{WSmall}__" in each:
+                shapes[each] = deepcopy(shapes[f"cby_{WSmall}__1_"])
+            else:
+                shapes[each] = deepcopy(shapes["cby_1__1_"])
+        if "sb" in each:
+            if f"__{HSmall}_" in each:
+                shapes[each] = deepcopy(shapes[f"sb_1__{HSmall}_"])
+            else:
+                shapes[each] = deepcopy(shapes["sb_1__1_"])
+        if "grid" in each:
+            shapes[each] = deepcopy(shapes["grid_clb"])
+
+    fpga.create_placement()
+    # fpga.update_module_label()
+
+    fpga.save_shaping_data(
+        "*",
+        scale=1 / GLOBAL_SCALE,
+        filename=f"{RELEASE_DIR}/rpts/pre_pnr/shaping.txt",
+    )
+
+    filename = SVG_DIR + f"{PROJ_NAME}_raw_floorplan.svg"
+    save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET)
+
+    # Adding Narrow channels
+    # %%
+    # **Adding margin**
+    #
+    for module in shapes:
+        if "grid_" in module:
+            shapes[module]["POINTS"][0] -= 16
+            shapes[module]["POINTS"][1] -= 2
+            shapes[module]["PLACEMENT"][0] += 8
+            shapes[module]["PLACEMENT"][1] += 1
+
+    for module in shapes:
+        if "cbx_" in module:
+            shapes[module]["POINTS"][0] -= 16
+            shapes[module]["PLACEMENT"][0] += 8
+
+    for module in shapes:
+        if "cby_" in module:
+            shapes[module]["POINTS"][1] -= 2
+            shapes[module]["PLACEMENT"][1] += 1
+
+    fpga.create_placement()
+
+    filename = SVG_DIR + f"{PROJ_NAME}_pre_tile_floorplan.svg"
+    save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET)
+
+    # Create tiles
+    fpga.register_tile_generator(Tile02)
+    fpga.create_tiles()
+    save_netlist(fpga)
+
+    filename = SVG_DIR + f"{PROJ_NAME}_floorplan.svg"
+    save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET)
+    # pickle.dump(
+    #     dwg, open(f"{PICKLE_DIR}/{PROJ_NAME}_floorplaned.pickle", "wb"))
+    logger.info("Saved floorplan in %s", filename)
+    # save_netlist_outline(fpga)
+
+def save_tiling_floorplan(fpga: OpenFPGA, filename: str, STYLE_SHEET=None):
+    """
+    Save currnt tiling strategy to SVG file
+    """
+    fp = FloorPlanViz(fpga.top_module)
+    fp.compose(skip_connections=True, skip_pins=True)
+    fp.custom_style_sheet = STYLE_SHEET
+    dwg = fp.get_svg()
+    dwg.add(fpga.placement_creator.design_grid.render_grid(return_group=True))
+
+    pattern = dwg.pattern(size=(4 * CPP, 2 * SC_HEIGHT), patternUnits="userSpaceOnUse")
+    pattern.add(dwg.circle(center=(2, 2), r=1, fill="black"))
+    pattern.add(dwg.circle(center=(2, SC_HEIGHT + 2), r=1, fill="red"))
+    dwg.defs.add(pattern)
+    dwg.defs.elements[0].elements[0].attribs["fill"] = pattern.get_funciri()
+    dwg.saveas(filename, pretty=True, indent=4)
+
+def save_netlist(fpga: OpenFPGA):
+    """
+    Save OpenFPGA netlist
+    """
+    base_dir = (VERILOG_DIRECTORY, "SRC")
+
+    shutil.rmtree(
+        os.path.join(*base_dir),
+        ignore_errors=True,
+    )
+    Path(os.path.join(*base_dir)).mkdir(parents=True, exist_ok=True)
+    options = {
+        "skip_constraints": True,
+        "sort_cables": True,
+        "sort_print": True,
+        "sort_instances": True,
+        "sort_ports": True,
+    }
+    fpga.save_netlist("logical_tile*", os.path.join(*base_dir, "submodules"), **options)
+    fpga.save_netlist("*tile*", os.path.join(*base_dir, "tile"), **options)
+    fpga.save_netlist("fpga_core", os.path.join(*base_dir), **options)
+    fpga.save_netlist("fpga_top", os.path.join(*base_dir), **options)
+    fpga.save_netlist("[!BUFF][!TIE][!DFQ]*", os.path.join(*base_dir, "submodules"), write_blackbox=False, **options)
+    include_file = os.path.join(*base_dir, "fabric_netlists.v")
+    fpga.write_include_file(include_file)
+
+def dump_top_definition_ports(fpga: OpenFPGA, rpt_file, pattern=None):
+    """
+    Create top level port
+    """
+    portmap = OrderedDict()
+    instances = {t.name: t for t in fpga.top_module.get_definitions()}
+    instances = OrderedDict(sorted(instances.items(), reverse=True))
+    for def_name, defs in instances.items():
+        if "ASSIGN" in def_name:
+            continue
+        if def_name.startswith("const"):
+            continue
+        portmap[def_name] = sorted([f"{port.size:04d}_{port.direction:5s},{port.name}" for port in defs.get_ports("*")])
+        if pattern:
+            portmap[def_name] = list(filter(pattern, portmap[def_name]))
+
+    json.dump(portmap, open(rpt_file, "w", encoding="UTF-8"), indent=4)
+
+
+def print_time_elpased(msg):
+    """ Prints runtime since previous call to this function """
+    global script_start_time
+    script_start_time_new = time.time()
+    logger.info("[%8.2d] %s", (script_start_time_new - script_start_time), msg)
+    script_start_time = script_start_time_new
+
+
+if __name__ == "__main__":
+    main()

SOFA_A/CommonFiles/sofa_netlist_synth_script.sh

@@ -0,0 +1,5 @@
+#! /usr/bin/env bash
+
+echo "Running netlist synthesis script"
+rm -rf ${VERILOG_PROJ_DIR}/SRCSynth/
+cp -r ${VERILOG_PROJ_DIR}/SRCLint/  ${VERILOG_PROJ_DIR}/SRCSynth/

SOFA_A/FPGA88_SOFA_A/.spydrnet

@@ -0,0 +1 @@
+spydrnet_physical

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/CustomModules/custom_module.txt

@@ -0,0 +1 @@
+# Dummy file to list all custom modules used in this project

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/arch/vpr_arch.xml

@@ -46,7 +46,7 @@
   <tiles>
     <!-- Top-side has 1 I/O per tile -->
     <tile name="io_top" area="0">
-      <sub_tile name="io_top" capacity="8">
+      <sub_tile name="io_top" capacity="4">
         <equivalent_sites>
           <site pb_type="io"/>
         </equivalent_sites>
@@ -60,7 +60,7 @@
     </tile>
     <!-- Right-side has 1 I/O per tile -->
     <tile name="io_right" area="0">
-      <sub_tile name="io_right" capacity="8">
+      <sub_tile name="io_right" capacity="4">
         <equivalent_sites>
           <site pb_type="io"/>
         </equivalent_sites>
@@ -74,7 +74,7 @@
     </tile>
     <!-- Bottom-side has 9 I/O per tile -->
     <tile name="io_bottom" area="0">
-      <sub_tile name="io_bottom" capacity="9">
+      <sub_tile name="io_bottom" capacity="4">
         <equivalent_sites>
           <site pb_type="io"/>
         </equivalent_sites>
@@ -88,7 +88,7 @@
     </tile>
     <!-- Left-side has 1 I/O per tile -->
     <tile name="io_left" area="0">
-      <sub_tile name="io_left" capacity="1">
+      <sub_tile name="io_left" capacity="4">
         <equivalent_sites>
           <site pb_type="io"/>
         </equivalent_sites>
@@ -174,6 +174,16 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
+    <fixed_layout name="FPGA88" width="10" height="10">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <row type="io_top" starty="H-1" priority="100"/>
+      <row type="io_bottom" starty="0" priority="100"/>
+      <col type="io_left" startx="0" priority="100"/>
+      <col type="io_right" startx="W-1" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
     <fixed_layout name="12x12" width="14" height="14">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <row type="io_top" starty="H-1" priority="100"/>

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_benchmarks.conf

@@ -22,7 +22,7 @@ openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
 openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
-openfpga_vpr_device_layout=12x12
+openfpga_vpr_device_layout=FPGA88
 openfpga_vpr_route_chan_width=60
 
 [ARCHITECTURES]

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_generation.conf

@@ -21,7 +21,7 @@ openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
 openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
-openfpga_vpr_device_layout=12x12
+openfpga_vpr_device_layout=FPGA88
 openfpga_vpr_route_chan_width=60
 
 [ARCHITECTURES]

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_simulation.conf

@@ -22,7 +22,7 @@ openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
 openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
-openfpga_vpr_device_layout=12x12
+openfpga_vpr_device_layout=FPGA88
 openfpga_vpr_route_chan_width=60
 
 [ARCHITECTURES]

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/flow_inputs/fabric_key.xml

@@ -0,0 +1,326 @@
+<?xml version="1.0" ?>
+<fabric_key>
+  <region id="0">
+    <key id="0" alias="grid_io_left_0__1_"/>
+    <key id="1" alias="grid_io_left_0__2_"/>
+    <key id="2" alias="grid_io_left_0__3_"/>
+    <key id="3" alias="grid_io_left_0__4_"/>
+    <key id="4" alias="grid_io_left_0__5_"/>
+    <key id="5" alias="grid_io_left_0__6_"/>
+    <key id="6" alias="grid_io_left_0__7_"/>
+    <key id="7" alias="grid_io_left_0__8_"/>
+    <key id="8" alias="sb_0__8_"/>
+    <key id="9" alias="cby_0__8_"/>
+    <key id="10" alias="sb_0__7_"/>
+    <key id="11" alias="cby_0__7_"/>
+    <key id="12" alias="sb_0__6_"/>
+    <key id="13" alias="cby_0__6_"/>
+    <key id="14" alias="sb_0__5_"/>
+    <key id="15" alias="cby_0__5_"/>
+    <key id="16" alias="sb_0__4_"/>
+    <key id="17" alias="cby_0__4_"/>
+    <key id="18" alias="sb_0__3_"/>
+    <key id="19" alias="cby_0__3_"/>
+    <key id="20" alias="sb_0__2_"/>
+    <key id="21" alias="cby_0__2_"/>
+    <key id="22" alias="sb_0__1_"/>
+    <key id="23" alias="cby_0__1_"/>
+    <key id="24" alias="sb_0__0_"/>
+    <key id="25" alias="grid_io_bottom_1__0_"/>
+    <key id="26" alias="cbx_1__0_"/>
+    <key id="27" alias="grid_clb_1__1_"/>
+    <key id="28" alias="cbx_1__1_"/>
+    <key id="29" alias="grid_clb_1__2_"/>
+    <key id="30" alias="cbx_1__2_"/>
+    <key id="31" alias="grid_clb_1__3_"/>
+    <key id="32" alias="cbx_1__3_"/>
+    <key id="33" alias="grid_clb_1__4_"/>
+    <key id="34" alias="cbx_1__4_"/>
+    <key id="35" alias="grid_clb_1__5_"/>
+    <key id="36" alias="cbx_1__5_"/>
+    <key id="37" alias="grid_clb_1__6_"/>
+    <key id="38" alias="cbx_1__6_"/>
+    <key id="39" alias="grid_clb_1__7_"/>
+    <key id="40" alias="cbx_1__7_"/>
+    <key id="41" alias="grid_clb_1__8_"/>
+    <key id="42" alias="cbx_1__8_"/>
+    <key id="43" alias="grid_io_top_1__9_"/>
+    <key id="44" alias="sb_1__8_"/>
+    <key id="45" alias="cby_1__8_"/>
+    <key id="46" alias="sb_1__7_"/>
+    <key id="47" alias="cby_1__7_"/>
+    <key id="48" alias="sb_1__6_"/>
+    <key id="49" alias="cby_1__6_"/>
+    <key id="50" alias="sb_1__5_"/>
+    <key id="51" alias="cby_1__5_"/>
+    <key id="52" alias="sb_1__4_"/>
+    <key id="53" alias="cby_1__4_"/>
+    <key id="54" alias="sb_1__3_"/>
+    <key id="55" alias="cby_1__3_"/>
+    <key id="56" alias="sb_1__2_"/>
+    <key id="57" alias="cby_1__2_"/>
+    <key id="58" alias="sb_1__1_"/>
+    <key id="59" alias="cby_1__1_"/>
+    <key id="60" alias="sb_1__0_"/>
+    <key id="61" alias="grid_io_bottom_2__0_"/>
+    <key id="62" alias="cbx_2__0_"/>
+    <key id="63" alias="grid_clb_2__1_"/>
+    <key id="64" alias="cbx_2__1_"/>
+    <key id="65" alias="grid_clb_2__2_"/>
+    <key id="66" alias="cbx_2__2_"/>
+    <key id="67" alias="grid_clb_2__3_"/>
+    <key id="68" alias="cbx_2__3_"/>
+    <key id="69" alias="grid_clb_2__4_"/>
+    <key id="70" alias="cbx_2__4_"/>
+    <key id="71" alias="grid_clb_2__5_"/>
+    <key id="72" alias="cbx_2__5_"/>
+    <key id="73" alias="grid_clb_2__6_"/>
+    <key id="74" alias="cbx_2__6_"/>
+    <key id="75" alias="grid_clb_2__7_"/>
+    <key id="76" alias="cbx_2__7_"/>
+    <key id="77" alias="grid_clb_2__8_"/>
+    <key id="78" alias="cbx_2__8_"/>
+    <key id="79" alias="grid_io_top_2__9_"/>
+    <key id="80" alias="sb_2__8_"/>
+    <key id="81" alias="cby_2__8_"/>
+    <key id="82" alias="sb_2__7_"/>
+    <key id="83" alias="cby_2__7_"/>
+    <key id="84" alias="sb_2__6_"/>
+    <key id="85" alias="cby_2__6_"/>
+    <key id="86" alias="sb_2__5_"/>
+    <key id="87" alias="cby_2__5_"/>
+    <key id="88" alias="sb_2__4_"/>
+    <key id="89" alias="cby_2__4_"/>
+    <key id="90" alias="sb_2__3_"/>
+    <key id="91" alias="cby_2__3_"/>
+    <key id="92" alias="sb_2__2_"/>
+    <key id="93" alias="cby_2__2_"/>
+    <key id="94" alias="sb_2__1_"/>
+    <key id="95" alias="cby_2__1_"/>
+    <key id="96" alias="sb_2__0_"/>
+    <key id="97" alias="grid_io_bottom_3__0_"/>
+    <key id="98" alias="cbx_3__0_"/>
+    <key id="99" alias="grid_clb_3__1_"/>
+    <key id="100" alias="cbx_3__1_"/>
+    <key id="101" alias="grid_clb_3__2_"/>
+    <key id="102" alias="cbx_3__2_"/>
+    <key id="103" alias="grid_clb_3__3_"/>
+    <key id="104" alias="cbx_3__3_"/>
+    <key id="105" alias="grid_clb_3__4_"/>
+    <key id="106" alias="cbx_3__4_"/>
+    <key id="107" alias="grid_clb_3__5_"/>
+    <key id="108" alias="cbx_3__5_"/>
+    <key id="109" alias="grid_clb_3__6_"/>
+    <key id="110" alias="cbx_3__6_"/>
+    <key id="111" alias="grid_clb_3__7_"/>
+    <key id="112" alias="cbx_3__7_"/>
+    <key id="113" alias="grid_clb_3__8_"/>
+    <key id="114" alias="cbx_3__8_"/>
+    <key id="115" alias="grid_io_top_3__9_"/>
+    <key id="116" alias="sb_3__8_"/>
+    <key id="117" alias="cby_3__8_"/>
+    <key id="118" alias="sb_3__7_"/>
+    <key id="119" alias="cby_3__7_"/>
+    <key id="120" alias="sb_3__6_"/>
+    <key id="121" alias="cby_3__6_"/>
+    <key id="122" alias="sb_3__5_"/>
+    <key id="123" alias="cby_3__5_"/>
+    <key id="124" alias="sb_3__4_"/>
+    <key id="125" alias="cby_3__4_"/>
+    <key id="126" alias="sb_3__3_"/>
+    <key id="127" alias="cby_3__3_"/>
+    <key id="128" alias="sb_3__2_"/>
+    <key id="129" alias="cby_3__2_"/>
+    <key id="130" alias="sb_3__1_"/>
+    <key id="131" alias="cby_3__1_"/>
+    <key id="132" alias="sb_3__0_"/>
+    <key id="133" alias="grid_io_bottom_4__0_"/>
+    <key id="134" alias="cbx_4__0_"/>
+    <key id="135" alias="grid_clb_4__1_"/>
+    <key id="136" alias="cbx_4__1_"/>
+    <key id="137" alias="grid_clb_4__2_"/>
+    <key id="138" alias="cbx_4__2_"/>
+    <key id="139" alias="grid_clb_4__3_"/>
+    <key id="140" alias="cbx_4__3_"/>
+    <key id="141" alias="grid_clb_4__4_"/>
+    <key id="142" alias="cbx_4__4_"/>
+    <key id="143" alias="grid_clb_4__5_"/>
+    <key id="144" alias="cbx_4__5_"/>
+    <key id="145" alias="grid_clb_4__6_"/>
+    <key id="146" alias="cbx_4__6_"/>
+    <key id="147" alias="grid_clb_4__7_"/>
+    <key id="148" alias="cbx_4__7_"/>
+    <key id="149" alias="grid_clb_4__8_"/>
+    <key id="150" alias="cbx_4__8_"/>
+    <key id="151" alias="grid_io_top_4__9_"/>
+    <key id="152" alias="sb_4__8_"/>
+    <key id="153" alias="cby_4__8_"/>
+    <key id="154" alias="sb_4__7_"/>
+    <key id="155" alias="cby_4__7_"/>
+    <key id="156" alias="sb_4__6_"/>
+    <key id="157" alias="cby_4__6_"/>
+    <key id="158" alias="sb_4__5_"/>
+    <key id="159" alias="cby_4__5_"/>
+    <key id="160" alias="sb_4__4_"/>
+    <key id="161" alias="cby_4__4_"/>
+    <key id="162" alias="sb_4__3_"/>
+    <key id="163" alias="cby_4__3_"/>
+    <key id="164" alias="sb_4__2_"/>
+    <key id="165" alias="cby_4__2_"/>
+    <key id="166" alias="sb_4__1_"/>
+    <key id="167" alias="cby_4__1_"/>
+    <key id="168" alias="sb_4__0_"/>
+    <key id="169" alias="grid_io_bottom_5__0_"/>
+    <key id="170" alias="cbx_5__0_"/>
+    <key id="171" alias="grid_clb_5__1_"/>
+    <key id="172" alias="cbx_5__1_"/>
+    <key id="173" alias="grid_clb_5__2_"/>
+    <key id="174" alias="cbx_5__2_"/>
+    <key id="175" alias="grid_clb_5__3_"/>
+    <key id="176" alias="cbx_5__3_"/>
+    <key id="177" alias="grid_clb_5__4_"/>
+    <key id="178" alias="cbx_5__4_"/>
+    <key id="179" alias="grid_clb_5__5_"/>
+    <key id="180" alias="cbx_5__5_"/>
+    <key id="181" alias="grid_clb_5__6_"/>
+    <key id="182" alias="cbx_5__6_"/>
+    <key id="183" alias="grid_clb_5__7_"/>
+    <key id="184" alias="cbx_5__7_"/>
+    <key id="185" alias="grid_clb_5__8_"/>
+    <key id="186" alias="cbx_5__8_"/>
+    <key id="187" alias="grid_io_top_5__9_"/>
+    <key id="188" alias="sb_5__8_"/>
+    <key id="189" alias="cby_5__8_"/>
+    <key id="190" alias="sb_5__7_"/>
+    <key id="191" alias="cby_5__7_"/>
+    <key id="192" alias="sb_5__6_"/>
+    <key id="193" alias="cby_5__6_"/>
+    <key id="194" alias="sb_5__5_"/>
+    <key id="195" alias="cby_5__5_"/>
+    <key id="196" alias="sb_5__4_"/>
+    <key id="197" alias="cby_5__4_"/>
+    <key id="198" alias="sb_5__3_"/>
+    <key id="199" alias="cby_5__3_"/>
+    <key id="200" alias="sb_5__2_"/>
+    <key id="201" alias="cby_5__2_"/>
+    <key id="202" alias="sb_5__1_"/>
+    <key id="203" alias="cby_5__1_"/>
+    <key id="204" alias="sb_5__0_"/>
+    <key id="205" alias="grid_io_bottom_6__0_"/>
+    <key id="206" alias="cbx_6__0_"/>
+    <key id="207" alias="grid_clb_6__1_"/>
+    <key id="208" alias="cbx_6__1_"/>
+    <key id="209" alias="grid_clb_6__2_"/>
+    <key id="210" alias="cbx_6__2_"/>
+    <key id="211" alias="grid_clb_6__3_"/>
+    <key id="212" alias="cbx_6__3_"/>
+    <key id="213" alias="grid_clb_6__4_"/>
+    <key id="214" alias="cbx_6__4_"/>
+    <key id="215" alias="grid_clb_6__5_"/>
+    <key id="216" alias="cbx_6__5_"/>
+    <key id="217" alias="grid_clb_6__6_"/>
+    <key id="218" alias="cbx_6__6_"/>
+    <key id="219" alias="grid_clb_6__7_"/>
+    <key id="220" alias="cbx_6__7_"/>
+    <key id="221" alias="grid_clb_6__8_"/>
+    <key id="222" alias="cbx_6__8_"/>
+    <key id="223" alias="grid_io_top_6__9_"/>
+    <key id="224" alias="sb_6__8_"/>
+    <key id="225" alias="cby_6__8_"/>
+    <key id="226" alias="sb_6__7_"/>
+    <key id="227" alias="cby_6__7_"/>
+    <key id="228" alias="sb_6__6_"/>
+    <key id="229" alias="cby_6__6_"/>
+    <key id="230" alias="sb_6__5_"/>
+    <key id="231" alias="cby_6__5_"/>
+    <key id="232" alias="sb_6__4_"/>
+    <key id="233" alias="cby_6__4_"/>
+    <key id="234" alias="sb_6__3_"/>
+    <key id="235" alias="cby_6__3_"/>
+    <key id="236" alias="sb_6__2_"/>
+    <key id="237" alias="cby_6__2_"/>
+    <key id="238" alias="sb_6__1_"/>
+    <key id="239" alias="cby_6__1_"/>
+    <key id="240" alias="sb_6__0_"/>
+    <key id="241" alias="grid_io_bottom_7__0_"/>
+    <key id="242" alias="cbx_7__0_"/>
+    <key id="243" alias="grid_clb_7__1_"/>
+    <key id="244" alias="cbx_7__1_"/>
+    <key id="245" alias="grid_clb_7__2_"/>
+    <key id="246" alias="cbx_7__2_"/>
+    <key id="247" alias="grid_clb_7__3_"/>
+    <key id="248" alias="cbx_7__3_"/>
+    <key id="249" alias="grid_clb_7__4_"/>
+    <key id="250" alias="cbx_7__4_"/>
+    <key id="251" alias="grid_clb_7__5_"/>
+    <key id="252" alias="cbx_7__5_"/>
+    <key id="253" alias="grid_clb_7__6_"/>
+    <key id="254" alias="cbx_7__6_"/>
+    <key id="255" alias="grid_clb_7__7_"/>
+    <key id="256" alias="cbx_7__7_"/>
+    <key id="257" alias="grid_clb_7__8_"/>
+    <key id="258" alias="cbx_7__8_"/>
+    <key id="259" alias="grid_io_top_7__9_"/>
+    <key id="260" alias="sb_7__8_"/>
+    <key id="261" alias="cby_7__8_"/>
+    <key id="262" alias="sb_7__7_"/>
+    <key id="263" alias="cby_7__7_"/>
+    <key id="264" alias="sb_7__6_"/>
+    <key id="265" alias="cby_7__6_"/>
+    <key id="266" alias="sb_7__5_"/>
+    <key id="267" alias="cby_7__5_"/>
+    <key id="268" alias="sb_7__4_"/>
+    <key id="269" alias="cby_7__4_"/>
+    <key id="270" alias="sb_7__3_"/>
+    <key id="271" alias="cby_7__3_"/>
+    <key id="272" alias="sb_7__2_"/>
+    <key id="273" alias="cby_7__2_"/>
+    <key id="274" alias="sb_7__1_"/>
+    <key id="275" alias="cby_7__1_"/>
+    <key id="276" alias="sb_7__0_"/>
+    <key id="277" alias="grid_io_bottom_8__0_"/>
+    <key id="278" alias="cbx_8__0_"/>
+    <key id="279" alias="grid_clb_8__1_"/>
+    <key id="280" alias="cbx_8__1_"/>
+    <key id="281" alias="grid_clb_8__2_"/>
+    <key id="282" alias="cbx_8__2_"/>
+    <key id="283" alias="grid_clb_8__3_"/>
+    <key id="284" alias="cbx_8__3_"/>
+    <key id="285" alias="grid_clb_8__4_"/>
+    <key id="286" alias="cbx_8__4_"/>
+    <key id="287" alias="grid_clb_8__5_"/>
+    <key id="288" alias="cbx_8__5_"/>
+    <key id="289" alias="grid_clb_8__6_"/>
+    <key id="290" alias="cbx_8__6_"/>
+    <key id="291" alias="grid_clb_8__7_"/>
+    <key id="292" alias="cbx_8__7_"/>
+    <key id="293" alias="grid_clb_8__8_"/>
+    <key id="294" alias="cbx_8__8_"/>
+    <key id="295" alias="grid_io_top_8__9_"/>
+    <key id="296" alias="sb_8__8_"/>
+    <key id="297" alias="cby_8__8_"/>
+    <key id="298" alias="sb_8__7_"/>
+    <key id="299" alias="cby_8__7_"/>
+    <key id="300" alias="sb_8__6_"/>
+    <key id="301" alias="cby_8__6_"/>
+    <key id="302" alias="sb_8__5_"/>
+    <key id="303" alias="cby_8__5_"/>
+    <key id="304" alias="sb_8__4_"/>
+    <key id="305" alias="cby_8__4_"/>
+    <key id="306" alias="sb_8__3_"/>
+    <key id="307" alias="cby_8__3_"/>
+    <key id="308" alias="sb_8__2_"/>
+    <key id="309" alias="cby_8__2_"/>
+    <key id="310" alias="sb_8__1_"/>
+    <key id="311" alias="cby_8__1_"/>
+    <key id="312" alias="sb_8__0_"/>
+    <key id="313" alias="grid_io_right_9__1_"/>
+    <key id="314" alias="grid_io_right_9__2_"/>
+    <key id="315" alias="grid_io_right_9__3_"/>
+    <key id="316" alias="grid_io_right_9__4_"/>
+    <key id="317" alias="grid_io_right_9__5_"/>
+    <key id="318" alias="grid_io_right_9__6_"/>
+    <key id="319" alias="grid_io_right_9__7_"/>
+    <key id="320" alias="grid_io_right_9__8_"/>
+  </region>
+</fabric_key>

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_fabric.openfpga

@@ -1,6 +1,12 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \
+  --clock_modeling ideal \
+  --device ${OPENFPGA_VPR_DEVICE_LAYOUT} \
+  --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} \
+  --absorb_buffer_luts off \
+  --write_rr_graph rr_graph_out.xml \
+  --skip_sync_clustering_and_routing_results on
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
@@ -33,7 +39,8 @@ write_fabric_hierarchy --file ./fabric_hierarchy.txt
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
 # Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
+repack
+# --verbose
 
 # Build the bitstream
 #  - Output the fabric-independent bitstream to a file
@@ -49,28 +56,4 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
 #  - Enable the use of explicit port mapping in Verilog netlist
 write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
 
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here
-write_pnr_sdc --file ./SDC
-
-# Write SDC to disable timing for configure ports
-write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file ./SDC_analysis
-
-# Finish and exit OpenFPGA
 exit
-
-# Note :
-# To run verification at the end of the flow maintain source in ./SRC directory

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fabric_netlists.v

@@ -0,0 +1,84 @@
+`include "./SRC/fpga_top.v"
+`include "./SRC/submodules/EMBEDDED_IO_HD.v"
+`include "./SRC/submodules/EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.v"
+`include "./SRC/submodules/cbx_1__0_.v"
+`include "./SRC/submodules/cbx_1__0__old.v"
+`include "./SRC/submodules/cbx_1__1_.v"
+`include "./SRC/submodules/cbx_1__8_.v"
+`include "./SRC/submodules/cbx_1__8__old.v"
+`include "./SRC/submodules/cby_0__1_.v"
+`include "./SRC/submodules/cby_0__1__old.v"
+`include "./SRC/submodules/cby_1__1_.v"
+`include "./SRC/submodules/cby_8__1_.v"
+`include "./SRC/submodules/cby_8__1__old.v"
+`include "./SRC/submodules/const0.v"
+`include "./SRC/submodules/const1.v"
+`include "./SRC/submodules/direct_interc.v"
+`include "./SRC/submodules/frac_lut4.v"
+`include "./SRC/submodules/frac_lut4_mux.v"
+`include "./SRC/submodules/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.v"
+`include "./SRC/submodules/grid_clb.v"
+`include "./SRC/submodules/grid_io_bottom_bottom.v"
+`include "./SRC/submodules/grid_io_left_left.v"
+`include "./SRC/submodules/grid_io_right_right.v"
+`include "./SRC/submodules/grid_io_top_top.v"
+`include "./SRC/submodules/logical_tile_clb_mode_clb_.v"
+`include "./SRC/submodules/logical_tile_clb_mode_default__fle.v"
+`include "./SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric.v"
+`include "./SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v"
+`include "./SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v"
+`include "./SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v"
+`include "./SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v"
+`include "./SRC/submodules/logical_tile_io_mode_io_.v"
+`include "./SRC/submodules/logical_tile_io_mode_physical__iopad.v"
+`include "./SRC/submodules/mux_tree_size2.v"
+`include "./SRC/submodules/mux_tree_size2_mem.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size10.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size10_mem.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size11.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size11_mem.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size12.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size12_mem.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size2.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size2_mem.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size3.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size3_mem.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size4.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size4_mem.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size5.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size5_mem.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size6.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size6_mem.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size7.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size7_mem.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size8.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size8_mem.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size9.v"
+`include "./SRC/submodules/mux_tree_tapbuf_size9_mem.v"
+`include "./SRC/submodules/sb_0__0_.v"
+`include "./SRC/submodules/sb_0__1_.v"
+`include "./SRC/submodules/sb_0__8_.v"
+`include "./SRC/submodules/sb_1__0_.v"
+`include "./SRC/submodules/sb_1__1_.v"
+`include "./SRC/submodules/sb_1__8_.v"
+`include "./SRC/submodules/sb_8__0_.v"
+`include "./SRC/submodules/sb_8__1_.v"
+`include "./SRC/submodules/sb_8__8_.v"
+`include "./SRC/submodules/sky130_fd_sc_hd__buf_2.v"
+`include "./SRC/submodules/sky130_fd_sc_hd__buf_4.v"
+`include "./SRC/submodules/sky130_fd_sc_hd__dfrtp_1.v"
+`include "./SRC/submodules/sky130_fd_sc_hd__inv_1.v"
+`include "./SRC/submodules/sky130_fd_sc_hd__inv_2.v"
+`include "./SRC/submodules/sky130_fd_sc_hd__mux2_1.v"
+`include "./SRC/submodules/sky130_fd_sc_hd__mux2_1_wrapper.v"
+`include "./SRC/submodules/sky130_fd_sc_hd__or2_1.v"
+`include "./SRC/submodules/sky130_fd_sc_hd__sdfrtp_1.v"
+`include "./SRC/tile/bottom_left_tile.v"
+`include "./SRC/tile/bottom_right_tile.v"
+`include "./SRC/tile/bottom_tile.v"
+`include "./SRC/tile/left_tile.v"
+`include "./SRC/tile/right_tile.v"
+`include "./SRC/tile/tile.v"
+`include "./SRC/tile/top_left_tile.v"
+`include "./SRC/tile/top_right_tile.v"
+`include "./SRC/tile/top_tile.v"

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD.v

@@ -0,0 +1,31 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module EMBEDDED_IO_HD
+(
+    FPGA_DIR,
+    FPGA_OUT,
+    IO_ISOL_N,
+    SOC_IN,
+    FPGA_IN,
+    SOC_DIR,
+    SOC_OUT
+);
+
+    input FPGA_DIR;
+    input FPGA_OUT;
+    input IO_ISOL_N;
+    input SOC_IN;
+    output FPGA_IN;
+    output SOC_DIR;
+    output SOC_OUT;
+
+    wire FPGA_DIR;
+    wire FPGA_IN;
+    wire FPGA_OUT;
+    wire IO_ISOL_N;
+    wire SOC_DIR;
+    wire SOC_IN;
+    wire SOC_OUT;
+
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.v

@@ -0,0 +1,33 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem
+(
+    ccff_head,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    mem_out
+);
+
+    input ccff_head;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output mem_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire mem_out;
+    wire pReset;
+    wire prog_clk;
+
+assign ccff_tail = mem_out;
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
+    (
+        .CLK(prog_clk),
+        .D(ccff_head),
+        .RESET_B(pReset),
+        .Q(mem_out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0_.v

@@ -0,0 +1,102 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module cbx_1__0_
+(
+    IO_ISOL_N,
+    ccff_head,
+    ccff_head_0,
+    chanx_left_in,
+    chanx_right_in,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    ccff_tail_0,
+    chanx_left_out,
+    chanx_right_out,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    top_width_0_height_0_subtile_0__pin_inpad_0_,
+    top_width_0_height_0_subtile_1__pin_inpad_0_,
+    top_width_0_height_0_subtile_2__pin_inpad_0_,
+    top_width_0_height_0_subtile_3__pin_inpad_0_
+);
+
+    input IO_ISOL_N;
+    input ccff_head;
+    input ccff_head_0;
+    input [29:0]chanx_left_in;
+    input [29:0]chanx_right_in;
+    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output ccff_tail_0;
+    output [29:0]chanx_left_out;
+    output [29:0]chanx_right_out;
+    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output top_width_0_height_0_subtile_0__pin_inpad_0_;
+    output top_width_0_height_0_subtile_1__pin_inpad_0_;
+    output top_width_0_height_0_subtile_2__pin_inpad_0_;
+    output top_width_0_height_0_subtile_3__pin_inpad_0_;
+
+    wire IO_ISOL_N;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
+    wire ccff_head;
+    wire ccff_head_0;
+    wire ccff_tail;
+    wire ccff_tail_0;
+    wire [29:0]chanx_left_in;
+    wire [29:0]chanx_left_out;
+    wire [29:0]chanx_right_in;
+    wire [29:0]chanx_right_out;
+    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire pReset;
+    wire prog_clk;
+    wire top_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire top_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire top_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire top_width_0_height_0_subtile_3__pin_inpad_0_;
+
+    cbx_1__0__old cbx_8__0_
+    (
+        .ccff_head(ccff_head_0),
+        .chanx_left_in(chanx_left_in),
+        .chanx_right_in(chanx_right_in),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
+        .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
+        .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
+        .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_),
+        .ccff_tail(ccff_tail_0),
+        .chanx_left_out(chanx_left_out),
+        .chanx_right_out(chanx_right_out)
+    );
+    grid_io_bottom_bottom grid_io_bottom_bottom_8__0_
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(ccff_head),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .top_width_0_height_0_subtile_0__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
+        .top_width_0_height_0_subtile_1__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
+        .top_width_0_height_0_subtile_2__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
+        .top_width_0_height_0_subtile_3__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_),
+        .ccff_tail(ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
+        .top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_),
+        .top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_),
+        .top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_),
+        .top_width_0_height_0_subtile_3__pin_inpad_0_(top_width_0_height_0_subtile_3__pin_inpad_0_)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0__old.v

@@ -0,0 +1,177 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module cbx_1__0__old
+(
+    ccff_head,
+    chanx_left_in,
+    chanx_right_in,
+    pReset,
+    prog_clk,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_,
+    bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_,
+    bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_,
+    bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_,
+    ccff_tail,
+    chanx_left_out,
+    chanx_right_out
+);
+
+    input ccff_head;
+    input [0:29]chanx_left_in;
+    input [0:29]chanx_right_in;
+    input pReset;
+    input prog_clk;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
+    output bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
+    output bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
+    output bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
+    output ccff_tail;
+    output [0:29]chanx_left_out;
+    output [0:29]chanx_right_out;
+
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:29]chanx_left_in;
+    wire [0:29]chanx_left_out;
+    wire [0:29]chanx_right_in;
+    wire [0:29]chanx_right_out;
+    wire [0:3]mux_top_ipin_0_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_1_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_2_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_3_undriven_sram_inv;
+    wire [0:3]mux_tree_tapbuf_size12_0_sram;
+    wire [0:3]mux_tree_tapbuf_size12_1_sram;
+    wire [0:3]mux_tree_tapbuf_size12_2_sram;
+    wire [0:3]mux_tree_tapbuf_size12_3_sram;
+    wire mux_tree_tapbuf_size12_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_2_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+
+assign chanx_right_out[0] = chanx_left_in[0];
+assign chanx_right_out[1] = chanx_left_in[1];
+assign chanx_right_out[10] = chanx_left_in[10];
+assign chanx_right_out[11] = chanx_left_in[11];
+assign chanx_right_out[12] = chanx_left_in[12];
+assign chanx_right_out[13] = chanx_left_in[13];
+assign chanx_right_out[14] = chanx_left_in[14];
+assign chanx_right_out[15] = chanx_left_in[15];
+assign chanx_right_out[16] = chanx_left_in[16];
+assign chanx_right_out[17] = chanx_left_in[17];
+assign chanx_right_out[18] = chanx_left_in[18];
+assign chanx_right_out[19] = chanx_left_in[19];
+assign chanx_right_out[2] = chanx_left_in[2];
+assign chanx_right_out[20] = chanx_left_in[20];
+assign chanx_right_out[21] = chanx_left_in[21];
+assign chanx_right_out[22] = chanx_left_in[22];
+assign chanx_right_out[23] = chanx_left_in[23];
+assign chanx_right_out[24] = chanx_left_in[24];
+assign chanx_right_out[25] = chanx_left_in[25];
+assign chanx_right_out[26] = chanx_left_in[26];
+assign chanx_right_out[27] = chanx_left_in[27];
+assign chanx_right_out[28] = chanx_left_in[28];
+assign chanx_right_out[29] = chanx_left_in[29];
+assign chanx_right_out[3] = chanx_left_in[3];
+assign chanx_left_out[0] = chanx_right_in[0];
+assign chanx_left_out[1] = chanx_right_in[1];
+assign chanx_left_out[2] = chanx_right_in[2];
+assign chanx_left_out[3] = chanx_right_in[3];
+assign chanx_left_out[4] = chanx_right_in[4];
+assign chanx_left_out[5] = chanx_right_in[5];
+assign chanx_left_out[6] = chanx_right_in[6];
+assign chanx_left_out[7] = chanx_right_in[7];
+assign chanx_left_out[8] = chanx_right_in[8];
+assign chanx_left_out[9] = chanx_right_in[9];
+assign chanx_right_out[4] = chanx_left_in[4];
+assign chanx_left_out[10] = chanx_right_in[10];
+assign chanx_left_out[11] = chanx_right_in[11];
+assign chanx_left_out[12] = chanx_right_in[12];
+assign chanx_left_out[13] = chanx_right_in[13];
+assign chanx_left_out[14] = chanx_right_in[14];
+assign chanx_left_out[15] = chanx_right_in[15];
+assign chanx_left_out[16] = chanx_right_in[16];
+assign chanx_left_out[17] = chanx_right_in[17];
+assign chanx_left_out[18] = chanx_right_in[18];
+assign chanx_left_out[19] = chanx_right_in[19];
+assign chanx_right_out[5] = chanx_left_in[5];
+assign chanx_left_out[20] = chanx_right_in[20];
+assign chanx_left_out[21] = chanx_right_in[21];
+assign chanx_left_out[22] = chanx_right_in[22];
+assign chanx_left_out[23] = chanx_right_in[23];
+assign chanx_left_out[24] = chanx_right_in[24];
+assign chanx_left_out[25] = chanx_right_in[25];
+assign chanx_left_out[26] = chanx_right_in[26];
+assign chanx_left_out[27] = chanx_right_in[27];
+assign chanx_left_out[28] = chanx_right_in[28];
+assign chanx_left_out[29] = chanx_right_in[29];
+assign chanx_right_out[6] = chanx_left_in[6];
+assign chanx_right_out[7] = chanx_left_in[7];
+assign chanx_right_out[8] = chanx_left_in[8];
+assign chanx_right_out[9] = chanx_left_in[9];
+    mux_tree_tapbuf_size12_mem mem_top_ipin_0
+    (
+        .ccff_head(ccff_head),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_0_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_1
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_1_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_2
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_2_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_3
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_3_sram)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_0
+    (
+        .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}),
+        .sram(mux_tree_tapbuf_size12_0_sram),
+        .sram_inv(mux_top_ipin_0_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_1
+    (
+        .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}),
+        .sram(mux_tree_tapbuf_size12_1_sram),
+        .sram_inv(mux_top_ipin_1_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_2
+    (
+        .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}),
+        .sram(mux_tree_tapbuf_size12_2_sram),
+        .sram_inv(mux_top_ipin_2_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_3
+    (
+        .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21], chanx_left_in[27], chanx_right_in[27]}),
+        .sram(mux_tree_tapbuf_size12_3_sram),
+        .sram_inv(mux_top_ipin_3_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__1_.v

@@ -0,0 +1,429 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module cbx_1__1_
+(
+    ccff_head,
+    chanx_left_in,
+    chanx_right_in,
+    pReset,
+    prog_clk,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_,
+    ccff_tail,
+    chanx_left_out,
+    chanx_right_out
+);
+
+    input ccff_head;
+    input [0:29]chanx_left_in;
+    input [0:29]chanx_right_in;
+    input pReset;
+    input prog_clk;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
+    output ccff_tail;
+    output [0:29]chanx_left_out;
+    output [0:29]chanx_right_out;
+
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:29]chanx_left_in;
+    wire [0:29]chanx_left_out;
+    wire [0:29]chanx_right_in;
+    wire [0:29]chanx_right_out;
+    wire [0:3]mux_top_ipin_0_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_10_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_11_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_12_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_13_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_14_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_15_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_1_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_2_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_3_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_4_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_5_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_6_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_7_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_8_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_9_undriven_sram_inv;
+    wire [0:3]mux_tree_tapbuf_size10_0_sram;
+    wire [0:3]mux_tree_tapbuf_size10_1_sram;
+    wire [0:3]mux_tree_tapbuf_size10_2_sram;
+    wire [0:3]mux_tree_tapbuf_size10_3_sram;
+    wire [0:3]mux_tree_tapbuf_size10_4_sram;
+    wire [0:3]mux_tree_tapbuf_size10_5_sram;
+    wire [0:3]mux_tree_tapbuf_size10_6_sram;
+    wire [0:3]mux_tree_tapbuf_size10_7_sram;
+    wire mux_tree_tapbuf_size10_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_6_ccff_tail;
+    wire [0:3]mux_tree_tapbuf_size12_0_sram;
+    wire [0:3]mux_tree_tapbuf_size12_1_sram;
+    wire [0:3]mux_tree_tapbuf_size12_2_sram;
+    wire [0:3]mux_tree_tapbuf_size12_3_sram;
+    wire [0:3]mux_tree_tapbuf_size12_4_sram;
+    wire [0:3]mux_tree_tapbuf_size12_5_sram;
+    wire [0:3]mux_tree_tapbuf_size12_6_sram;
+    wire [0:3]mux_tree_tapbuf_size12_7_sram;
+    wire mux_tree_tapbuf_size12_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_6_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_7_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+
+assign chanx_right_out[0] = chanx_left_in[0];
+assign chanx_right_out[1] = chanx_left_in[1];
+assign chanx_right_out[10] = chanx_left_in[10];
+assign chanx_right_out[11] = chanx_left_in[11];
+assign chanx_right_out[12] = chanx_left_in[12];
+assign chanx_right_out[13] = chanx_left_in[13];
+assign chanx_right_out[14] = chanx_left_in[14];
+assign chanx_right_out[15] = chanx_left_in[15];
+assign chanx_right_out[16] = chanx_left_in[16];
+assign chanx_right_out[17] = chanx_left_in[17];
+assign chanx_right_out[18] = chanx_left_in[18];
+assign chanx_right_out[19] = chanx_left_in[19];
+assign chanx_right_out[2] = chanx_left_in[2];
+assign chanx_right_out[20] = chanx_left_in[20];
+assign chanx_right_out[21] = chanx_left_in[21];
+assign chanx_right_out[22] = chanx_left_in[22];
+assign chanx_right_out[23] = chanx_left_in[23];
+assign chanx_right_out[24] = chanx_left_in[24];
+assign chanx_right_out[25] = chanx_left_in[25];
+assign chanx_right_out[26] = chanx_left_in[26];
+assign chanx_right_out[27] = chanx_left_in[27];
+assign chanx_right_out[28] = chanx_left_in[28];
+assign chanx_right_out[29] = chanx_left_in[29];
+assign chanx_right_out[3] = chanx_left_in[3];
+assign chanx_left_out[0] = chanx_right_in[0];
+assign chanx_left_out[1] = chanx_right_in[1];
+assign chanx_left_out[2] = chanx_right_in[2];
+assign chanx_left_out[3] = chanx_right_in[3];
+assign chanx_left_out[4] = chanx_right_in[4];
+assign chanx_left_out[5] = chanx_right_in[5];
+assign chanx_left_out[6] = chanx_right_in[6];
+assign chanx_left_out[7] = chanx_right_in[7];
+assign chanx_left_out[8] = chanx_right_in[8];
+assign chanx_left_out[9] = chanx_right_in[9];
+assign chanx_right_out[4] = chanx_left_in[4];
+assign chanx_left_out[10] = chanx_right_in[10];
+assign chanx_left_out[11] = chanx_right_in[11];
+assign chanx_left_out[12] = chanx_right_in[12];
+assign chanx_left_out[13] = chanx_right_in[13];
+assign chanx_left_out[14] = chanx_right_in[14];
+assign chanx_left_out[15] = chanx_right_in[15];
+assign chanx_left_out[16] = chanx_right_in[16];
+assign chanx_left_out[17] = chanx_right_in[17];
+assign chanx_left_out[18] = chanx_right_in[18];
+assign chanx_left_out[19] = chanx_right_in[19];
+assign chanx_right_out[5] = chanx_left_in[5];
+assign chanx_left_out[20] = chanx_right_in[20];
+assign chanx_left_out[21] = chanx_right_in[21];
+assign chanx_left_out[22] = chanx_right_in[22];
+assign chanx_left_out[23] = chanx_right_in[23];
+assign chanx_left_out[24] = chanx_right_in[24];
+assign chanx_left_out[25] = chanx_right_in[25];
+assign chanx_left_out[26] = chanx_right_in[26];
+assign chanx_left_out[27] = chanx_right_in[27];
+assign chanx_left_out[28] = chanx_right_in[28];
+assign chanx_left_out[29] = chanx_right_in[29];
+assign chanx_right_out[6] = chanx_left_in[6];
+assign chanx_right_out[7] = chanx_left_in[7];
+assign chanx_right_out[8] = chanx_left_in[8];
+assign chanx_right_out[9] = chanx_left_in[9];
+    mux_tree_tapbuf_size12_mem mem_top_ipin_0
+    (
+        .ccff_head(ccff_head),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_0_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_1
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_0_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_10
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_5_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_11
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_5_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_12
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_6_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_13
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_6_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_14
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_7_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_15
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_7_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_2
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_1_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_3
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_1_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_4
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_2_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_5
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_2_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_6
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_3_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_7
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_3_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_8
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_4_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_9
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_4_sram)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_0
+    (
+        .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}),
+        .sram(mux_tree_tapbuf_size12_0_sram),
+        .sram_inv(mux_top_ipin_0_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_1
+    (
+        .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[16], chanx_right_in[16], chanx_left_in[25], chanx_right_in[25]}),
+        .sram(mux_tree_tapbuf_size10_0_sram),
+        .sram_inv(mux_top_ipin_1_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_10
+    (
+        .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}),
+        .sram(mux_tree_tapbuf_size12_5_sram),
+        .sram_inv(mux_top_ipin_10_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_11
+    (
+        .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17], chanx_left_in[26], chanx_right_in[26]}),
+        .sram(mux_tree_tapbuf_size10_5_sram),
+        .sram_inv(mux_top_ipin_11_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_12
+    (
+        .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}),
+        .sram(mux_tree_tapbuf_size12_6_sram),
+        .sram_inv(mux_top_ipin_12_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_13
+    (
+        .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[28], chanx_right_in[28]}),
+        .sram(mux_tree_tapbuf_size10_6_sram),
+        .sram_inv(mux_top_ipin_13_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_14
+    (
+        .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}),
+        .sram(mux_tree_tapbuf_size12_7_sram),
+        .sram_inv(mux_top_ipin_14_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_15
+    (
+        .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21]}),
+        .sram(mux_tree_tapbuf_size10_7_sram),
+        .sram_inv(mux_top_ipin_15_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_2
+    (
+        .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}),
+        .sram(mux_tree_tapbuf_size12_1_sram),
+        .sram_inv(mux_top_ipin_2_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_3
+    (
+        .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[18], chanx_right_in[18], chanx_left_in[27], chanx_right_in[27]}),
+        .sram(mux_tree_tapbuf_size10_1_sram),
+        .sram_inv(mux_top_ipin_3_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_4
+    (
+        .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}),
+        .sram(mux_tree_tapbuf_size12_2_sram),
+        .sram_inv(mux_top_ipin_4_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_5
+    (
+        .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[20], chanx_right_in[20], chanx_left_in[29], chanx_right_in[29]}),
+        .sram(mux_tree_tapbuf_size10_2_sram),
+        .sram_inv(mux_top_ipin_5_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_6
+    (
+        .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}),
+        .sram(mux_tree_tapbuf_size12_3_sram),
+        .sram_inv(mux_top_ipin_6_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_7
+    (
+        .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[22], chanx_right_in[22]}),
+        .sram(mux_tree_tapbuf_size10_3_sram),
+        .sram_inv(mux_top_ipin_7_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_8
+    (
+        .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}),
+        .sram(mux_tree_tapbuf_size12_4_sram),
+        .sram_inv(mux_top_ipin_8_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_9
+    (
+        .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[24], chanx_right_in[24]}),
+        .sram(mux_tree_tapbuf_size10_4_sram),
+        .sram_inv(mux_top_ipin_9_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8_.v

@@ -0,0 +1,161 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module cbx_1__8_
+(
+    IO_ISOL_N,
+    ccff_head_0,
+    chanx_left_in,
+    chanx_right_in,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
+    pReset,
+    prog_clk,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_,
+    bottom_width_0_height_0_subtile_0__pin_inpad_0_,
+    bottom_width_0_height_0_subtile_1__pin_inpad_0_,
+    bottom_width_0_height_0_subtile_2__pin_inpad_0_,
+    bottom_width_0_height_0_subtile_3__pin_inpad_0_,
+    ccff_tail,
+    chanx_left_out,
+    chanx_right_out,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT
+);
+
+    input IO_ISOL_N;
+    input ccff_head_0;
+    input [29:0]chanx_left_in;
+    input [29:0]chanx_right_in;
+    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    input pReset;
+    input prog_clk;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
+    output bottom_width_0_height_0_subtile_0__pin_inpad_0_;
+    output bottom_width_0_height_0_subtile_1__pin_inpad_0_;
+    output bottom_width_0_height_0_subtile_2__pin_inpad_0_;
+    output bottom_width_0_height_0_subtile_3__pin_inpad_0_;
+    output ccff_tail;
+    output [29:0]chanx_left_out;
+    output [29:0]chanx_right_out;
+    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+
+    wire IO_ISOL_N;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
+    wire bottom_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire bottom_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire bottom_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire bottom_width_0_height_0_subtile_3__pin_inpad_0_;
+    wire ccff_head_0;
+    wire ccff_tail;
+    wire ccff_tail_0;
+    wire [29:0]chanx_left_in;
+    wire [29:0]chanx_left_out;
+    wire [29:0]chanx_right_in;
+    wire [29:0]chanx_right_out;
+    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire pReset;
+    wire prog_clk;
+    wire top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
+    wire top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
+    wire top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
+    wire top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_;
+
+    cbx_1__8__old cbx_1__8_
+    (
+        .ccff_head(ccff_head_0),
+        .chanx_left_in(chanx_left_in),
+        .chanx_right_in(chanx_right_in),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_),
+        .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_),
+        .ccff_tail(ccff_tail_0),
+        .chanx_left_out(chanx_left_out),
+        .chanx_right_out(chanx_right_out),
+        .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
+        .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
+        .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
+        .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_)
+    );
+    grid_io_top_top grid_io_top_top_1__9_
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .bottom_width_0_height_0_subtile_0__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
+        .bottom_width_0_height_0_subtile_1__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
+        .bottom_width_0_height_0_subtile_2__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
+        .bottom_width_0_height_0_subtile_3__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_),
+        .ccff_head(ccff_tail_0),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .bottom_width_0_height_0_subtile_0__pin_inpad_0_(bottom_width_0_height_0_subtile_0__pin_inpad_0_),
+        .bottom_width_0_height_0_subtile_1__pin_inpad_0_(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
+        .bottom_width_0_height_0_subtile_2__pin_inpad_0_(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
+        .bottom_width_0_height_0_subtile_3__pin_inpad_0_(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
+        .ccff_tail(ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8__old.v

@@ -0,0 +1,513 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module cbx_1__8__old
+(
+    ccff_head,
+    chanx_left_in,
+    chanx_right_in,
+    pReset,
+    prog_clk,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_,
+    bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_,
+    ccff_tail,
+    chanx_left_out,
+    chanx_right_out,
+    top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_,
+    top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_,
+    top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_,
+    top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_
+);
+
+    input ccff_head;
+    input [0:29]chanx_left_in;
+    input [0:29]chanx_right_in;
+    input pReset;
+    input prog_clk;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_;
+    output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
+    output ccff_tail;
+    output [0:29]chanx_left_out;
+    output [0:29]chanx_right_out;
+    output top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
+    output top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
+    output top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
+    output top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_;
+
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_;
+    wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:29]chanx_left_in;
+    wire [0:29]chanx_left_out;
+    wire [0:29]chanx_right_in;
+    wire [0:29]chanx_right_out;
+    wire [0:3]mux_bottom_ipin_0_undriven_sram_inv;
+    wire [0:3]mux_bottom_ipin_1_undriven_sram_inv;
+    wire [0:3]mux_bottom_ipin_2_undriven_sram_inv;
+    wire [0:3]mux_bottom_ipin_3_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_0_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_10_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_11_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_12_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_13_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_14_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_15_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_1_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_2_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_3_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_4_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_5_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_6_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_7_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_8_undriven_sram_inv;
+    wire [0:3]mux_top_ipin_9_undriven_sram_inv;
+    wire [0:3]mux_tree_tapbuf_size10_0_sram;
+    wire [0:3]mux_tree_tapbuf_size10_1_sram;
+    wire [0:3]mux_tree_tapbuf_size10_2_sram;
+    wire [0:3]mux_tree_tapbuf_size10_3_sram;
+    wire [0:3]mux_tree_tapbuf_size10_4_sram;
+    wire [0:3]mux_tree_tapbuf_size10_5_sram;
+    wire [0:3]mux_tree_tapbuf_size10_6_sram;
+    wire [0:3]mux_tree_tapbuf_size10_7_sram;
+    wire mux_tree_tapbuf_size10_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_6_ccff_tail;
+    wire [0:3]mux_tree_tapbuf_size12_0_sram;
+    wire [0:3]mux_tree_tapbuf_size12_10_sram;
+    wire [0:3]mux_tree_tapbuf_size12_11_sram;
+    wire [0:3]mux_tree_tapbuf_size12_1_sram;
+    wire [0:3]mux_tree_tapbuf_size12_2_sram;
+    wire [0:3]mux_tree_tapbuf_size12_3_sram;
+    wire [0:3]mux_tree_tapbuf_size12_4_sram;
+    wire [0:3]mux_tree_tapbuf_size12_5_sram;
+    wire [0:3]mux_tree_tapbuf_size12_6_sram;
+    wire [0:3]mux_tree_tapbuf_size12_7_sram;
+    wire [0:3]mux_tree_tapbuf_size12_8_sram;
+    wire [0:3]mux_tree_tapbuf_size12_9_sram;
+    wire mux_tree_tapbuf_size12_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_10_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_11_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_6_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_7_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_8_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_9_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+    wire top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
+    wire top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
+    wire top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
+    wire top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_;
+
+assign chanx_right_out[0] = chanx_left_in[0];
+assign chanx_right_out[1] = chanx_left_in[1];
+assign chanx_right_out[10] = chanx_left_in[10];
+assign chanx_right_out[11] = chanx_left_in[11];
+assign chanx_right_out[12] = chanx_left_in[12];
+assign chanx_right_out[13] = chanx_left_in[13];
+assign chanx_right_out[14] = chanx_left_in[14];
+assign chanx_right_out[15] = chanx_left_in[15];
+assign chanx_right_out[16] = chanx_left_in[16];
+assign chanx_right_out[17] = chanx_left_in[17];
+assign chanx_right_out[18] = chanx_left_in[18];
+assign chanx_right_out[19] = chanx_left_in[19];
+assign chanx_right_out[2] = chanx_left_in[2];
+assign chanx_right_out[20] = chanx_left_in[20];
+assign chanx_right_out[21] = chanx_left_in[21];
+assign chanx_right_out[22] = chanx_left_in[22];
+assign chanx_right_out[23] = chanx_left_in[23];
+assign chanx_right_out[24] = chanx_left_in[24];
+assign chanx_right_out[25] = chanx_left_in[25];
+assign chanx_right_out[26] = chanx_left_in[26];
+assign chanx_right_out[27] = chanx_left_in[27];
+assign chanx_right_out[28] = chanx_left_in[28];
+assign chanx_right_out[29] = chanx_left_in[29];
+assign chanx_right_out[3] = chanx_left_in[3];
+assign chanx_left_out[0] = chanx_right_in[0];
+assign chanx_left_out[1] = chanx_right_in[1];
+assign chanx_left_out[2] = chanx_right_in[2];
+assign chanx_left_out[3] = chanx_right_in[3];
+assign chanx_left_out[4] = chanx_right_in[4];
+assign chanx_left_out[5] = chanx_right_in[5];
+assign chanx_left_out[6] = chanx_right_in[6];
+assign chanx_left_out[7] = chanx_right_in[7];
+assign chanx_left_out[8] = chanx_right_in[8];
+assign chanx_left_out[9] = chanx_right_in[9];
+assign chanx_right_out[4] = chanx_left_in[4];
+assign chanx_left_out[10] = chanx_right_in[10];
+assign chanx_left_out[11] = chanx_right_in[11];
+assign chanx_left_out[12] = chanx_right_in[12];
+assign chanx_left_out[13] = chanx_right_in[13];
+assign chanx_left_out[14] = chanx_right_in[14];
+assign chanx_left_out[15] = chanx_right_in[15];
+assign chanx_left_out[16] = chanx_right_in[16];
+assign chanx_left_out[17] = chanx_right_in[17];
+assign chanx_left_out[18] = chanx_right_in[18];
+assign chanx_left_out[19] = chanx_right_in[19];
+assign chanx_right_out[5] = chanx_left_in[5];
+assign chanx_left_out[20] = chanx_right_in[20];
+assign chanx_left_out[21] = chanx_right_in[21];
+assign chanx_left_out[22] = chanx_right_in[22];
+assign chanx_left_out[23] = chanx_right_in[23];
+assign chanx_left_out[24] = chanx_right_in[24];
+assign chanx_left_out[25] = chanx_right_in[25];
+assign chanx_left_out[26] = chanx_right_in[26];
+assign chanx_left_out[27] = chanx_right_in[27];
+assign chanx_left_out[28] = chanx_right_in[28];
+assign chanx_left_out[29] = chanx_right_in[29];
+assign chanx_right_out[6] = chanx_left_in[6];
+assign chanx_right_out[7] = chanx_left_in[7];
+assign chanx_right_out[8] = chanx_left_in[8];
+assign chanx_right_out[9] = chanx_left_in[9];
+    mux_tree_tapbuf_size12_mem mem_bottom_ipin_0
+    (
+        .ccff_head(ccff_head),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_0_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_bottom_ipin_1
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_1_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_bottom_ipin_2
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_2_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_bottom_ipin_3
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_3_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_0
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_4_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_1
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_0_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_10
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_9_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_11
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_5_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_12
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_10_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_13
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_6_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_14
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_11_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_15
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_7_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_2
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_5_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_3
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_1_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_4
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_6_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_5
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_2_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_6
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_7_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_7
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_3_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_top_ipin_8
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_8_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_top_ipin_9
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_4_sram)
+    );
+    mux_tree_tapbuf_size12 mux_bottom_ipin_0
+    (
+        .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}),
+        .sram(mux_tree_tapbuf_size12_0_sram),
+        .sram_inv(mux_bottom_ipin_0_undriven_sram_inv),
+        .out(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_)
+    );
+    mux_tree_tapbuf_size12 mux_bottom_ipin_1
+    (
+        .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}),
+        .sram(mux_tree_tapbuf_size12_1_sram),
+        .sram_inv(mux_bottom_ipin_1_undriven_sram_inv),
+        .out(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_)
+    );
+    mux_tree_tapbuf_size12 mux_bottom_ipin_2
+    (
+        .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}),
+        .sram(mux_tree_tapbuf_size12_2_sram),
+        .sram_inv(mux_bottom_ipin_2_undriven_sram_inv),
+        .out(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_)
+    );
+    mux_tree_tapbuf_size12 mux_bottom_ipin_3
+    (
+        .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21], chanx_left_in[27], chanx_right_in[27]}),
+        .sram(mux_tree_tapbuf_size12_3_sram),
+        .sram_inv(mux_bottom_ipin_3_undriven_sram_inv),
+        .out(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_0
+    (
+        .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}),
+        .sram(mux_tree_tapbuf_size12_4_sram),
+        .sram_inv(mux_top_ipin_0_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_1
+    (
+        .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[20], chanx_right_in[20], chanx_left_in[29], chanx_right_in[29]}),
+        .sram(mux_tree_tapbuf_size10_0_sram),
+        .sram_inv(mux_top_ipin_1_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_10
+    (
+        .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}),
+        .sram(mux_tree_tapbuf_size12_9_sram),
+        .sram_inv(mux_top_ipin_10_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_11
+    (
+        .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21]}),
+        .sram(mux_tree_tapbuf_size10_5_sram),
+        .sram_inv(mux_top_ipin_11_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_12
+    (
+        .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}),
+        .sram(mux_tree_tapbuf_size12_10_sram),
+        .sram_inv(mux_top_ipin_12_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_13
+    (
+        .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[17], chanx_right_in[17], chanx_left_in[23], chanx_right_in[23]}),
+        .sram(mux_tree_tapbuf_size10_6_sram),
+        .sram_inv(mux_top_ipin_13_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_14
+    (
+        .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}),
+        .sram(mux_tree_tapbuf_size12_11_sram),
+        .sram_inv(mux_top_ipin_14_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_15
+    (
+        .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}),
+        .sram(mux_tree_tapbuf_size10_7_sram),
+        .sram_inv(mux_top_ipin_15_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_2
+    (
+        .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}),
+        .sram(mux_tree_tapbuf_size12_5_sram),
+        .sram_inv(mux_top_ipin_2_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_3
+    (
+        .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[22], chanx_right_in[22]}),
+        .sram(mux_tree_tapbuf_size10_1_sram),
+        .sram_inv(mux_top_ipin_3_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_4
+    (
+        .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}),
+        .sram(mux_tree_tapbuf_size12_6_sram),
+        .sram_inv(mux_top_ipin_4_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_5
+    (
+        .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[24], chanx_right_in[24]}),
+        .sram(mux_tree_tapbuf_size10_2_sram),
+        .sram_inv(mux_top_ipin_5_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_6
+    (
+        .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}),
+        .sram(mux_tree_tapbuf_size12_7_sram),
+        .sram_inv(mux_top_ipin_6_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_7
+    (
+        .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17], chanx_left_in[26], chanx_right_in[26]}),
+        .sram(mux_tree_tapbuf_size10_3_sram),
+        .sram_inv(mux_top_ipin_7_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_top_ipin_8
+    (
+        .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}),
+        .sram(mux_tree_tapbuf_size12_8_sram),
+        .sram_inv(mux_top_ipin_8_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_)
+    );
+    mux_tree_tapbuf_size10 mux_top_ipin_9
+    (
+        .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[28], chanx_right_in[28]}),
+        .sram(mux_tree_tapbuf_size10_4_sram),
+        .sram_inv(mux_top_ipin_9_undriven_sram_inv),
+        .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1_.v

@@ -0,0 +1,97 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module cby_0__1_
+(
+    IO_ISOL_N,
+    ccff_head_0,
+    chany_bottom_in,
+    chany_top_in,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    chany_bottom_out,
+    chany_top_out,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    right_width_0_height_0_subtile_0__pin_inpad_0_,
+    right_width_0_height_0_subtile_1__pin_inpad_0_,
+    right_width_0_height_0_subtile_2__pin_inpad_0_,
+    right_width_0_height_0_subtile_3__pin_inpad_0_
+);
+
+    input IO_ISOL_N;
+    input ccff_head_0;
+    input [29:0]chany_bottom_in;
+    input [29:0]chany_top_in;
+    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [29:0]chany_bottom_out;
+    output [29:0]chany_top_out;
+    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output right_width_0_height_0_subtile_0__pin_inpad_0_;
+    output right_width_0_height_0_subtile_1__pin_inpad_0_;
+    output right_width_0_height_0_subtile_2__pin_inpad_0_;
+    output right_width_0_height_0_subtile_3__pin_inpad_0_;
+
+    wire IO_ISOL_N;
+    wire ccff_head_0;
+    wire ccff_tail;
+    wire ccff_tail_0;
+    wire [29:0]chany_bottom_in;
+    wire [29:0]chany_bottom_out;
+    wire [29:0]chany_top_in;
+    wire [29:0]chany_top_out;
+    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
+    wire left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_;
+    wire left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_;
+    wire left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
+    wire pReset;
+    wire prog_clk;
+    wire right_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire right_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire right_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire right_width_0_height_0_subtile_3__pin_inpad_0_;
+
+    cby_0__1__old cby_0__1_
+    (
+        .ccff_head(ccff_head_0),
+        .chany_bottom_in(chany_bottom_in),
+        .chany_top_in(chany_top_in),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail_0),
+        .chany_bottom_out(chany_bottom_out),
+        .chany_top_out(chany_top_out),
+        .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
+        .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
+        .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
+        .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_)
+    );
+    grid_io_left_left grid_io_left_left_0__1_
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(ccff_tail_0),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .right_width_0_height_0_subtile_0__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
+        .right_width_0_height_0_subtile_1__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
+        .right_width_0_height_0_subtile_2__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
+        .right_width_0_height_0_subtile_3__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_),
+        .ccff_tail(ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
+        .right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_),
+        .right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_),
+        .right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_),
+        .right_width_0_height_0_subtile_3__pin_inpad_0_(right_width_0_height_0_subtile_3__pin_inpad_0_)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1__old.v

@@ -0,0 +1,177 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module cby_0__1__old
+(
+    ccff_head,
+    chany_bottom_in,
+    chany_top_in,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    chany_bottom_out,
+    chany_top_out,
+    left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_,
+    left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_,
+    left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_,
+    left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_
+);
+
+    input ccff_head;
+    input [0:29]chany_bottom_in;
+    input [0:29]chany_top_in;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:29]chany_bottom_out;
+    output [0:29]chany_top_out;
+    output left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
+    output left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_;
+    output left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_;
+    output left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:29]chany_bottom_in;
+    wire [0:29]chany_bottom_out;
+    wire [0:29]chany_top_in;
+    wire [0:29]chany_top_out;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
+    wire left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_;
+    wire left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_;
+    wire left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
+    wire [0:3]mux_right_ipin_0_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_1_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_2_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_3_undriven_sram_inv;
+    wire [0:3]mux_tree_tapbuf_size12_0_sram;
+    wire [0:3]mux_tree_tapbuf_size12_1_sram;
+    wire [0:3]mux_tree_tapbuf_size12_2_sram;
+    wire [0:3]mux_tree_tapbuf_size12_3_sram;
+    wire mux_tree_tapbuf_size12_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_2_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+
+assign chany_top_out[0] = chany_bottom_in[0];
+assign chany_top_out[1] = chany_bottom_in[1];
+assign chany_top_out[10] = chany_bottom_in[10];
+assign chany_top_out[11] = chany_bottom_in[11];
+assign chany_top_out[12] = chany_bottom_in[12];
+assign chany_top_out[13] = chany_bottom_in[13];
+assign chany_top_out[14] = chany_bottom_in[14];
+assign chany_top_out[15] = chany_bottom_in[15];
+assign chany_top_out[16] = chany_bottom_in[16];
+assign chany_top_out[17] = chany_bottom_in[17];
+assign chany_top_out[18] = chany_bottom_in[18];
+assign chany_top_out[19] = chany_bottom_in[19];
+assign chany_top_out[2] = chany_bottom_in[2];
+assign chany_top_out[20] = chany_bottom_in[20];
+assign chany_top_out[21] = chany_bottom_in[21];
+assign chany_top_out[22] = chany_bottom_in[22];
+assign chany_top_out[23] = chany_bottom_in[23];
+assign chany_top_out[24] = chany_bottom_in[24];
+assign chany_top_out[25] = chany_bottom_in[25];
+assign chany_top_out[26] = chany_bottom_in[26];
+assign chany_top_out[27] = chany_bottom_in[27];
+assign chany_top_out[28] = chany_bottom_in[28];
+assign chany_top_out[29] = chany_bottom_in[29];
+assign chany_top_out[3] = chany_bottom_in[3];
+assign chany_bottom_out[0] = chany_top_in[0];
+assign chany_bottom_out[1] = chany_top_in[1];
+assign chany_bottom_out[2] = chany_top_in[2];
+assign chany_bottom_out[3] = chany_top_in[3];
+assign chany_bottom_out[4] = chany_top_in[4];
+assign chany_bottom_out[5] = chany_top_in[5];
+assign chany_bottom_out[6] = chany_top_in[6];
+assign chany_bottom_out[7] = chany_top_in[7];
+assign chany_bottom_out[8] = chany_top_in[8];
+assign chany_bottom_out[9] = chany_top_in[9];
+assign chany_top_out[4] = chany_bottom_in[4];
+assign chany_bottom_out[10] = chany_top_in[10];
+assign chany_bottom_out[11] = chany_top_in[11];
+assign chany_bottom_out[12] = chany_top_in[12];
+assign chany_bottom_out[13] = chany_top_in[13];
+assign chany_bottom_out[14] = chany_top_in[14];
+assign chany_bottom_out[15] = chany_top_in[15];
+assign chany_bottom_out[16] = chany_top_in[16];
+assign chany_bottom_out[17] = chany_top_in[17];
+assign chany_bottom_out[18] = chany_top_in[18];
+assign chany_bottom_out[19] = chany_top_in[19];
+assign chany_top_out[5] = chany_bottom_in[5];
+assign chany_bottom_out[20] = chany_top_in[20];
+assign chany_bottom_out[21] = chany_top_in[21];
+assign chany_bottom_out[22] = chany_top_in[22];
+assign chany_bottom_out[23] = chany_top_in[23];
+assign chany_bottom_out[24] = chany_top_in[24];
+assign chany_bottom_out[25] = chany_top_in[25];
+assign chany_bottom_out[26] = chany_top_in[26];
+assign chany_bottom_out[27] = chany_top_in[27];
+assign chany_bottom_out[28] = chany_top_in[28];
+assign chany_bottom_out[29] = chany_top_in[29];
+assign chany_top_out[6] = chany_bottom_in[6];
+assign chany_top_out[7] = chany_bottom_in[7];
+assign chany_top_out[8] = chany_bottom_in[8];
+assign chany_top_out[9] = chany_bottom_in[9];
+    mux_tree_tapbuf_size12_mem mem_right_ipin_0
+    (
+        .ccff_head(ccff_head),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_0_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_1
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_1_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_2
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_2_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_3
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_3_sram)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_0
+    (
+        .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
+        .sram(mux_tree_tapbuf_size12_0_sram),
+        .sram_inv(mux_right_ipin_0_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_1
+    (
+        .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}),
+        .sram(mux_tree_tapbuf_size12_1_sram),
+        .sram_inv(mux_right_ipin_1_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_2
+    (
+        .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}),
+        .sram(mux_tree_tapbuf_size12_2_sram),
+        .sram_inv(mux_right_ipin_2_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_3
+    (
+        .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21], chany_bottom_in[27], chany_top_in[27]}),
+        .sram(mux_tree_tapbuf_size12_3_sram),
+        .sram_inv(mux_right_ipin_3_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_1__1_.v

@@ -0,0 +1,429 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module cby_1__1_
+(
+    ccff_head,
+    chany_bottom_in,
+    chany_top_in,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    chany_bottom_out,
+    chany_top_out,
+    left_grid_right_width_0_height_0_subtile_0__pin_I4_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I4_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I5_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I5_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I6_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I6_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I7_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I7_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_
+);
+
+    input ccff_head;
+    input [0:29]chany_bottom_in;
+    input [0:29]chany_top_in;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:29]chany_bottom_out;
+    output [0:29]chany_top_out;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I5_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I5_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I6_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I6_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I7_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:29]chany_bottom_in;
+    wire [0:29]chany_bottom_out;
+    wire [0:29]chany_top_in;
+    wire [0:29]chany_top_out;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
+    wire [0:3]mux_right_ipin_0_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_10_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_11_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_12_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_13_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_14_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_15_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_1_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_2_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_3_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_4_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_5_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_6_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_7_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_8_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_9_undriven_sram_inv;
+    wire [0:3]mux_tree_tapbuf_size10_0_sram;
+    wire [0:3]mux_tree_tapbuf_size10_1_sram;
+    wire [0:3]mux_tree_tapbuf_size10_2_sram;
+    wire [0:3]mux_tree_tapbuf_size10_3_sram;
+    wire [0:3]mux_tree_tapbuf_size10_4_sram;
+    wire [0:3]mux_tree_tapbuf_size10_5_sram;
+    wire [0:3]mux_tree_tapbuf_size10_6_sram;
+    wire [0:3]mux_tree_tapbuf_size10_7_sram;
+    wire mux_tree_tapbuf_size10_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_6_ccff_tail;
+    wire [0:3]mux_tree_tapbuf_size12_0_sram;
+    wire [0:3]mux_tree_tapbuf_size12_1_sram;
+    wire [0:3]mux_tree_tapbuf_size12_2_sram;
+    wire [0:3]mux_tree_tapbuf_size12_3_sram;
+    wire [0:3]mux_tree_tapbuf_size12_4_sram;
+    wire [0:3]mux_tree_tapbuf_size12_5_sram;
+    wire [0:3]mux_tree_tapbuf_size12_6_sram;
+    wire [0:3]mux_tree_tapbuf_size12_7_sram;
+    wire mux_tree_tapbuf_size12_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_6_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_7_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+
+assign chany_top_out[0] = chany_bottom_in[0];
+assign chany_top_out[1] = chany_bottom_in[1];
+assign chany_top_out[10] = chany_bottom_in[10];
+assign chany_top_out[11] = chany_bottom_in[11];
+assign chany_top_out[12] = chany_bottom_in[12];
+assign chany_top_out[13] = chany_bottom_in[13];
+assign chany_top_out[14] = chany_bottom_in[14];
+assign chany_top_out[15] = chany_bottom_in[15];
+assign chany_top_out[16] = chany_bottom_in[16];
+assign chany_top_out[17] = chany_bottom_in[17];
+assign chany_top_out[18] = chany_bottom_in[18];
+assign chany_top_out[19] = chany_bottom_in[19];
+assign chany_top_out[2] = chany_bottom_in[2];
+assign chany_top_out[20] = chany_bottom_in[20];
+assign chany_top_out[21] = chany_bottom_in[21];
+assign chany_top_out[22] = chany_bottom_in[22];
+assign chany_top_out[23] = chany_bottom_in[23];
+assign chany_top_out[24] = chany_bottom_in[24];
+assign chany_top_out[25] = chany_bottom_in[25];
+assign chany_top_out[26] = chany_bottom_in[26];
+assign chany_top_out[27] = chany_bottom_in[27];
+assign chany_top_out[28] = chany_bottom_in[28];
+assign chany_top_out[29] = chany_bottom_in[29];
+assign chany_top_out[3] = chany_bottom_in[3];
+assign chany_bottom_out[0] = chany_top_in[0];
+assign chany_bottom_out[1] = chany_top_in[1];
+assign chany_bottom_out[2] = chany_top_in[2];
+assign chany_bottom_out[3] = chany_top_in[3];
+assign chany_bottom_out[4] = chany_top_in[4];
+assign chany_bottom_out[5] = chany_top_in[5];
+assign chany_bottom_out[6] = chany_top_in[6];
+assign chany_bottom_out[7] = chany_top_in[7];
+assign chany_bottom_out[8] = chany_top_in[8];
+assign chany_bottom_out[9] = chany_top_in[9];
+assign chany_top_out[4] = chany_bottom_in[4];
+assign chany_bottom_out[10] = chany_top_in[10];
+assign chany_bottom_out[11] = chany_top_in[11];
+assign chany_bottom_out[12] = chany_top_in[12];
+assign chany_bottom_out[13] = chany_top_in[13];
+assign chany_bottom_out[14] = chany_top_in[14];
+assign chany_bottom_out[15] = chany_top_in[15];
+assign chany_bottom_out[16] = chany_top_in[16];
+assign chany_bottom_out[17] = chany_top_in[17];
+assign chany_bottom_out[18] = chany_top_in[18];
+assign chany_bottom_out[19] = chany_top_in[19];
+assign chany_top_out[5] = chany_bottom_in[5];
+assign chany_bottom_out[20] = chany_top_in[20];
+assign chany_bottom_out[21] = chany_top_in[21];
+assign chany_bottom_out[22] = chany_top_in[22];
+assign chany_bottom_out[23] = chany_top_in[23];
+assign chany_bottom_out[24] = chany_top_in[24];
+assign chany_bottom_out[25] = chany_top_in[25];
+assign chany_bottom_out[26] = chany_top_in[26];
+assign chany_bottom_out[27] = chany_top_in[27];
+assign chany_bottom_out[28] = chany_top_in[28];
+assign chany_bottom_out[29] = chany_top_in[29];
+assign chany_top_out[6] = chany_bottom_in[6];
+assign chany_top_out[7] = chany_bottom_in[7];
+assign chany_top_out[8] = chany_bottom_in[8];
+assign chany_top_out[9] = chany_bottom_in[9];
+    mux_tree_tapbuf_size12_mem mem_right_ipin_0
+    (
+        .ccff_head(ccff_head),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_0_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_1
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_0_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_10
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_5_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_11
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_5_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_12
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_6_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_13
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_6_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_14
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_7_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_15
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_7_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_2
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_1_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_3
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_1_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_4
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_2_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_5
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_2_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_6
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_3_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_7
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_3_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_8
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_4_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_9
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_4_sram)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_0
+    (
+        .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
+        .sram(mux_tree_tapbuf_size12_0_sram),
+        .sram_inv(mux_right_ipin_0_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_1
+    (
+        .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[25], chany_top_in[25]}),
+        .sram(mux_tree_tapbuf_size10_0_sram),
+        .sram_inv(mux_right_ipin_1_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_10
+    (
+        .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}),
+        .sram(mux_tree_tapbuf_size12_5_sram),
+        .sram_inv(mux_right_ipin_10_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_11
+    (
+        .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[26], chany_top_in[26]}),
+        .sram(mux_tree_tapbuf_size10_5_sram),
+        .sram_inv(mux_right_ipin_11_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_12
+    (
+        .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
+        .sram(mux_tree_tapbuf_size12_6_sram),
+        .sram_inv(mux_right_ipin_12_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_13
+    (
+        .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[28], chany_top_in[28]}),
+        .sram(mux_tree_tapbuf_size10_6_sram),
+        .sram_inv(mux_right_ipin_13_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_14
+    (
+        .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}),
+        .sram(mux_tree_tapbuf_size12_7_sram),
+        .sram_inv(mux_right_ipin_14_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_15
+    (
+        .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21]}),
+        .sram(mux_tree_tapbuf_size10_7_sram),
+        .sram_inv(mux_right_ipin_15_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_2
+    (
+        .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}),
+        .sram(mux_tree_tapbuf_size12_1_sram),
+        .sram_inv(mux_right_ipin_2_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_3
+    (
+        .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[27], chany_top_in[27]}),
+        .sram(mux_tree_tapbuf_size10_1_sram),
+        .sram_inv(mux_right_ipin_3_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_4
+    (
+        .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}),
+        .sram(mux_tree_tapbuf_size12_2_sram),
+        .sram_inv(mux_right_ipin_4_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_5
+    (
+        .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[29], chany_top_in[29]}),
+        .sram(mux_tree_tapbuf_size10_2_sram),
+        .sram_inv(mux_right_ipin_5_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_6
+    (
+        .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
+        .sram(mux_tree_tapbuf_size12_3_sram),
+        .sram_inv(mux_right_ipin_6_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_7
+    (
+        .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[22], chany_top_in[22]}),
+        .sram(mux_tree_tapbuf_size10_3_sram),
+        .sram_inv(mux_right_ipin_7_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_8
+    (
+        .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}),
+        .sram(mux_tree_tapbuf_size12_4_sram),
+        .sram_inv(mux_right_ipin_8_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_9
+    (
+        .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[24], chany_top_in[24]}),
+        .sram(mux_tree_tapbuf_size10_4_sram),
+        .sram_inv(mux_right_ipin_9_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1_.v

@@ -0,0 +1,166 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module cby_8__1_
+(
+    IO_ISOL_N,
+    ccff_head,
+    ccff_head_0,
+    chany_bottom_in,
+    chany_top_in,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    ccff_tail_0,
+    chany_bottom_out,
+    chany_top_out,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    left_grid_right_width_0_height_0_subtile_0__pin_I4_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I4_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I5_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I5_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I6_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I6_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I7_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I7_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_,
+    left_width_0_height_0_subtile_0__pin_inpad_0_,
+    left_width_0_height_0_subtile_1__pin_inpad_0_,
+    left_width_0_height_0_subtile_2__pin_inpad_0_,
+    left_width_0_height_0_subtile_3__pin_inpad_0_
+);
+
+    input IO_ISOL_N;
+    input ccff_head;
+    input ccff_head_0;
+    input [29:0]chany_bottom_in;
+    input [29:0]chany_top_in;
+    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output ccff_tail_0;
+    output [29:0]chany_bottom_out;
+    output [29:0]chany_top_out;
+    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I5_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I5_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I6_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I6_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I7_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
+    output left_width_0_height_0_subtile_0__pin_inpad_0_;
+    output left_width_0_height_0_subtile_1__pin_inpad_0_;
+    output left_width_0_height_0_subtile_2__pin_inpad_0_;
+    output left_width_0_height_0_subtile_3__pin_inpad_0_;
+
+    wire IO_ISOL_N;
+    wire ccff_head;
+    wire ccff_head_0;
+    wire ccff_tail;
+    wire ccff_tail_0;
+    wire [29:0]chany_bottom_in;
+    wire [29:0]chany_bottom_out;
+    wire [29:0]chany_top_in;
+    wire [29:0]chany_top_out;
+    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
+    wire left_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire left_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire left_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire left_width_0_height_0_subtile_3__pin_inpad_0_;
+    wire pReset;
+    wire prog_clk;
+    wire right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
+    wire right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
+    wire right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
+    wire right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_;
+
+    cby_8__1__old cby_8__8_
+    (
+        .ccff_head(ccff_head_0),
+        .chany_bottom_in(chany_bottom_in),
+        .chany_top_in(chany_top_in),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail_0),
+        .chany_bottom_out(chany_bottom_out),
+        .chany_top_out(chany_top_out),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
+        .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
+        .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
+        .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
+        .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
+        .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_)
+    );
+    grid_io_right_right grid_io_right_right_9__8_
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(ccff_head),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
+        .left_width_0_height_0_subtile_0__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
+        .left_width_0_height_0_subtile_1__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
+        .left_width_0_height_0_subtile_2__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
+        .left_width_0_height_0_subtile_3__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
+        .left_width_0_height_0_subtile_0__pin_inpad_0_(left_width_0_height_0_subtile_0__pin_inpad_0_),
+        .left_width_0_height_0_subtile_1__pin_inpad_0_(left_width_0_height_0_subtile_1__pin_inpad_0_),
+        .left_width_0_height_0_subtile_2__pin_inpad_0_(left_width_0_height_0_subtile_2__pin_inpad_0_),
+        .left_width_0_height_0_subtile_3__pin_inpad_0_(left_width_0_height_0_subtile_3__pin_inpad_0_)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1__old.v

@@ -0,0 +1,513 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module cby_8__1__old
+(
+    ccff_head,
+    chany_bottom_in,
+    chany_top_in,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    chany_bottom_out,
+    chany_top_out,
+    left_grid_right_width_0_height_0_subtile_0__pin_I4_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I4_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I5_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I5_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I6_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I6_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I7_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I7_1_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_,
+    left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_,
+    right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_,
+    right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_,
+    right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_,
+    right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_
+);
+
+    input ccff_head;
+    input [0:29]chany_bottom_in;
+    input [0:29]chany_top_in;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:29]chany_bottom_out;
+    output [0:29]chany_top_out;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I5_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I5_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I6_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I6_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I7_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
+    output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
+    output right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
+    output right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
+    output right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
+    output right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:29]chany_bottom_in;
+    wire [0:29]chany_bottom_out;
+    wire [0:29]chany_top_in;
+    wire [0:29]chany_top_out;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
+    wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
+    wire [0:3]mux_left_ipin_0_undriven_sram_inv;
+    wire [0:3]mux_left_ipin_1_undriven_sram_inv;
+    wire [0:3]mux_left_ipin_2_undriven_sram_inv;
+    wire [0:3]mux_left_ipin_3_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_0_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_10_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_11_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_12_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_13_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_14_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_15_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_1_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_2_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_3_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_4_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_5_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_6_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_7_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_8_undriven_sram_inv;
+    wire [0:3]mux_right_ipin_9_undriven_sram_inv;
+    wire [0:3]mux_tree_tapbuf_size10_0_sram;
+    wire [0:3]mux_tree_tapbuf_size10_1_sram;
+    wire [0:3]mux_tree_tapbuf_size10_2_sram;
+    wire [0:3]mux_tree_tapbuf_size10_3_sram;
+    wire [0:3]mux_tree_tapbuf_size10_4_sram;
+    wire [0:3]mux_tree_tapbuf_size10_5_sram;
+    wire [0:3]mux_tree_tapbuf_size10_6_sram;
+    wire [0:3]mux_tree_tapbuf_size10_7_sram;
+    wire mux_tree_tapbuf_size10_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size10_mem_6_ccff_tail;
+    wire [0:3]mux_tree_tapbuf_size12_0_sram;
+    wire [0:3]mux_tree_tapbuf_size12_10_sram;
+    wire [0:3]mux_tree_tapbuf_size12_11_sram;
+    wire [0:3]mux_tree_tapbuf_size12_1_sram;
+    wire [0:3]mux_tree_tapbuf_size12_2_sram;
+    wire [0:3]mux_tree_tapbuf_size12_3_sram;
+    wire [0:3]mux_tree_tapbuf_size12_4_sram;
+    wire [0:3]mux_tree_tapbuf_size12_5_sram;
+    wire [0:3]mux_tree_tapbuf_size12_6_sram;
+    wire [0:3]mux_tree_tapbuf_size12_7_sram;
+    wire [0:3]mux_tree_tapbuf_size12_8_sram;
+    wire [0:3]mux_tree_tapbuf_size12_9_sram;
+    wire mux_tree_tapbuf_size12_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_10_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_11_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_6_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_7_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_8_ccff_tail;
+    wire mux_tree_tapbuf_size12_mem_9_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+    wire right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
+    wire right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
+    wire right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
+    wire right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_;
+
+assign chany_top_out[0] = chany_bottom_in[0];
+assign chany_top_out[1] = chany_bottom_in[1];
+assign chany_top_out[10] = chany_bottom_in[10];
+assign chany_top_out[11] = chany_bottom_in[11];
+assign chany_top_out[12] = chany_bottom_in[12];
+assign chany_top_out[13] = chany_bottom_in[13];
+assign chany_top_out[14] = chany_bottom_in[14];
+assign chany_top_out[15] = chany_bottom_in[15];
+assign chany_top_out[16] = chany_bottom_in[16];
+assign chany_top_out[17] = chany_bottom_in[17];
+assign chany_top_out[18] = chany_bottom_in[18];
+assign chany_top_out[19] = chany_bottom_in[19];
+assign chany_top_out[2] = chany_bottom_in[2];
+assign chany_top_out[20] = chany_bottom_in[20];
+assign chany_top_out[21] = chany_bottom_in[21];
+assign chany_top_out[22] = chany_bottom_in[22];
+assign chany_top_out[23] = chany_bottom_in[23];
+assign chany_top_out[24] = chany_bottom_in[24];
+assign chany_top_out[25] = chany_bottom_in[25];
+assign chany_top_out[26] = chany_bottom_in[26];
+assign chany_top_out[27] = chany_bottom_in[27];
+assign chany_top_out[28] = chany_bottom_in[28];
+assign chany_top_out[29] = chany_bottom_in[29];
+assign chany_top_out[3] = chany_bottom_in[3];
+assign chany_bottom_out[0] = chany_top_in[0];
+assign chany_bottom_out[1] = chany_top_in[1];
+assign chany_bottom_out[2] = chany_top_in[2];
+assign chany_bottom_out[3] = chany_top_in[3];
+assign chany_bottom_out[4] = chany_top_in[4];
+assign chany_bottom_out[5] = chany_top_in[5];
+assign chany_bottom_out[6] = chany_top_in[6];
+assign chany_bottom_out[7] = chany_top_in[7];
+assign chany_bottom_out[8] = chany_top_in[8];
+assign chany_bottom_out[9] = chany_top_in[9];
+assign chany_top_out[4] = chany_bottom_in[4];
+assign chany_bottom_out[10] = chany_top_in[10];
+assign chany_bottom_out[11] = chany_top_in[11];
+assign chany_bottom_out[12] = chany_top_in[12];
+assign chany_bottom_out[13] = chany_top_in[13];
+assign chany_bottom_out[14] = chany_top_in[14];
+assign chany_bottom_out[15] = chany_top_in[15];
+assign chany_bottom_out[16] = chany_top_in[16];
+assign chany_bottom_out[17] = chany_top_in[17];
+assign chany_bottom_out[18] = chany_top_in[18];
+assign chany_bottom_out[19] = chany_top_in[19];
+assign chany_top_out[5] = chany_bottom_in[5];
+assign chany_bottom_out[20] = chany_top_in[20];
+assign chany_bottom_out[21] = chany_top_in[21];
+assign chany_bottom_out[22] = chany_top_in[22];
+assign chany_bottom_out[23] = chany_top_in[23];
+assign chany_bottom_out[24] = chany_top_in[24];
+assign chany_bottom_out[25] = chany_top_in[25];
+assign chany_bottom_out[26] = chany_top_in[26];
+assign chany_bottom_out[27] = chany_top_in[27];
+assign chany_bottom_out[28] = chany_top_in[28];
+assign chany_bottom_out[29] = chany_top_in[29];
+assign chany_top_out[6] = chany_bottom_in[6];
+assign chany_top_out[7] = chany_bottom_in[7];
+assign chany_top_out[8] = chany_bottom_in[8];
+assign chany_top_out[9] = chany_bottom_in[9];
+    mux_tree_tapbuf_size12_mem mem_left_ipin_0
+    (
+        .ccff_head(ccff_head),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_0_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_left_ipin_1
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_1_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_left_ipin_2
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_2_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_left_ipin_3
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_3_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_0
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_4_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_1
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_0_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_10
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_9_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_11
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_5_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_12
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_10_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_13
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_6_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_14
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_11_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_15
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_7_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_2
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_5_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_3
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_1_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_4
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_6_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_5
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_2_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_6
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_7_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_7
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_3_sram)
+    );
+    mux_tree_tapbuf_size12_mem mem_right_ipin_8
+    (
+        .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size12_8_sram)
+    );
+    mux_tree_tapbuf_size10_mem mem_right_ipin_9
+    (
+        .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size10_4_sram)
+    );
+    mux_tree_tapbuf_size12 mux_left_ipin_0
+    (
+        .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
+        .sram(mux_tree_tapbuf_size12_0_sram),
+        .sram_inv(mux_left_ipin_0_undriven_sram_inv),
+        .out(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_)
+    );
+    mux_tree_tapbuf_size12 mux_left_ipin_1
+    (
+        .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}),
+        .sram(mux_tree_tapbuf_size12_1_sram),
+        .sram_inv(mux_left_ipin_1_undriven_sram_inv),
+        .out(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_)
+    );
+    mux_tree_tapbuf_size12 mux_left_ipin_2
+    (
+        .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}),
+        .sram(mux_tree_tapbuf_size12_2_sram),
+        .sram_inv(mux_left_ipin_2_undriven_sram_inv),
+        .out(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_)
+    );
+    mux_tree_tapbuf_size12 mux_left_ipin_3
+    (
+        .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21], chany_bottom_in[27], chany_top_in[27]}),
+        .sram(mux_tree_tapbuf_size12_3_sram),
+        .sram_inv(mux_left_ipin_3_undriven_sram_inv),
+        .out(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_0
+    (
+        .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}),
+        .sram(mux_tree_tapbuf_size12_4_sram),
+        .sram_inv(mux_right_ipin_0_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_1
+    (
+        .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[29], chany_top_in[29]}),
+        .sram(mux_tree_tapbuf_size10_0_sram),
+        .sram_inv(mux_right_ipin_1_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_10
+    (
+        .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}),
+        .sram(mux_tree_tapbuf_size12_9_sram),
+        .sram_inv(mux_right_ipin_10_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_11
+    (
+        .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21]}),
+        .sram(mux_tree_tapbuf_size10_5_sram),
+        .sram_inv(mux_right_ipin_11_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_12
+    (
+        .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}),
+        .sram(mux_tree_tapbuf_size12_10_sram),
+        .sram_inv(mux_right_ipin_12_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_13
+    (
+        .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[23], chany_top_in[23]}),
+        .sram(mux_tree_tapbuf_size10_6_sram),
+        .sram_inv(mux_right_ipin_13_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_14
+    (
+        .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
+        .sram(mux_tree_tapbuf_size12_11_sram),
+        .sram_inv(mux_right_ipin_14_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_15
+    (
+        .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}),
+        .sram(mux_tree_tapbuf_size10_7_sram),
+        .sram_inv(mux_right_ipin_15_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_2
+    (
+        .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
+        .sram(mux_tree_tapbuf_size12_5_sram),
+        .sram_inv(mux_right_ipin_2_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_3
+    (
+        .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[22], chany_top_in[22]}),
+        .sram(mux_tree_tapbuf_size10_1_sram),
+        .sram_inv(mux_right_ipin_3_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_4
+    (
+        .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}),
+        .sram(mux_tree_tapbuf_size12_6_sram),
+        .sram_inv(mux_right_ipin_4_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_5
+    (
+        .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[24], chany_top_in[24]}),
+        .sram(mux_tree_tapbuf_size10_2_sram),
+        .sram_inv(mux_right_ipin_5_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_6
+    (
+        .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}),
+        .sram(mux_tree_tapbuf_size12_7_sram),
+        .sram_inv(mux_right_ipin_6_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_7
+    (
+        .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[26], chany_top_in[26]}),
+        .sram(mux_tree_tapbuf_size10_3_sram),
+        .sram_inv(mux_right_ipin_7_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_)
+    );
+    mux_tree_tapbuf_size12 mux_right_ipin_8
+    (
+        .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
+        .sram(mux_tree_tapbuf_size12_8_sram),
+        .sram_inv(mux_right_ipin_8_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_)
+    );
+    mux_tree_tapbuf_size10 mux_right_ipin_9
+    (
+        .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[28], chany_top_in[28]}),
+        .sram(mux_tree_tapbuf_size10_4_sram),
+        .sram_inv(mux_right_ipin_9_undriven_sram_inv),
+        .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/const0.v

@@ -0,0 +1,15 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module const0
+(
+    const0
+);
+
+    output const0;
+
+    wire \<const0> ;
+    wire const0;
+
+assign const0 = \<const0> ;
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/const1.v

@@ -0,0 +1,15 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module const1
+(
+    const1
+);
+
+    output const1;
+
+    wire \<const1> ;
+    wire const1;
+
+assign const1 = \<const1> ;
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/direct_interc.v

@@ -0,0 +1,17 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module direct_interc
+(
+    in,
+    out
+);
+
+    input in;
+    output out;
+
+    wire in;
+    wire out;
+
+assign out = in;
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4.v

@@ -0,0 +1,98 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module frac_lut4
+(
+    in,
+    mode,
+    mode_inv,
+    sram,
+    sram_inv,
+    lut2_out,
+    lut3_out,
+    lut4_out
+);
+
+    input [0:3]in;
+    input mode;
+    input mode_inv;
+    input [0:15]sram;
+    input [0:15]sram_inv;
+    output [0:1]lut2_out;
+    output [0:1]lut3_out;
+    output lut4_out;
+
+    wire [0:3]in;
+    wire [0:1]lut2_out;
+    wire [0:1]lut3_out;
+    wire lut4_out;
+    wire mode;
+    wire mode_inv;
+    wire sky130_fd_sc_hd__buf_2_0_X;
+    wire sky130_fd_sc_hd__buf_2_1_X;
+    wire sky130_fd_sc_hd__buf_2_2_X;
+    wire sky130_fd_sc_hd__buf_2_3_X;
+    wire sky130_fd_sc_hd__inv_1_0_Y;
+    wire sky130_fd_sc_hd__inv_1_1_Y;
+    wire sky130_fd_sc_hd__inv_1_2_Y;
+    wire sky130_fd_sc_hd__inv_1_3_Y;
+    wire sky130_fd_sc_hd__or2_1_0_X;
+    wire [0:15]sram;
+    wire [0:15]sram_inv;
+
+    frac_lut4_mux frac_lut4_mux_0_
+    (
+        .in(sram),
+        .sram({sky130_fd_sc_hd__buf_2_0_X, sky130_fd_sc_hd__buf_2_1_X, sky130_fd_sc_hd__buf_2_2_X, sky130_fd_sc_hd__buf_2_3_X}),
+        .sram_inv({sky130_fd_sc_hd__inv_1_0_Y, sky130_fd_sc_hd__inv_1_1_Y, sky130_fd_sc_hd__inv_1_2_Y, sky130_fd_sc_hd__inv_1_3_Y}),
+        .lut2_out(lut2_out),
+        .lut3_out(lut3_out),
+        .lut4_out(lut4_out)
+    );
+    sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_
+    (
+        .A(in[0]),
+        .X(sky130_fd_sc_hd__buf_2_0_X)
+    );
+    sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_
+    (
+        .A(in[1]),
+        .X(sky130_fd_sc_hd__buf_2_1_X)
+    );
+    sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_
+    (
+        .A(in[2]),
+        .X(sky130_fd_sc_hd__buf_2_2_X)
+    );
+    sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_
+    (
+        .A(sky130_fd_sc_hd__or2_1_0_X),
+        .X(sky130_fd_sc_hd__buf_2_3_X)
+    );
+    sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_
+    (
+        .A(in[0]),
+        .Y(sky130_fd_sc_hd__inv_1_0_Y)
+    );
+    sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_
+    (
+        .A(in[1]),
+        .Y(sky130_fd_sc_hd__inv_1_1_Y)
+    );
+    sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_
+    (
+        .A(in[2]),
+        .Y(sky130_fd_sc_hd__inv_1_2_Y)
+    );
+    sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_
+    (
+        .A(sky130_fd_sc_hd__or2_1_0_X),
+        .Y(sky130_fd_sc_hd__inv_1_3_Y)
+    );
+    sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_
+    (
+        .A(mode),
+        .B(in[3]),
+        .X(sky130_fd_sc_hd__or2_1_0_X)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4_mux.v

@@ -0,0 +1,185 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module frac_lut4_mux
+(
+    in,
+    sram,
+    sram_inv,
+    lut2_out,
+    lut3_out,
+    lut4_out
+);
+
+    input [0:15]in;
+    input [0:3]sram;
+    input [0:3]sram_inv;
+    output [0:1]lut2_out;
+    output [0:1]lut3_out;
+    output lut4_out;
+
+    wire [0:15]in;
+    wire [0:1]lut2_out;
+    wire [0:1]lut3_out;
+    wire lut4_out;
+    wire sky130_fd_sc_hd__buf_2_5_X;
+    wire sky130_fd_sc_hd__buf_2_6_X;
+    wire sky130_fd_sc_hd__mux2_1_0_X;
+    wire sky130_fd_sc_hd__mux2_1_10_X;
+    wire sky130_fd_sc_hd__mux2_1_11_X;
+    wire sky130_fd_sc_hd__mux2_1_12_X;
+    wire sky130_fd_sc_hd__mux2_1_13_X;
+    wire sky130_fd_sc_hd__mux2_1_14_X;
+    wire sky130_fd_sc_hd__mux2_1_1_X;
+    wire sky130_fd_sc_hd__mux2_1_2_X;
+    wire sky130_fd_sc_hd__mux2_1_3_X;
+    wire sky130_fd_sc_hd__mux2_1_4_X;
+    wire sky130_fd_sc_hd__mux2_1_5_X;
+    wire sky130_fd_sc_hd__mux2_1_6_X;
+    wire sky130_fd_sc_hd__mux2_1_7_X;
+    wire sky130_fd_sc_hd__mux2_1_8_X;
+    wire sky130_fd_sc_hd__mux2_1_9_X;
+    wire [0:3]sram;
+    wire [0:3]sram_inv;
+
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
+    (
+        .A0(in[1]),
+        .A1(in[0]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_0_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
+    (
+        .A0(in[3]),
+        .A1(in[2]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_1_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_2_
+    (
+        .A0(in[5]),
+        .A1(in[4]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_2_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_3_
+    (
+        .A0(in[7]),
+        .A1(in[6]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_3_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_4_
+    (
+        .A0(in[9]),
+        .A1(in[8]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_4_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_5_
+    (
+        .A0(in[11]),
+        .A1(in[10]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_5_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_6_
+    (
+        .A0(in[13]),
+        .A1(in[12]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_6_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_7_
+    (
+        .A0(in[15]),
+        .A1(in[14]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_7_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_1_X),
+        .A1(sky130_fd_sc_hd__mux2_1_0_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_8_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_3_X),
+        .A1(sky130_fd_sc_hd__mux2_1_2_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_9_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_2_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_5_X),
+        .A1(sky130_fd_sc_hd__mux2_1_4_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_10_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_3_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_7_X),
+        .A1(sky130_fd_sc_hd__mux2_1_6_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_11_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
+    (
+        .A0(sky130_fd_sc_hd__buf_2_6_X),
+        .A1(sky130_fd_sc_hd__buf_2_5_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_12_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_1_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_11_X),
+        .A1(sky130_fd_sc_hd__mux2_1_10_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_13_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l4_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_13_X),
+        .A1(sky130_fd_sc_hd__mux2_1_12_X),
+        .S(sram[3]),
+        .X(sky130_fd_sc_hd__mux2_1_14_X)
+    );
+    sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_10_X),
+        .X(lut2_out[0])
+    );
+    sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_11_X),
+        .X(lut2_out[1])
+    );
+    sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_12_X),
+        .X(lut3_out[0])
+    );
+    sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_13_X),
+        .X(lut3_out[1])
+    );
+    sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_14_X),
+        .X(lut4_out)
+    );
+    sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_8_X),
+        .X(sky130_fd_sc_hd__buf_2_5_X)
+    );
+    sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_9_X),
+        .X(sky130_fd_sc_hd__buf_2_6_X)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.v

@@ -0,0 +1,145 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
+(
+    ccff_head,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    mem_out
+);
+
+    input ccff_head;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:16]mem_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:16]mem_out;
+    wire pReset;
+    wire prog_clk;
+
+assign ccff_tail = mem_out[16];
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
+    (
+        .CLK(prog_clk),
+        .D(ccff_head),
+        .RESET_B(pReset),
+        .Q(mem_out[0])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[9]),
+        .RESET_B(pReset),
+        .Q(mem_out[10])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[10]),
+        .RESET_B(pReset),
+        .Q(mem_out[11])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[11]),
+        .RESET_B(pReset),
+        .Q(mem_out[12])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[12]),
+        .RESET_B(pReset),
+        .Q(mem_out[13])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[13]),
+        .RESET_B(pReset),
+        .Q(mem_out[14])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[14]),
+        .RESET_B(pReset),
+        .Q(mem_out[15])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[15]),
+        .RESET_B(pReset),
+        .Q(mem_out[16])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[0]),
+        .RESET_B(pReset),
+        .Q(mem_out[1])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[1]),
+        .RESET_B(pReset),
+        .Q(mem_out[2])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[2]),
+        .RESET_B(pReset),
+        .Q(mem_out[3])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[3]),
+        .RESET_B(pReset),
+        .Q(mem_out[4])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[4]),
+        .RESET_B(pReset),
+        .Q(mem_out[5])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[5]),
+        .RESET_B(pReset),
+        .Q(mem_out[6])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[6]),
+        .RESET_B(pReset),
+        .Q(mem_out[7])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[7]),
+        .RESET_B(pReset),
+        .Q(mem_out[8])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[8]),
+        .RESET_B(pReset),
+        .Q(mem_out[9])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_clb.v

@@ -0,0 +1,226 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module grid_clb
+(
+    Test_en,
+    ccff_head,
+    left_width_0_height_0_subtile_0__pin_clk_0_,
+    left_width_0_height_0_subtile_0__pin_reset_0_,
+    pReset,
+    prog_clk,
+    right_width_0_height_0_subtile_0__pin_I4_0_,
+    right_width_0_height_0_subtile_0__pin_I4_1_,
+    right_width_0_height_0_subtile_0__pin_I4i_0_,
+    right_width_0_height_0_subtile_0__pin_I4i_1_,
+    right_width_0_height_0_subtile_0__pin_I5_0_,
+    right_width_0_height_0_subtile_0__pin_I5_1_,
+    right_width_0_height_0_subtile_0__pin_I5i_0_,
+    right_width_0_height_0_subtile_0__pin_I5i_1_,
+    right_width_0_height_0_subtile_0__pin_I6_0_,
+    right_width_0_height_0_subtile_0__pin_I6_1_,
+    right_width_0_height_0_subtile_0__pin_I6i_0_,
+    right_width_0_height_0_subtile_0__pin_I6i_1_,
+    right_width_0_height_0_subtile_0__pin_I7_0_,
+    right_width_0_height_0_subtile_0__pin_I7_1_,
+    right_width_0_height_0_subtile_0__pin_I7i_0_,
+    right_width_0_height_0_subtile_0__pin_I7i_1_,
+    top_width_0_height_0_subtile_0__pin_I0_0_,
+    top_width_0_height_0_subtile_0__pin_I0_1_,
+    top_width_0_height_0_subtile_0__pin_I0i_0_,
+    top_width_0_height_0_subtile_0__pin_I0i_1_,
+    top_width_0_height_0_subtile_0__pin_I1_0_,
+    top_width_0_height_0_subtile_0__pin_I1_1_,
+    top_width_0_height_0_subtile_0__pin_I1i_0_,
+    top_width_0_height_0_subtile_0__pin_I1i_1_,
+    top_width_0_height_0_subtile_0__pin_I2_0_,
+    top_width_0_height_0_subtile_0__pin_I2_1_,
+    top_width_0_height_0_subtile_0__pin_I2i_0_,
+    top_width_0_height_0_subtile_0__pin_I2i_1_,
+    top_width_0_height_0_subtile_0__pin_I3_0_,
+    top_width_0_height_0_subtile_0__pin_I3_1_,
+    top_width_0_height_0_subtile_0__pin_I3i_0_,
+    top_width_0_height_0_subtile_0__pin_I3i_1_,
+    top_width_0_height_0_subtile_0__pin_cin_0_,
+    top_width_0_height_0_subtile_0__pin_reg_in_0_,
+    top_width_0_height_0_subtile_0__pin_sc_in_0_,
+    bottom_width_0_height_0_subtile_0__pin_cout_0_,
+    bottom_width_0_height_0_subtile_0__pin_reg_out_0_,
+    bottom_width_0_height_0_subtile_0__pin_sc_out_0_,
+    ccff_tail,
+    right_width_0_height_0_subtile_0__pin_O_10_,
+    right_width_0_height_0_subtile_0__pin_O_11_,
+    right_width_0_height_0_subtile_0__pin_O_12_,
+    right_width_0_height_0_subtile_0__pin_O_13_,
+    right_width_0_height_0_subtile_0__pin_O_14_,
+    right_width_0_height_0_subtile_0__pin_O_15_,
+    right_width_0_height_0_subtile_0__pin_O_8_,
+    right_width_0_height_0_subtile_0__pin_O_9_,
+    top_width_0_height_0_subtile_0__pin_O_0_,
+    top_width_0_height_0_subtile_0__pin_O_1_,
+    top_width_0_height_0_subtile_0__pin_O_2_,
+    top_width_0_height_0_subtile_0__pin_O_3_,
+    top_width_0_height_0_subtile_0__pin_O_4_,
+    top_width_0_height_0_subtile_0__pin_O_5_,
+    top_width_0_height_0_subtile_0__pin_O_6_,
+    top_width_0_height_0_subtile_0__pin_O_7_
+);
+
+    input Test_en;
+    input ccff_head;
+    input left_width_0_height_0_subtile_0__pin_clk_0_;
+    input left_width_0_height_0_subtile_0__pin_reset_0_;
+    input pReset;
+    input prog_clk;
+    input right_width_0_height_0_subtile_0__pin_I4_0_;
+    input right_width_0_height_0_subtile_0__pin_I4_1_;
+    input right_width_0_height_0_subtile_0__pin_I4i_0_;
+    input right_width_0_height_0_subtile_0__pin_I4i_1_;
+    input right_width_0_height_0_subtile_0__pin_I5_0_;
+    input right_width_0_height_0_subtile_0__pin_I5_1_;
+    input right_width_0_height_0_subtile_0__pin_I5i_0_;
+    input right_width_0_height_0_subtile_0__pin_I5i_1_;
+    input right_width_0_height_0_subtile_0__pin_I6_0_;
+    input right_width_0_height_0_subtile_0__pin_I6_1_;
+    input right_width_0_height_0_subtile_0__pin_I6i_0_;
+    input right_width_0_height_0_subtile_0__pin_I6i_1_;
+    input right_width_0_height_0_subtile_0__pin_I7_0_;
+    input right_width_0_height_0_subtile_0__pin_I7_1_;
+    input right_width_0_height_0_subtile_0__pin_I7i_0_;
+    input right_width_0_height_0_subtile_0__pin_I7i_1_;
+    input top_width_0_height_0_subtile_0__pin_I0_0_;
+    input top_width_0_height_0_subtile_0__pin_I0_1_;
+    input top_width_0_height_0_subtile_0__pin_I0i_0_;
+    input top_width_0_height_0_subtile_0__pin_I0i_1_;
+    input top_width_0_height_0_subtile_0__pin_I1_0_;
+    input top_width_0_height_0_subtile_0__pin_I1_1_;
+    input top_width_0_height_0_subtile_0__pin_I1i_0_;
+    input top_width_0_height_0_subtile_0__pin_I1i_1_;
+    input top_width_0_height_0_subtile_0__pin_I2_0_;
+    input top_width_0_height_0_subtile_0__pin_I2_1_;
+    input top_width_0_height_0_subtile_0__pin_I2i_0_;
+    input top_width_0_height_0_subtile_0__pin_I2i_1_;
+    input top_width_0_height_0_subtile_0__pin_I3_0_;
+    input top_width_0_height_0_subtile_0__pin_I3_1_;
+    input top_width_0_height_0_subtile_0__pin_I3i_0_;
+    input top_width_0_height_0_subtile_0__pin_I3i_1_;
+    input top_width_0_height_0_subtile_0__pin_cin_0_;
+    input top_width_0_height_0_subtile_0__pin_reg_in_0_;
+    input top_width_0_height_0_subtile_0__pin_sc_in_0_;
+    output bottom_width_0_height_0_subtile_0__pin_cout_0_;
+    output bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
+    output bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
+    output ccff_tail;
+    output right_width_0_height_0_subtile_0__pin_O_10_;
+    output right_width_0_height_0_subtile_0__pin_O_11_;
+    output right_width_0_height_0_subtile_0__pin_O_12_;
+    output right_width_0_height_0_subtile_0__pin_O_13_;
+    output right_width_0_height_0_subtile_0__pin_O_14_;
+    output right_width_0_height_0_subtile_0__pin_O_15_;
+    output right_width_0_height_0_subtile_0__pin_O_8_;
+    output right_width_0_height_0_subtile_0__pin_O_9_;
+    output top_width_0_height_0_subtile_0__pin_O_0_;
+    output top_width_0_height_0_subtile_0__pin_O_1_;
+    output top_width_0_height_0_subtile_0__pin_O_2_;
+    output top_width_0_height_0_subtile_0__pin_O_3_;
+    output top_width_0_height_0_subtile_0__pin_O_4_;
+    output top_width_0_height_0_subtile_0__pin_O_5_;
+    output top_width_0_height_0_subtile_0__pin_O_6_;
+    output top_width_0_height_0_subtile_0__pin_O_7_;
+
+    wire Test_en;
+    wire bottom_width_0_height_0_subtile_0__pin_cout_0_;
+    wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
+    wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
+    wire ccff_head;
+    wire ccff_tail;
+    wire left_width_0_height_0_subtile_0__pin_clk_0_;
+    wire left_width_0_height_0_subtile_0__pin_reset_0_;
+    wire pReset;
+    wire prog_clk;
+    wire right_width_0_height_0_subtile_0__pin_I4_0_;
+    wire right_width_0_height_0_subtile_0__pin_I4_1_;
+    wire right_width_0_height_0_subtile_0__pin_I4i_0_;
+    wire right_width_0_height_0_subtile_0__pin_I4i_1_;
+    wire right_width_0_height_0_subtile_0__pin_I5_0_;
+    wire right_width_0_height_0_subtile_0__pin_I5_1_;
+    wire right_width_0_height_0_subtile_0__pin_I5i_0_;
+    wire right_width_0_height_0_subtile_0__pin_I5i_1_;
+    wire right_width_0_height_0_subtile_0__pin_I6_0_;
+    wire right_width_0_height_0_subtile_0__pin_I6_1_;
+    wire right_width_0_height_0_subtile_0__pin_I6i_0_;
+    wire right_width_0_height_0_subtile_0__pin_I6i_1_;
+    wire right_width_0_height_0_subtile_0__pin_I7_0_;
+    wire right_width_0_height_0_subtile_0__pin_I7_1_;
+    wire right_width_0_height_0_subtile_0__pin_I7i_0_;
+    wire right_width_0_height_0_subtile_0__pin_I7i_1_;
+    wire right_width_0_height_0_subtile_0__pin_O_10_;
+    wire right_width_0_height_0_subtile_0__pin_O_11_;
+    wire right_width_0_height_0_subtile_0__pin_O_12_;
+    wire right_width_0_height_0_subtile_0__pin_O_13_;
+    wire right_width_0_height_0_subtile_0__pin_O_14_;
+    wire right_width_0_height_0_subtile_0__pin_O_15_;
+    wire right_width_0_height_0_subtile_0__pin_O_8_;
+    wire right_width_0_height_0_subtile_0__pin_O_9_;
+    wire top_width_0_height_0_subtile_0__pin_I0_0_;
+    wire top_width_0_height_0_subtile_0__pin_I0_1_;
+    wire top_width_0_height_0_subtile_0__pin_I0i_0_;
+    wire top_width_0_height_0_subtile_0__pin_I0i_1_;
+    wire top_width_0_height_0_subtile_0__pin_I1_0_;
+    wire top_width_0_height_0_subtile_0__pin_I1_1_;
+    wire top_width_0_height_0_subtile_0__pin_I1i_0_;
+    wire top_width_0_height_0_subtile_0__pin_I1i_1_;
+    wire top_width_0_height_0_subtile_0__pin_I2_0_;
+    wire top_width_0_height_0_subtile_0__pin_I2_1_;
+    wire top_width_0_height_0_subtile_0__pin_I2i_0_;
+    wire top_width_0_height_0_subtile_0__pin_I2i_1_;
+    wire top_width_0_height_0_subtile_0__pin_I3_0_;
+    wire top_width_0_height_0_subtile_0__pin_I3_1_;
+    wire top_width_0_height_0_subtile_0__pin_I3i_0_;
+    wire top_width_0_height_0_subtile_0__pin_I3i_1_;
+    wire top_width_0_height_0_subtile_0__pin_O_0_;
+    wire top_width_0_height_0_subtile_0__pin_O_1_;
+    wire top_width_0_height_0_subtile_0__pin_O_2_;
+    wire top_width_0_height_0_subtile_0__pin_O_3_;
+    wire top_width_0_height_0_subtile_0__pin_O_4_;
+    wire top_width_0_height_0_subtile_0__pin_O_5_;
+    wire top_width_0_height_0_subtile_0__pin_O_6_;
+    wire top_width_0_height_0_subtile_0__pin_O_7_;
+    wire top_width_0_height_0_subtile_0__pin_cin_0_;
+    wire top_width_0_height_0_subtile_0__pin_reg_in_0_;
+    wire top_width_0_height_0_subtile_0__pin_sc_in_0_;
+
+    logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0
+    (
+        .Test_en(Test_en),
+        .ccff_head(ccff_head),
+        .clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}),
+        .clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}),
+        .clb_I1({top_width_0_height_0_subtile_0__pin_I1_0_, top_width_0_height_0_subtile_0__pin_I1_1_}),
+        .clb_I1i({top_width_0_height_0_subtile_0__pin_I1i_0_, top_width_0_height_0_subtile_0__pin_I1i_1_}),
+        .clb_I2({top_width_0_height_0_subtile_0__pin_I2_0_, top_width_0_height_0_subtile_0__pin_I2_1_}),
+        .clb_I2i({top_width_0_height_0_subtile_0__pin_I2i_0_, top_width_0_height_0_subtile_0__pin_I2i_1_}),
+        .clb_I3({top_width_0_height_0_subtile_0__pin_I3_0_, top_width_0_height_0_subtile_0__pin_I3_1_}),
+        .clb_I3i({top_width_0_height_0_subtile_0__pin_I3i_0_, top_width_0_height_0_subtile_0__pin_I3i_1_}),
+        .clb_I4({right_width_0_height_0_subtile_0__pin_I4_0_, right_width_0_height_0_subtile_0__pin_I4_1_}),
+        .clb_I4i({right_width_0_height_0_subtile_0__pin_I4i_0_, right_width_0_height_0_subtile_0__pin_I4i_1_}),
+        .clb_I5({right_width_0_height_0_subtile_0__pin_I5_0_, right_width_0_height_0_subtile_0__pin_I5_1_}),
+        .clb_I5i({right_width_0_height_0_subtile_0__pin_I5i_0_, right_width_0_height_0_subtile_0__pin_I5i_1_}),
+        .clb_I6({right_width_0_height_0_subtile_0__pin_I6_0_, right_width_0_height_0_subtile_0__pin_I6_1_}),
+        .clb_I6i({right_width_0_height_0_subtile_0__pin_I6i_0_, right_width_0_height_0_subtile_0__pin_I6i_1_}),
+        .clb_I7({right_width_0_height_0_subtile_0__pin_I7_0_, right_width_0_height_0_subtile_0__pin_I7_1_}),
+        .clb_I7i({right_width_0_height_0_subtile_0__pin_I7i_0_, right_width_0_height_0_subtile_0__pin_I7i_1_}),
+        .clb_cin(top_width_0_height_0_subtile_0__pin_cin_0_),
+        .clb_clk(left_width_0_height_0_subtile_0__pin_clk_0_),
+        .clb_reg_in(top_width_0_height_0_subtile_0__pin_reg_in_0_),
+        .clb_reset(left_width_0_height_0_subtile_0__pin_reset_0_),
+        .clb_sc_in(top_width_0_height_0_subtile_0__pin_sc_in_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .clb_O({top_width_0_height_0_subtile_0__pin_O_0_, top_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, top_width_0_height_0_subtile_0__pin_O_3_, top_width_0_height_0_subtile_0__pin_O_4_, top_width_0_height_0_subtile_0__pin_O_5_, top_width_0_height_0_subtile_0__pin_O_6_, top_width_0_height_0_subtile_0__pin_O_7_, right_width_0_height_0_subtile_0__pin_O_8_, right_width_0_height_0_subtile_0__pin_O_9_, right_width_0_height_0_subtile_0__pin_O_10_, right_width_0_height_0_subtile_0__pin_O_11_, right_width_0_height_0_subtile_0__pin_O_12_, right_width_0_height_0_subtile_0__pin_O_13_, right_width_0_height_0_subtile_0__pin_O_14_, right_width_0_height_0_subtile_0__pin_O_15_}),
+        .clb_cout(bottom_width_0_height_0_subtile_0__pin_cout_0_),
+        .clb_reg_out(bottom_width_0_height_0_subtile_0__pin_reg_out_0_),
+        .clb_sc_out(bottom_width_0_height_0_subtile_0__pin_sc_out_0_)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_bottom_bottom.v

@@ -0,0 +1,113 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module grid_io_bottom_bottom
+(
+    IO_ISOL_N,
+    ccff_head,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
+    pReset,
+    prog_clk,
+    top_width_0_height_0_subtile_0__pin_outpad_0_,
+    top_width_0_height_0_subtile_1__pin_outpad_0_,
+    top_width_0_height_0_subtile_2__pin_outpad_0_,
+    top_width_0_height_0_subtile_3__pin_outpad_0_,
+    ccff_tail,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    top_width_0_height_0_subtile_0__pin_inpad_0_,
+    top_width_0_height_0_subtile_1__pin_inpad_0_,
+    top_width_0_height_0_subtile_2__pin_inpad_0_,
+    top_width_0_height_0_subtile_3__pin_inpad_0_
+);
+
+    input IO_ISOL_N;
+    input ccff_head;
+    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    input pReset;
+    input prog_clk;
+    input top_width_0_height_0_subtile_0__pin_outpad_0_;
+    input top_width_0_height_0_subtile_1__pin_outpad_0_;
+    input top_width_0_height_0_subtile_2__pin_outpad_0_;
+    input top_width_0_height_0_subtile_3__pin_outpad_0_;
+    output ccff_tail;
+    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output top_width_0_height_0_subtile_0__pin_inpad_0_;
+    output top_width_0_height_0_subtile_1__pin_inpad_0_;
+    output top_width_0_height_0_subtile_2__pin_inpad_0_;
+    output top_width_0_height_0_subtile_3__pin_inpad_0_;
+
+    wire IO_ISOL_N;
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire logical_tile_io_mode_io__0_ccff_tail;
+    wire logical_tile_io_mode_io__1_ccff_tail;
+    wire logical_tile_io_mode_io__2_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+    wire top_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire top_width_0_height_0_subtile_0__pin_outpad_0_;
+    wire top_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire top_width_0_height_0_subtile_1__pin_outpad_0_;
+    wire top_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire top_width_0_height_0_subtile_2__pin_outpad_0_;
+    wire top_width_0_height_0_subtile_3__pin_inpad_0_;
+    wire top_width_0_height_0_subtile_3__pin_outpad_0_;
+
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__0
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(ccff_head),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
+        .io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_io_mode_io__0_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
+        .io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_)
+    );
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__1
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
+        .io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_io_mode_io__1_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
+        .io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_)
+    );
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__2
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
+        .io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_io_mode_io__2_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
+        .io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_)
+    );
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__3
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
+        .io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
+        .io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_left_left.v

@@ -0,0 +1,113 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module grid_io_left_left
+(
+    IO_ISOL_N,
+    ccff_head,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
+    pReset,
+    prog_clk,
+    right_width_0_height_0_subtile_0__pin_outpad_0_,
+    right_width_0_height_0_subtile_1__pin_outpad_0_,
+    right_width_0_height_0_subtile_2__pin_outpad_0_,
+    right_width_0_height_0_subtile_3__pin_outpad_0_,
+    ccff_tail,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    right_width_0_height_0_subtile_0__pin_inpad_0_,
+    right_width_0_height_0_subtile_1__pin_inpad_0_,
+    right_width_0_height_0_subtile_2__pin_inpad_0_,
+    right_width_0_height_0_subtile_3__pin_inpad_0_
+);
+
+    input IO_ISOL_N;
+    input ccff_head;
+    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    input pReset;
+    input prog_clk;
+    input right_width_0_height_0_subtile_0__pin_outpad_0_;
+    input right_width_0_height_0_subtile_1__pin_outpad_0_;
+    input right_width_0_height_0_subtile_2__pin_outpad_0_;
+    input right_width_0_height_0_subtile_3__pin_outpad_0_;
+    output ccff_tail;
+    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output right_width_0_height_0_subtile_0__pin_inpad_0_;
+    output right_width_0_height_0_subtile_1__pin_inpad_0_;
+    output right_width_0_height_0_subtile_2__pin_inpad_0_;
+    output right_width_0_height_0_subtile_3__pin_inpad_0_;
+
+    wire IO_ISOL_N;
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire logical_tile_io_mode_io__0_ccff_tail;
+    wire logical_tile_io_mode_io__1_ccff_tail;
+    wire logical_tile_io_mode_io__2_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+    wire right_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire right_width_0_height_0_subtile_0__pin_outpad_0_;
+    wire right_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire right_width_0_height_0_subtile_1__pin_outpad_0_;
+    wire right_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire right_width_0_height_0_subtile_2__pin_outpad_0_;
+    wire right_width_0_height_0_subtile_3__pin_inpad_0_;
+    wire right_width_0_height_0_subtile_3__pin_outpad_0_;
+
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__0
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(ccff_head),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
+        .io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_io_mode_io__0_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
+        .io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_)
+    );
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__1
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
+        .io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_io_mode_io__1_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
+        .io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_)
+    );
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__2
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
+        .io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_io_mode_io__2_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
+        .io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_)
+    );
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__3
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
+        .io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
+        .io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_right_right.v

@@ -0,0 +1,113 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module grid_io_right_right
+(
+    IO_ISOL_N,
+    ccff_head,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
+    left_width_0_height_0_subtile_0__pin_outpad_0_,
+    left_width_0_height_0_subtile_1__pin_outpad_0_,
+    left_width_0_height_0_subtile_2__pin_outpad_0_,
+    left_width_0_height_0_subtile_3__pin_outpad_0_,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    left_width_0_height_0_subtile_0__pin_inpad_0_,
+    left_width_0_height_0_subtile_1__pin_inpad_0_,
+    left_width_0_height_0_subtile_2__pin_inpad_0_,
+    left_width_0_height_0_subtile_3__pin_inpad_0_
+);
+
+    input IO_ISOL_N;
+    input ccff_head;
+    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    input left_width_0_height_0_subtile_0__pin_outpad_0_;
+    input left_width_0_height_0_subtile_1__pin_outpad_0_;
+    input left_width_0_height_0_subtile_2__pin_outpad_0_;
+    input left_width_0_height_0_subtile_3__pin_outpad_0_;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output left_width_0_height_0_subtile_0__pin_inpad_0_;
+    output left_width_0_height_0_subtile_1__pin_inpad_0_;
+    output left_width_0_height_0_subtile_2__pin_inpad_0_;
+    output left_width_0_height_0_subtile_3__pin_inpad_0_;
+
+    wire IO_ISOL_N;
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire left_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire left_width_0_height_0_subtile_0__pin_outpad_0_;
+    wire left_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire left_width_0_height_0_subtile_1__pin_outpad_0_;
+    wire left_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire left_width_0_height_0_subtile_2__pin_outpad_0_;
+    wire left_width_0_height_0_subtile_3__pin_inpad_0_;
+    wire left_width_0_height_0_subtile_3__pin_outpad_0_;
+    wire logical_tile_io_mode_io__0_ccff_tail;
+    wire logical_tile_io_mode_io__1_ccff_tail;
+    wire logical_tile_io_mode_io__2_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__0
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(ccff_head),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
+        .io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_io_mode_io__0_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
+        .io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_)
+    );
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__1
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
+        .io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_io_mode_io__1_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
+        .io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_)
+    );
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__2
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
+        .io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_io_mode_io__2_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
+        .io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_)
+    );
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__3
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
+        .io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
+        .io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_top_top.v

@@ -0,0 +1,113 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module grid_io_top_top
+(
+    IO_ISOL_N,
+    bottom_width_0_height_0_subtile_0__pin_outpad_0_,
+    bottom_width_0_height_0_subtile_1__pin_outpad_0_,
+    bottom_width_0_height_0_subtile_2__pin_outpad_0_,
+    bottom_width_0_height_0_subtile_3__pin_outpad_0_,
+    ccff_head,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
+    pReset,
+    prog_clk,
+    bottom_width_0_height_0_subtile_0__pin_inpad_0_,
+    bottom_width_0_height_0_subtile_1__pin_inpad_0_,
+    bottom_width_0_height_0_subtile_2__pin_inpad_0_,
+    bottom_width_0_height_0_subtile_3__pin_inpad_0_,
+    ccff_tail,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT
+);
+
+    input IO_ISOL_N;
+    input bottom_width_0_height_0_subtile_0__pin_outpad_0_;
+    input bottom_width_0_height_0_subtile_1__pin_outpad_0_;
+    input bottom_width_0_height_0_subtile_2__pin_outpad_0_;
+    input bottom_width_0_height_0_subtile_3__pin_outpad_0_;
+    input ccff_head;
+    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    input pReset;
+    input prog_clk;
+    output bottom_width_0_height_0_subtile_0__pin_inpad_0_;
+    output bottom_width_0_height_0_subtile_1__pin_inpad_0_;
+    output bottom_width_0_height_0_subtile_2__pin_inpad_0_;
+    output bottom_width_0_height_0_subtile_3__pin_inpad_0_;
+    output ccff_tail;
+    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+
+    wire IO_ISOL_N;
+    wire bottom_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire bottom_width_0_height_0_subtile_0__pin_outpad_0_;
+    wire bottom_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire bottom_width_0_height_0_subtile_1__pin_outpad_0_;
+    wire bottom_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire bottom_width_0_height_0_subtile_2__pin_outpad_0_;
+    wire bottom_width_0_height_0_subtile_3__pin_inpad_0_;
+    wire bottom_width_0_height_0_subtile_3__pin_outpad_0_;
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire logical_tile_io_mode_io__0_ccff_tail;
+    wire logical_tile_io_mode_io__1_ccff_tail;
+    wire logical_tile_io_mode_io__2_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__0
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(ccff_head),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
+        .io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_io_mode_io__0_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
+        .io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_)
+    );
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__1
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
+        .io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_io_mode_io__1_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
+        .io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_)
+    );
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__2
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
+        .io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_io_mode_io__2_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
+        .io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_)
+    );
+    logical_tile_io_mode_io_ logical_tile_io_mode_io__3
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
+        .io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
+        .io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_clb_.v

@@ -0,0 +1,810 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module logical_tile_clb_mode_clb_
+(
+    Test_en,
+    ccff_head,
+    clb_I0,
+    clb_I0i,
+    clb_I1,
+    clb_I1i,
+    clb_I2,
+    clb_I2i,
+    clb_I3,
+    clb_I3i,
+    clb_I4,
+    clb_I4i,
+    clb_I5,
+    clb_I5i,
+    clb_I6,
+    clb_I6i,
+    clb_I7,
+    clb_I7i,
+    clb_cin,
+    clb_clk,
+    clb_reg_in,
+    clb_reset,
+    clb_sc_in,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    clb_O,
+    clb_cout,
+    clb_reg_out,
+    clb_sc_out
+);
+
+    input Test_en;
+    input ccff_head;
+    input [0:1]clb_I0;
+    input [0:1]clb_I0i;
+    input [0:1]clb_I1;
+    input [0:1]clb_I1i;
+    input [0:1]clb_I2;
+    input [0:1]clb_I2i;
+    input [0:1]clb_I3;
+    input [0:1]clb_I3i;
+    input [0:1]clb_I4;
+    input [0:1]clb_I4i;
+    input [0:1]clb_I5;
+    input [0:1]clb_I5i;
+    input [0:1]clb_I6;
+    input [0:1]clb_I6i;
+    input [0:1]clb_I7;
+    input [0:1]clb_I7i;
+    input clb_cin;
+    input clb_clk;
+    input clb_reg_in;
+    input clb_reset;
+    input clb_sc_in;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:15]clb_O;
+    output clb_cout;
+    output clb_reg_out;
+    output clb_sc_out;
+
+    wire Test_en;
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:1]clb_I0;
+    wire [0:1]clb_I0i;
+    wire [0:1]clb_I1;
+    wire [0:1]clb_I1i;
+    wire [0:1]clb_I2;
+    wire [0:1]clb_I2i;
+    wire [0:1]clb_I3;
+    wire [0:1]clb_I3i;
+    wire [0:1]clb_I4;
+    wire [0:1]clb_I4i;
+    wire [0:1]clb_I5;
+    wire [0:1]clb_I5i;
+    wire [0:1]clb_I6;
+    wire [0:1]clb_I6i;
+    wire [0:1]clb_I7;
+    wire [0:1]clb_I7i;
+    wire [0:15]clb_O;
+    wire clb_cin;
+    wire clb_clk;
+    wire clb_cout;
+    wire clb_reg_in;
+    wire clb_reg_out;
+    wire clb_reset;
+    wire clb_sc_in;
+    wire clb_sc_out;
+    wire direct_interc_19_out;
+    wire direct_interc_20_out;
+    wire direct_interc_21_out;
+    wire direct_interc_22_out;
+    wire direct_interc_23_out;
+    wire direct_interc_24_out;
+    wire direct_interc_25_out;
+    wire direct_interc_26_out;
+    wire direct_interc_27_out;
+    wire direct_interc_28_out;
+    wire direct_interc_29_out;
+    wire direct_interc_30_out;
+    wire direct_interc_31_out;
+    wire direct_interc_32_out;
+    wire direct_interc_33_out;
+    wire direct_interc_34_out;
+    wire direct_interc_35_out;
+    wire direct_interc_36_out;
+    wire direct_interc_37_out;
+    wire direct_interc_38_out;
+    wire direct_interc_39_out;
+    wire direct_interc_40_out;
+    wire direct_interc_41_out;
+    wire direct_interc_42_out;
+    wire direct_interc_43_out;
+    wire direct_interc_44_out;
+    wire direct_interc_45_out;
+    wire direct_interc_46_out;
+    wire direct_interc_47_out;
+    wire direct_interc_48_out;
+    wire direct_interc_49_out;
+    wire direct_interc_50_out;
+    wire direct_interc_51_out;
+    wire direct_interc_52_out;
+    wire direct_interc_53_out;
+    wire direct_interc_54_out;
+    wire direct_interc_55_out;
+    wire direct_interc_56_out;
+    wire direct_interc_57_out;
+    wire direct_interc_58_out;
+    wire direct_interc_59_out;
+    wire direct_interc_60_out;
+    wire direct_interc_61_out;
+    wire direct_interc_62_out;
+    wire direct_interc_63_out;
+    wire direct_interc_64_out;
+    wire direct_interc_65_out;
+    wire direct_interc_66_out;
+    wire direct_interc_67_out;
+    wire direct_interc_68_out;
+    wire direct_interc_69_out;
+    wire direct_interc_70_out;
+    wire direct_interc_71_out;
+    wire direct_interc_72_out;
+    wire direct_interc_73_out;
+    wire direct_interc_74_out;
+    wire direct_interc_75_out;
+    wire direct_interc_76_out;
+    wire direct_interc_77_out;
+    wire direct_interc_78_out;
+    wire direct_interc_79_out;
+    wire direct_interc_80_out;
+    wire direct_interc_81_out;
+    wire direct_interc_82_out;
+    wire direct_interc_83_out;
+    wire direct_interc_84_out;
+    wire direct_interc_85_out;
+    wire direct_interc_86_out;
+    wire direct_interc_87_out;
+    wire direct_interc_88_out;
+    wire direct_interc_89_out;
+    wire direct_interc_90_out;
+    wire logical_tile_clb_mode_default__fle_0_ccff_tail;
+    wire logical_tile_clb_mode_default__fle_0_fle_cout;
+    wire [0:1]logical_tile_clb_mode_default__fle_0_fle_out;
+    wire logical_tile_clb_mode_default__fle_0_fle_reg_out;
+    wire logical_tile_clb_mode_default__fle_0_fle_sc_out;
+    wire logical_tile_clb_mode_default__fle_1_ccff_tail;
+    wire logical_tile_clb_mode_default__fle_1_fle_cout;
+    wire [0:1]logical_tile_clb_mode_default__fle_1_fle_out;
+    wire logical_tile_clb_mode_default__fle_1_fle_reg_out;
+    wire logical_tile_clb_mode_default__fle_1_fle_sc_out;
+    wire logical_tile_clb_mode_default__fle_2_ccff_tail;
+    wire logical_tile_clb_mode_default__fle_2_fle_cout;
+    wire [0:1]logical_tile_clb_mode_default__fle_2_fle_out;
+    wire logical_tile_clb_mode_default__fle_2_fle_reg_out;
+    wire logical_tile_clb_mode_default__fle_2_fle_sc_out;
+    wire logical_tile_clb_mode_default__fle_3_ccff_tail;
+    wire logical_tile_clb_mode_default__fle_3_fle_cout;
+    wire [0:1]logical_tile_clb_mode_default__fle_3_fle_out;
+    wire logical_tile_clb_mode_default__fle_3_fle_reg_out;
+    wire logical_tile_clb_mode_default__fle_3_fle_sc_out;
+    wire logical_tile_clb_mode_default__fle_4_ccff_tail;
+    wire logical_tile_clb_mode_default__fle_4_fle_cout;
+    wire [0:1]logical_tile_clb_mode_default__fle_4_fle_out;
+    wire logical_tile_clb_mode_default__fle_4_fle_reg_out;
+    wire logical_tile_clb_mode_default__fle_4_fle_sc_out;
+    wire logical_tile_clb_mode_default__fle_5_ccff_tail;
+    wire logical_tile_clb_mode_default__fle_5_fle_cout;
+    wire [0:1]logical_tile_clb_mode_default__fle_5_fle_out;
+    wire logical_tile_clb_mode_default__fle_5_fle_reg_out;
+    wire logical_tile_clb_mode_default__fle_5_fle_sc_out;
+    wire logical_tile_clb_mode_default__fle_6_ccff_tail;
+    wire logical_tile_clb_mode_default__fle_6_fle_cout;
+    wire [0:1]logical_tile_clb_mode_default__fle_6_fle_out;
+    wire logical_tile_clb_mode_default__fle_6_fle_reg_out;
+    wire logical_tile_clb_mode_default__fle_6_fle_sc_out;
+    wire logical_tile_clb_mode_default__fle_7_fle_cout;
+    wire [0:1]logical_tile_clb_mode_default__fle_7_fle_out;
+    wire logical_tile_clb_mode_default__fle_7_fle_reg_out;
+    wire logical_tile_clb_mode_default__fle_7_fle_sc_out;
+    wire pReset;
+    wire prog_clk;
+
+    direct_interc direct_interc_0_
+    (
+        .in(logical_tile_clb_mode_default__fle_0_fle_out[1]),
+        .out(clb_O[0])
+    );
+    direct_interc direct_interc_10_
+    (
+        .in(logical_tile_clb_mode_default__fle_5_fle_out[1]),
+        .out(clb_O[10])
+    );
+    direct_interc direct_interc_11_
+    (
+        .in(logical_tile_clb_mode_default__fle_5_fle_out[0]),
+        .out(clb_O[11])
+    );
+    direct_interc direct_interc_12_
+    (
+        .in(logical_tile_clb_mode_default__fle_6_fle_out[1]),
+        .out(clb_O[12])
+    );
+    direct_interc direct_interc_13_
+    (
+        .in(logical_tile_clb_mode_default__fle_6_fle_out[0]),
+        .out(clb_O[13])
+    );
+    direct_interc direct_interc_14_
+    (
+        .in(logical_tile_clb_mode_default__fle_7_fle_out[1]),
+        .out(clb_O[14])
+    );
+    direct_interc direct_interc_15_
+    (
+        .in(logical_tile_clb_mode_default__fle_7_fle_out[0]),
+        .out(clb_O[15])
+    );
+    direct_interc direct_interc_16_
+    (
+        .in(logical_tile_clb_mode_default__fle_7_fle_reg_out),
+        .out(clb_reg_out)
+    );
+    direct_interc direct_interc_17_
+    (
+        .in(logical_tile_clb_mode_default__fle_7_fle_sc_out),
+        .out(clb_sc_out)
+    );
+    direct_interc direct_interc_18_
+    (
+        .in(logical_tile_clb_mode_default__fle_7_fle_cout),
+        .out(clb_cout)
+    );
+    direct_interc direct_interc_19_
+    (
+        .in(clb_I0[0]),
+        .out(direct_interc_19_out)
+    );
+    direct_interc direct_interc_1_
+    (
+        .in(logical_tile_clb_mode_default__fle_0_fle_out[0]),
+        .out(clb_O[1])
+    );
+    direct_interc direct_interc_20_
+    (
+        .in(clb_I0[1]),
+        .out(direct_interc_20_out)
+    );
+    direct_interc direct_interc_21_
+    (
+        .in(clb_I0i[0]),
+        .out(direct_interc_21_out)
+    );
+    direct_interc direct_interc_22_
+    (
+        .in(clb_I0i[1]),
+        .out(direct_interc_22_out)
+    );
+    direct_interc direct_interc_23_
+    (
+        .in(clb_reg_in),
+        .out(direct_interc_23_out)
+    );
+    direct_interc direct_interc_24_
+    (
+        .in(clb_sc_in),
+        .out(direct_interc_24_out)
+    );
+    direct_interc direct_interc_25_
+    (
+        .in(clb_cin),
+        .out(direct_interc_25_out)
+    );
+    direct_interc direct_interc_26_
+    (
+        .in(clb_reset),
+        .out(direct_interc_26_out)
+    );
+    direct_interc direct_interc_27_
+    (
+        .in(clb_clk),
+        .out(direct_interc_27_out)
+    );
+    direct_interc direct_interc_28_
+    (
+        .in(clb_I1[0]),
+        .out(direct_interc_28_out)
+    );
+    direct_interc direct_interc_29_
+    (
+        .in(clb_I1[1]),
+        .out(direct_interc_29_out)
+    );
+    direct_interc direct_interc_2_
+    (
+        .in(logical_tile_clb_mode_default__fle_1_fle_out[1]),
+        .out(clb_O[2])
+    );
+    direct_interc direct_interc_30_
+    (
+        .in(clb_I1i[0]),
+        .out(direct_interc_30_out)
+    );
+    direct_interc direct_interc_31_
+    (
+        .in(clb_I1i[1]),
+        .out(direct_interc_31_out)
+    );
+    direct_interc direct_interc_32_
+    (
+        .in(logical_tile_clb_mode_default__fle_0_fle_reg_out),
+        .out(direct_interc_32_out)
+    );
+    direct_interc direct_interc_33_
+    (
+        .in(logical_tile_clb_mode_default__fle_0_fle_sc_out),
+        .out(direct_interc_33_out)
+    );
+    direct_interc direct_interc_34_
+    (
+        .in(logical_tile_clb_mode_default__fle_0_fle_cout),
+        .out(direct_interc_34_out)
+    );
+    direct_interc direct_interc_35_
+    (
+        .in(clb_reset),
+        .out(direct_interc_35_out)
+    );
+    direct_interc direct_interc_36_
+    (
+        .in(clb_clk),
+        .out(direct_interc_36_out)
+    );
+    direct_interc direct_interc_37_
+    (
+        .in(clb_I2[0]),
+        .out(direct_interc_37_out)
+    );
+    direct_interc direct_interc_38_
+    (
+        .in(clb_I2[1]),
+        .out(direct_interc_38_out)
+    );
+    direct_interc direct_interc_39_
+    (
+        .in(clb_I2i[0]),
+        .out(direct_interc_39_out)
+    );
+    direct_interc direct_interc_3_
+    (
+        .in(logical_tile_clb_mode_default__fle_1_fle_out[0]),
+        .out(clb_O[3])
+    );
+    direct_interc direct_interc_40_
+    (
+        .in(clb_I2i[1]),
+        .out(direct_interc_40_out)
+    );
+    direct_interc direct_interc_41_
+    (
+        .in(logical_tile_clb_mode_default__fle_1_fle_reg_out),
+        .out(direct_interc_41_out)
+    );
+    direct_interc direct_interc_42_
+    (
+        .in(logical_tile_clb_mode_default__fle_1_fle_sc_out),
+        .out(direct_interc_42_out)
+    );
+    direct_interc direct_interc_43_
+    (
+        .in(logical_tile_clb_mode_default__fle_1_fle_cout),
+        .out(direct_interc_43_out)
+    );
+    direct_interc direct_interc_44_
+    (
+        .in(clb_reset),
+        .out(direct_interc_44_out)
+    );
+    direct_interc direct_interc_45_
+    (
+        .in(clb_clk),
+        .out(direct_interc_45_out)
+    );
+    direct_interc direct_interc_46_
+    (
+        .in(clb_I3[0]),
+        .out(direct_interc_46_out)
+    );
+    direct_interc direct_interc_47_
+    (
+        .in(clb_I3[1]),
+        .out(direct_interc_47_out)
+    );
+    direct_interc direct_interc_48_
+    (
+        .in(clb_I3i[0]),
+        .out(direct_interc_48_out)
+    );
+    direct_interc direct_interc_49_
+    (
+        .in(clb_I3i[1]),
+        .out(direct_interc_49_out)
+    );
+    direct_interc direct_interc_4_
+    (
+        .in(logical_tile_clb_mode_default__fle_2_fle_out[1]),
+        .out(clb_O[4])
+    );
+    direct_interc direct_interc_50_
+    (
+        .in(logical_tile_clb_mode_default__fle_2_fle_reg_out),
+        .out(direct_interc_50_out)
+    );
+    direct_interc direct_interc_51_
+    (
+        .in(logical_tile_clb_mode_default__fle_2_fle_sc_out),
+        .out(direct_interc_51_out)
+    );
+    direct_interc direct_interc_52_
+    (
+        .in(logical_tile_clb_mode_default__fle_2_fle_cout),
+        .out(direct_interc_52_out)
+    );
+    direct_interc direct_interc_53_
+    (
+        .in(clb_reset),
+        .out(direct_interc_53_out)
+    );
+    direct_interc direct_interc_54_
+    (
+        .in(clb_clk),
+        .out(direct_interc_54_out)
+    );
+    direct_interc direct_interc_55_
+    (
+        .in(clb_I4[0]),
+        .out(direct_interc_55_out)
+    );
+    direct_interc direct_interc_56_
+    (
+        .in(clb_I4[1]),
+        .out(direct_interc_56_out)
+    );
+    direct_interc direct_interc_57_
+    (
+        .in(clb_I4i[0]),
+        .out(direct_interc_57_out)
+    );
+    direct_interc direct_interc_58_
+    (
+        .in(clb_I4i[1]),
+        .out(direct_interc_58_out)
+    );
+    direct_interc direct_interc_59_
+    (
+        .in(logical_tile_clb_mode_default__fle_3_fle_reg_out),
+        .out(direct_interc_59_out)
+    );
+    direct_interc direct_interc_5_
+    (
+        .in(logical_tile_clb_mode_default__fle_2_fle_out[0]),
+        .out(clb_O[5])
+    );
+    direct_interc direct_interc_60_
+    (
+        .in(logical_tile_clb_mode_default__fle_3_fle_sc_out),
+        .out(direct_interc_60_out)
+    );
+    direct_interc direct_interc_61_
+    (
+        .in(logical_tile_clb_mode_default__fle_3_fle_cout),
+        .out(direct_interc_61_out)
+    );
+    direct_interc direct_interc_62_
+    (
+        .in(clb_reset),
+        .out(direct_interc_62_out)
+    );
+    direct_interc direct_interc_63_
+    (
+        .in(clb_clk),
+        .out(direct_interc_63_out)
+    );
+    direct_interc direct_interc_64_
+    (
+        .in(clb_I5[0]),
+        .out(direct_interc_64_out)
+    );
+    direct_interc direct_interc_65_
+    (
+        .in(clb_I5[1]),
+        .out(direct_interc_65_out)
+    );
+    direct_interc direct_interc_66_
+    (
+        .in(clb_I5i[0]),
+        .out(direct_interc_66_out)
+    );
+    direct_interc direct_interc_67_
+    (
+        .in(clb_I5i[1]),
+        .out(direct_interc_67_out)
+    );
+    direct_interc direct_interc_68_
+    (
+        .in(logical_tile_clb_mode_default__fle_4_fle_reg_out),
+        .out(direct_interc_68_out)
+    );
+    direct_interc direct_interc_69_
+    (
+        .in(logical_tile_clb_mode_default__fle_4_fle_sc_out),
+        .out(direct_interc_69_out)
+    );
+    direct_interc direct_interc_6_
+    (
+        .in(logical_tile_clb_mode_default__fle_3_fle_out[1]),
+        .out(clb_O[6])
+    );
+    direct_interc direct_interc_70_
+    (
+        .in(logical_tile_clb_mode_default__fle_4_fle_cout),
+        .out(direct_interc_70_out)
+    );
+    direct_interc direct_interc_71_
+    (
+        .in(clb_reset),
+        .out(direct_interc_71_out)
+    );
+    direct_interc direct_interc_72_
+    (
+        .in(clb_clk),
+        .out(direct_interc_72_out)
+    );
+    direct_interc direct_interc_73_
+    (
+        .in(clb_I6[0]),
+        .out(direct_interc_73_out)
+    );
+    direct_interc direct_interc_74_
+    (
+        .in(clb_I6[1]),
+        .out(direct_interc_74_out)
+    );
+    direct_interc direct_interc_75_
+    (
+        .in(clb_I6i[0]),
+        .out(direct_interc_75_out)
+    );
+    direct_interc direct_interc_76_
+    (
+        .in(clb_I6i[1]),
+        .out(direct_interc_76_out)
+    );
+    direct_interc direct_interc_77_
+    (
+        .in(logical_tile_clb_mode_default__fle_5_fle_reg_out),
+        .out(direct_interc_77_out)
+    );
+    direct_interc direct_interc_78_
+    (
+        .in(logical_tile_clb_mode_default__fle_5_fle_sc_out),
+        .out(direct_interc_78_out)
+    );
+    direct_interc direct_interc_79_
+    (
+        .in(logical_tile_clb_mode_default__fle_5_fle_cout),
+        .out(direct_interc_79_out)
+    );
+    direct_interc direct_interc_7_
+    (
+        .in(logical_tile_clb_mode_default__fle_3_fle_out[0]),
+        .out(clb_O[7])
+    );
+    direct_interc direct_interc_80_
+    (
+        .in(clb_reset),
+        .out(direct_interc_80_out)
+    );
+    direct_interc direct_interc_81_
+    (
+        .in(clb_clk),
+        .out(direct_interc_81_out)
+    );
+    direct_interc direct_interc_82_
+    (
+        .in(clb_I7[0]),
+        .out(direct_interc_82_out)
+    );
+    direct_interc direct_interc_83_
+    (
+        .in(clb_I7[1]),
+        .out(direct_interc_83_out)
+    );
+    direct_interc direct_interc_84_
+    (
+        .in(clb_I7i[0]),
+        .out(direct_interc_84_out)
+    );
+    direct_interc direct_interc_85_
+    (
+        .in(clb_I7i[1]),
+        .out(direct_interc_85_out)
+    );
+    direct_interc direct_interc_86_
+    (
+        .in(logical_tile_clb_mode_default__fle_6_fle_reg_out),
+        .out(direct_interc_86_out)
+    );
+    direct_interc direct_interc_87_
+    (
+        .in(logical_tile_clb_mode_default__fle_6_fle_sc_out),
+        .out(direct_interc_87_out)
+    );
+    direct_interc direct_interc_88_
+    (
+        .in(logical_tile_clb_mode_default__fle_6_fle_cout),
+        .out(direct_interc_88_out)
+    );
+    direct_interc direct_interc_89_
+    (
+        .in(clb_reset),
+        .out(direct_interc_89_out)
+    );
+    direct_interc direct_interc_8_
+    (
+        .in(logical_tile_clb_mode_default__fle_4_fle_out[1]),
+        .out(clb_O[8])
+    );
+    direct_interc direct_interc_90_
+    (
+        .in(clb_clk),
+        .out(direct_interc_90_out)
+    );
+    direct_interc direct_interc_9_
+    (
+        .in(logical_tile_clb_mode_default__fle_4_fle_out[0]),
+        .out(clb_O[9])
+    );
+    logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0
+    (
+        .Test_en(Test_en),
+        .ccff_head(ccff_head),
+        .fle_cin(direct_interc_25_out),
+        .fle_clk(direct_interc_27_out),
+        .fle_in({direct_interc_19_out, direct_interc_20_out, direct_interc_21_out, direct_interc_22_out}),
+        .fle_reg_in(direct_interc_23_out),
+        .fle_reset(direct_interc_26_out),
+        .fle_sc_in(direct_interc_24_out),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail),
+        .fle_cout(logical_tile_clb_mode_default__fle_0_fle_cout),
+        .fle_out(logical_tile_clb_mode_default__fle_0_fle_out),
+        .fle_reg_out(logical_tile_clb_mode_default__fle_0_fle_reg_out),
+        .fle_sc_out(logical_tile_clb_mode_default__fle_0_fle_sc_out)
+    );
+    logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1
+    (
+        .Test_en(Test_en),
+        .ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail),
+        .fle_cin(direct_interc_34_out),
+        .fle_clk(direct_interc_36_out),
+        .fle_in({direct_interc_28_out, direct_interc_29_out, direct_interc_30_out, direct_interc_31_out}),
+        .fle_reg_in(direct_interc_32_out),
+        .fle_reset(direct_interc_35_out),
+        .fle_sc_in(direct_interc_33_out),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail),
+        .fle_cout(logical_tile_clb_mode_default__fle_1_fle_cout),
+        .fle_out(logical_tile_clb_mode_default__fle_1_fle_out),
+        .fle_reg_out(logical_tile_clb_mode_default__fle_1_fle_reg_out),
+        .fle_sc_out(logical_tile_clb_mode_default__fle_1_fle_sc_out)
+    );
+    logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2
+    (
+        .Test_en(Test_en),
+        .ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail),
+        .fle_cin(direct_interc_43_out),
+        .fle_clk(direct_interc_45_out),
+        .fle_in({direct_interc_37_out, direct_interc_38_out, direct_interc_39_out, direct_interc_40_out}),
+        .fle_reg_in(direct_interc_41_out),
+        .fle_reset(direct_interc_44_out),
+        .fle_sc_in(direct_interc_42_out),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail),
+        .fle_cout(logical_tile_clb_mode_default__fle_2_fle_cout),
+        .fle_out(logical_tile_clb_mode_default__fle_2_fle_out),
+        .fle_reg_out(logical_tile_clb_mode_default__fle_2_fle_reg_out),
+        .fle_sc_out(logical_tile_clb_mode_default__fle_2_fle_sc_out)
+    );
+    logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3
+    (
+        .Test_en(Test_en),
+        .ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail),
+        .fle_cin(direct_interc_52_out),
+        .fle_clk(direct_interc_54_out),
+        .fle_in({direct_interc_46_out, direct_interc_47_out, direct_interc_48_out, direct_interc_49_out}),
+        .fle_reg_in(direct_interc_50_out),
+        .fle_reset(direct_interc_53_out),
+        .fle_sc_in(direct_interc_51_out),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail),
+        .fle_cout(logical_tile_clb_mode_default__fle_3_fle_cout),
+        .fle_out(logical_tile_clb_mode_default__fle_3_fle_out),
+        .fle_reg_out(logical_tile_clb_mode_default__fle_3_fle_reg_out),
+        .fle_sc_out(logical_tile_clb_mode_default__fle_3_fle_sc_out)
+    );
+    logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4
+    (
+        .Test_en(Test_en),
+        .ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail),
+        .fle_cin(direct_interc_61_out),
+        .fle_clk(direct_interc_63_out),
+        .fle_in({direct_interc_55_out, direct_interc_56_out, direct_interc_57_out, direct_interc_58_out}),
+        .fle_reg_in(direct_interc_59_out),
+        .fle_reset(direct_interc_62_out),
+        .fle_sc_in(direct_interc_60_out),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail),
+        .fle_cout(logical_tile_clb_mode_default__fle_4_fle_cout),
+        .fle_out(logical_tile_clb_mode_default__fle_4_fle_out),
+        .fle_reg_out(logical_tile_clb_mode_default__fle_4_fle_reg_out),
+        .fle_sc_out(logical_tile_clb_mode_default__fle_4_fle_sc_out)
+    );
+    logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5
+    (
+        .Test_en(Test_en),
+        .ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail),
+        .fle_cin(direct_interc_70_out),
+        .fle_clk(direct_interc_72_out),
+        .fle_in({direct_interc_64_out, direct_interc_65_out, direct_interc_66_out, direct_interc_67_out}),
+        .fle_reg_in(direct_interc_68_out),
+        .fle_reset(direct_interc_71_out),
+        .fle_sc_in(direct_interc_69_out),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail),
+        .fle_cout(logical_tile_clb_mode_default__fle_5_fle_cout),
+        .fle_out(logical_tile_clb_mode_default__fle_5_fle_out),
+        .fle_reg_out(logical_tile_clb_mode_default__fle_5_fle_reg_out),
+        .fle_sc_out(logical_tile_clb_mode_default__fle_5_fle_sc_out)
+    );
+    logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6
+    (
+        .Test_en(Test_en),
+        .ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail),
+        .fle_cin(direct_interc_79_out),
+        .fle_clk(direct_interc_81_out),
+        .fle_in({direct_interc_73_out, direct_interc_74_out, direct_interc_75_out, direct_interc_76_out}),
+        .fle_reg_in(direct_interc_77_out),
+        .fle_reset(direct_interc_80_out),
+        .fle_sc_in(direct_interc_78_out),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail),
+        .fle_cout(logical_tile_clb_mode_default__fle_6_fle_cout),
+        .fle_out(logical_tile_clb_mode_default__fle_6_fle_out),
+        .fle_reg_out(logical_tile_clb_mode_default__fle_6_fle_reg_out),
+        .fle_sc_out(logical_tile_clb_mode_default__fle_6_fle_sc_out)
+    );
+    logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7
+    (
+        .Test_en(Test_en),
+        .ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail),
+        .fle_cin(direct_interc_88_out),
+        .fle_clk(direct_interc_90_out),
+        .fle_in({direct_interc_82_out, direct_interc_83_out, direct_interc_84_out, direct_interc_85_out}),
+        .fle_reg_in(direct_interc_86_out),
+        .fle_reset(direct_interc_89_out),
+        .fle_sc_in(direct_interc_87_out),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .fle_cout(logical_tile_clb_mode_default__fle_7_fle_cout),
+        .fle_out(logical_tile_clb_mode_default__fle_7_fle_out),
+        .fle_reg_out(logical_tile_clb_mode_default__fle_7_fle_reg_out),
+        .fle_sc_out(logical_tile_clb_mode_default__fle_7_fle_sc_out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle.v

@@ -0,0 +1,156 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module logical_tile_clb_mode_default__fle
+(
+    Test_en,
+    ccff_head,
+    fle_cin,
+    fle_clk,
+    fle_in,
+    fle_reg_in,
+    fle_reset,
+    fle_sc_in,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    fle_cout,
+    fle_out,
+    fle_reg_out,
+    fle_sc_out
+);
+
+    input Test_en;
+    input ccff_head;
+    input fle_cin;
+    input fle_clk;
+    input [0:3]fle_in;
+    input fle_reg_in;
+    input fle_reset;
+    input fle_sc_in;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output fle_cout;
+    output [0:1]fle_out;
+    output fle_reg_out;
+    output fle_sc_out;
+
+    wire Test_en;
+    wire ccff_head;
+    wire ccff_tail;
+    wire direct_interc_10_out;
+    wire direct_interc_11_out;
+    wire direct_interc_12_out;
+    wire direct_interc_13_out;
+    wire direct_interc_5_out;
+    wire direct_interc_6_out;
+    wire direct_interc_7_out;
+    wire direct_interc_8_out;
+    wire direct_interc_9_out;
+    wire fle_cin;
+    wire fle_clk;
+    wire fle_cout;
+    wire [0:3]fle_in;
+    wire [0:1]fle_out;
+    wire fle_reg_in;
+    wire fle_reg_out;
+    wire fle_reset;
+    wire fle_sc_in;
+    wire fle_sc_out;
+    wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout;
+    wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out;
+    wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out;
+    wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out;
+    wire pReset;
+    wire prog_clk;
+
+    direct_interc direct_interc_0_
+    (
+        .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0]),
+        .out(fle_out[0])
+    );
+    direct_interc direct_interc_10_
+    (
+        .in(fle_sc_in),
+        .out(direct_interc_10_out)
+    );
+    direct_interc direct_interc_11_
+    (
+        .in(fle_cin),
+        .out(direct_interc_11_out)
+    );
+    direct_interc direct_interc_12_
+    (
+        .in(fle_reset),
+        .out(direct_interc_12_out)
+    );
+    direct_interc direct_interc_13_
+    (
+        .in(fle_clk),
+        .out(direct_interc_13_out)
+    );
+    direct_interc direct_interc_1_
+    (
+        .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[1]),
+        .out(fle_out[1])
+    );
+    direct_interc direct_interc_2_
+    (
+        .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out),
+        .out(fle_reg_out)
+    );
+    direct_interc direct_interc_3_
+    (
+        .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out),
+        .out(fle_sc_out)
+    );
+    direct_interc direct_interc_4_
+    (
+        .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout),
+        .out(fle_cout)
+    );
+    direct_interc direct_interc_5_
+    (
+        .in(fle_in[0]),
+        .out(direct_interc_5_out)
+    );
+    direct_interc direct_interc_6_
+    (
+        .in(fle_in[1]),
+        .out(direct_interc_6_out)
+    );
+    direct_interc direct_interc_7_
+    (
+        .in(fle_in[2]),
+        .out(direct_interc_7_out)
+    );
+    direct_interc direct_interc_8_
+    (
+        .in(fle_in[3]),
+        .out(direct_interc_8_out)
+    );
+    direct_interc direct_interc_9_
+    (
+        .in(fle_reg_in),
+        .out(direct_interc_9_out)
+    );
+    logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0
+    (
+        .Test_en(Test_en),
+        .ccff_head(ccff_head),
+        .fabric_cin(direct_interc_11_out),
+        .fabric_clk(direct_interc_13_out),
+        .fabric_in({direct_interc_5_out, direct_interc_6_out, direct_interc_7_out, direct_interc_8_out}),
+        .fabric_reg_in(direct_interc_9_out),
+        .fabric_reset(direct_interc_12_out),
+        .fabric_sc_in(direct_interc_10_out),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .fabric_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout),
+        .fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out),
+        .fabric_reg_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out),
+        .fabric_sc_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric.v

@@ -0,0 +1,243 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module logical_tile_clb_mode_default__fle_mode_physical__fabric
+(
+    Test_en,
+    ccff_head,
+    fabric_cin,
+    fabric_clk,
+    fabric_in,
+    fabric_reg_in,
+    fabric_reset,
+    fabric_sc_in,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    fabric_cout,
+    fabric_out,
+    fabric_reg_out,
+    fabric_sc_out
+);
+
+    input Test_en;
+    input ccff_head;
+    input fabric_cin;
+    input fabric_clk;
+    input [0:3]fabric_in;
+    input fabric_reg_in;
+    input fabric_reset;
+    input fabric_sc_in;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output fabric_cout;
+    output [0:1]fabric_out;
+    output fabric_reg_out;
+    output fabric_sc_out;
+
+    wire Test_en;
+    wire ccff_head;
+    wire ccff_tail;
+    wire direct_interc_10_out;
+    wire direct_interc_11_out;
+    wire direct_interc_12_out;
+    wire direct_interc_13_out;
+    wire direct_interc_3_out;
+    wire direct_interc_4_out;
+    wire direct_interc_5_out;
+    wire direct_interc_6_out;
+    wire direct_interc_7_out;
+    wire direct_interc_8_out;
+    wire direct_interc_9_out;
+    wire fabric_cin;
+    wire fabric_clk;
+    wire fabric_cout;
+    wire [0:3]fabric_in;
+    wire [0:1]fabric_out;
+    wire fabric_reg_in;
+    wire fabric_reg_out;
+    wire fabric_reset;
+    wire fabric_sc_in;
+    wire fabric_sc_out;
+    wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q;
+    wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q;
+    wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail;
+    wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout;
+    wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out;
+    wire [0:1]mux_fabric_out_0_undriven_sram_inv;
+    wire [0:1]mux_fabric_out_1_undriven_sram_inv;
+    wire [0:1]mux_ff_0_D_0_undriven_sram_inv;
+    wire [0:1]mux_ff_1_D_0_undriven_sram_inv;
+    wire [0:1]mux_tree_size2_0_sram;
+    wire [0:1]mux_tree_size2_1_sram;
+    wire mux_tree_size2_2_out;
+    wire [0:1]mux_tree_size2_2_sram;
+    wire mux_tree_size2_3_out;
+    wire [0:1]mux_tree_size2_3_sram;
+    wire mux_tree_size2_mem_0_ccff_tail;
+    wire mux_tree_size2_mem_1_ccff_tail;
+    wire mux_tree_size2_mem_2_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+
+    direct_interc direct_interc_0_
+    (
+        .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q),
+        .out(fabric_reg_out)
+    );
+    direct_interc direct_interc_10_
+    (
+        .in(fabric_clk),
+        .out(direct_interc_10_out)
+    );
+    direct_interc direct_interc_11_
+    (
+        .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q),
+        .out(direct_interc_11_out)
+    );
+    direct_interc direct_interc_12_
+    (
+        .in(fabric_reset),
+        .out(direct_interc_12_out)
+    );
+    direct_interc direct_interc_13_
+    (
+        .in(fabric_clk),
+        .out(direct_interc_13_out)
+    );
+    direct_interc direct_interc_1_
+    (
+        .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q),
+        .out(fabric_sc_out)
+    );
+    direct_interc direct_interc_2_
+    (
+        .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout),
+        .out(fabric_cout)
+    );
+    direct_interc direct_interc_3_
+    (
+        .in(fabric_in[0]),
+        .out(direct_interc_3_out)
+    );
+    direct_interc direct_interc_4_
+    (
+        .in(fabric_in[1]),
+        .out(direct_interc_4_out)
+    );
+    direct_interc direct_interc_5_
+    (
+        .in(fabric_in[2]),
+        .out(direct_interc_5_out)
+    );
+    direct_interc direct_interc_6_
+    (
+        .in(fabric_in[3]),
+        .out(direct_interc_6_out)
+    );
+    direct_interc direct_interc_7_
+    (
+        .in(fabric_cin),
+        .out(direct_interc_7_out)
+    );
+    direct_interc direct_interc_8_
+    (
+        .in(fabric_sc_in),
+        .out(direct_interc_8_out)
+    );
+    direct_interc direct_interc_9_
+    (
+        .in(fabric_reset),
+        .out(direct_interc_9_out)
+    );
+    logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0
+    (
+        .Test_en(Test_en),
+        .ff_D(mux_tree_size2_2_out),
+        .ff_DI(direct_interc_8_out),
+        .ff_clk(direct_interc_10_out),
+        .ff_reset(direct_interc_9_out),
+        .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q)
+    );
+    logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1
+    (
+        .Test_en(Test_en),
+        .ff_D(mux_tree_size2_3_out),
+        .ff_DI(direct_interc_11_out),
+        .ff_clk(direct_interc_13_out),
+        .ff_reset(direct_interc_12_out),
+        .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q)
+    );
+    logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0
+    (
+        .ccff_head(ccff_head),
+        .frac_logic_cin(direct_interc_7_out),
+        .frac_logic_in({direct_interc_3_out, direct_interc_4_out, direct_interc_5_out, direct_interc_6_out}),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail),
+        .frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout),
+        .frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out)
+    );
+    mux_tree_size2_mem mem_fabric_out_0
+    (
+        .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_size2_mem_0_ccff_tail),
+        .mem_out(mux_tree_size2_0_sram)
+    );
+    mux_tree_size2_mem mem_fabric_out_1
+    (
+        .ccff_head(mux_tree_size2_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_size2_mem_1_ccff_tail),
+        .mem_out(mux_tree_size2_1_sram)
+    );
+    mux_tree_size2_mem mem_ff_0_D_0
+    (
+        .ccff_head(mux_tree_size2_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_size2_mem_2_ccff_tail),
+        .mem_out(mux_tree_size2_2_sram)
+    );
+    mux_tree_size2_mem mem_ff_1_D_0
+    (
+        .ccff_head(mux_tree_size2_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .mem_out(mux_tree_size2_3_sram)
+    );
+    mux_tree_size2 mux_fabric_out_0
+    (
+        .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}),
+        .sram(mux_tree_size2_0_sram),
+        .sram_inv(mux_fabric_out_0_undriven_sram_inv),
+        .out(fabric_out[0])
+    );
+    mux_tree_size2 mux_fabric_out_1
+    (
+        .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}),
+        .sram(mux_tree_size2_1_sram),
+        .sram_inv(mux_fabric_out_1_undriven_sram_inv),
+        .out(fabric_out[1])
+    );
+    mux_tree_size2 mux_ff_0_D_0
+    (
+        .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_reg_in}),
+        .sram(mux_tree_size2_2_sram),
+        .sram_inv(mux_ff_0_D_0_undriven_sram_inv),
+        .out(mux_tree_size2_2_out)
+    );
+    mux_tree_size2 mux_ff_1_D_0
+    (
+        .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q}),
+        .sram(mux_tree_size2_3_sram),
+        .sram_inv(mux_ff_1_D_0_undriven_sram_inv),
+        .out(mux_tree_size2_3_out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v

@@ -0,0 +1,37 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
+(
+    Test_en,
+    ff_D,
+    ff_DI,
+    ff_clk,
+    ff_reset,
+    ff_Q
+);
+
+    input Test_en;
+    input ff_D;
+    input ff_DI;
+    input ff_clk;
+    input ff_reset;
+    output ff_Q;
+
+    wire Test_en;
+    wire ff_D;
+    wire ff_DI;
+    wire ff_Q;
+    wire ff_clk;
+    wire ff_reset;
+
+    sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_
+    (
+        .CLK(ff_clk),
+        .D(ff_D),
+        .RESET_B(ff_reset),
+        .SCD(ff_DI),
+        .SCE(Test_en),
+        .Q(ff_Q)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v

@@ -0,0 +1,139 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic
+(
+    ccff_head,
+    frac_logic_cin,
+    frac_logic_in,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    frac_logic_cout,
+    frac_logic_out
+);
+
+    input ccff_head;
+    input frac_logic_cin;
+    input [0:3]frac_logic_in;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output frac_logic_cout;
+    output [0:1]frac_logic_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire direct_interc_2_out;
+    wire direct_interc_3_out;
+    wire direct_interc_4_out;
+    wire direct_interc_5_out;
+    wire direct_interc_6_out;
+    wire direct_interc_7_out;
+    wire frac_logic_cin;
+    wire frac_logic_cout;
+    wire [0:3]frac_logic_in;
+    wire [0:1]frac_logic_out;
+    wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout;
+    wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail;
+    wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out;
+    wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out;
+    wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out;
+    wire [0:1]mux_frac_logic_out_0_undriven_sram_inv;
+    wire [0:1]mux_frac_lut4_0_in_2_undriven_sram_inv;
+    wire [0:1]mux_tree_size2_0_sram;
+    wire mux_tree_size2_1_out;
+    wire [0:1]mux_tree_size2_1_sram;
+    wire mux_tree_size2_mem_0_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+
+    direct_interc direct_interc_0_
+    (
+        .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]),
+        .out(frac_logic_out[1])
+    );
+    direct_interc direct_interc_1_
+    (
+        .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout),
+        .out(frac_logic_cout)
+    );
+    direct_interc direct_interc_2_
+    (
+        .in(frac_logic_in[0]),
+        .out(direct_interc_2_out)
+    );
+    direct_interc direct_interc_3_
+    (
+        .in(frac_logic_in[1]),
+        .out(direct_interc_3_out)
+    );
+    direct_interc direct_interc_4_
+    (
+        .in(frac_logic_in[3]),
+        .out(direct_interc_4_out)
+    );
+    direct_interc direct_interc_5_
+    (
+        .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[1]),
+        .out(direct_interc_5_out)
+    );
+    direct_interc direct_interc_6_
+    (
+        .in(frac_logic_cin),
+        .out(direct_interc_6_out)
+    );
+    direct_interc direct_interc_7_
+    (
+        .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[0]),
+        .out(direct_interc_7_out)
+    );
+    logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0
+    (
+        .carry_follower_a(direct_interc_5_out),
+        .carry_follower_b(direct_interc_6_out),
+        .carry_follower_cin(direct_interc_7_out),
+        .carry_follower_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout)
+    );
+    logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0
+    (
+        .ccff_head(ccff_head),
+        .frac_lut4_in({direct_interc_2_out, direct_interc_3_out, mux_tree_size2_1_out, direct_interc_4_out}),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail),
+        .frac_lut4_lut2_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out),
+        .frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out),
+        .frac_lut4_lut4_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out)
+    );
+    mux_tree_size2_mem mem_frac_logic_out_0
+    (
+        .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_size2_mem_0_ccff_tail),
+        .mem_out(mux_tree_size2_0_sram)
+    );
+    mux_tree_size2_mem mem_frac_lut4_0_in_2
+    (
+        .ccff_head(mux_tree_size2_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .mem_out(mux_tree_size2_1_sram)
+    );
+    mux_tree_size2 mux_frac_logic_out_0
+    (
+        .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}),
+        .sram(mux_tree_size2_0_sram),
+        .sram_inv(mux_frac_logic_out_0_undriven_sram_inv),
+        .out(frac_logic_out[0])
+    );
+    mux_tree_size2 mux_frac_lut4_0_in_2
+    (
+        .in({frac_logic_cin, frac_logic_in[2]}),
+        .sram(mux_tree_size2_1_sram),
+        .sram_inv(mux_frac_lut4_0_in_2_undriven_sram_inv),
+        .out(mux_tree_size2_1_out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v

@@ -0,0 +1,29 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower
+(
+    carry_follower_a,
+    carry_follower_b,
+    carry_follower_cin,
+    carry_follower_cout
+);
+
+    input carry_follower_a;
+    input carry_follower_b;
+    input carry_follower_cin;
+    output carry_follower_cout;
+
+    wire carry_follower_a;
+    wire carry_follower_b;
+    wire carry_follower_cin;
+    wire carry_follower_cout;
+
+    sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_
+    (
+        .A0(carry_follower_a),
+        .A1(carry_follower_b),
+        .S(carry_follower_cin),
+        .X(carry_follower_cout)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v

@@ -0,0 +1,57 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4
+(
+    ccff_head,
+    frac_lut4_in,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    frac_lut4_lut2_out,
+    frac_lut4_lut3_out,
+    frac_lut4_lut4_out
+);
+
+    input ccff_head;
+    input [0:3]frac_lut4_in;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:1]frac_lut4_lut2_out;
+    output [0:1]frac_lut4_lut3_out;
+    output frac_lut4_lut4_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire frac_lut4_0__undriven_mode_inv;
+    wire [0:15]frac_lut4_0__undriven_sram_inv;
+    wire frac_lut4_0_mode;
+    wire [0:15]frac_lut4_0_sram;
+    wire [0:3]frac_lut4_in;
+    wire [0:1]frac_lut4_lut2_out;
+    wire [0:1]frac_lut4_lut3_out;
+    wire frac_lut4_lut4_out;
+    wire pReset;
+    wire prog_clk;
+
+    frac_lut4 frac_lut4_0_
+    (
+        .in(frac_lut4_in),
+        .mode(frac_lut4_0_mode),
+        .mode_inv(frac_lut4_0__undriven_mode_inv),
+        .sram(frac_lut4_0_sram),
+        .sram_inv(frac_lut4_0__undriven_sram_inv),
+        .lut2_out(frac_lut4_lut2_out),
+        .lut3_out(frac_lut4_lut3_out),
+        .lut4_out(frac_lut4_lut4_out)
+    );
+    frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
+    (
+        .ccff_head(ccff_head),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .mem_out({frac_lut4_0_sram[0], frac_lut4_0_sram[1], frac_lut4_0_sram[2], frac_lut4_0_sram[3], frac_lut4_0_sram[4], frac_lut4_0_sram[5], frac_lut4_0_sram[6], frac_lut4_0_sram[7], frac_lut4_0_sram[8], frac_lut4_0_sram[9], frac_lut4_0_sram[10], frac_lut4_0_sram[11], frac_lut4_0_sram[12], frac_lut4_0_sram[13], frac_lut4_0_sram[14], frac_lut4_0_sram[15], frac_lut4_0_mode})
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_io_.v

@@ -0,0 +1,65 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module logical_tile_io_mode_io_
+(
+    IO_ISOL_N,
+    ccff_head,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
+    io_outpad,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    io_inpad
+);
+
+    input IO_ISOL_N;
+    input ccff_head;
+    input gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    input io_outpad;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output io_inpad;
+
+    wire IO_ISOL_N;
+    wire ccff_head;
+    wire ccff_tail;
+    wire direct_interc_1_out;
+    wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire io_inpad;
+    wire io_outpad;
+    wire logical_tile_io_mode_physical__iopad_0_iopad_inpad;
+    wire pReset;
+    wire prog_clk;
+
+    direct_interc direct_interc_0_
+    (
+        .in(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
+        .out(io_inpad)
+    );
+    direct_interc direct_interc_1_
+    (
+        .in(io_outpad),
+        .out(direct_interc_1_out)
+    );
+    logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0
+    (
+        .IO_ISOL_N(IO_ISOL_N),
+        .ccff_head(ccff_head),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
+        .iopad_outpad(direct_interc_1_out),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
+        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
+        .iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_physical__iopad.v

@@ -0,0 +1,59 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module logical_tile_io_mode_physical__iopad
+(
+    IO_ISOL_N,
+    ccff_head,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
+    iopad_outpad,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    iopad_inpad
+);
+
+    input IO_ISOL_N;
+    input ccff_head;
+    input gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    input iopad_outpad;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output iopad_inpad;
+
+    wire EMBEDDED_IO_HD_0_en;
+    wire IO_ISOL_N;
+    wire ccff_head;
+    wire ccff_tail;
+    wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire iopad_inpad;
+    wire iopad_outpad;
+    wire pReset;
+    wire prog_clk;
+
+    EMBEDDED_IO_HD EMBEDDED_IO_HD_0_
+    (
+        .FPGA_DIR(EMBEDDED_IO_HD_0_en),
+        .FPGA_OUT(iopad_outpad),
+        .IO_ISOL_N(IO_ISOL_N),
+        .SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
+        .FPGA_IN(iopad_inpad),
+        .SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
+        .SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT)
+    );
+    EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem
+    (
+        .ccff_head(ccff_head),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .mem_out(EMBEDDED_IO_HD_0_en)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_size2.v

@@ -0,0 +1,42 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_size2
+(
+    in,
+    sram,
+    sram_inv,
+    out
+);
+
+    input [0:1]in;
+    input [0:1]sram;
+    input [0:1]sram_inv;
+    output out;
+
+    wire const1_0_const1;
+    wire [0:1]in;
+    wire out;
+    wire sky130_fd_sc_hd__mux2_1_0_X;
+    wire [0:1]sram;
+    wire [0:1]sram_inv;
+
+    const1 const1_0_
+    (
+        .const1(const1_0_const1)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
+    (
+        .A0(in[1]),
+        .A1(in[0]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_0_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
+    (
+        .A0(const1_0_const1),
+        .A1(sky130_fd_sc_hd__mux2_1_0_X),
+        .S(sram[1]),
+        .X(out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_size2_mem.v

@@ -0,0 +1,40 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_size2_mem
+(
+    ccff_head,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    mem_out
+);
+
+    input ccff_head;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:1]mem_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:1]mem_out;
+    wire pReset;
+    wire prog_clk;
+
+assign ccff_tail = mem_out[1];
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
+    (
+        .CLK(prog_clk),
+        .D(ccff_head),
+        .RESET_B(pReset),
+        .Q(mem_out[0])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[0]),
+        .RESET_B(pReset),
+        .Q(mem_out[1])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size10.v

@@ -0,0 +1,112 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size10
+(
+    in,
+    sram,
+    sram_inv,
+    out
+);
+
+    input [0:9]in;
+    input [0:3]sram;
+    input [0:3]sram_inv;
+    output out;
+
+    wire const1_0_const1;
+    wire [0:9]in;
+    wire out;
+    wire sky130_fd_sc_hd__mux2_1_0_X;
+    wire sky130_fd_sc_hd__mux2_1_1_X;
+    wire sky130_fd_sc_hd__mux2_1_2_X;
+    wire sky130_fd_sc_hd__mux2_1_3_X;
+    wire sky130_fd_sc_hd__mux2_1_4_X;
+    wire sky130_fd_sc_hd__mux2_1_5_X;
+    wire sky130_fd_sc_hd__mux2_1_6_X;
+    wire sky130_fd_sc_hd__mux2_1_7_X;
+    wire sky130_fd_sc_hd__mux2_1_8_X;
+    wire sky130_fd_sc_hd__mux2_1_9_X;
+    wire [0:3]sram;
+    wire [0:3]sram_inv;
+
+    const1 const1_0_
+    (
+        .const1(const1_0_const1)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
+    (
+        .A0(in[1]),
+        .A1(in[0]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_0_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
+    (
+        .A0(in[3]),
+        .A1(in[2]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_1_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_2_
+    (
+        .A0(in[5]),
+        .A1(in[4]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_2_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_1_X),
+        .A1(sky130_fd_sc_hd__mux2_1_0_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_3_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
+    (
+        .A0(in[6]),
+        .A1(sky130_fd_sc_hd__mux2_1_2_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_4_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_2_
+    (
+        .A0(in[8]),
+        .A1(in[7]),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_5_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_3_
+    (
+        .A0(const1_0_const1),
+        .A1(in[9]),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_6_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_4_X),
+        .A1(sky130_fd_sc_hd__mux2_1_3_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_7_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_1_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_6_X),
+        .A1(sky130_fd_sc_hd__mux2_1_5_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_8_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l4_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_8_X),
+        .A1(sky130_fd_sc_hd__mux2_1_7_X),
+        .S(sram[3]),
+        .X(sky130_fd_sc_hd__mux2_1_9_X)
+    );
+    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_9_X),
+        .X(out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size10_mem.v

@@ -0,0 +1,54 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size10_mem
+(
+    ccff_head,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    mem_out
+);
+
+    input ccff_head;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:3]mem_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:3]mem_out;
+    wire pReset;
+    wire prog_clk;
+
+assign ccff_tail = mem_out[3];
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
+    (
+        .CLK(prog_clk),
+        .D(ccff_head),
+        .RESET_B(pReset),
+        .Q(mem_out[0])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[0]),
+        .RESET_B(pReset),
+        .Q(mem_out[1])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[1]),
+        .RESET_B(pReset),
+        .Q(mem_out[2])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[2]),
+        .RESET_B(pReset),
+        .Q(mem_out[3])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size11.v

@@ -0,0 +1,120 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size11
+(
+    in,
+    sram,
+    sram_inv,
+    out
+);
+
+    input [0:10]in;
+    input [0:3]sram;
+    input [0:3]sram_inv;
+    output out;
+
+    wire const1_0_const1;
+    wire [0:10]in;
+    wire out;
+    wire sky130_fd_sc_hd__mux2_1_0_X;
+    wire sky130_fd_sc_hd__mux2_1_10_X;
+    wire sky130_fd_sc_hd__mux2_1_1_X;
+    wire sky130_fd_sc_hd__mux2_1_2_X;
+    wire sky130_fd_sc_hd__mux2_1_3_X;
+    wire sky130_fd_sc_hd__mux2_1_4_X;
+    wire sky130_fd_sc_hd__mux2_1_5_X;
+    wire sky130_fd_sc_hd__mux2_1_6_X;
+    wire sky130_fd_sc_hd__mux2_1_7_X;
+    wire sky130_fd_sc_hd__mux2_1_8_X;
+    wire sky130_fd_sc_hd__mux2_1_9_X;
+    wire [0:3]sram;
+    wire [0:3]sram_inv;
+
+    const1 const1_0_
+    (
+        .const1(const1_0_const1)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
+    (
+        .A0(in[1]),
+        .A1(in[0]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_0_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
+    (
+        .A0(in[3]),
+        .A1(in[2]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_1_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_2_
+    (
+        .A0(in[5]),
+        .A1(in[4]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_2_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_3_
+    (
+        .A0(in[7]),
+        .A1(in[6]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_3_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_1_X),
+        .A1(sky130_fd_sc_hd__mux2_1_0_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_4_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_3_X),
+        .A1(sky130_fd_sc_hd__mux2_1_2_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_5_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_2_
+    (
+        .A0(in[9]),
+        .A1(in[8]),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_6_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_3_
+    (
+        .A0(const1_0_const1),
+        .A1(in[10]),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_7_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_5_X),
+        .A1(sky130_fd_sc_hd__mux2_1_4_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_8_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_1_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_7_X),
+        .A1(sky130_fd_sc_hd__mux2_1_6_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_9_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l4_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_9_X),
+        .A1(sky130_fd_sc_hd__mux2_1_8_X),
+        .S(sram[3]),
+        .X(sky130_fd_sc_hd__mux2_1_10_X)
+    );
+    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_10_X),
+        .X(out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size11_mem.v

@@ -0,0 +1,54 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size11_mem
+(
+    ccff_head,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    mem_out
+);
+
+    input ccff_head;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:3]mem_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:3]mem_out;
+    wire pReset;
+    wire prog_clk;
+
+assign ccff_tail = mem_out[3];
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
+    (
+        .CLK(prog_clk),
+        .D(ccff_head),
+        .RESET_B(pReset),
+        .Q(mem_out[0])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[0]),
+        .RESET_B(pReset),
+        .Q(mem_out[1])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[1]),
+        .RESET_B(pReset),
+        .Q(mem_out[2])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[2]),
+        .RESET_B(pReset),
+        .Q(mem_out[3])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size12.v

@@ -0,0 +1,128 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size12
+(
+    in,
+    sram,
+    sram_inv,
+    out
+);
+
+    input [0:11]in;
+    input [0:3]sram;
+    input [0:3]sram_inv;
+    output out;
+
+    wire const1_0_const1;
+    wire [0:11]in;
+    wire out;
+    wire sky130_fd_sc_hd__mux2_1_0_X;
+    wire sky130_fd_sc_hd__mux2_1_10_X;
+    wire sky130_fd_sc_hd__mux2_1_11_X;
+    wire sky130_fd_sc_hd__mux2_1_1_X;
+    wire sky130_fd_sc_hd__mux2_1_2_X;
+    wire sky130_fd_sc_hd__mux2_1_3_X;
+    wire sky130_fd_sc_hd__mux2_1_4_X;
+    wire sky130_fd_sc_hd__mux2_1_5_X;
+    wire sky130_fd_sc_hd__mux2_1_6_X;
+    wire sky130_fd_sc_hd__mux2_1_7_X;
+    wire sky130_fd_sc_hd__mux2_1_8_X;
+    wire sky130_fd_sc_hd__mux2_1_9_X;
+    wire [0:3]sram;
+    wire [0:3]sram_inv;
+
+    const1 const1_0_
+    (
+        .const1(const1_0_const1)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
+    (
+        .A0(in[1]),
+        .A1(in[0]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_0_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
+    (
+        .A0(in[3]),
+        .A1(in[2]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_1_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_2_
+    (
+        .A0(in[5]),
+        .A1(in[4]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_2_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_3_
+    (
+        .A0(in[7]),
+        .A1(in[6]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_3_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_4_
+    (
+        .A0(in[9]),
+        .A1(in[8]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_4_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_1_X),
+        .A1(sky130_fd_sc_hd__mux2_1_0_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_5_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_3_X),
+        .A1(sky130_fd_sc_hd__mux2_1_2_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_6_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_2_
+    (
+        .A0(in[10]),
+        .A1(sky130_fd_sc_hd__mux2_1_4_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_7_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_3_
+    (
+        .A0(const1_0_const1),
+        .A1(in[11]),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_8_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_6_X),
+        .A1(sky130_fd_sc_hd__mux2_1_5_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_9_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_1_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_8_X),
+        .A1(sky130_fd_sc_hd__mux2_1_7_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_10_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l4_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_10_X),
+        .A1(sky130_fd_sc_hd__mux2_1_9_X),
+        .S(sram[3]),
+        .X(sky130_fd_sc_hd__mux2_1_11_X)
+    );
+    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_11_X),
+        .X(out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size12_mem.v

@@ -0,0 +1,54 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size12_mem
+(
+    ccff_head,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    mem_out
+);
+
+    input ccff_head;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:3]mem_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:3]mem_out;
+    wire pReset;
+    wire prog_clk;
+
+assign ccff_tail = mem_out[3];
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
+    (
+        .CLK(prog_clk),
+        .D(ccff_head),
+        .RESET_B(pReset),
+        .Q(mem_out[0])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[0]),
+        .RESET_B(pReset),
+        .Q(mem_out[1])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[1]),
+        .RESET_B(pReset),
+        .Q(mem_out[2])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[2]),
+        .RESET_B(pReset),
+        .Q(mem_out[3])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size2.v

@@ -0,0 +1,48 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size2
+(
+    in,
+    sram,
+    sram_inv,
+    out
+);
+
+    input [0:1]in;
+    input [0:1]sram;
+    input [0:1]sram_inv;
+    output out;
+
+    wire const1_0_const1;
+    wire [0:1]in;
+    wire out;
+    wire sky130_fd_sc_hd__mux2_1_0_X;
+    wire sky130_fd_sc_hd__mux2_1_1_X;
+    wire [0:1]sram;
+    wire [0:1]sram_inv;
+
+    const1 const1_0_
+    (
+        .const1(const1_0_const1)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
+    (
+        .A0(in[1]),
+        .A1(in[0]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_0_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
+    (
+        .A0(const1_0_const1),
+        .A1(sky130_fd_sc_hd__mux2_1_0_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_1_X)
+    );
+    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_1_X),
+        .X(out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size2_mem.v

@@ -0,0 +1,40 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size2_mem
+(
+    ccff_head,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    mem_out
+);
+
+    input ccff_head;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:1]mem_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:1]mem_out;
+    wire pReset;
+    wire prog_clk;
+
+assign ccff_tail = mem_out[1];
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
+    (
+        .CLK(prog_clk),
+        .D(ccff_head),
+        .RESET_B(pReset),
+        .Q(mem_out[0])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[0]),
+        .RESET_B(pReset),
+        .Q(mem_out[1])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size3.v

@@ -0,0 +1,56 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size3
+(
+    in,
+    sram,
+    sram_inv,
+    out
+);
+
+    input [0:2]in;
+    input [0:1]sram;
+    input [0:1]sram_inv;
+    output out;
+
+    wire const1_0_const1;
+    wire [0:2]in;
+    wire out;
+    wire sky130_fd_sc_hd__mux2_1_0_X;
+    wire sky130_fd_sc_hd__mux2_1_1_X;
+    wire sky130_fd_sc_hd__mux2_1_2_X;
+    wire [0:1]sram;
+    wire [0:1]sram_inv;
+
+    const1 const1_0_
+    (
+        .const1(const1_0_const1)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
+    (
+        .A0(in[1]),
+        .A1(in[0]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_0_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
+    (
+        .A0(const1_0_const1),
+        .A1(in[2]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_1_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_1_X),
+        .A1(sky130_fd_sc_hd__mux2_1_0_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_2_X)
+    );
+    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_2_X),
+        .X(out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size3_mem.v

@@ -0,0 +1,40 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size3_mem
+(
+    ccff_head,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    mem_out
+);
+
+    input ccff_head;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:1]mem_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:1]mem_out;
+    wire pReset;
+    wire prog_clk;
+
+assign ccff_tail = mem_out[1];
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
+    (
+        .CLK(prog_clk),
+        .D(ccff_head),
+        .RESET_B(pReset),
+        .Q(mem_out[0])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[0]),
+        .RESET_B(pReset),
+        .Q(mem_out[1])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size4.v

@@ -0,0 +1,64 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size4
+(
+    in,
+    sram,
+    sram_inv,
+    out
+);
+
+    input [0:3]in;
+    input [0:2]sram;
+    input [0:2]sram_inv;
+    output out;
+
+    wire const1_0_const1;
+    wire [0:3]in;
+    wire out;
+    wire sky130_fd_sc_hd__mux2_1_0_X;
+    wire sky130_fd_sc_hd__mux2_1_1_X;
+    wire sky130_fd_sc_hd__mux2_1_2_X;
+    wire sky130_fd_sc_hd__mux2_1_3_X;
+    wire [0:2]sram;
+    wire [0:2]sram_inv;
+
+    const1 const1_0_
+    (
+        .const1(const1_0_const1)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
+    (
+        .A0(in[1]),
+        .A1(in[0]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_0_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
+    (
+        .A0(in[2]),
+        .A1(sky130_fd_sc_hd__mux2_1_0_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_1_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
+    (
+        .A0(const1_0_const1),
+        .A1(in[3]),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_2_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_2_X),
+        .A1(sky130_fd_sc_hd__mux2_1_1_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_3_X)
+    );
+    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_3_X),
+        .X(out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size4_mem.v

@@ -0,0 +1,47 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size4_mem
+(
+    ccff_head,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    mem_out
+);
+
+    input ccff_head;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:2]mem_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:2]mem_out;
+    wire pReset;
+    wire prog_clk;
+
+assign ccff_tail = mem_out[2];
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
+    (
+        .CLK(prog_clk),
+        .D(ccff_head),
+        .RESET_B(pReset),
+        .Q(mem_out[0])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[0]),
+        .RESET_B(pReset),
+        .Q(mem_out[1])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[1]),
+        .RESET_B(pReset),
+        .Q(mem_out[2])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size5.v

@@ -0,0 +1,72 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size5
+(
+    in,
+    sram,
+    sram_inv,
+    out
+);
+
+    input [0:4]in;
+    input [0:2]sram;
+    input [0:2]sram_inv;
+    output out;
+
+    wire const1_0_const1;
+    wire [0:4]in;
+    wire out;
+    wire sky130_fd_sc_hd__mux2_1_0_X;
+    wire sky130_fd_sc_hd__mux2_1_1_X;
+    wire sky130_fd_sc_hd__mux2_1_2_X;
+    wire sky130_fd_sc_hd__mux2_1_3_X;
+    wire sky130_fd_sc_hd__mux2_1_4_X;
+    wire [0:2]sram;
+    wire [0:2]sram_inv;
+
+    const1 const1_0_
+    (
+        .const1(const1_0_const1)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
+    (
+        .A0(in[1]),
+        .A1(in[0]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_0_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
+    (
+        .A0(in[3]),
+        .A1(in[2]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_1_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_1_X),
+        .A1(sky130_fd_sc_hd__mux2_1_0_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_2_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
+    (
+        .A0(const1_0_const1),
+        .A1(in[4]),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_3_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_3_X),
+        .A1(sky130_fd_sc_hd__mux2_1_2_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_4_X)
+    );
+    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_4_X),
+        .X(out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size5_mem.v

@@ -0,0 +1,47 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size5_mem
+(
+    ccff_head,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    mem_out
+);
+
+    input ccff_head;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:2]mem_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:2]mem_out;
+    wire pReset;
+    wire prog_clk;
+
+assign ccff_tail = mem_out[2];
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
+    (
+        .CLK(prog_clk),
+        .D(ccff_head),
+        .RESET_B(pReset),
+        .Q(mem_out[0])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[0]),
+        .RESET_B(pReset),
+        .Q(mem_out[1])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[1]),
+        .RESET_B(pReset),
+        .Q(mem_out[2])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size6.v

@@ -0,0 +1,80 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size6
+(
+    in,
+    sram,
+    sram_inv,
+    out
+);
+
+    input [0:5]in;
+    input [0:2]sram;
+    input [0:2]sram_inv;
+    output out;
+
+    wire const1_0_const1;
+    wire [0:5]in;
+    wire out;
+    wire sky130_fd_sc_hd__mux2_1_0_X;
+    wire sky130_fd_sc_hd__mux2_1_1_X;
+    wire sky130_fd_sc_hd__mux2_1_2_X;
+    wire sky130_fd_sc_hd__mux2_1_3_X;
+    wire sky130_fd_sc_hd__mux2_1_4_X;
+    wire sky130_fd_sc_hd__mux2_1_5_X;
+    wire [0:2]sram;
+    wire [0:2]sram_inv;
+
+    const1 const1_0_
+    (
+        .const1(const1_0_const1)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
+    (
+        .A0(in[1]),
+        .A1(in[0]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_0_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
+    (
+        .A0(in[3]),
+        .A1(in[2]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_1_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_2_
+    (
+        .A0(in[5]),
+        .A1(in[4]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_2_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_1_X),
+        .A1(sky130_fd_sc_hd__mux2_1_0_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_3_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
+    (
+        .A0(const1_0_const1),
+        .A1(sky130_fd_sc_hd__mux2_1_2_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_4_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_4_X),
+        .A1(sky130_fd_sc_hd__mux2_1_3_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_5_X)
+    );
+    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_5_X),
+        .X(out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size6_mem.v

@@ -0,0 +1,47 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size6_mem
+(
+    ccff_head,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    mem_out
+);
+
+    input ccff_head;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:2]mem_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:2]mem_out;
+    wire pReset;
+    wire prog_clk;
+
+assign ccff_tail = mem_out[2];
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
+    (
+        .CLK(prog_clk),
+        .D(ccff_head),
+        .RESET_B(pReset),
+        .Q(mem_out[0])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[0]),
+        .RESET_B(pReset),
+        .Q(mem_out[1])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[1]),
+        .RESET_B(pReset),
+        .Q(mem_out[2])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size7.v

@@ -0,0 +1,88 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size7
+(
+    in,
+    sram,
+    sram_inv,
+    out
+);
+
+    input [0:6]in;
+    input [0:2]sram;
+    input [0:2]sram_inv;
+    output out;
+
+    wire const1_0_const1;
+    wire [0:6]in;
+    wire out;
+    wire sky130_fd_sc_hd__mux2_1_0_X;
+    wire sky130_fd_sc_hd__mux2_1_1_X;
+    wire sky130_fd_sc_hd__mux2_1_2_X;
+    wire sky130_fd_sc_hd__mux2_1_3_X;
+    wire sky130_fd_sc_hd__mux2_1_4_X;
+    wire sky130_fd_sc_hd__mux2_1_5_X;
+    wire sky130_fd_sc_hd__mux2_1_6_X;
+    wire [0:2]sram;
+    wire [0:2]sram_inv;
+
+    const1 const1_0_
+    (
+        .const1(const1_0_const1)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
+    (
+        .A0(in[1]),
+        .A1(in[0]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_0_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
+    (
+        .A0(in[3]),
+        .A1(in[2]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_1_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_2_
+    (
+        .A0(in[5]),
+        .A1(in[4]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_2_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_3_
+    (
+        .A0(const1_0_const1),
+        .A1(in[6]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_3_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_1_X),
+        .A1(sky130_fd_sc_hd__mux2_1_0_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_4_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_3_X),
+        .A1(sky130_fd_sc_hd__mux2_1_2_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_5_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_5_X),
+        .A1(sky130_fd_sc_hd__mux2_1_4_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_6_X)
+    );
+    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_6_X),
+        .X(out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size7_mem.v

@@ -0,0 +1,47 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size7_mem
+(
+    ccff_head,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    mem_out
+);
+
+    input ccff_head;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:2]mem_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:2]mem_out;
+    wire pReset;
+    wire prog_clk;
+
+assign ccff_tail = mem_out[2];
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
+    (
+        .CLK(prog_clk),
+        .D(ccff_head),
+        .RESET_B(pReset),
+        .Q(mem_out[0])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[0]),
+        .RESET_B(pReset),
+        .Q(mem_out[1])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[1]),
+        .RESET_B(pReset),
+        .Q(mem_out[2])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size8.v

@@ -0,0 +1,96 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size8
+(
+    in,
+    sram,
+    sram_inv,
+    out
+);
+
+    input [0:7]in;
+    input [0:3]sram;
+    input [0:3]sram_inv;
+    output out;
+
+    wire const1_0_const1;
+    wire [0:7]in;
+    wire out;
+    wire sky130_fd_sc_hd__mux2_1_0_X;
+    wire sky130_fd_sc_hd__mux2_1_1_X;
+    wire sky130_fd_sc_hd__mux2_1_2_X;
+    wire sky130_fd_sc_hd__mux2_1_3_X;
+    wire sky130_fd_sc_hd__mux2_1_4_X;
+    wire sky130_fd_sc_hd__mux2_1_5_X;
+    wire sky130_fd_sc_hd__mux2_1_6_X;
+    wire sky130_fd_sc_hd__mux2_1_7_X;
+    wire [0:3]sram;
+    wire [0:3]sram_inv;
+
+    const1 const1_0_
+    (
+        .const1(const1_0_const1)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
+    (
+        .A0(in[1]),
+        .A1(in[0]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_0_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
+    (
+        .A0(in[2]),
+        .A1(sky130_fd_sc_hd__mux2_1_0_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_1_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
+    (
+        .A0(in[4]),
+        .A1(in[3]),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_2_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_2_
+    (
+        .A0(in[6]),
+        .A1(in[5]),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_3_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_3_
+    (
+        .A0(const1_0_const1),
+        .A1(in[7]),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_4_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_2_X),
+        .A1(sky130_fd_sc_hd__mux2_1_1_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_5_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_1_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_4_X),
+        .A1(sky130_fd_sc_hd__mux2_1_3_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_6_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l4_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_6_X),
+        .A1(sky130_fd_sc_hd__mux2_1_5_X),
+        .S(sram[3]),
+        .X(sky130_fd_sc_hd__mux2_1_7_X)
+    );
+    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_7_X),
+        .X(out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size8_mem.v

@@ -0,0 +1,54 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size8_mem
+(
+    ccff_head,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    mem_out
+);
+
+    input ccff_head;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:3]mem_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:3]mem_out;
+    wire pReset;
+    wire prog_clk;
+
+assign ccff_tail = mem_out[3];
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
+    (
+        .CLK(prog_clk),
+        .D(ccff_head),
+        .RESET_B(pReset),
+        .Q(mem_out[0])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[0]),
+        .RESET_B(pReset),
+        .Q(mem_out[1])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[1]),
+        .RESET_B(pReset),
+        .Q(mem_out[2])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[2]),
+        .RESET_B(pReset),
+        .Q(mem_out[3])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size9.v

@@ -0,0 +1,104 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size9
+(
+    in,
+    sram,
+    sram_inv,
+    out
+);
+
+    input [0:8]in;
+    input [0:3]sram;
+    input [0:3]sram_inv;
+    output out;
+
+    wire const1_0_const1;
+    wire [0:8]in;
+    wire out;
+    wire sky130_fd_sc_hd__mux2_1_0_X;
+    wire sky130_fd_sc_hd__mux2_1_1_X;
+    wire sky130_fd_sc_hd__mux2_1_2_X;
+    wire sky130_fd_sc_hd__mux2_1_3_X;
+    wire sky130_fd_sc_hd__mux2_1_4_X;
+    wire sky130_fd_sc_hd__mux2_1_5_X;
+    wire sky130_fd_sc_hd__mux2_1_6_X;
+    wire sky130_fd_sc_hd__mux2_1_7_X;
+    wire sky130_fd_sc_hd__mux2_1_8_X;
+    wire [0:3]sram;
+    wire [0:3]sram_inv;
+
+    const1 const1_0_
+    (
+        .const1(const1_0_const1)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
+    (
+        .A0(in[1]),
+        .A1(in[0]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_0_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
+    (
+        .A0(in[3]),
+        .A1(in[2]),
+        .S(sram[0]),
+        .X(sky130_fd_sc_hd__mux2_1_1_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_1_X),
+        .A1(sky130_fd_sc_hd__mux2_1_0_X),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_2_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
+    (
+        .A0(in[5]),
+        .A1(in[4]),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_3_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_2_
+    (
+        .A0(in[7]),
+        .A1(in[6]),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_4_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l2_in_3_
+    (
+        .A0(const1_0_const1),
+        .A1(in[8]),
+        .S(sram[1]),
+        .X(sky130_fd_sc_hd__mux2_1_5_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_3_X),
+        .A1(sky130_fd_sc_hd__mux2_1_2_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_6_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l3_in_1_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_5_X),
+        .A1(sky130_fd_sc_hd__mux2_1_4_X),
+        .S(sram[2]),
+        .X(sky130_fd_sc_hd__mux2_1_7_X)
+    );
+    sky130_fd_sc_hd__mux2_1 mux_l4_in_0_
+    (
+        .A0(sky130_fd_sc_hd__mux2_1_7_X),
+        .A1(sky130_fd_sc_hd__mux2_1_6_X),
+        .S(sram[3]),
+        .X(sky130_fd_sc_hd__mux2_1_8_X)
+    );
+    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
+    (
+        .A(sky130_fd_sc_hd__mux2_1_8_X),
+        .X(out)
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size9_mem.v

@@ -0,0 +1,54 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module mux_tree_tapbuf_size9_mem
+(
+    ccff_head,
+    pReset,
+    prog_clk,
+    ccff_tail,
+    mem_out
+);
+
+    input ccff_head;
+    input pReset;
+    input prog_clk;
+    output ccff_tail;
+    output [0:3]mem_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:3]mem_out;
+    wire pReset;
+    wire prog_clk;
+
+assign ccff_tail = mem_out[3];
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
+    (
+        .CLK(prog_clk),
+        .D(ccff_head),
+        .RESET_B(pReset),
+        .Q(mem_out[0])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[0]),
+        .RESET_B(pReset),
+        .Q(mem_out[1])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[1]),
+        .RESET_B(pReset),
+        .Q(mem_out[2])
+    );
+    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
+    (
+        .CLK(prog_clk),
+        .D(mem_out[2]),
+        .RESET_B(pReset),
+        .Q(mem_out[3])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__0_.v

@@ -0,0 +1,729 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module sb_0__0_
+(
+    ccff_head,
+    chanx_right_in,
+    chany_top_in,
+    pReset,
+    prog_clk,
+    right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
+    right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
+    right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
+    right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
+    top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
+    top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
+    top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
+    ccff_tail,
+    chanx_right_out,
+    chany_top_out
+);
+
+    input ccff_head;
+    input [0:29]chanx_right_in;
+    input [0:29]chany_top_in;
+    input pReset;
+    input prog_clk;
+    input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
+    input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
+    input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
+    input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
+    input top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
+    input top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
+    input top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
+    output ccff_tail;
+    output [0:29]chanx_right_out;
+    output [0:29]chany_top_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:29]chanx_right_in;
+    wire [0:29]chanx_right_out;
+    wire [0:29]chany_top_in;
+    wire [0:29]chany_top_out;
+    wire [0:1]mux_right_track_0_undriven_sram_inv;
+    wire [0:1]mux_right_track_10_undriven_sram_inv;
+    wire [0:1]mux_right_track_12_undriven_sram_inv;
+    wire [0:1]mux_right_track_14_undriven_sram_inv;
+    wire [0:1]mux_right_track_16_undriven_sram_inv;
+    wire [0:1]mux_right_track_18_undriven_sram_inv;
+    wire [0:1]mux_right_track_28_undriven_sram_inv;
+    wire [0:1]mux_right_track_2_undriven_sram_inv;
+    wire [0:1]mux_right_track_30_undriven_sram_inv;
+    wire [0:1]mux_right_track_32_undriven_sram_inv;
+    wire [0:1]mux_right_track_34_undriven_sram_inv;
+    wire [0:1]mux_right_track_44_undriven_sram_inv;
+    wire [0:1]mux_right_track_46_undriven_sram_inv;
+    wire [0:1]mux_right_track_48_undriven_sram_inv;
+    wire [0:1]mux_right_track_4_undriven_sram_inv;
+    wire [0:1]mux_right_track_50_undriven_sram_inv;
+    wire [0:1]mux_right_track_6_undriven_sram_inv;
+    wire [0:1]mux_right_track_8_undriven_sram_inv;
+    wire [0:1]mux_top_track_0_undriven_sram_inv;
+    wire [0:1]mux_top_track_10_undriven_sram_inv;
+    wire [0:1]mux_top_track_12_undriven_sram_inv;
+    wire [0:1]mux_top_track_14_undriven_sram_inv;
+    wire [0:1]mux_top_track_16_undriven_sram_inv;
+    wire [0:1]mux_top_track_18_undriven_sram_inv;
+    wire [0:1]mux_top_track_28_undriven_sram_inv;
+    wire [0:1]mux_top_track_2_undriven_sram_inv;
+    wire [0:1]mux_top_track_30_undriven_sram_inv;
+    wire [0:1]mux_top_track_32_undriven_sram_inv;
+    wire [0:1]mux_top_track_34_undriven_sram_inv;
+    wire [0:1]mux_top_track_44_undriven_sram_inv;
+    wire [0:1]mux_top_track_46_undriven_sram_inv;
+    wire [0:1]mux_top_track_48_undriven_sram_inv;
+    wire [0:1]mux_top_track_4_undriven_sram_inv;
+    wire [0:1]mux_top_track_50_undriven_sram_inv;
+    wire [0:1]mux_top_track_6_undriven_sram_inv;
+    wire [0:1]mux_top_track_8_undriven_sram_inv;
+    wire [0:1]mux_tree_tapbuf_size2_0_sram;
+    wire [0:1]mux_tree_tapbuf_size2_10_sram;
+    wire [0:1]mux_tree_tapbuf_size2_11_sram;
+    wire [0:1]mux_tree_tapbuf_size2_12_sram;
+    wire [0:1]mux_tree_tapbuf_size2_13_sram;
+    wire [0:1]mux_tree_tapbuf_size2_14_sram;
+    wire [0:1]mux_tree_tapbuf_size2_15_sram;
+    wire [0:1]mux_tree_tapbuf_size2_16_sram;
+    wire [0:1]mux_tree_tapbuf_size2_17_sram;
+    wire [0:1]mux_tree_tapbuf_size2_18_sram;
+    wire [0:1]mux_tree_tapbuf_size2_19_sram;
+    wire [0:1]mux_tree_tapbuf_size2_1_sram;
+    wire [0:1]mux_tree_tapbuf_size2_20_sram;
+    wire [0:1]mux_tree_tapbuf_size2_21_sram;
+    wire [0:1]mux_tree_tapbuf_size2_22_sram;
+    wire [0:1]mux_tree_tapbuf_size2_23_sram;
+    wire [0:1]mux_tree_tapbuf_size2_24_sram;
+    wire [0:1]mux_tree_tapbuf_size2_25_sram;
+    wire [0:1]mux_tree_tapbuf_size2_26_sram;
+    wire [0:1]mux_tree_tapbuf_size2_27_sram;
+    wire [0:1]mux_tree_tapbuf_size2_28_sram;
+    wire [0:1]mux_tree_tapbuf_size2_29_sram;
+    wire [0:1]mux_tree_tapbuf_size2_2_sram;
+    wire [0:1]mux_tree_tapbuf_size2_30_sram;
+    wire [0:1]mux_tree_tapbuf_size2_31_sram;
+    wire [0:1]mux_tree_tapbuf_size2_3_sram;
+    wire [0:1]mux_tree_tapbuf_size2_4_sram;
+    wire [0:1]mux_tree_tapbuf_size2_5_sram;
+    wire [0:1]mux_tree_tapbuf_size2_6_sram;
+    wire [0:1]mux_tree_tapbuf_size2_7_sram;
+    wire [0:1]mux_tree_tapbuf_size2_8_sram;
+    wire [0:1]mux_tree_tapbuf_size2_9_sram;
+    wire mux_tree_tapbuf_size2_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_10_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_11_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_12_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_13_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_14_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_15_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_16_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_17_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_18_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_19_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_20_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_21_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_22_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_23_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_24_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_25_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_26_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_27_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_28_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_29_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_30_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_6_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_7_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_8_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_9_ccff_tail;
+    wire [0:1]mux_tree_tapbuf_size3_0_sram;
+    wire [0:1]mux_tree_tapbuf_size3_1_sram;
+    wire [0:1]mux_tree_tapbuf_size3_2_sram;
+    wire [0:1]mux_tree_tapbuf_size3_3_sram;
+    wire mux_tree_tapbuf_size3_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_3_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+    wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
+
+assign chanx_right_out[10] = chany_top_in[9];
+assign chanx_right_out[11] = chany_top_in[10];
+assign chanx_right_out[28] = chany_top_in[27];
+assign chanx_right_out[29] = chany_top_in[28];
+assign chany_top_out[29] = chanx_right_in[0];
+assign chany_top_out[10] = chanx_right_in[11];
+assign chany_top_out[11] = chanx_right_in[12];
+assign chany_top_out[12] = chanx_right_in[13];
+assign chany_top_out[13] = chanx_right_in[14];
+assign chany_top_out[18] = chanx_right_in[19];
+assign chany_top_out[19] = chanx_right_in[20];
+assign chany_top_out[20] = chanx_right_in[21];
+assign chanx_right_out[12] = chany_top_in[11];
+assign chany_top_out[21] = chanx_right_in[22];
+assign chany_top_out[26] = chanx_right_in[27];
+assign chany_top_out[27] = chanx_right_in[28];
+assign chany_top_out[28] = chanx_right_in[29];
+assign chanx_right_out[13] = chany_top_in[12];
+assign chanx_right_out[18] = chany_top_in[17];
+assign chanx_right_out[19] = chany_top_in[18];
+assign chanx_right_out[20] = chany_top_in[19];
+assign chanx_right_out[21] = chany_top_in[20];
+assign chanx_right_out[26] = chany_top_in[25];
+assign chanx_right_out[27] = chany_top_in[26];
+    mux_tree_tapbuf_size3_mem mem_right_track_0
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_2_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_10
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_19_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_12
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_20_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_14
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_21_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_16
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_22_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_18
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_23_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_2
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_16_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_28
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_24_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_30
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_25_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_32
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_26_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_34
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_27_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_4
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_17_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_44
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_28_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_28_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_46
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_28_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_29_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_29_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_48
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_29_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_30_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_30_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_50
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_30_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_31_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_right_track_6
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_3_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_8
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_18_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_top_track_0
+    (
+        .ccff_head(ccff_head),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_0_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_10
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_3_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_12
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_4_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_14
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_5_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_16
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_6_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_18
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_7_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_2
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_0_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_28
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_8_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_30
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_9_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_32
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_10_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_34
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_11_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_4
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_1_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_44
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_12_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_46
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_13_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_48
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_14_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_50
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_15_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_top_track_6
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_1_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_8
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_2_sram)
+    );
+    mux_tree_tapbuf_size3 mux_right_track_0
+    (
+        .in({chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size3_2_sram),
+        .sram_inv(mux_right_track_0_undriven_sram_inv),
+        .out(chanx_right_out[0])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_10
+    (
+        .in({chany_top_in[4], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_19_sram),
+        .sram_inv(mux_right_track_10_undriven_sram_inv),
+        .out(chanx_right_out[5])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_12
+    (
+        .in({chany_top_in[5], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_20_sram),
+        .sram_inv(mux_right_track_12_undriven_sram_inv),
+        .out(chanx_right_out[6])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_14
+    (
+        .in({chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_21_sram),
+        .sram_inv(mux_right_track_14_undriven_sram_inv),
+        .out(chanx_right_out[7])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_16
+    (
+        .in({chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_22_sram),
+        .sram_inv(mux_right_track_16_undriven_sram_inv),
+        .out(chanx_right_out[8])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_18
+    (
+        .in({chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_23_sram),
+        .sram_inv(mux_right_track_18_undriven_sram_inv),
+        .out(chanx_right_out[9])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_2
+    (
+        .in({chany_top_in[0], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_16_sram),
+        .sram_inv(mux_right_track_2_undriven_sram_inv),
+        .out(chanx_right_out[1])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_28
+    (
+        .in({chany_top_in[13], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_24_sram),
+        .sram_inv(mux_right_track_28_undriven_sram_inv),
+        .out(chanx_right_out[14])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_30
+    (
+        .in({chany_top_in[14], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_25_sram),
+        .sram_inv(mux_right_track_30_undriven_sram_inv),
+        .out(chanx_right_out[15])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_32
+    (
+        .in({chany_top_in[15], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_26_sram),
+        .sram_inv(mux_right_track_32_undriven_sram_inv),
+        .out(chanx_right_out[16])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_34
+    (
+        .in({chany_top_in[16], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_27_sram),
+        .sram_inv(mux_right_track_34_undriven_sram_inv),
+        .out(chanx_right_out[17])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_4
+    (
+        .in({chany_top_in[1], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_17_sram),
+        .sram_inv(mux_right_track_4_undriven_sram_inv),
+        .out(chanx_right_out[2])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_44
+    (
+        .in({chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_28_sram),
+        .sram_inv(mux_right_track_44_undriven_sram_inv),
+        .out(chanx_right_out[22])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_46
+    (
+        .in({chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_29_sram),
+        .sram_inv(mux_right_track_46_undriven_sram_inv),
+        .out(chanx_right_out[23])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_48
+    (
+        .in({chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_30_sram),
+        .sram_inv(mux_right_track_48_undriven_sram_inv),
+        .out(chanx_right_out[24])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_50
+    (
+        .in({chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_31_sram),
+        .sram_inv(mux_right_track_50_undriven_sram_inv),
+        .out(chanx_right_out[25])
+    );
+    mux_tree_tapbuf_size3 mux_right_track_6
+    (
+        .in({chany_top_in[2], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size3_3_sram),
+        .sram_inv(mux_right_track_6_undriven_sram_inv),
+        .out(chanx_right_out[3])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_8
+    (
+        .in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_18_sram),
+        .sram_inv(mux_right_track_8_undriven_sram_inv),
+        .out(chanx_right_out[4])
+    );
+    mux_tree_tapbuf_size3 mux_top_track_0
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[1]}),
+        .sram(mux_tree_tapbuf_size3_0_sram),
+        .sram_inv(mux_top_track_0_undriven_sram_inv),
+        .out(chany_top_out[0])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_10
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[6]}),
+        .sram(mux_tree_tapbuf_size2_3_sram),
+        .sram_inv(mux_top_track_10_undriven_sram_inv),
+        .out(chany_top_out[5])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_12
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[7]}),
+        .sram(mux_tree_tapbuf_size2_4_sram),
+        .sram_inv(mux_top_track_12_undriven_sram_inv),
+        .out(chany_top_out[6])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_14
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[8]}),
+        .sram(mux_tree_tapbuf_size2_5_sram),
+        .sram_inv(mux_top_track_14_undriven_sram_inv),
+        .out(chany_top_out[7])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_16
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[9]}),
+        .sram(mux_tree_tapbuf_size2_6_sram),
+        .sram_inv(mux_top_track_16_undriven_sram_inv),
+        .out(chany_top_out[8])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_18
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[10]}),
+        .sram(mux_tree_tapbuf_size2_7_sram),
+        .sram_inv(mux_top_track_18_undriven_sram_inv),
+        .out(chany_top_out[9])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_2
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[2]}),
+        .sram(mux_tree_tapbuf_size2_0_sram),
+        .sram_inv(mux_top_track_2_undriven_sram_inv),
+        .out(chany_top_out[1])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_28
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[15]}),
+        .sram(mux_tree_tapbuf_size2_8_sram),
+        .sram_inv(mux_top_track_28_undriven_sram_inv),
+        .out(chany_top_out[14])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_30
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[16]}),
+        .sram(mux_tree_tapbuf_size2_9_sram),
+        .sram_inv(mux_top_track_30_undriven_sram_inv),
+        .out(chany_top_out[15])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_32
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[17]}),
+        .sram(mux_tree_tapbuf_size2_10_sram),
+        .sram_inv(mux_top_track_32_undriven_sram_inv),
+        .out(chany_top_out[16])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_34
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[18]}),
+        .sram(mux_tree_tapbuf_size2_11_sram),
+        .sram_inv(mux_top_track_34_undriven_sram_inv),
+        .out(chany_top_out[17])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_4
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[3]}),
+        .sram(mux_tree_tapbuf_size2_1_sram),
+        .sram_inv(mux_top_track_4_undriven_sram_inv),
+        .out(chany_top_out[2])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_44
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[23]}),
+        .sram(mux_tree_tapbuf_size2_12_sram),
+        .sram_inv(mux_top_track_44_undriven_sram_inv),
+        .out(chany_top_out[22])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_46
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[24]}),
+        .sram(mux_tree_tapbuf_size2_13_sram),
+        .sram_inv(mux_top_track_46_undriven_sram_inv),
+        .out(chany_top_out[23])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_48
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[25]}),
+        .sram(mux_tree_tapbuf_size2_14_sram),
+        .sram_inv(mux_top_track_48_undriven_sram_inv),
+        .out(chany_top_out[24])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_50
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[26]}),
+        .sram(mux_tree_tapbuf_size2_15_sram),
+        .sram_inv(mux_top_track_50_undriven_sram_inv),
+        .out(chany_top_out[25])
+    );
+    mux_tree_tapbuf_size3 mux_top_track_6
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[4]}),
+        .sram(mux_tree_tapbuf_size3_1_sram),
+        .sram_inv(mux_top_track_6_undriven_sram_inv),
+        .out(chany_top_out[3])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_8
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[5]}),
+        .sram(mux_tree_tapbuf_size2_2_sram),
+        .sram_inv(mux_top_track_8_undriven_sram_inv),
+        .out(chany_top_out[4])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__8_.v

@@ -0,0 +1,957 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module sb_0__8_
+(
+    bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
+    bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
+    bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
+    bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
+    ccff_head,
+    chanx_right_in,
+    chany_bottom_in,
+    pReset,
+    prog_clk,
+    right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
+    right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
+    right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
+    right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_,
+    right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_,
+    right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
+    right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
+    right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
+    right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
+    right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
+    right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
+    right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
+    ccff_tail,
+    chanx_right_out,
+    chany_bottom_out
+);
+
+    input bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
+    input bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
+    input bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
+    input bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
+    input ccff_head;
+    input [0:29]chanx_right_in;
+    input [0:29]chany_bottom_in;
+    input pReset;
+    input prog_clk;
+    input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
+    input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
+    input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
+    input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_;
+    input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_;
+    input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
+    input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
+    input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
+    input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
+    input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
+    input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
+    input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
+    output ccff_tail;
+    output [0:29]chanx_right_out;
+    output [0:29]chany_bottom_out;
+
+    wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:29]chanx_right_in;
+    wire [0:29]chanx_right_out;
+    wire [0:29]chany_bottom_in;
+    wire [0:29]chany_bottom_out;
+    wire [0:1]mux_bottom_track_11_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_13_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_15_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_17_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_19_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_1_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_29_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_31_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_33_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_35_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_3_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_45_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_47_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_49_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_51_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_5_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_7_undriven_sram_inv;
+    wire [0:1]mux_bottom_track_9_undriven_sram_inv;
+    wire [0:2]mux_right_track_0_undriven_sram_inv;
+    wire [0:2]mux_right_track_10_undriven_sram_inv;
+    wire [0:1]mux_right_track_12_undriven_sram_inv;
+    wire [0:1]mux_right_track_14_undriven_sram_inv;
+    wire [0:1]mux_right_track_16_undriven_sram_inv;
+    wire [0:1]mux_right_track_18_undriven_sram_inv;
+    wire [0:1]mux_right_track_20_undriven_sram_inv;
+    wire [0:1]mux_right_track_22_undriven_sram_inv;
+    wire [0:1]mux_right_track_24_undriven_sram_inv;
+    wire [0:1]mux_right_track_26_undriven_sram_inv;
+    wire [0:1]mux_right_track_28_undriven_sram_inv;
+    wire [0:2]mux_right_track_2_undriven_sram_inv;
+    wire [0:1]mux_right_track_30_undriven_sram_inv;
+    wire [0:1]mux_right_track_32_undriven_sram_inv;
+    wire [0:1]mux_right_track_34_undriven_sram_inv;
+    wire [0:1]mux_right_track_36_undriven_sram_inv;
+    wire [0:1]mux_right_track_38_undriven_sram_inv;
+    wire [0:1]mux_right_track_40_undriven_sram_inv;
+    wire [0:1]mux_right_track_42_undriven_sram_inv;
+    wire [0:1]mux_right_track_44_undriven_sram_inv;
+    wire [0:1]mux_right_track_46_undriven_sram_inv;
+    wire [0:1]mux_right_track_48_undriven_sram_inv;
+    wire [0:2]mux_right_track_4_undriven_sram_inv;
+    wire [0:1]mux_right_track_50_undriven_sram_inv;
+    wire [0:1]mux_right_track_52_undriven_sram_inv;
+    wire [0:1]mux_right_track_54_undriven_sram_inv;
+    wire [0:1]mux_right_track_56_undriven_sram_inv;
+    wire [0:1]mux_right_track_58_undriven_sram_inv;
+    wire [0:2]mux_right_track_6_undriven_sram_inv;
+    wire [0:2]mux_right_track_8_undriven_sram_inv;
+    wire [0:1]mux_tree_tapbuf_size2_0_sram;
+    wire [0:1]mux_tree_tapbuf_size2_10_sram;
+    wire [0:1]mux_tree_tapbuf_size2_11_sram;
+    wire [0:1]mux_tree_tapbuf_size2_12_sram;
+    wire [0:1]mux_tree_tapbuf_size2_13_sram;
+    wire [0:1]mux_tree_tapbuf_size2_14_sram;
+    wire [0:1]mux_tree_tapbuf_size2_15_sram;
+    wire [0:1]mux_tree_tapbuf_size2_16_sram;
+    wire [0:1]mux_tree_tapbuf_size2_17_sram;
+    wire [0:1]mux_tree_tapbuf_size2_18_sram;
+    wire [0:1]mux_tree_tapbuf_size2_19_sram;
+    wire [0:1]mux_tree_tapbuf_size2_1_sram;
+    wire [0:1]mux_tree_tapbuf_size2_20_sram;
+    wire [0:1]mux_tree_tapbuf_size2_21_sram;
+    wire [0:1]mux_tree_tapbuf_size2_22_sram;
+    wire [0:1]mux_tree_tapbuf_size2_23_sram;
+    wire [0:1]mux_tree_tapbuf_size2_24_sram;
+    wire [0:1]mux_tree_tapbuf_size2_25_sram;
+    wire [0:1]mux_tree_tapbuf_size2_26_sram;
+    wire [0:1]mux_tree_tapbuf_size2_27_sram;
+    wire [0:1]mux_tree_tapbuf_size2_28_sram;
+    wire [0:1]mux_tree_tapbuf_size2_2_sram;
+    wire [0:1]mux_tree_tapbuf_size2_3_sram;
+    wire [0:1]mux_tree_tapbuf_size2_4_sram;
+    wire [0:1]mux_tree_tapbuf_size2_5_sram;
+    wire [0:1]mux_tree_tapbuf_size2_6_sram;
+    wire [0:1]mux_tree_tapbuf_size2_7_sram;
+    wire [0:1]mux_tree_tapbuf_size2_8_sram;
+    wire [0:1]mux_tree_tapbuf_size2_9_sram;
+    wire mux_tree_tapbuf_size2_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_10_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_11_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_12_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_13_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_14_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_15_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_16_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_17_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_18_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_19_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_20_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_21_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_22_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_23_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_24_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_25_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_26_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_27_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_6_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_7_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_8_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_9_ccff_tail;
+    wire [0:1]mux_tree_tapbuf_size3_0_sram;
+    wire [0:1]mux_tree_tapbuf_size3_10_sram;
+    wire [0:1]mux_tree_tapbuf_size3_11_sram;
+    wire [0:1]mux_tree_tapbuf_size3_12_sram;
+    wire [0:1]mux_tree_tapbuf_size3_1_sram;
+    wire [0:1]mux_tree_tapbuf_size3_2_sram;
+    wire [0:1]mux_tree_tapbuf_size3_3_sram;
+    wire [0:1]mux_tree_tapbuf_size3_4_sram;
+    wire [0:1]mux_tree_tapbuf_size3_5_sram;
+    wire [0:1]mux_tree_tapbuf_size3_6_sram;
+    wire [0:1]mux_tree_tapbuf_size3_7_sram;
+    wire [0:1]mux_tree_tapbuf_size3_8_sram;
+    wire [0:1]mux_tree_tapbuf_size3_9_sram;
+    wire mux_tree_tapbuf_size3_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_10_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_11_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_12_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_6_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_7_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_8_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_9_ccff_tail;
+    wire [0:2]mux_tree_tapbuf_size5_0_sram;
+    wire [0:2]mux_tree_tapbuf_size5_1_sram;
+    wire [0:2]mux_tree_tapbuf_size5_2_sram;
+    wire [0:2]mux_tree_tapbuf_size5_3_sram;
+    wire [0:2]mux_tree_tapbuf_size5_4_sram;
+    wire [0:2]mux_tree_tapbuf_size5_5_sram;
+    wire mux_tree_tapbuf_size5_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size5_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size5_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size5_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size5_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size5_mem_5_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+    wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
+    wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
+    wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
+    wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_;
+    wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_;
+    wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
+    wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
+    wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
+    wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
+
+assign chany_bottom_out[28] = chanx_right_in[0];
+assign chany_bottom_out[27] = chanx_right_in[1];
+assign chany_bottom_out[10] = chanx_right_in[18];
+assign chany_bottom_out[29] = chanx_right_in[29];
+assign chany_bottom_out[26] = chanx_right_in[2];
+assign chany_bottom_out[21] = chanx_right_in[7];
+assign chany_bottom_out[20] = chanx_right_in[8];
+assign chany_bottom_out[19] = chanx_right_in[9];
+assign chany_bottom_out[18] = chanx_right_in[10];
+assign chany_bottom_out[13] = chanx_right_in[15];
+assign chany_bottom_out[12] = chanx_right_in[16];
+assign chany_bottom_out[11] = chanx_right_in[17];
+    mux_tree_tapbuf_size3_mem mem_bottom_track_1
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_11_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_11
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_16_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_13
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_17_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_15
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_18_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_17
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_19_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_19
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_20_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_29
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_21_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_3
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_13_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_31
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_22_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_33
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_23_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_35
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_24_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_45
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_25_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_47
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_26_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_49
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_27_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_5
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_14_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_51
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_28_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_bottom_track_7
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_12_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_bottom_track_9
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_15_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_right_track_0
+    (
+        .ccff_head(ccff_head),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_0_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_right_track_10
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_5_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_right_track_12
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_0_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_right_track_14
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_1_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_right_track_16
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_2_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_18
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_0_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_right_track_2
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_1_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_20
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_1_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_22
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_2_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_24
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_3_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_26
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_4_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_right_track_28
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_3_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_right_track_30
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_4_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_right_track_32
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_5_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_right_track_34
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_6_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_36
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_5_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_38
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_6_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_right_track_4
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_2_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_40
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_7_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_42
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_8_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_right_track_44
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_7_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_right_track_46
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_8_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_right_track_48
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_9_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_50
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_9_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_52
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_10_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_54
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_11_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_right_track_56
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_12_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_right_track_58
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_10_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_right_track_6
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_3_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_right_track_8
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_4_sram)
+    );
+    mux_tree_tapbuf_size3 mux_bottom_track_1
+    (
+        .in({chanx_right_in[28], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size3_11_sram),
+        .sram_inv(mux_bottom_track_1_undriven_sram_inv),
+        .out(chany_bottom_out[0])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_11
+    (
+        .in({chanx_right_in[23], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_16_sram),
+        .sram_inv(mux_bottom_track_11_undriven_sram_inv),
+        .out(chany_bottom_out[5])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_13
+    (
+        .in({chanx_right_in[22], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_17_sram),
+        .sram_inv(mux_bottom_track_13_undriven_sram_inv),
+        .out(chany_bottom_out[6])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_15
+    (
+        .in({chanx_right_in[21], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_18_sram),
+        .sram_inv(mux_bottom_track_15_undriven_sram_inv),
+        .out(chany_bottom_out[7])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_17
+    (
+        .in({chanx_right_in[20], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_19_sram),
+        .sram_inv(mux_bottom_track_17_undriven_sram_inv),
+        .out(chany_bottom_out[8])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_19
+    (
+        .in({chanx_right_in[19], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_20_sram),
+        .sram_inv(mux_bottom_track_19_undriven_sram_inv),
+        .out(chany_bottom_out[9])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_29
+    (
+        .in({chanx_right_in[14], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_21_sram),
+        .sram_inv(mux_bottom_track_29_undriven_sram_inv),
+        .out(chany_bottom_out[14])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_3
+    (
+        .in({chanx_right_in[27], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_13_sram),
+        .sram_inv(mux_bottom_track_3_undriven_sram_inv),
+        .out(chany_bottom_out[1])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_31
+    (
+        .in({chanx_right_in[13], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_22_sram),
+        .sram_inv(mux_bottom_track_31_undriven_sram_inv),
+        .out(chany_bottom_out[15])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_33
+    (
+        .in({chanx_right_in[12], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_23_sram),
+        .sram_inv(mux_bottom_track_33_undriven_sram_inv),
+        .out(chany_bottom_out[16])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_35
+    (
+        .in({chanx_right_in[11], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_24_sram),
+        .sram_inv(mux_bottom_track_35_undriven_sram_inv),
+        .out(chany_bottom_out[17])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_45
+    (
+        .in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_25_sram),
+        .sram_inv(mux_bottom_track_45_undriven_sram_inv),
+        .out(chany_bottom_out[22])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_47
+    (
+        .in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_26_sram),
+        .sram_inv(mux_bottom_track_47_undriven_sram_inv),
+        .out(chany_bottom_out[23])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_49
+    (
+        .in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_27_sram),
+        .sram_inv(mux_bottom_track_49_undriven_sram_inv),
+        .out(chany_bottom_out[24])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_5
+    (
+        .in({chanx_right_in[26], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_14_sram),
+        .sram_inv(mux_bottom_track_5_undriven_sram_inv),
+        .out(chany_bottom_out[2])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_51
+    (
+        .in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_28_sram),
+        .sram_inv(mux_bottom_track_51_undriven_sram_inv),
+        .out(chany_bottom_out[25])
+    );
+    mux_tree_tapbuf_size3 mux_bottom_track_7
+    (
+        .in({chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size3_12_sram),
+        .sram_inv(mux_bottom_track_7_undriven_sram_inv),
+        .out(chany_bottom_out[3])
+    );
+    mux_tree_tapbuf_size2 mux_bottom_track_9
+    (
+        .in({chanx_right_in[24], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_15_sram),
+        .sram_inv(mux_bottom_track_9_undriven_sram_inv),
+        .out(chany_bottom_out[4])
+    );
+    mux_tree_tapbuf_size5 mux_right_track_0
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[28]}),
+        .sram(mux_tree_tapbuf_size5_0_sram),
+        .sram_inv(mux_right_track_0_undriven_sram_inv),
+        .out(chanx_right_out[0])
+    );
+    mux_tree_tapbuf_size5 mux_right_track_10
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[23]}),
+        .sram(mux_tree_tapbuf_size5_5_sram),
+        .sram_inv(mux_right_track_10_undriven_sram_inv),
+        .out(chanx_right_out[5])
+    );
+    mux_tree_tapbuf_size3 mux_right_track_12
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[22]}),
+        .sram(mux_tree_tapbuf_size3_0_sram),
+        .sram_inv(mux_right_track_12_undriven_sram_inv),
+        .out(chanx_right_out[6])
+    );
+    mux_tree_tapbuf_size3 mux_right_track_14
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[21]}),
+        .sram(mux_tree_tapbuf_size3_1_sram),
+        .sram_inv(mux_right_track_14_undriven_sram_inv),
+        .out(chanx_right_out[7])
+    );
+    mux_tree_tapbuf_size3 mux_right_track_16
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[20]}),
+        .sram(mux_tree_tapbuf_size3_2_sram),
+        .sram_inv(mux_right_track_16_undriven_sram_inv),
+        .out(chanx_right_out[8])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_18
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[19]}),
+        .sram(mux_tree_tapbuf_size2_0_sram),
+        .sram_inv(mux_right_track_18_undriven_sram_inv),
+        .out(chanx_right_out[9])
+    );
+    mux_tree_tapbuf_size5 mux_right_track_2
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[27]}),
+        .sram(mux_tree_tapbuf_size5_1_sram),
+        .sram_inv(mux_right_track_2_undriven_sram_inv),
+        .out(chanx_right_out[1])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_20
+    (
+        .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[18]}),
+        .sram(mux_tree_tapbuf_size2_1_sram),
+        .sram_inv(mux_right_track_20_undriven_sram_inv),
+        .out(chanx_right_out[10])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_22
+    (
+        .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[17]}),
+        .sram(mux_tree_tapbuf_size2_2_sram),
+        .sram_inv(mux_right_track_22_undriven_sram_inv),
+        .out(chanx_right_out[11])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_24
+    (
+        .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[16]}),
+        .sram(mux_tree_tapbuf_size2_3_sram),
+        .sram_inv(mux_right_track_24_undriven_sram_inv),
+        .out(chanx_right_out[12])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_26
+    (
+        .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[15]}),
+        .sram(mux_tree_tapbuf_size2_4_sram),
+        .sram_inv(mux_right_track_26_undriven_sram_inv),
+        .out(chanx_right_out[13])
+    );
+    mux_tree_tapbuf_size3 mux_right_track_28
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[14]}),
+        .sram(mux_tree_tapbuf_size3_3_sram),
+        .sram_inv(mux_right_track_28_undriven_sram_inv),
+        .out(chanx_right_out[14])
+    );
+    mux_tree_tapbuf_size3 mux_right_track_30
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[13]}),
+        .sram(mux_tree_tapbuf_size3_4_sram),
+        .sram_inv(mux_right_track_30_undriven_sram_inv),
+        .out(chanx_right_out[15])
+    );
+    mux_tree_tapbuf_size3 mux_right_track_32
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[12]}),
+        .sram(mux_tree_tapbuf_size3_5_sram),
+        .sram_inv(mux_right_track_32_undriven_sram_inv),
+        .out(chanx_right_out[16])
+    );
+    mux_tree_tapbuf_size3 mux_right_track_34
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[11]}),
+        .sram(mux_tree_tapbuf_size3_6_sram),
+        .sram_inv(mux_right_track_34_undriven_sram_inv),
+        .out(chanx_right_out[17])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_36
+    (
+        .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[10]}),
+        .sram(mux_tree_tapbuf_size2_5_sram),
+        .sram_inv(mux_right_track_36_undriven_sram_inv),
+        .out(chanx_right_out[18])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_38
+    (
+        .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[9]}),
+        .sram(mux_tree_tapbuf_size2_6_sram),
+        .sram_inv(mux_right_track_38_undriven_sram_inv),
+        .out(chanx_right_out[19])
+    );
+    mux_tree_tapbuf_size5 mux_right_track_4
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[26]}),
+        .sram(mux_tree_tapbuf_size5_2_sram),
+        .sram_inv(mux_right_track_4_undriven_sram_inv),
+        .out(chanx_right_out[2])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_40
+    (
+        .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[8]}),
+        .sram(mux_tree_tapbuf_size2_7_sram),
+        .sram_inv(mux_right_track_40_undriven_sram_inv),
+        .out(chanx_right_out[20])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_42
+    (
+        .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[7]}),
+        .sram(mux_tree_tapbuf_size2_8_sram),
+        .sram_inv(mux_right_track_42_undriven_sram_inv),
+        .out(chanx_right_out[21])
+    );
+    mux_tree_tapbuf_size3 mux_right_track_44
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[6]}),
+        .sram(mux_tree_tapbuf_size3_7_sram),
+        .sram_inv(mux_right_track_44_undriven_sram_inv),
+        .out(chanx_right_out[22])
+    );
+    mux_tree_tapbuf_size3 mux_right_track_46
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[5]}),
+        .sram(mux_tree_tapbuf_size3_8_sram),
+        .sram_inv(mux_right_track_46_undriven_sram_inv),
+        .out(chanx_right_out[23])
+    );
+    mux_tree_tapbuf_size3 mux_right_track_48
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[4]}),
+        .sram(mux_tree_tapbuf_size3_9_sram),
+        .sram_inv(mux_right_track_48_undriven_sram_inv),
+        .out(chanx_right_out[24])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_50
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[3]}),
+        .sram(mux_tree_tapbuf_size2_9_sram),
+        .sram_inv(mux_right_track_50_undriven_sram_inv),
+        .out(chanx_right_out[25])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_52
+    (
+        .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[2]}),
+        .sram(mux_tree_tapbuf_size2_10_sram),
+        .sram_inv(mux_right_track_52_undriven_sram_inv),
+        .out(chanx_right_out[26])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_54
+    (
+        .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[1]}),
+        .sram(mux_tree_tapbuf_size2_11_sram),
+        .sram_inv(mux_right_track_54_undriven_sram_inv),
+        .out(chanx_right_out[27])
+    );
+    mux_tree_tapbuf_size2 mux_right_track_56
+    (
+        .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[0]}),
+        .sram(mux_tree_tapbuf_size2_12_sram),
+        .sram_inv(mux_right_track_56_undriven_sram_inv),
+        .out(chanx_right_out[28])
+    );
+    mux_tree_tapbuf_size3 mux_right_track_58
+    (
+        .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[29]}),
+        .sram(mux_tree_tapbuf_size3_10_sram),
+        .sram_inv(mux_right_track_58_undriven_sram_inv),
+        .out(chanx_right_out[29])
+    );
+    mux_tree_tapbuf_size5 mux_right_track_6
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[25]}),
+        .sram(mux_tree_tapbuf_size5_3_sram),
+        .sram_inv(mux_right_track_6_undriven_sram_inv),
+        .out(chanx_right_out[3])
+    );
+    mux_tree_tapbuf_size5 mux_right_track_8
+    (
+        .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[24]}),
+        .sram(mux_tree_tapbuf_size5_4_sram),
+        .sram_inv(mux_right_track_8_undriven_sram_inv),
+        .out(chanx_right_out[4])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__0_.v

@@ -0,0 +1,993 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module sb_1__0_
+(
+    ccff_head,
+    chanx_left_in,
+    chanx_right_in,
+    chany_top_in,
+    left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
+    left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
+    left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
+    left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
+    pReset,
+    prog_clk,
+    right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
+    right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
+    right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
+    right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_,
+    ccff_tail,
+    chanx_left_out,
+    chanx_right_out,
+    chany_top_out
+);
+
+    input ccff_head;
+    input [0:29]chanx_left_in;
+    input [0:29]chanx_right_in;
+    input [0:29]chany_top_in;
+    input left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
+    input left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
+    input left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
+    input left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
+    input pReset;
+    input prog_clk;
+    input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
+    input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
+    input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
+    input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
+    output ccff_tail;
+    output [0:29]chanx_left_out;
+    output [0:29]chanx_right_out;
+    output [0:29]chany_top_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:29]chanx_left_in;
+    wire [0:29]chanx_left_out;
+    wire [0:29]chanx_right_in;
+    wire [0:29]chanx_right_out;
+    wire [0:29]chany_top_in;
+    wire [0:29]chany_top_out;
+    wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
+    wire [0:2]mux_left_track_11_undriven_sram_inv;
+    wire [0:2]mux_left_track_13_undriven_sram_inv;
+    wire [0:2]mux_left_track_1_undriven_sram_inv;
+    wire [0:2]mux_left_track_21_undriven_sram_inv;
+    wire [0:2]mux_left_track_29_undriven_sram_inv;
+    wire [0:2]mux_left_track_37_undriven_sram_inv;
+    wire [0:2]mux_left_track_3_undriven_sram_inv;
+    wire [0:2]mux_left_track_45_undriven_sram_inv;
+    wire [0:2]mux_left_track_53_undriven_sram_inv;
+    wire [0:2]mux_left_track_5_undriven_sram_inv;
+    wire [0:2]mux_left_track_7_undriven_sram_inv;
+    wire [0:2]mux_right_track_0_undriven_sram_inv;
+    wire [0:2]mux_right_track_10_undriven_sram_inv;
+    wire [0:2]mux_right_track_12_undriven_sram_inv;
+    wire [0:2]mux_right_track_20_undriven_sram_inv;
+    wire [0:2]mux_right_track_28_undriven_sram_inv;
+    wire [0:2]mux_right_track_2_undriven_sram_inv;
+    wire [0:2]mux_right_track_36_undriven_sram_inv;
+    wire [0:1]mux_right_track_44_undriven_sram_inv;
+    wire [0:2]mux_right_track_4_undriven_sram_inv;
+    wire [0:1]mux_right_track_52_undriven_sram_inv;
+    wire [0:2]mux_right_track_6_undriven_sram_inv;
+    wire [0:2]mux_top_track_0_undriven_sram_inv;
+    wire [0:2]mux_top_track_10_undriven_sram_inv;
+    wire [0:2]mux_top_track_12_undriven_sram_inv;
+    wire [0:2]mux_top_track_14_undriven_sram_inv;
+    wire [0:2]mux_top_track_16_undriven_sram_inv;
+    wire [0:2]mux_top_track_18_undriven_sram_inv;
+    wire [0:1]mux_top_track_20_undriven_sram_inv;
+    wire [0:1]mux_top_track_22_undriven_sram_inv;
+    wire [0:1]mux_top_track_24_undriven_sram_inv;
+    wire [0:1]mux_top_track_26_undriven_sram_inv;
+    wire [0:1]mux_top_track_28_undriven_sram_inv;
+    wire [0:2]mux_top_track_2_undriven_sram_inv;
+    wire [0:1]mux_top_track_30_undriven_sram_inv;
+    wire [0:1]mux_top_track_32_undriven_sram_inv;
+    wire [0:1]mux_top_track_34_undriven_sram_inv;
+    wire [0:1]mux_top_track_36_undriven_sram_inv;
+    wire [0:1]mux_top_track_40_undriven_sram_inv;
+    wire [0:1]mux_top_track_42_undriven_sram_inv;
+    wire [0:1]mux_top_track_44_undriven_sram_inv;
+    wire [0:1]mux_top_track_46_undriven_sram_inv;
+    wire [0:1]mux_top_track_48_undriven_sram_inv;
+    wire [0:2]mux_top_track_4_undriven_sram_inv;
+    wire [0:1]mux_top_track_50_undriven_sram_inv;
+    wire [0:1]mux_top_track_58_undriven_sram_inv;
+    wire [0:2]mux_top_track_6_undriven_sram_inv;
+    wire [0:2]mux_top_track_8_undriven_sram_inv;
+    wire [0:1]mux_tree_tapbuf_size2_0_sram;
+    wire [0:1]mux_tree_tapbuf_size2_10_sram;
+    wire [0:1]mux_tree_tapbuf_size2_1_sram;
+    wire [0:1]mux_tree_tapbuf_size2_2_sram;
+    wire [0:1]mux_tree_tapbuf_size2_3_sram;
+    wire [0:1]mux_tree_tapbuf_size2_4_sram;
+    wire [0:1]mux_tree_tapbuf_size2_5_sram;
+    wire [0:1]mux_tree_tapbuf_size2_6_sram;
+    wire [0:1]mux_tree_tapbuf_size2_7_sram;
+    wire [0:1]mux_tree_tapbuf_size2_8_sram;
+    wire [0:1]mux_tree_tapbuf_size2_9_sram;
+    wire mux_tree_tapbuf_size2_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_10_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_6_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_7_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_8_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_9_ccff_tail;
+    wire [0:1]mux_tree_tapbuf_size3_0_sram;
+    wire [0:1]mux_tree_tapbuf_size3_1_sram;
+    wire [0:1]mux_tree_tapbuf_size3_2_sram;
+    wire [0:1]mux_tree_tapbuf_size3_3_sram;
+    wire [0:1]mux_tree_tapbuf_size3_4_sram;
+    wire [0:1]mux_tree_tapbuf_size3_5_sram;
+    wire [0:1]mux_tree_tapbuf_size3_6_sram;
+    wire mux_tree_tapbuf_size3_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_6_ccff_tail;
+    wire [0:2]mux_tree_tapbuf_size4_0_sram;
+    wire [0:2]mux_tree_tapbuf_size4_1_sram;
+    wire [0:2]mux_tree_tapbuf_size4_2_sram;
+    wire [0:2]mux_tree_tapbuf_size4_3_sram;
+    wire [0:2]mux_tree_tapbuf_size4_4_sram;
+    wire [0:2]mux_tree_tapbuf_size4_5_sram;
+    wire mux_tree_tapbuf_size4_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size4_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size4_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size4_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size4_mem_4_ccff_tail;
+    wire [0:2]mux_tree_tapbuf_size5_0_sram;
+    wire [0:2]mux_tree_tapbuf_size5_1_sram;
+    wire [0:2]mux_tree_tapbuf_size5_2_sram;
+    wire [0:2]mux_tree_tapbuf_size5_3_sram;
+    wire [0:2]mux_tree_tapbuf_size5_4_sram;
+    wire [0:2]mux_tree_tapbuf_size5_5_sram;
+    wire mux_tree_tapbuf_size5_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size5_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size5_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size5_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size5_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size5_mem_5_ccff_tail;
+    wire [0:2]mux_tree_tapbuf_size6_0_sram;
+    wire [0:2]mux_tree_tapbuf_size6_10_sram;
+    wire [0:2]mux_tree_tapbuf_size6_11_sram;
+    wire [0:2]mux_tree_tapbuf_size6_12_sram;
+    wire [0:2]mux_tree_tapbuf_size6_1_sram;
+    wire [0:2]mux_tree_tapbuf_size6_2_sram;
+    wire [0:2]mux_tree_tapbuf_size6_3_sram;
+    wire [0:2]mux_tree_tapbuf_size6_4_sram;
+    wire [0:2]mux_tree_tapbuf_size6_5_sram;
+    wire [0:2]mux_tree_tapbuf_size6_6_sram;
+    wire [0:2]mux_tree_tapbuf_size6_7_sram;
+    wire [0:2]mux_tree_tapbuf_size6_8_sram;
+    wire [0:2]mux_tree_tapbuf_size6_9_sram;
+    wire mux_tree_tapbuf_size6_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size6_mem_10_ccff_tail;
+    wire mux_tree_tapbuf_size6_mem_11_ccff_tail;
+    wire mux_tree_tapbuf_size6_mem_12_ccff_tail;
+    wire mux_tree_tapbuf_size6_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size6_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size6_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size6_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size6_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size6_mem_6_ccff_tail;
+    wire mux_tree_tapbuf_size6_mem_7_ccff_tail;
+    wire mux_tree_tapbuf_size6_mem_8_ccff_tail;
+    wire mux_tree_tapbuf_size6_mem_9_ccff_tail;
+    wire [0:2]mux_tree_tapbuf_size7_0_sram;
+    wire [0:2]mux_tree_tapbuf_size7_1_sram;
+    wire [0:2]mux_tree_tapbuf_size7_2_sram;
+    wire [0:2]mux_tree_tapbuf_size7_3_sram;
+    wire [0:2]mux_tree_tapbuf_size7_4_sram;
+    wire mux_tree_tapbuf_size7_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size7_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size7_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size7_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size7_mem_4_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+    wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
+
+assign chany_top_out[19] = top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
+assign chanx_left_out[4] = chanx_right_in[3];
+assign chanx_left_out[17] = chanx_right_in[16];
+assign chanx_left_out[19] = chanx_right_in[18];
+assign chanx_left_out[20] = chanx_right_in[19];
+assign chanx_left_out[21] = chanx_right_in[20];
+assign chanx_left_out[23] = chanx_right_in[22];
+assign chanx_left_out[24] = chanx_right_in[23];
+assign chanx_left_out[25] = chanx_right_in[24];
+assign chanx_left_out[27] = chanx_right_in[26];
+assign chanx_left_out[28] = chanx_right_in[27];
+assign chanx_left_out[29] = chanx_right_in[28];
+assign chanx_left_out[7] = chanx_right_in[6];
+assign chany_top_out[28] = chanx_left_in[2];
+assign chanx_right_out[4] = chanx_left_in[3];
+assign chany_top_out[27] = chanx_left_in[4];
+assign chany_top_out[26] = chanx_left_in[5];
+assign chanx_right_out[7] = chanx_left_in[6];
+assign chanx_right_out[8] = chanx_left_in[7];
+assign chanx_right_out[9] = chanx_left_in[8];
+assign chanx_right_out[11] = chanx_left_in[10];
+assign chanx_right_out[12] = chanx_left_in[11];
+assign chanx_right_out[13] = chanx_left_in[12];
+assign chanx_left_out[8] = chanx_right_in[7];
+assign chanx_right_out[15] = chanx_left_in[14];
+assign chanx_right_out[16] = chanx_left_in[15];
+assign chanx_right_out[17] = chanx_left_in[16];
+assign chanx_right_out[19] = chanx_left_in[18];
+assign chanx_right_out[20] = chanx_left_in[19];
+assign chanx_right_out[21] = chanx_left_in[20];
+assign chanx_right_out[23] = chanx_left_in[22];
+assign chanx_right_out[24] = chanx_left_in[23];
+assign chanx_right_out[25] = chanx_left_in[24];
+assign chanx_right_out[27] = chanx_left_in[26];
+assign chanx_left_out[9] = chanx_right_in[8];
+assign chanx_right_out[28] = chanx_left_in[27];
+assign chanx_right_out[29] = chanx_left_in[28];
+assign chanx_left_out[11] = chanx_right_in[10];
+assign chanx_left_out[12] = chanx_right_in[11];
+assign chanx_left_out[13] = chanx_right_in[12];
+assign chanx_left_out[15] = chanx_right_in[14];
+assign chanx_left_out[16] = chanx_right_in[15];
+    mux_tree_tapbuf_size7_mem mem_left_track_1
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size7_3_sram)
+    );
+    mux_tree_tapbuf_size7_mem mem_left_track_11
+    (
+        .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size7_4_sram)
+    );
+    mux_tree_tapbuf_size6_mem mem_left_track_13
+    (
+        .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size6_10_sram)
+    );
+    mux_tree_tapbuf_size6_mem mem_left_track_21
+    (
+        .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size6_11_sram)
+    );
+    mux_tree_tapbuf_size6_mem mem_left_track_29
+    (
+        .ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size6_mem_12_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size6_12_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_left_track_3
+    (
+        .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_3_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_left_track_37
+    (
+        .ccff_head(mux_tree_tapbuf_size6_mem_12_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_5_sram)
+    );
+    mux_tree_tapbuf_size4_mem mem_left_track_45
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size4_4_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_left_track_5
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_4_sram)
+    );
+    mux_tree_tapbuf_size4_mem mem_left_track_53
+    (
+        .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .mem_out(mux_tree_tapbuf_size4_5_sram)
+    );
+    mux_tree_tapbuf_size6_mem mem_left_track_7
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size6_9_sram)
+    );
+    mux_tree_tapbuf_size6_mem mem_right_track_0
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size6_3_sram)
+    );
+    mux_tree_tapbuf_size7_mem mem_right_track_10
+    (
+        .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size7_2_sram)
+    );
+    mux_tree_tapbuf_size6_mem mem_right_track_12
+    (
+        .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size6_6_sram)
+    );
+    mux_tree_tapbuf_size6_mem mem_right_track_2
+    (
+        .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size6_4_sram)
+    );
+    mux_tree_tapbuf_size6_mem mem_right_track_20
+    (
+        .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size6_7_sram)
+    );
+    mux_tree_tapbuf_size6_mem mem_right_track_28
+    (
+        .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size6_8_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_right_track_36
+    (
+        .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_2_sram)
+    );
+    mux_tree_tapbuf_size6_mem mem_right_track_4
+    (
+        .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size6_5_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_right_track_44
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_5_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_right_track_52
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_6_sram)
+    );
+    mux_tree_tapbuf_size7_mem mem_right_track_6
+    (
+        .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size7_1_sram)
+    );
+    mux_tree_tapbuf_size7_mem mem_top_track_0
+    (
+        .ccff_head(ccff_head),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size7_0_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_top_track_10
+    (
+        .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_1_sram)
+    );
+    mux_tree_tapbuf_size4_mem mem_top_track_12
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size4_0_sram)
+    );
+    mux_tree_tapbuf_size4_mem mem_top_track_14
+    (
+        .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size4_1_sram)
+    );
+    mux_tree_tapbuf_size4_mem mem_top_track_16
+    (
+        .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size4_2_sram)
+    );
+    mux_tree_tapbuf_size4_mem mem_top_track_18
+    (
+        .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size4_3_sram)
+    );
+    mux_tree_tapbuf_size6_mem mem_top_track_2
+    (
+        .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size6_0_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_top_track_20
+    (
+        .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_0_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_top_track_22
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_1_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_top_track_24
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_2_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_top_track_26
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_3_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_28
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_0_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_30
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_1_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_32
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_2_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_34
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_3_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_top_track_36
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_4_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_top_track_4
+    (
+        .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_0_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_40
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_4_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_42
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_5_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_44
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_6_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_46
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_7_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_48
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_8_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_50
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_9_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_58
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_10_sram)
+    );
+    mux_tree_tapbuf_size6_mem mem_top_track_6
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size6_1_sram)
+    );
+    mux_tree_tapbuf_size6_mem mem_top_track_8
+    (
+        .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size6_2_sram)
+    );
+    mux_tree_tapbuf_size7 mux_left_track_1
+    (
+        .in({chany_top_in[0], chany_top_in[11], chany_top_in[22], chanx_right_in[3], chanx_right_in[19], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size7_3_sram),
+        .sram_inv(mux_left_track_1_undriven_sram_inv),
+        .out(chanx_left_out[0])
+    );
+    mux_tree_tapbuf_size7 mux_left_track_11
+    (
+        .in({chany_top_in[7], chany_top_in[18], chany_top_in[29], chanx_right_in[10], chanx_right_in[24], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size7_4_sram),
+        .sram_inv(mux_left_track_11_undriven_sram_inv),
+        .out(chanx_left_out[5])
+    );
+    mux_tree_tapbuf_size6 mux_left_track_13
+    (
+        .in({chany_top_in[6], chany_top_in[17], chany_top_in[28], chanx_right_in[11], chanx_right_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size6_10_sram),
+        .sram_inv(mux_left_track_13_undriven_sram_inv),
+        .out(chanx_left_out[6])
+    );
+    mux_tree_tapbuf_size6 mux_left_track_21
+    (
+        .in({chany_top_in[5], chany_top_in[16], chany_top_in[27], chanx_right_in[12], chanx_right_in[27], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size6_11_sram),
+        .sram_inv(mux_left_track_21_undriven_sram_inv),
+        .out(chanx_left_out[10])
+    );
+    mux_tree_tapbuf_size6 mux_left_track_29
+    (
+        .in({chany_top_in[4], chany_top_in[15], chany_top_in[26], chanx_right_in[14], chanx_right_in[28], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size6_12_sram),
+        .sram_inv(mux_left_track_29_undriven_sram_inv),
+        .out(chanx_left_out[14])
+    );
+    mux_tree_tapbuf_size5 mux_left_track_3
+    (
+        .in({chany_top_in[10], chany_top_in[21], chanx_right_in[6], chanx_right_in[20], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size5_3_sram),
+        .sram_inv(mux_left_track_3_undriven_sram_inv),
+        .out(chanx_left_out[1])
+    );
+    mux_tree_tapbuf_size5 mux_left_track_37
+    (
+        .in({chany_top_in[3], chany_top_in[14], chany_top_in[25], chanx_right_in[15], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size5_5_sram),
+        .sram_inv(mux_left_track_37_undriven_sram_inv),
+        .out(chanx_left_out[18])
+    );
+    mux_tree_tapbuf_size4 mux_left_track_45
+    (
+        .in({chany_top_in[2], chany_top_in[13], chany_top_in[24], chanx_right_in[16]}),
+        .sram(mux_tree_tapbuf_size4_4_sram),
+        .sram_inv(mux_left_track_45_undriven_sram_inv),
+        .out(chanx_left_out[22])
+    );
+    mux_tree_tapbuf_size5 mux_left_track_5
+    (
+        .in({chany_top_in[9], chany_top_in[20], chanx_right_in[7], chanx_right_in[22], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size5_4_sram),
+        .sram_inv(mux_left_track_5_undriven_sram_inv),
+        .out(chanx_left_out[2])
+    );
+    mux_tree_tapbuf_size4 mux_left_track_53
+    (
+        .in({chany_top_in[1], chany_top_in[12], chany_top_in[23], chanx_right_in[18]}),
+        .sram(mux_tree_tapbuf_size4_5_sram),
+        .sram_inv(mux_left_track_53_undriven_sram_inv),
+        .out(chanx_left_out[26])
+    );
+    mux_tree_tapbuf_size6 mux_left_track_7
+    (
+        .in({chany_top_in[8], chany_top_in[19], chanx_right_in[8], chanx_right_in[23], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size6_9_sram),
+        .sram_inv(mux_left_track_7_undriven_sram_inv),
+        .out(chanx_left_out[3])
+    );
+    mux_tree_tapbuf_size6 mux_right_track_0
+    (
+        .in({chany_top_in[10], chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3], chanx_left_in[19]}),
+        .sram(mux_tree_tapbuf_size6_3_sram),
+        .sram_inv(mux_right_track_0_undriven_sram_inv),
+        .out(chanx_right_out[0])
+    );
+    mux_tree_tapbuf_size7 mux_right_track_10
+    (
+        .in({chany_top_in[3], chany_top_in[14], chany_top_in[25], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10], chanx_left_in[24]}),
+        .sram(mux_tree_tapbuf_size7_2_sram),
+        .sram_inv(mux_right_track_10_undriven_sram_inv),
+        .out(chanx_right_out[5])
+    );
+    mux_tree_tapbuf_size6 mux_right_track_12
+    (
+        .in({chany_top_in[4], chany_top_in[15], chany_top_in[26], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[11], chanx_left_in[26]}),
+        .sram(mux_tree_tapbuf_size6_6_sram),
+        .sram_inv(mux_right_track_12_undriven_sram_inv),
+        .out(chanx_right_out[6])
+    );
+    mux_tree_tapbuf_size6 mux_right_track_2
+    (
+        .in({chany_top_in[0], chany_top_in[11], chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[6], chanx_left_in[20]}),
+        .sram(mux_tree_tapbuf_size6_4_sram),
+        .sram_inv(mux_right_track_2_undriven_sram_inv),
+        .out(chanx_right_out[1])
+    );
+    mux_tree_tapbuf_size6 mux_right_track_20
+    (
+        .in({chany_top_in[5], chany_top_in[16], chany_top_in[27], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[12], chanx_left_in[27]}),
+        .sram(mux_tree_tapbuf_size6_7_sram),
+        .sram_inv(mux_right_track_20_undriven_sram_inv),
+        .out(chanx_right_out[10])
+    );
+    mux_tree_tapbuf_size6 mux_right_track_28
+    (
+        .in({chany_top_in[6], chany_top_in[17], chany_top_in[28], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[14], chanx_left_in[28]}),
+        .sram(mux_tree_tapbuf_size6_8_sram),
+        .sram_inv(mux_right_track_28_undriven_sram_inv),
+        .out(chanx_right_out[14])
+    );
+    mux_tree_tapbuf_size5 mux_right_track_36
+    (
+        .in({chany_top_in[7], chany_top_in[18], chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[15]}),
+        .sram(mux_tree_tapbuf_size5_2_sram),
+        .sram_inv(mux_right_track_36_undriven_sram_inv),
+        .out(chanx_right_out[18])
+    );
+    mux_tree_tapbuf_size6 mux_right_track_4
+    (
+        .in({chany_top_in[1], chany_top_in[12], chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[7], chanx_left_in[22]}),
+        .sram(mux_tree_tapbuf_size6_5_sram),
+        .sram_inv(mux_right_track_4_undriven_sram_inv),
+        .out(chanx_right_out[2])
+    );
+    mux_tree_tapbuf_size3 mux_right_track_44
+    (
+        .in({chany_top_in[8], chany_top_in[19], chanx_left_in[16]}),
+        .sram(mux_tree_tapbuf_size3_5_sram),
+        .sram_inv(mux_right_track_44_undriven_sram_inv),
+        .out(chanx_right_out[22])
+    );
+    mux_tree_tapbuf_size3 mux_right_track_52
+    (
+        .in({chany_top_in[9], chany_top_in[20], chanx_left_in[18]}),
+        .sram(mux_tree_tapbuf_size3_6_sram),
+        .sram_inv(mux_right_track_52_undriven_sram_inv),
+        .out(chanx_right_out[26])
+    );
+    mux_tree_tapbuf_size7 mux_right_track_6
+    (
+        .in({chany_top_in[2], chany_top_in[13], chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[8], chanx_left_in[23]}),
+        .sram(mux_tree_tapbuf_size7_1_sram),
+        .sram_inv(mux_right_track_6_undriven_sram_inv),
+        .out(chanx_right_out[3])
+    );
+    mux_tree_tapbuf_size7 mux_top_track_0
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[1], chanx_right_in[3], chanx_left_in[0], chanx_left_in[3]}),
+        .sram(mux_tree_tapbuf_size7_0_sram),
+        .sram_inv(mux_top_track_0_undriven_sram_inv),
+        .out(chany_top_out[0])
+    );
+    mux_tree_tapbuf_size5 mux_top_track_10
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[11], chanx_right_in[13], chanx_left_in[11]}),
+        .sram(mux_tree_tapbuf_size5_1_sram),
+        .sram_inv(mux_top_track_10_undriven_sram_inv),
+        .out(chany_top_out[5])
+    );
+    mux_tree_tapbuf_size4 mux_top_track_12
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_right_in[12], chanx_right_in[17], chanx_left_in[12]}),
+        .sram(mux_tree_tapbuf_size4_0_sram),
+        .sram_inv(mux_top_track_12_undriven_sram_inv),
+        .out(chany_top_out[6])
+    );
+    mux_tree_tapbuf_size4 mux_top_track_14
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_right_in[14], chanx_right_in[21], chanx_left_in[14]}),
+        .sram(mux_tree_tapbuf_size4_1_sram),
+        .sram_inv(mux_top_track_14_undriven_sram_inv),
+        .out(chany_top_out[7])
+    );
+    mux_tree_tapbuf_size4 mux_top_track_16
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_right_in[15], chanx_right_in[25], chanx_left_in[15]}),
+        .sram(mux_tree_tapbuf_size4_2_sram),
+        .sram_inv(mux_top_track_16_undriven_sram_inv),
+        .out(chany_top_out[8])
+    );
+    mux_tree_tapbuf_size4 mux_top_track_18
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_right_in[16], chanx_right_in[29], chanx_left_in[16]}),
+        .sram(mux_tree_tapbuf_size4_3_sram),
+        .sram_inv(mux_top_track_18_undriven_sram_inv),
+        .out(chany_top_out[9])
+    );
+    mux_tree_tapbuf_size6 mux_top_track_2
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[2], chanx_right_in[6], chanx_left_in[6]}),
+        .sram(mux_tree_tapbuf_size6_0_sram),
+        .sram_inv(mux_top_track_2_undriven_sram_inv),
+        .out(chany_top_out[1])
+    );
+    mux_tree_tapbuf_size3 mux_top_track_20
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_right_in[18], chanx_left_in[18]}),
+        .sram(mux_tree_tapbuf_size3_0_sram),
+        .sram_inv(mux_top_track_20_undriven_sram_inv),
+        .out(chany_top_out[10])
+    );
+    mux_tree_tapbuf_size3 mux_top_track_22
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[19], chanx_left_in[19]}),
+        .sram(mux_tree_tapbuf_size3_1_sram),
+        .sram_inv(mux_top_track_22_undriven_sram_inv),
+        .out(chany_top_out[11])
+    );
+    mux_tree_tapbuf_size3 mux_top_track_24
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[20], chanx_left_in[20]}),
+        .sram(mux_tree_tapbuf_size3_2_sram),
+        .sram_inv(mux_top_track_24_undriven_sram_inv),
+        .out(chany_top_out[12])
+    );
+    mux_tree_tapbuf_size3 mux_top_track_26
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[22], chanx_left_in[22]}),
+        .sram(mux_tree_tapbuf_size3_3_sram),
+        .sram_inv(mux_top_track_26_undriven_sram_inv),
+        .out(chany_top_out[13])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_28
+    (
+        .in({chanx_right_in[23], chanx_left_in[23]}),
+        .sram(mux_tree_tapbuf_size2_0_sram),
+        .sram_inv(mux_top_track_28_undriven_sram_inv),
+        .out(chany_top_out[14])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_30
+    (
+        .in({chanx_right_in[24], chanx_left_in[24]}),
+        .sram(mux_tree_tapbuf_size2_1_sram),
+        .sram_inv(mux_top_track_30_undriven_sram_inv),
+        .out(chany_top_out[15])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_32
+    (
+        .in({chanx_right_in[26], chanx_left_in[26]}),
+        .sram(mux_tree_tapbuf_size2_2_sram),
+        .sram_inv(mux_top_track_32_undriven_sram_inv),
+        .out(chany_top_out[16])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_34
+    (
+        .in({chanx_right_in[27], chanx_left_in[27]}),
+        .sram(mux_tree_tapbuf_size2_3_sram),
+        .sram_inv(mux_top_track_34_undriven_sram_inv),
+        .out(chany_top_out[17])
+    );
+    mux_tree_tapbuf_size3 mux_top_track_36
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_right_in[28], chanx_left_in[28]}),
+        .sram(mux_tree_tapbuf_size3_4_sram),
+        .sram_inv(mux_top_track_36_undriven_sram_inv),
+        .out(chany_top_out[18])
+    );
+    mux_tree_tapbuf_size5 mux_top_track_4
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[4], chanx_right_in[7], chanx_left_in[7]}),
+        .sram(mux_tree_tapbuf_size5_0_sram),
+        .sram_inv(mux_top_track_4_undriven_sram_inv),
+        .out(chany_top_out[2])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_40
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[29]}),
+        .sram(mux_tree_tapbuf_size2_4_sram),
+        .sram_inv(mux_top_track_40_undriven_sram_inv),
+        .out(chany_top_out[20])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_42
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[25]}),
+        .sram(mux_tree_tapbuf_size2_5_sram),
+        .sram_inv(mux_top_track_42_undriven_sram_inv),
+        .out(chany_top_out[21])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_44
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[21]}),
+        .sram(mux_tree_tapbuf_size2_6_sram),
+        .sram_inv(mux_top_track_44_undriven_sram_inv),
+        .out(chany_top_out[22])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_46
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[17]}),
+        .sram(mux_tree_tapbuf_size2_7_sram),
+        .sram_inv(mux_top_track_46_undriven_sram_inv),
+        .out(chany_top_out[23])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_48
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[13]}),
+        .sram(mux_tree_tapbuf_size2_8_sram),
+        .sram_inv(mux_top_track_48_undriven_sram_inv),
+        .out(chany_top_out[24])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_50
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[9]}),
+        .sram(mux_tree_tapbuf_size2_9_sram),
+        .sram_inv(mux_top_track_50_undriven_sram_inv),
+        .out(chany_top_out[25])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_58
+    (
+        .in({chanx_right_in[0], chanx_left_in[1]}),
+        .sram(mux_tree_tapbuf_size2_10_sram),
+        .sram_inv(mux_top_track_58_undriven_sram_inv),
+        .out(chany_top_out[29])
+    );
+    mux_tree_tapbuf_size6 mux_top_track_6
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[5], chanx_right_in[8], chanx_left_in[8]}),
+        .sram(mux_tree_tapbuf_size6_1_sram),
+        .sram_inv(mux_top_track_6_undriven_sram_inv),
+        .out(chany_top_out[3])
+    );
+    mux_tree_tapbuf_size6 mux_top_track_8
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[9], chanx_right_in[10], chanx_left_in[10]}),
+        .sram(mux_tree_tapbuf_size6_2_sram),
+        .sram_inv(mux_top_track_8_undriven_sram_inv),
+        .out(chany_top_out[4])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__0_.v

@@ -0,0 +1,889 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module sb_8__0_
+(
+    ccff_head,
+    chanx_left_in,
+    chany_top_in,
+    left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
+    left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
+    left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
+    left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
+    pReset,
+    prog_clk,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
+    top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_,
+    top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
+    top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
+    top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
+    top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
+    ccff_tail,
+    chanx_left_out,
+    chany_top_out
+);
+
+    input ccff_head;
+    input [0:29]chanx_left_in;
+    input [0:29]chany_top_in;
+    input left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
+    input left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
+    input left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
+    input left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
+    input pReset;
+    input prog_clk;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
+    input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
+    input top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
+    input top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
+    input top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
+    input top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
+    output ccff_tail;
+    output [0:29]chanx_left_out;
+    output [0:29]chany_top_out;
+
+    wire ccff_head;
+    wire ccff_tail;
+    wire [0:29]chanx_left_in;
+    wire [0:29]chanx_left_out;
+    wire [0:29]chany_top_in;
+    wire [0:29]chany_top_out;
+    wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
+    wire [0:1]mux_left_track_11_undriven_sram_inv;
+    wire [0:1]mux_left_track_13_undriven_sram_inv;
+    wire [0:1]mux_left_track_15_undriven_sram_inv;
+    wire [0:1]mux_left_track_17_undriven_sram_inv;
+    wire [0:1]mux_left_track_19_undriven_sram_inv;
+    wire [0:1]mux_left_track_1_undriven_sram_inv;
+    wire [0:1]mux_left_track_29_undriven_sram_inv;
+    wire [0:1]mux_left_track_31_undriven_sram_inv;
+    wire [0:1]mux_left_track_33_undriven_sram_inv;
+    wire [0:1]mux_left_track_35_undriven_sram_inv;
+    wire [0:1]mux_left_track_3_undriven_sram_inv;
+    wire [0:1]mux_left_track_45_undriven_sram_inv;
+    wire [0:1]mux_left_track_47_undriven_sram_inv;
+    wire [0:1]mux_left_track_49_undriven_sram_inv;
+    wire [0:1]mux_left_track_51_undriven_sram_inv;
+    wire [0:1]mux_left_track_5_undriven_sram_inv;
+    wire [0:1]mux_left_track_7_undriven_sram_inv;
+    wire [0:1]mux_left_track_9_undriven_sram_inv;
+    wire [0:2]mux_top_track_0_undriven_sram_inv;
+    wire [0:2]mux_top_track_10_undriven_sram_inv;
+    wire [0:1]mux_top_track_12_undriven_sram_inv;
+    wire [0:1]mux_top_track_14_undriven_sram_inv;
+    wire [0:1]mux_top_track_16_undriven_sram_inv;
+    wire [0:1]mux_top_track_18_undriven_sram_inv;
+    wire [0:1]mux_top_track_20_undriven_sram_inv;
+    wire [0:1]mux_top_track_22_undriven_sram_inv;
+    wire [0:1]mux_top_track_24_undriven_sram_inv;
+    wire [0:1]mux_top_track_26_undriven_sram_inv;
+    wire [0:1]mux_top_track_28_undriven_sram_inv;
+    wire [0:2]mux_top_track_2_undriven_sram_inv;
+    wire [0:1]mux_top_track_30_undriven_sram_inv;
+    wire [0:1]mux_top_track_32_undriven_sram_inv;
+    wire [0:1]mux_top_track_34_undriven_sram_inv;
+    wire [0:1]mux_top_track_36_undriven_sram_inv;
+    wire [0:1]mux_top_track_38_undriven_sram_inv;
+    wire [0:1]mux_top_track_40_undriven_sram_inv;
+    wire [0:1]mux_top_track_42_undriven_sram_inv;
+    wire [0:1]mux_top_track_44_undriven_sram_inv;
+    wire [0:1]mux_top_track_46_undriven_sram_inv;
+    wire [0:1]mux_top_track_48_undriven_sram_inv;
+    wire [0:2]mux_top_track_4_undriven_sram_inv;
+    wire [0:1]mux_top_track_50_undriven_sram_inv;
+    wire [0:2]mux_top_track_6_undriven_sram_inv;
+    wire [0:2]mux_top_track_8_undriven_sram_inv;
+    wire [0:1]mux_tree_tapbuf_size2_0_sram;
+    wire [0:1]mux_tree_tapbuf_size2_10_sram;
+    wire [0:1]mux_tree_tapbuf_size2_11_sram;
+    wire [0:1]mux_tree_tapbuf_size2_12_sram;
+    wire [0:1]mux_tree_tapbuf_size2_13_sram;
+    wire [0:1]mux_tree_tapbuf_size2_14_sram;
+    wire [0:1]mux_tree_tapbuf_size2_15_sram;
+    wire [0:1]mux_tree_tapbuf_size2_16_sram;
+    wire [0:1]mux_tree_tapbuf_size2_17_sram;
+    wire [0:1]mux_tree_tapbuf_size2_18_sram;
+    wire [0:1]mux_tree_tapbuf_size2_19_sram;
+    wire [0:1]mux_tree_tapbuf_size2_1_sram;
+    wire [0:1]mux_tree_tapbuf_size2_20_sram;
+    wire [0:1]mux_tree_tapbuf_size2_21_sram;
+    wire [0:1]mux_tree_tapbuf_size2_22_sram;
+    wire [0:1]mux_tree_tapbuf_size2_23_sram;
+    wire [0:1]mux_tree_tapbuf_size2_24_sram;
+    wire [0:1]mux_tree_tapbuf_size2_25_sram;
+    wire [0:1]mux_tree_tapbuf_size2_26_sram;
+    wire [0:1]mux_tree_tapbuf_size2_27_sram;
+    wire [0:1]mux_tree_tapbuf_size2_2_sram;
+    wire [0:1]mux_tree_tapbuf_size2_3_sram;
+    wire [0:1]mux_tree_tapbuf_size2_4_sram;
+    wire [0:1]mux_tree_tapbuf_size2_5_sram;
+    wire [0:1]mux_tree_tapbuf_size2_6_sram;
+    wire [0:1]mux_tree_tapbuf_size2_7_sram;
+    wire [0:1]mux_tree_tapbuf_size2_8_sram;
+    wire [0:1]mux_tree_tapbuf_size2_9_sram;
+    wire mux_tree_tapbuf_size2_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_10_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_11_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_12_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_13_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_14_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_15_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_16_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_17_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_18_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_19_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_20_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_21_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_22_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_23_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_24_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_25_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_26_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_6_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_7_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_8_ccff_tail;
+    wire mux_tree_tapbuf_size2_mem_9_ccff_tail;
+    wire [0:1]mux_tree_tapbuf_size3_0_sram;
+    wire [0:1]mux_tree_tapbuf_size3_1_sram;
+    wire [0:1]mux_tree_tapbuf_size3_2_sram;
+    wire [0:1]mux_tree_tapbuf_size3_3_sram;
+    wire [0:1]mux_tree_tapbuf_size3_4_sram;
+    wire [0:1]mux_tree_tapbuf_size3_5_sram;
+    wire [0:1]mux_tree_tapbuf_size3_6_sram;
+    wire [0:1]mux_tree_tapbuf_size3_7_sram;
+    wire [0:1]mux_tree_tapbuf_size3_8_sram;
+    wire [0:1]mux_tree_tapbuf_size3_9_sram;
+    wire mux_tree_tapbuf_size3_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_5_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_6_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_7_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_8_ccff_tail;
+    wire mux_tree_tapbuf_size3_mem_9_ccff_tail;
+    wire [0:2]mux_tree_tapbuf_size5_0_sram;
+    wire [0:2]mux_tree_tapbuf_size5_1_sram;
+    wire [0:2]mux_tree_tapbuf_size5_2_sram;
+    wire [0:2]mux_tree_tapbuf_size5_3_sram;
+    wire [0:2]mux_tree_tapbuf_size5_4_sram;
+    wire [0:2]mux_tree_tapbuf_size5_5_sram;
+    wire mux_tree_tapbuf_size5_mem_0_ccff_tail;
+    wire mux_tree_tapbuf_size5_mem_1_ccff_tail;
+    wire mux_tree_tapbuf_size5_mem_2_ccff_tail;
+    wire mux_tree_tapbuf_size5_mem_3_ccff_tail;
+    wire mux_tree_tapbuf_size5_mem_4_ccff_tail;
+    wire mux_tree_tapbuf_size5_mem_5_ccff_tail;
+    wire pReset;
+    wire prog_clk;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
+    wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
+    wire top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
+    wire top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
+    wire top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
+    wire top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
+
+assign chanx_left_out[29] = chany_top_in[1];
+assign chanx_left_out[28] = chany_top_in[2];
+assign chanx_left_out[11] = chany_top_in[19];
+assign chanx_left_out[10] = chany_top_in[20];
+assign chany_top_out[29] = chanx_left_in[1];
+assign chany_top_out[28] = chanx_left_in[2];
+assign chany_top_out[27] = chanx_left_in[3];
+assign chany_top_out[26] = chanx_left_in[4];
+assign chanx_left_out[27] = chany_top_in[3];
+assign chanx_left_out[26] = chany_top_in[4];
+assign chanx_left_out[21] = chany_top_in[9];
+assign chanx_left_out[20] = chany_top_in[10];
+assign chanx_left_out[19] = chany_top_in[11];
+assign chanx_left_out[18] = chany_top_in[12];
+assign chanx_left_out[13] = chany_top_in[17];
+assign chanx_left_out[12] = chany_top_in[18];
+    mux_tree_tapbuf_size3_mem mem_left_track_1
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_8_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_11
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_15_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_13
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_16_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_15
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_17_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_17
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_18_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_19
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_19_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_29
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_20_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_3
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_12_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_31
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_21_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_33
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_22_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_35
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_23_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_45
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_24_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_47
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_25_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_49
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_26_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_5
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_13_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_51
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_27_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_left_track_7
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_9_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_left_track_9
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_14_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_top_track_0
+    (
+        .ccff_head(ccff_head),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_0_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_top_track_10
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_5_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_top_track_12
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_0_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_top_track_14
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_1_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_top_track_16
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_2_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_top_track_18
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_3_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_top_track_2
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_1_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_20
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_0_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_22
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_1_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_24
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_2_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_26
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_3_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_28
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_4_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_30
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_5_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_32
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_6_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_34
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_7_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_36
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_8_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_38
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_9_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_top_track_4
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_2_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_40
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_10_sram)
+    );
+    mux_tree_tapbuf_size2_mem mem_top_track_42
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size2_11_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_top_track_44
+    (
+        .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_4_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_top_track_46
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_5_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_top_track_48
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_6_sram)
+    );
+    mux_tree_tapbuf_size3_mem mem_top_track_50
+    (
+        .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size3_7_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_top_track_6
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_3_sram)
+    );
+    mux_tree_tapbuf_size5_mem mem_top_track_8
+    (
+        .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
+        .pReset(pReset),
+        .prog_clk(prog_clk),
+        .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
+        .mem_out(mux_tree_tapbuf_size5_4_sram)
+    );
+    mux_tree_tapbuf_size3 mux_left_track_1
+    (
+        .in({chany_top_in[0], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size3_8_sram),
+        .sram_inv(mux_left_track_1_undriven_sram_inv),
+        .out(chanx_left_out[0])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_11
+    (
+        .in({chany_top_in[25], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_15_sram),
+        .sram_inv(mux_left_track_11_undriven_sram_inv),
+        .out(chanx_left_out[5])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_13
+    (
+        .in({chany_top_in[24], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_16_sram),
+        .sram_inv(mux_left_track_13_undriven_sram_inv),
+        .out(chanx_left_out[6])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_15
+    (
+        .in({chany_top_in[23], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_17_sram),
+        .sram_inv(mux_left_track_15_undriven_sram_inv),
+        .out(chanx_left_out[7])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_17
+    (
+        .in({chany_top_in[22], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_18_sram),
+        .sram_inv(mux_left_track_17_undriven_sram_inv),
+        .out(chanx_left_out[8])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_19
+    (
+        .in({chany_top_in[21], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_19_sram),
+        .sram_inv(mux_left_track_19_undriven_sram_inv),
+        .out(chanx_left_out[9])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_29
+    (
+        .in({chany_top_in[16], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_20_sram),
+        .sram_inv(mux_left_track_29_undriven_sram_inv),
+        .out(chanx_left_out[14])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_3
+    (
+        .in({chany_top_in[29], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_12_sram),
+        .sram_inv(mux_left_track_3_undriven_sram_inv),
+        .out(chanx_left_out[1])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_31
+    (
+        .in({chany_top_in[15], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_21_sram),
+        .sram_inv(mux_left_track_31_undriven_sram_inv),
+        .out(chanx_left_out[15])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_33
+    (
+        .in({chany_top_in[14], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_22_sram),
+        .sram_inv(mux_left_track_33_undriven_sram_inv),
+        .out(chanx_left_out[16])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_35
+    (
+        .in({chany_top_in[13], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_23_sram),
+        .sram_inv(mux_left_track_35_undriven_sram_inv),
+        .out(chanx_left_out[17])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_45
+    (
+        .in({chany_top_in[8], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_24_sram),
+        .sram_inv(mux_left_track_45_undriven_sram_inv),
+        .out(chanx_left_out[22])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_47
+    (
+        .in({chany_top_in[7], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_25_sram),
+        .sram_inv(mux_left_track_47_undriven_sram_inv),
+        .out(chanx_left_out[23])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_49
+    (
+        .in({chany_top_in[6], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_26_sram),
+        .sram_inv(mux_left_track_49_undriven_sram_inv),
+        .out(chanx_left_out[24])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_5
+    (
+        .in({chany_top_in[28], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_13_sram),
+        .sram_inv(mux_left_track_5_undriven_sram_inv),
+        .out(chanx_left_out[2])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_51
+    (
+        .in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_27_sram),
+        .sram_inv(mux_left_track_51_undriven_sram_inv),
+        .out(chanx_left_out[25])
+    );
+    mux_tree_tapbuf_size3 mux_left_track_7
+    (
+        .in({chany_top_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size3_9_sram),
+        .sram_inv(mux_left_track_7_undriven_sram_inv),
+        .out(chanx_left_out[3])
+    );
+    mux_tree_tapbuf_size2 mux_left_track_9
+    (
+        .in({chany_top_in[26], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
+        .sram(mux_tree_tapbuf_size2_14_sram),
+        .sram_inv(mux_left_track_9_undriven_sram_inv),
+        .out(chanx_left_out[4])
+    );
+    mux_tree_tapbuf_size5 mux_top_track_0
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[0]}),
+        .sram(mux_tree_tapbuf_size5_0_sram),
+        .sram_inv(mux_top_track_0_undriven_sram_inv),
+        .out(chany_top_out[0])
+    );
+    mux_tree_tapbuf_size5 mux_top_track_10
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[25]}),
+        .sram(mux_tree_tapbuf_size5_5_sram),
+        .sram_inv(mux_top_track_10_undriven_sram_inv),
+        .out(chany_top_out[5])
+    );
+    mux_tree_tapbuf_size3 mux_top_track_12
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[24]}),
+        .sram(mux_tree_tapbuf_size3_0_sram),
+        .sram_inv(mux_top_track_12_undriven_sram_inv),
+        .out(chany_top_out[6])
+    );
+    mux_tree_tapbuf_size3 mux_top_track_14
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[23]}),
+        .sram(mux_tree_tapbuf_size3_1_sram),
+        .sram_inv(mux_top_track_14_undriven_sram_inv),
+        .out(chany_top_out[7])
+    );
+    mux_tree_tapbuf_size3 mux_top_track_16
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[22]}),
+        .sram(mux_tree_tapbuf_size3_2_sram),
+        .sram_inv(mux_top_track_16_undriven_sram_inv),
+        .out(chany_top_out[8])
+    );
+    mux_tree_tapbuf_size3 mux_top_track_18
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[21]}),
+        .sram(mux_tree_tapbuf_size3_3_sram),
+        .sram_inv(mux_top_track_18_undriven_sram_inv),
+        .out(chany_top_out[9])
+    );
+    mux_tree_tapbuf_size5 mux_top_track_2
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[29]}),
+        .sram(mux_tree_tapbuf_size5_1_sram),
+        .sram_inv(mux_top_track_2_undriven_sram_inv),
+        .out(chany_top_out[1])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_20
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[20]}),
+        .sram(mux_tree_tapbuf_size2_0_sram),
+        .sram_inv(mux_top_track_20_undriven_sram_inv),
+        .out(chany_top_out[10])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_22
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[19]}),
+        .sram(mux_tree_tapbuf_size2_1_sram),
+        .sram_inv(mux_top_track_22_undriven_sram_inv),
+        .out(chany_top_out[11])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_24
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[18]}),
+        .sram(mux_tree_tapbuf_size2_2_sram),
+        .sram_inv(mux_top_track_24_undriven_sram_inv),
+        .out(chany_top_out[12])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_26
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[17]}),
+        .sram(mux_tree_tapbuf_size2_3_sram),
+        .sram_inv(mux_top_track_26_undriven_sram_inv),
+        .out(chany_top_out[13])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_28
+    (
+        .in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[16]}),
+        .sram(mux_tree_tapbuf_size2_4_sram),
+        .sram_inv(mux_top_track_28_undriven_sram_inv),
+        .out(chany_top_out[14])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_30
+    (
+        .in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[15]}),
+        .sram(mux_tree_tapbuf_size2_5_sram),
+        .sram_inv(mux_top_track_30_undriven_sram_inv),
+        .out(chany_top_out[15])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_32
+    (
+        .in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[14]}),
+        .sram(mux_tree_tapbuf_size2_6_sram),
+        .sram_inv(mux_top_track_32_undriven_sram_inv),
+        .out(chany_top_out[16])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_34
+    (
+        .in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[13]}),
+        .sram(mux_tree_tapbuf_size2_7_sram),
+        .sram_inv(mux_top_track_34_undriven_sram_inv),
+        .out(chany_top_out[17])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_36
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[12]}),
+        .sram(mux_tree_tapbuf_size2_8_sram),
+        .sram_inv(mux_top_track_36_undriven_sram_inv),
+        .out(chany_top_out[18])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_38
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[11]}),
+        .sram(mux_tree_tapbuf_size2_9_sram),
+        .sram_inv(mux_top_track_38_undriven_sram_inv),
+        .out(chany_top_out[19])
+    );
+    mux_tree_tapbuf_size5 mux_top_track_4
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[28]}),
+        .sram(mux_tree_tapbuf_size5_2_sram),
+        .sram_inv(mux_top_track_4_undriven_sram_inv),
+        .out(chany_top_out[2])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_40
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[10]}),
+        .sram(mux_tree_tapbuf_size2_10_sram),
+        .sram_inv(mux_top_track_40_undriven_sram_inv),
+        .out(chany_top_out[20])
+    );
+    mux_tree_tapbuf_size2 mux_top_track_42
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[9]}),
+        .sram(mux_tree_tapbuf_size2_11_sram),
+        .sram_inv(mux_top_track_42_undriven_sram_inv),
+        .out(chany_top_out[21])
+    );
+    mux_tree_tapbuf_size3 mux_top_track_44
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[8]}),
+        .sram(mux_tree_tapbuf_size3_4_sram),
+        .sram_inv(mux_top_track_44_undriven_sram_inv),
+        .out(chany_top_out[22])
+    );
+    mux_tree_tapbuf_size3 mux_top_track_46
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[7]}),
+        .sram(mux_tree_tapbuf_size3_5_sram),
+        .sram_inv(mux_top_track_46_undriven_sram_inv),
+        .out(chany_top_out[23])
+    );
+    mux_tree_tapbuf_size3 mux_top_track_48
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[6]}),
+        .sram(mux_tree_tapbuf_size3_6_sram),
+        .sram_inv(mux_top_track_48_undriven_sram_inv),
+        .out(chany_top_out[24])
+    );
+    mux_tree_tapbuf_size3 mux_top_track_50
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[5]}),
+        .sram(mux_tree_tapbuf_size3_7_sram),
+        .sram_inv(mux_top_track_50_undriven_sram_inv),
+        .out(chany_top_out[25])
+    );
+    mux_tree_tapbuf_size5 mux_top_track_6
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[27]}),
+        .sram(mux_tree_tapbuf_size5_3_sram),
+        .sram_inv(mux_top_track_6_undriven_sram_inv),
+        .out(chany_top_out[3])
+    );
+    mux_tree_tapbuf_size5 mux_top_track_8
+    (
+        .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[26]}),
+        .sram(mux_tree_tapbuf_size5_4_sram),
+        .sram_inv(mux_top_track_8_undriven_sram_inv),
+        .out(chany_top_out[4])
+    );
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__buf_2.v

@@ -0,0 +1,16 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module sky130_fd_sc_hd__buf_2
+(
+    A,
+    X
+);
+
+    input A;
+    output X;
+
+    wire A;
+    wire X;
+
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__buf_4.v

@@ -0,0 +1,16 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module sky130_fd_sc_hd__buf_4
+(
+    A,
+    X
+);
+
+    input A;
+    output X;
+
+    wire A;
+    wire X;
+
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__dfrtp_1.v

@@ -0,0 +1,22 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module sky130_fd_sc_hd__dfrtp_1
+(
+    CLK,
+    D,
+    RESET_B,
+    Q
+);
+
+    input CLK;
+    input D;
+    input RESET_B;
+    output Q;
+
+    wire CLK;
+    wire D;
+    wire Q;
+    wire RESET_B;
+
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__inv_1.v

@@ -0,0 +1,16 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module sky130_fd_sc_hd__inv_1
+(
+    A,
+    Y
+);
+
+    input A;
+    output Y;
+
+    wire A;
+    wire Y;
+
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__inv_2.v

@@ -0,0 +1,16 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module sky130_fd_sc_hd__inv_2
+(
+    A,
+    Y
+);
+
+    input A;
+    output Y;
+
+    wire A;
+    wire Y;
+
+endmodule
+

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__mux2_1.v

@@ -0,0 +1,22 @@
+//Generated from netlist by SpyDrNet
+//netlist name: FPGA88_SOFA_A
+module sky130_fd_sc_hd__mux2_1
+(
+    A0,
+    A1,
+    S,
+    X
+);
+
+    input A0;
+    input A1;
+    input S;
+    output X;
+
+    wire A0;
+    wire A1;
+    wire S;
+    wire X;
+
+endmodule
+