diff --git a/.gitignore b/.gitignore index 80ea0d6..f3211ec 100644 --- a/.gitignore +++ b/.gitignore @@ -16,3 +16,4 @@ **/*_task/run** **/*_task/config/task.conf .vscode/ +LoadTools.sh diff --git a/SOFA_A/.gitignore b/SOFA_A/.gitignore new file mode 100644 index 0000000..8826fc4 --- /dev/null +++ b/SOFA_A/.gitignore @@ -0,0 +1,24 @@ +# Ignore all +* +# Unignore all with extensions +!*.* +# Unignore all dirs +!*/ +# Unignore makefiles +!Makefile* +# Ignore directories starting with . in from root directory +/.*/ +# All files starting underscroll +_*.* +# All directories starting underscroll +_* +# Unignore python init_file +!__init__.py + + +# OpenFPGA Task ignore files +task.conf +!*_pnr/*_task/** +**/*_task/latest +**/*_task/run* +**/release/pickle/ \ No newline at end of file diff --git a/SOFA_A/CommonFiles/render_sofa_a.py b/SOFA_A/CommonFiles/render_sofa_a.py new file mode 100644 index 0000000..7c45695 --- /dev/null +++ b/SOFA_A/CommonFiles/render_sofa_a.py @@ -0,0 +1,126 @@ +""" +This file redners the fabric before the netlist generation +""" +import logging +import os +import pickle +from glob import glob +from pathlib import Path + +from spydrnet_physical.util import FPGAGridGen + +logger = logging.getLogger("spydrnet_logs") + +PROJ_NAME = os.environ["PROJ_NAME"] +RELEASE_DIR = os.environ["RELEASE_DIRECTORY"] +LAYOUT = os.environ["LAYOUT"] +TASK_DIR_NAME = os.environ["TASK_DIR_NAME"] +SVG_DIR = f"{RELEASE_DIR}/svg" +XML_DIR = f"{RELEASE_DIR}/xml" +PICKLE_DIR = f"{RELEASE_DIR}/pickle" + +def main(): + """ + Main flow + """ + try: + VPR_ARCH_FILE = glob((f"{TASK_DIR_NAME}/arch/*vpr*"))[0] + except IndexError: + logger.exception( + "Architecture file not found ['%s/arch/*vpr*']", TASK_DIR_NAME) + exit(1) + logger.info("Reading architeture file %s", VPR_ARCH_FILE) + # Demonstrates how to modify the structure + fpga = FPGAGridGen( + design_name=PROJ_NAME, + arch_file=VPR_ARCH_FILE, + release_root=RELEASE_DIR, + layout=LAYOUT, + ) + logger.info("Loading Layout %s", LAYOUT) + fpga.enumerate_grid() + fpga.default_parameters["cbx"][0] = 10 # uncomment to force square plan + fpga.default_parameters["cby"][1] = 10 # uncomment to force square plan + Path(SVG_DIR).mkdir(parents=True, exist_ok=True) + Path(PICKLE_DIR).mkdir(parents=True, exist_ok=True) + + dwg = fpga.render_layout( + filename=f"{SVG_DIR}/{PROJ_NAME}_render.svg", grid_io=True) + + dwg.save(pretty=True, indent=4) + pickle.dump(dwg, open(f"{PICKLE_DIR}/{PROJ_NAME}_render.pickle", "wb")) + logger.info("Saving file %s/%s_render.svg", SVG_DIR, PROJ_NAME) + + # ============ Modify your floorplan here ============ + # Adding stylesheet + fpga.add_style("symbol[id*='sides_merged'] * { fill:green; opacity:0.5 }") + fpga.add_style("symbol[id*='corner'] * { fill:#28f7c7; opacity:0.5 }") + fpga.add_style("symbol[id*='main_tile'] * { fill:#F0A35E; opacity:0.5 }") + fpga.add_style("symbol[id*='merged'] * { stroke:white; stroke-width:1px;}") + + # Extract width and height + w = fpga.get_width() + h = fpga.get_height() + + for y in range(2, h): + x = 0 + instances = [f"cby_{x}__{y}_", f"sb_{x}__{y}_", + f"cbx_{x+1}__{y}_", f"clb_{x+1}__{y}_", + f"cby_{x+1}__{y}_", f"sb_{x+1}__{y}_"] + fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}") + x = w + instances = [f"cby_{x}__{y}_", f"sb_{x}__{y}_", + f"cbx_{x}__{y}_", f"clb_{x}__{y}_"] + fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}") + + for x in range(2, w): + y = 0 + instances = [f"cbx_{x}__{y}_", f"sb_{x}__{y}_", + f"cby_{x}__{y+1}_", f"clb_{x}__{y+1}_", + f"cbx_{x}__{y+1}_", f"sb_{x}__{y+1}_"] + fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}") + y = h + instances = [f"cbx_{x}__{y}_", f"sb_{x}__{y}_", + f"cby_{x}__{y}_", f"clb_{x}__{y}_"] + fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}") + + # Main tile + for x in range(2, w): + for y in range(2, h): + fpga.merge_symbol( + [ f"clb_{x}__{y}_", f"sb_{x}__{y}_", + f"cbx_{x}__{y}_", f"cby_{x}__{y}_"], + f"main_tile_merged_{x}_{y}") + + # Corner Tiles + fpga.merge_symbol( + [f"cby_0__{h}_", f"sb_0__{h}_", f"cbx_1__{h}_", + f"cby_1__{h}_", f"sb_1__{h}_"], "corner_merged_ltop") + fpga.merge_symbol( + [f"cbx_{w}__{h}_", f"cby_{w}__{h}_", + f"clb_{w}__{h}_", f"sb_{w}__{h}_"], "corner_merged_rtop") + fpga.merge_symbol( + [f"cbx_{w}__0_", f"cbx_{w}__1_", + f"sb_{w}__0_", f"sb_{w}__1_", + f"cby_{w}__1_", f"clb_{w}__1_"], "corner_merged_rbottom") + fpga.merge_symbol( + ["cbx_1__0_", "cbx_1__1_", + "sb_0__0_", "sb_0__1_", + "sb_1__0_", "sb_1__1_", + "cby_1__1_", "clb_1__1_"], "corner_merged_lbottom") + + # ====================== END ========================= + + dwg.saveas( + filename=f"{SVG_DIR}/{PROJ_NAME}_restruct_render.svg", pretty=True, indent=4 + ) + pickle.dump( + dwg, open(f"{PICKLE_DIR}/{PROJ_NAME}_restruct_render.pickle", "wb")) + pickle.dump(fpga, open( + f"{PICKLE_DIR}/{PROJ_NAME}_fpgagridgen.pickle", "wb")) + logger.info("Saving file %s/%s_restruct_render.svg", SVG_DIR, PROJ_NAME) + return dwg + + +if __name__ == "__main__": + main() diff --git a/SOFA_A/CommonFiles/render_sofa_a_fabric_key.py b/SOFA_A/CommonFiles/render_sofa_a_fabric_key.py new file mode 100644 index 0000000..1c943fa --- /dev/null +++ b/SOFA_A/CommonFiles/render_sofa_a_fabric_key.py @@ -0,0 +1,84 @@ +# ############################################################################## +# Tool: OpenFPGA-Physical +# Script: generate_fabric_key.py +# Description : This script cretes a fabric_key.xml file for give size of FPGA +# Currently this script generate pattern which routes configuration chain +# from right top corner to left bottom corner by traversing horizontally +# in every row of the FPGA grid +################################################################################ +""" +File Title +""" + + +import logging +import os +from glob import glob +import pickle +from copy import deepcopy +from pathlib import Path + +from spydrnet_physical.util import FabricKeyGenCCFF + +logger = logging.getLogger("spydrnet_logs") + + +PROJ_NAME = os.environ["PROJ_NAME"] +RELEASE_DIR = os.environ["RELEASE_DIRECTORY"] +FPGA_WIDTH = int(os.environ.get("FPGA_SIZE_X")) +FPGA_HEIGHT = int(os.environ.get("FPGA_SIZE_Y")) +FABRIC_KEY_PATTERN = os.environ["FABRIC_KEY_PATTERN"] +TASK_DIR_NAME = os.environ.get("TASK_DIR_NAME") +LAYOUT = os.environ["LAYOUT"] +TASK_DIR_NAME = os.environ["TASK_DIR_NAME"] +VERILOG_PROJ_DIR = os.environ["VERILOG_PROJ_DIR"] +SVG_DIR = f"{RELEASE_DIR}/svg" +XML_DIR = f"{RELEASE_DIR}/xml" +PICKLE_DIR = f"{RELEASE_DIR}/pickle" + + + +class CustomFabricKey(FabricKeyGenCCFF): + """ + Extending `FabricKeyGenCCFF` + """ + + def create_fabric_key(self, pattern=None): + """ + Create fabric key command + """ + super().create_fabric_key(pattern) + + +def main(): + """ + Main method to execute function + """ + with open(f"{PICKLE_DIR}/{PROJ_NAME}_fpgagridgen.pickle", "rb") as file_ptr: + fpga = pickle.load(file_ptr) + fabric_key = CustomFabricKey(fpga) + + fabric_key.create_fabric_key(FABRIC_KEY_PATTERN) + filename = os.path.join(SVG_DIR, f"{PROJ_NAME}_CCFF_Chain.svg") + fabric_key.render_svg(filename=filename) + + fabric_filename = os.path.join(TASK_DIR_NAME, "flow_inputs", "fabric_key.xml") + fabric_key.save_fabric_key(filename=fabric_filename) + + try: + bitstream_dist_file = glob(f"{RELEASE_DIR}/*_verilog/XML/*_distribution.xml")[0] + fabric_key.read_bistream_distribution(bitstream_dist_file) + fabric_key.validate_key( + skip_missing_checks=False, skip_extra_instance_checks=False + ) + bit_stat = fabric_key.bitstream_stats() + max_bits = max(bit_stat.values()) + for region, bitstream in bit_stat.items(): + print(f"{region:10s} ", end="") + print("█" * round(100 * (bitstream / max_bits)), end="") + print(f" {bitstream/max_bits:.1%} [{bitstream:>6d}]") + except IndexError: + logger.warning("bitstream_dist_file not found skipping validation") + +if __name__ == "__main__": + main() diff --git a/SOFA_A/CommonFiles/restructure_fabric_sofa_a.py b/SOFA_A/CommonFiles/restructure_fabric_sofa_a.py new file mode 100644 index 0000000..2fff185 --- /dev/null +++ b/SOFA_A/CommonFiles/restructure_fabric_sofa_a.py @@ -0,0 +1,308 @@ +""" +Restructuring for castor +Template : restructure_fabric.py [openfpga-physical] +Author: Ganesh Gore + +Stages for tiling + +- *_raw_floorplan +- *_original_floorplan +- *_pre_tile floorplan +- *_final_floorplan + +""" +import gzip +import json +import logging +import os +import pickle +import re +import shutil +import sys +import time +import xml.etree.ElementTree as ET +from collections import OrderedDict +from copy import deepcopy +from fnmatch import fnmatch +from glob import glob +from itertools import chain +from pathlib import Path + +import spydrnet as sdn +import yaml +from spydrnet_physical.util import ( + ConnectPointList, + FloorPlanViz, + FPGAGridGen, + OpenFPGA, + Tile02, + get_names, + initial_hetero_placement, +) +from spydrnet_physical.util.shell import launch_shell +from svgwrite.container import Group + +logger = logging.getLogger("spydrnet_logs") +sdn.enable_file_logging(LOG_LEVEL="INFO", filename="restructuring") + + +# Constants Decalartion Section +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +PROP = "VERILOG.InlineConstraints" + +LAYOUT = os.environ.get("LAYOUT") +PROJ_NAME = os.environ.get("PROJ_NAME") +TASK_DIR_NAME = os.environ.get("TASK_DIR_NAME") +VERILOG_DIRECTORY = os.environ.get("VERILOG_PROJ_DIR") +FPGA_WIDTH = int(os.environ.get("FPGA_SIZE_X")) +FPGA_HEIGHT = int(os.environ.get("FPGA_SIZE_Y")) +RELEASE_DIR = os.environ["RELEASE_DIRECTORY"] +SVG_DIR = f"{RELEASE_DIR}/svg/" +PICKLE_DIR = f"{RELEASE_DIR}/pickle/" +XML_DIR = f"{RELEASE_DIR}/xml" + +CBX_COLOR = "#d9d9f3" +CBY_COLOR = "#a8d0db" +SB_COLOR = "#ceefe4" +GRID_COLOR = "#ddd0b1" + +GLOBAL_SCALE = 1000 +SC_HEIGHT = 480 +CPP = 96 +SC_GRID = SC_HEIGHT * CPP + +ADDITIONAL_STYLES = "" +STYLE_SHEET = """ + symbol {mix-blend-mode: difference;} + symbol[id*='grid_dsp'] * {fill:#70AE98;} + symbol[id*='grid_io'] * {fill:#e6a210;} + symbol[id*='grid_bram'] * {fill:#BC85C3;} + .over_util {fill:#b22222 !important} + text{font-family: Lato; font-style: italic; font-size: 3500px;} + rect.highlight_box { fill:none; stroke-width:40; stroke:green;} + text.highlight_box { font-size:500px; font-weight:800; fill:red} + line {stroke-width:20px !important;} +""" + +mapping = {} +script_start_time = time.time() + +# %% +# Main method to perform restructuring +# + + +def main(): + """ + Main method + """ + global ADDITIONAL_STYLES + + Path(f"{RELEASE_DIR}/post_synth").mkdir(parents=True, exist_ok=True) + Path(f"{RELEASE_DIR}/rpts/pre_pnr").mkdir(parents=True, exist_ok=True) + try: + VPR_ARCH_FILE = glob((f"{TASK_DIR_NAME}/arch/*vpr*.xml"))[0] + except IndexError: + logger.exception( + "Arch file not found ['%s/arch/*vpr*.xml']", TASK_DIR_NAME) + sys.exit() + source_files = glob(f"{VERILOG_DIRECTORY}/SRCSynth/*.v") + source_files += glob(f"{VERILOG_DIRECTORY}/SRCSynth/*/*.v") + + for file in source_files: + logger.debug("Reading file: %s", file) + fpga = OpenFPGA(grid=(FPGA_WIDTH, FPGA_HEIGHT), verilog_files=source_files) + fpga.netlist.name = PROJ_NAME + print_time_elpased("Finished netlist parsing") + + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + Path(SVG_DIR).mkdir(parents=True, exist_ok=True) + Path(PICKLE_DIR).mkdir(parents=True, exist_ok=True) + + # Read eaternal area information + filename = f"{RELEASE_DIR}/post_synth/fpga_top_module_area.rpt" + if os.path.isfile(filename): + fpga.annotate_area_information(filename, skipline=1) + + # sump top level port information + filename = f"{RELEASE_DIR}/post_synth/top_instances_ports.txt" + dump_top_definition_ports(fpga, rpt_file=filename) + + # Visualize Floorplan + fpga_grid = FPGAGridGen( + design_name=PROJ_NAME, layout=LAYOUT, arch_file=VPR_ARCH_FILE, release_root=None + ) + fpga_grid.enumerate_grid() + fpga.load_grid(fpga_grid) + + fpga.register_placement_creator( + initial_hetero_placement, + areaFile={}, + ) + fpga.merge_all_grid_ios() + fpga.remove_direct_interc() + + fpga.placement_creator.CPP = CPP + fpga.placement_creator.SC_HEIGHT = SC_HEIGHT + fpga.placement_creator.SC_GRID = CPP * SC_HEIGHT + top = fpga.top_module + + WSmall, HSmall = fpga.fpga_size + W, H = fpga.fpga_size + + # ========================================================================== + with open(r'shapes.yaml', 'r', encoding="UTF-8") as file: + m = yaml.safe_load(file) + # ========================================================================== + fpga.placement_creator.update_shaping_param(m) + fpga.placement_creator.derive_sb_paramters() + auto_shaped_modules = fpga.placement_creator.create_shapes( + w_override=WSmall, h_override=HSmall, shape_all=True) + shapes = fpga.placement_creator.module_shapes + + print(auto_shaped_modules) + for each in auto_shaped_modules: + if "cbx" in each: + if "__0_" in each: + shapes[each] = deepcopy(shapes["cbx_1__0_"]) + elif f"__{HSmall}_" in each: + shapes[each] = deepcopy(shapes[f"cbx_1__{HSmall}_"]) + else: + shapes[each] = deepcopy(shapes["cbx_1__1_"]) + if "cby" in each: + if "_0__" in each: + shapes[each] = deepcopy(shapes["cby_0__1_"]) + elif f"_{WSmall}__" in each: + shapes[each] = deepcopy(shapes[f"cby_{WSmall}__1_"]) + else: + shapes[each] = deepcopy(shapes["cby_1__1_"]) + if "sb" in each: + if f"__{HSmall}_" in each: + shapes[each] = deepcopy(shapes[f"sb_1__{HSmall}_"]) + else: + shapes[each] = deepcopy(shapes["sb_1__1_"]) + if "grid" in each: + shapes[each] = deepcopy(shapes["grid_clb"]) + + fpga.create_placement() + # fpga.update_module_label() + + fpga.save_shaping_data( + "*", + scale=1 / GLOBAL_SCALE, + filename=f"{RELEASE_DIR}/rpts/pre_pnr/shaping.txt", + ) + + filename = SVG_DIR + f"{PROJ_NAME}_raw_floorplan.svg" + save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET) + + # Adding Narrow channels + # %% + # **Adding margin** + # + for module in shapes: + if "grid_" in module: + shapes[module]["POINTS"][0] -= 16 + shapes[module]["POINTS"][1] -= 2 + shapes[module]["PLACEMENT"][0] += 8 + shapes[module]["PLACEMENT"][1] += 1 + + for module in shapes: + if "cbx_" in module: + shapes[module]["POINTS"][0] -= 16 + shapes[module]["PLACEMENT"][0] += 8 + + for module in shapes: + if "cby_" in module: + shapes[module]["POINTS"][1] -= 2 + shapes[module]["PLACEMENT"][1] += 1 + + fpga.create_placement() + + filename = SVG_DIR + f"{PROJ_NAME}_pre_tile_floorplan.svg" + save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET) + + # Create tiles + fpga.register_tile_generator(Tile02) + fpga.create_tiles() + save_netlist(fpga) + + filename = SVG_DIR + f"{PROJ_NAME}_floorplan.svg" + save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET) + # pickle.dump( + # dwg, open(f"{PICKLE_DIR}/{PROJ_NAME}_floorplaned.pickle", "wb")) + logger.info("Saved floorplan in %s", filename) + # save_netlist_outline(fpga) + +def save_tiling_floorplan(fpga: OpenFPGA, filename: str, STYLE_SHEET=None): + """ + Save currnt tiling strategy to SVG file + """ + fp = FloorPlanViz(fpga.top_module) + fp.compose(skip_connections=True, skip_pins=True) + fp.custom_style_sheet = STYLE_SHEET + dwg = fp.get_svg() + dwg.add(fpga.placement_creator.design_grid.render_grid(return_group=True)) + + pattern = dwg.pattern(size=(4 * CPP, 2 * SC_HEIGHT), patternUnits="userSpaceOnUse") + pattern.add(dwg.circle(center=(2, 2), r=1, fill="black")) + pattern.add(dwg.circle(center=(2, SC_HEIGHT + 2), r=1, fill="red")) + dwg.defs.add(pattern) + dwg.defs.elements[0].elements[0].attribs["fill"] = pattern.get_funciri() + dwg.saveas(filename, pretty=True, indent=4) + +def save_netlist(fpga: OpenFPGA): + """ + Save OpenFPGA netlist + """ + base_dir = (VERILOG_DIRECTORY, "SRC") + + shutil.rmtree( + os.path.join(*base_dir), + ignore_errors=True, + ) + Path(os.path.join(*base_dir)).mkdir(parents=True, exist_ok=True) + options = { + "skip_constraints": True, + "sort_cables": True, + "sort_print": True, + "sort_instances": True, + "sort_ports": True, + } + fpga.save_netlist("logical_tile*", os.path.join(*base_dir, "submodules"), **options) + fpga.save_netlist("*tile*", os.path.join(*base_dir, "tile"), **options) + fpga.save_netlist("fpga_core", os.path.join(*base_dir), **options) + fpga.save_netlist("fpga_top", os.path.join(*base_dir), **options) + fpga.save_netlist("[!BUFF][!TIE][!DFQ]*", os.path.join(*base_dir, "submodules"), write_blackbox=False, **options) + include_file = os.path.join(*base_dir, "fabric_netlists.v") + fpga.write_include_file(include_file) + +def dump_top_definition_ports(fpga: OpenFPGA, rpt_file, pattern=None): + """ + Create top level port + """ + portmap = OrderedDict() + instances = {t.name: t for t in fpga.top_module.get_definitions()} + instances = OrderedDict(sorted(instances.items(), reverse=True)) + for def_name, defs in instances.items(): + if "ASSIGN" in def_name: + continue + if def_name.startswith("const"): + continue + portmap[def_name] = sorted([f"{port.size:04d}_{port.direction:5s},{port.name}" for port in defs.get_ports("*")]) + if pattern: + portmap[def_name] = list(filter(pattern, portmap[def_name])) + + json.dump(portmap, open(rpt_file, "w", encoding="UTF-8"), indent=4) + + +def print_time_elpased(msg): + """ Prints runtime since previous call to this function """ + global script_start_time + script_start_time_new = time.time() + logger.info("[%8.2d] %s", (script_start_time_new - script_start_time), msg) + script_start_time = script_start_time_new + + +if __name__ == "__main__": + main() diff --git a/SOFA_A/CommonFiles/sofa_netlist_synth_script.sh b/SOFA_A/CommonFiles/sofa_netlist_synth_script.sh new file mode 100644 index 0000000..33e5861 --- /dev/null +++ b/SOFA_A/CommonFiles/sofa_netlist_synth_script.sh @@ -0,0 +1,5 @@ +#! /usr/bin/env bash + +echo "Running netlist synthesis script" +rm -rf ${VERILOG_PROJ_DIR}/SRCSynth/ +cp -r ${VERILOG_PROJ_DIR}/SRCLint/ ${VERILOG_PROJ_DIR}/SRCSynth/ \ No newline at end of file diff --git a/SOFA_A/FPGA88_SOFA_A/.spydrnet b/SOFA_A/FPGA88_SOFA_A/.spydrnet new file mode 100644 index 0000000..ee64190 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/.spydrnet @@ -0,0 +1 @@ +spydrnet_physical diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/CustomModules/custom_module.txt b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/CustomModules/custom_module.txt new file mode 100644 index 0000000..3834131 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/CustomModules/custom_module.txt @@ -0,0 +1 @@ +# Dummy file to list all custom modules used in this project \ No newline at end of file diff --git a/SOFA_A/SOFA_A_task/arch/fabric_key.xml b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/arch/fabric_key.xml similarity index 100% rename from SOFA_A/SOFA_A_task/arch/fabric_key.xml rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/arch/fabric_key.xml diff --git a/SOFA_A/SOFA_A_task/arch/openfpga_arch.xml b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/arch/openfpga_arch.xml similarity index 100% rename from SOFA_A/SOFA_A_task/arch/openfpga_arch.xml rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/arch/openfpga_arch.xml diff --git a/SOFA_A/SOFA_A_task/arch/vpr_arch.xml b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/arch/vpr_arch.xml similarity index 98% rename from SOFA_A/SOFA_A_task/arch/vpr_arch.xml rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/arch/vpr_arch.xml index 775c552..44dfcfd 100644 --- a/SOFA_A/SOFA_A_task/arch/vpr_arch.xml +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/arch/vpr_arch.xml @@ -46,7 +46,7 @@ - + @@ -60,7 +60,7 @@ - + @@ -74,7 +74,7 @@ - + @@ -88,7 +88,7 @@ - + @@ -174,6 +174,16 @@ + + + + + + + + + + diff --git a/SOFA_A/SOFA_A_task/config/task_benchmarks.conf b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_benchmarks.conf similarity index 98% rename from SOFA_A/SOFA_A_task/config/task_benchmarks.conf rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_benchmarks.conf index 2d3bff6..eb44839 100644 --- a/SOFA_A/SOFA_A_task/config/task_benchmarks.conf +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_benchmarks.conf @@ -22,7 +22,7 @@ openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml -openfpga_vpr_device_layout=12x12 +openfpga_vpr_device_layout=FPGA88 openfpga_vpr_route_chan_width=60 [ARCHITECTURES] diff --git a/SOFA_A/SOFA_A_task/config/task_generation.conf b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_generation.conf similarity index 97% rename from SOFA_A/SOFA_A_task/config/task_generation.conf rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_generation.conf index 66d79ea..f2dd990 100644 --- a/SOFA_A/SOFA_A_task/config/task_generation.conf +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_generation.conf @@ -21,7 +21,7 @@ openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml -openfpga_vpr_device_layout=12x12 +openfpga_vpr_device_layout=FPGA88 openfpga_vpr_route_chan_width=60 [ARCHITECTURES] diff --git a/SOFA_A/SOFA_A_task/config/task_simulation.conf b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_simulation.conf similarity index 97% rename from SOFA_A/SOFA_A_task/config/task_simulation.conf rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_simulation.conf index 5145e73..b080fba 100644 --- a/SOFA_A/SOFA_A_task/config/task_simulation.conf +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_simulation.conf @@ -22,7 +22,7 @@ openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml -openfpga_vpr_device_layout=12x12 +openfpga_vpr_device_layout=FPGA88 openfpga_vpr_route_chan_width=60 [ARCHITECTURES] diff --git a/SOFA_A/SOFA_A_task/design_variables.yml b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/design_variables.yml similarity index 100% rename from SOFA_A/SOFA_A_task/design_variables.yml rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/design_variables.yml diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/flow_inputs/fabric_key.xml b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/flow_inputs/fabric_key.xml new file mode 100644 index 0000000..af85473 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/flow_inputs/fabric_key.xml @@ -0,0 +1,326 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SOFA_A/SOFA_A_task/generate_fabric.openfpga b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_fabric.openfpga similarity index 54% rename from SOFA_A/SOFA_A_task/generate_fabric.openfpga rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_fabric.openfpga index a6a2cbc..427bd36 100644 --- a/SOFA_A/SOFA_A_task/generate_fabric.openfpga +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_fabric.openfpga @@ -1,6 +1,12 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \ + --clock_modeling ideal \ + --device ${OPENFPGA_VPR_DEVICE_LAYOUT} \ + --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} \ + --absorb_buffer_luts off \ + --write_rr_graph rr_graph_out.xml \ + --skip_sync_clustering_and_routing_results on # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -33,7 +39,8 @@ write_fabric_hierarchy --file ./fabric_hierarchy.txt # Repack the netlist to physical pbs # This must be done before bitstream generator and testbench generation # Strongly recommend it is done after all the fix-up have been applied -repack #--verbose +repack +# --verbose # Build the bitstream # - Output the fabric-independent bitstream to a file @@ -49,28 +56,4 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # - Enable the use of explicit port mapping in Verilog netlist write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file ./SDC - -# Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file ./SDC_analysis - -# Finish and exit OpenFPGA -exit - -# Note : -# To run verification at the end of the flow maintain source in ./SRC directory +exit \ No newline at end of file diff --git a/SOFA_A/SOFA_A_task/generate_testbench.openfpga b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_testbench.openfpga similarity index 100% rename from SOFA_A/SOFA_A_task/generate_testbench.openfpga rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_testbench.openfpga diff --git a/SOFA_A/SOFA_A_task/micro_benchmark/and.act b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/micro_benchmark/and.act similarity index 100% rename from SOFA_A/SOFA_A_task/micro_benchmark/and.act rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/micro_benchmark/and.act diff --git a/SOFA_A/SOFA_A_task/micro_benchmark/and.blif b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/micro_benchmark/and.blif similarity index 100% rename from SOFA_A/SOFA_A_task/micro_benchmark/and.blif rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/micro_benchmark/and.blif diff --git a/SOFA_A/SOFA_A_task/micro_benchmark/and.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/micro_benchmark/and.v similarity index 100% rename from SOFA_A/SOFA_A_task/micro_benchmark/and.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/micro_benchmark/and.v diff --git a/SOFA_A/SOFA_A_task/process_top_def.sh b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/process_top_def.sh similarity index 100% rename from SOFA_A/SOFA_A_task/process_top_def.sh rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/process_top_def.sh diff --git a/SOFA_A/SOFA_A_task/sc_verilog/digital_io_hd.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/sc_verilog/digital_io_hd.v similarity index 100% rename from SOFA_A/SOFA_A_task/sc_verilog/digital_io_hd.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/sc_verilog/digital_io_hd.v diff --git a/SOFA_A/SOFA_A_task/sc_verilog/fpga_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/sc_verilog/fpga_top.v similarity index 100% rename from SOFA_A/SOFA_A_task/sc_verilog/fpga_top.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/sc_verilog/fpga_top.v diff --git a/SOFA_A/SOFA_A_task/sc_verilog/sky130_fd_sc_hd_wrapper .v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/sc_verilog/sky130_fd_sc_hd_wrapper .v similarity index 100% rename from SOFA_A/SOFA_A_task/sc_verilog/sky130_fd_sc_hd_wrapper .v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/sc_verilog/sky130_fd_sc_hd_wrapper .v diff --git a/SOFA_A/SOFA_A_task/user_project_wrapper_empty.def b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/user_project_wrapper_empty.def similarity index 100% rename from SOFA_A/SOFA_A_task/user_project_wrapper_empty.def rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/user_project_wrapper_empty.def diff --git a/SOFA_A/SOFA_A_task/user_project_wrapper_template.def b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/user_project_wrapper_template.def similarity index 100% rename from SOFA_A/SOFA_A_task/user_project_wrapper_template.def rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/user_project_wrapper_template.def diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fabric_netlists.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fabric_netlists.v new file mode 100644 index 0000000..8ed58ab --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fabric_netlists.v @@ -0,0 +1,84 @@ +`include "./SRC/fpga_top.v" +`include "./SRC/submodules/EMBEDDED_IO_HD.v" +`include "./SRC/submodules/EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.v" +`include "./SRC/submodules/cbx_1__0_.v" +`include "./SRC/submodules/cbx_1__0__old.v" +`include "./SRC/submodules/cbx_1__1_.v" +`include "./SRC/submodules/cbx_1__8_.v" +`include "./SRC/submodules/cbx_1__8__old.v" +`include "./SRC/submodules/cby_0__1_.v" +`include "./SRC/submodules/cby_0__1__old.v" +`include "./SRC/submodules/cby_1__1_.v" +`include "./SRC/submodules/cby_8__1_.v" +`include "./SRC/submodules/cby_8__1__old.v" +`include "./SRC/submodules/const0.v" +`include "./SRC/submodules/const1.v" +`include "./SRC/submodules/direct_interc.v" +`include "./SRC/submodules/frac_lut4.v" +`include "./SRC/submodules/frac_lut4_mux.v" +`include "./SRC/submodules/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.v" +`include "./SRC/submodules/grid_clb.v" +`include "./SRC/submodules/grid_io_bottom_bottom.v" +`include "./SRC/submodules/grid_io_left_left.v" +`include "./SRC/submodules/grid_io_right_right.v" +`include "./SRC/submodules/grid_io_top_top.v" +`include "./SRC/submodules/logical_tile_clb_mode_clb_.v" +`include "./SRC/submodules/logical_tile_clb_mode_default__fle.v" +`include "./SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric.v" +`include "./SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v" +`include "./SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v" +`include "./SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v" +`include "./SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v" +`include "./SRC/submodules/logical_tile_io_mode_io_.v" +`include "./SRC/submodules/logical_tile_io_mode_physical__iopad.v" +`include "./SRC/submodules/mux_tree_size2.v" +`include "./SRC/submodules/mux_tree_size2_mem.v" +`include "./SRC/submodules/mux_tree_tapbuf_size10.v" +`include "./SRC/submodules/mux_tree_tapbuf_size10_mem.v" +`include "./SRC/submodules/mux_tree_tapbuf_size11.v" +`include "./SRC/submodules/mux_tree_tapbuf_size11_mem.v" +`include "./SRC/submodules/mux_tree_tapbuf_size12.v" +`include "./SRC/submodules/mux_tree_tapbuf_size12_mem.v" +`include "./SRC/submodules/mux_tree_tapbuf_size2.v" +`include "./SRC/submodules/mux_tree_tapbuf_size2_mem.v" +`include "./SRC/submodules/mux_tree_tapbuf_size3.v" +`include "./SRC/submodules/mux_tree_tapbuf_size3_mem.v" +`include "./SRC/submodules/mux_tree_tapbuf_size4.v" +`include "./SRC/submodules/mux_tree_tapbuf_size4_mem.v" +`include "./SRC/submodules/mux_tree_tapbuf_size5.v" +`include "./SRC/submodules/mux_tree_tapbuf_size5_mem.v" +`include "./SRC/submodules/mux_tree_tapbuf_size6.v" +`include "./SRC/submodules/mux_tree_tapbuf_size6_mem.v" +`include "./SRC/submodules/mux_tree_tapbuf_size7.v" +`include "./SRC/submodules/mux_tree_tapbuf_size7_mem.v" +`include "./SRC/submodules/mux_tree_tapbuf_size8.v" +`include "./SRC/submodules/mux_tree_tapbuf_size8_mem.v" +`include "./SRC/submodules/mux_tree_tapbuf_size9.v" +`include "./SRC/submodules/mux_tree_tapbuf_size9_mem.v" +`include "./SRC/submodules/sb_0__0_.v" +`include "./SRC/submodules/sb_0__1_.v" +`include "./SRC/submodules/sb_0__8_.v" +`include "./SRC/submodules/sb_1__0_.v" +`include "./SRC/submodules/sb_1__1_.v" +`include "./SRC/submodules/sb_1__8_.v" +`include "./SRC/submodules/sb_8__0_.v" +`include "./SRC/submodules/sb_8__1_.v" +`include "./SRC/submodules/sb_8__8_.v" +`include "./SRC/submodules/sky130_fd_sc_hd__buf_2.v" +`include "./SRC/submodules/sky130_fd_sc_hd__buf_4.v" +`include "./SRC/submodules/sky130_fd_sc_hd__dfrtp_1.v" +`include "./SRC/submodules/sky130_fd_sc_hd__inv_1.v" +`include "./SRC/submodules/sky130_fd_sc_hd__inv_2.v" +`include "./SRC/submodules/sky130_fd_sc_hd__mux2_1.v" +`include "./SRC/submodules/sky130_fd_sc_hd__mux2_1_wrapper.v" +`include "./SRC/submodules/sky130_fd_sc_hd__or2_1.v" +`include "./SRC/submodules/sky130_fd_sc_hd__sdfrtp_1.v" +`include "./SRC/tile/bottom_left_tile.v" +`include "./SRC/tile/bottom_right_tile.v" +`include "./SRC/tile/bottom_tile.v" +`include "./SRC/tile/left_tile.v" +`include "./SRC/tile/right_tile.v" +`include "./SRC/tile/tile.v" +`include "./SRC/tile/top_left_tile.v" +`include "./SRC/tile/top_right_tile.v" +`include "./SRC/tile/top_tile.v" diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v new file mode 100644 index 0000000..f79db83 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v @@ -0,0 +1,8975 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module fpga_top +( + IO_ISOL_N, + Reset, + Test_en, + ccff_head, + clk, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + pReset, + prog_clk, + ccff_tail, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT +); + + input IO_ISOL_N; + input Reset; + input Test_en; + input ccff_head; + input clk; + input [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input pReset; + input prog_clk; + output ccff_tail; + output [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + + wire IO_ISOL_N; + wire Reset; + wire Test_en; + wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__0_ccff_tail; + wire [0:29]cbx_1__0__0_chanx_left_out; + wire [0:29]cbx_1__0__0_chanx_right_out; + wire cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__1_ccff_tail; + wire [0:29]cbx_1__0__1_chanx_left_out; + wire [0:29]cbx_1__0__1_chanx_right_out; + wire cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__2_ccff_tail; + wire [0:29]cbx_1__0__2_chanx_left_out; + wire [0:29]cbx_1__0__2_chanx_right_out; + wire cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__3_ccff_tail; + wire [0:29]cbx_1__0__3_chanx_left_out; + wire [0:29]cbx_1__0__3_chanx_right_out; + wire cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__4_ccff_tail; + wire [0:29]cbx_1__0__4_chanx_left_out; + wire [0:29]cbx_1__0__4_chanx_right_out; + wire cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__5_ccff_tail; + wire [0:29]cbx_1__0__5_chanx_left_out; + wire [0:29]cbx_1__0__5_chanx_right_out; + wire cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__6_ccff_tail; + wire [0:29]cbx_1__0__6_chanx_left_out; + wire [0:29]cbx_1__0__6_chanx_right_out; + wire cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__7_ccff_tail; + wire [0:29]cbx_1__0__7_chanx_left_out; + wire [0:29]cbx_1__0__7_chanx_right_out; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__0_ccff_tail; + wire [0:29]cbx_1__1__0_chanx_left_out; + wire [0:29]cbx_1__1__0_chanx_right_out; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__10_ccff_tail; + wire [0:29]cbx_1__1__10_chanx_left_out; + wire [0:29]cbx_1__1__10_chanx_right_out; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__11_ccff_tail; + wire [0:29]cbx_1__1__11_chanx_left_out; + wire [0:29]cbx_1__1__11_chanx_right_out; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__12_ccff_tail; + wire [0:29]cbx_1__1__12_chanx_left_out; + wire [0:29]cbx_1__1__12_chanx_right_out; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__13_ccff_tail; + wire [0:29]cbx_1__1__13_chanx_left_out; + wire [0:29]cbx_1__1__13_chanx_right_out; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__14_ccff_tail; + wire [0:29]cbx_1__1__14_chanx_left_out; + wire [0:29]cbx_1__1__14_chanx_right_out; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__15_ccff_tail; + wire [0:29]cbx_1__1__15_chanx_left_out; + wire [0:29]cbx_1__1__15_chanx_right_out; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__16_ccff_tail; + wire [0:29]cbx_1__1__16_chanx_left_out; + wire [0:29]cbx_1__1__16_chanx_right_out; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__17_ccff_tail; + wire [0:29]cbx_1__1__17_chanx_left_out; + wire [0:29]cbx_1__1__17_chanx_right_out; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__18_ccff_tail; + wire [0:29]cbx_1__1__18_chanx_left_out; + wire [0:29]cbx_1__1__18_chanx_right_out; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__19_ccff_tail; + wire [0:29]cbx_1__1__19_chanx_left_out; + wire [0:29]cbx_1__1__19_chanx_right_out; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__1_ccff_tail; + wire [0:29]cbx_1__1__1_chanx_left_out; + wire [0:29]cbx_1__1__1_chanx_right_out; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__20_ccff_tail; + wire [0:29]cbx_1__1__20_chanx_left_out; + wire [0:29]cbx_1__1__20_chanx_right_out; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__21_ccff_tail; + wire [0:29]cbx_1__1__21_chanx_left_out; + wire [0:29]cbx_1__1__21_chanx_right_out; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__22_ccff_tail; + wire [0:29]cbx_1__1__22_chanx_left_out; + wire [0:29]cbx_1__1__22_chanx_right_out; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__23_ccff_tail; + wire [0:29]cbx_1__1__23_chanx_left_out; + wire [0:29]cbx_1__1__23_chanx_right_out; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__24_ccff_tail; + wire [0:29]cbx_1__1__24_chanx_left_out; + wire [0:29]cbx_1__1__24_chanx_right_out; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__25_ccff_tail; + wire [0:29]cbx_1__1__25_chanx_left_out; + wire [0:29]cbx_1__1__25_chanx_right_out; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__26_ccff_tail; + wire [0:29]cbx_1__1__26_chanx_left_out; + wire [0:29]cbx_1__1__26_chanx_right_out; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__27_ccff_tail; + wire [0:29]cbx_1__1__27_chanx_left_out; + wire [0:29]cbx_1__1__27_chanx_right_out; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__28_ccff_tail; + wire [0:29]cbx_1__1__28_chanx_left_out; + wire [0:29]cbx_1__1__28_chanx_right_out; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__29_ccff_tail; + wire [0:29]cbx_1__1__29_chanx_left_out; + wire [0:29]cbx_1__1__29_chanx_right_out; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__2_ccff_tail; + wire [0:29]cbx_1__1__2_chanx_left_out; + wire [0:29]cbx_1__1__2_chanx_right_out; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__30_ccff_tail; + wire [0:29]cbx_1__1__30_chanx_left_out; + wire [0:29]cbx_1__1__30_chanx_right_out; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__31_ccff_tail; + wire [0:29]cbx_1__1__31_chanx_left_out; + wire [0:29]cbx_1__1__31_chanx_right_out; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__32_ccff_tail; + wire [0:29]cbx_1__1__32_chanx_left_out; + wire [0:29]cbx_1__1__32_chanx_right_out; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__33_ccff_tail; + wire [0:29]cbx_1__1__33_chanx_left_out; + wire [0:29]cbx_1__1__33_chanx_right_out; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__34_ccff_tail; + wire [0:29]cbx_1__1__34_chanx_left_out; + wire [0:29]cbx_1__1__34_chanx_right_out; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__35_ccff_tail; + wire [0:29]cbx_1__1__35_chanx_left_out; + wire [0:29]cbx_1__1__35_chanx_right_out; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__36_ccff_tail; + wire [0:29]cbx_1__1__36_chanx_left_out; + wire [0:29]cbx_1__1__36_chanx_right_out; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__37_ccff_tail; + wire [0:29]cbx_1__1__37_chanx_left_out; + wire [0:29]cbx_1__1__37_chanx_right_out; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__38_ccff_tail; + wire [0:29]cbx_1__1__38_chanx_left_out; + wire [0:29]cbx_1__1__38_chanx_right_out; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__39_ccff_tail; + wire [0:29]cbx_1__1__39_chanx_left_out; + wire [0:29]cbx_1__1__39_chanx_right_out; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__3_ccff_tail; + wire [0:29]cbx_1__1__3_chanx_left_out; + wire [0:29]cbx_1__1__3_chanx_right_out; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__40_ccff_tail; + wire [0:29]cbx_1__1__40_chanx_left_out; + wire [0:29]cbx_1__1__40_chanx_right_out; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__41_ccff_tail; + wire [0:29]cbx_1__1__41_chanx_left_out; + wire [0:29]cbx_1__1__41_chanx_right_out; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__42_ccff_tail; + wire [0:29]cbx_1__1__42_chanx_left_out; + wire [0:29]cbx_1__1__42_chanx_right_out; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__43_ccff_tail; + wire [0:29]cbx_1__1__43_chanx_left_out; + wire [0:29]cbx_1__1__43_chanx_right_out; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__44_ccff_tail; + wire [0:29]cbx_1__1__44_chanx_left_out; + wire [0:29]cbx_1__1__44_chanx_right_out; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__45_ccff_tail; + wire [0:29]cbx_1__1__45_chanx_left_out; + wire [0:29]cbx_1__1__45_chanx_right_out; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__46_ccff_tail; + wire [0:29]cbx_1__1__46_chanx_left_out; + wire [0:29]cbx_1__1__46_chanx_right_out; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__47_ccff_tail; + wire [0:29]cbx_1__1__47_chanx_left_out; + wire [0:29]cbx_1__1__47_chanx_right_out; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__48_ccff_tail; + wire [0:29]cbx_1__1__48_chanx_left_out; + wire [0:29]cbx_1__1__48_chanx_right_out; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__49_ccff_tail; + wire [0:29]cbx_1__1__49_chanx_left_out; + wire [0:29]cbx_1__1__49_chanx_right_out; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__4_ccff_tail; + wire [0:29]cbx_1__1__4_chanx_left_out; + wire [0:29]cbx_1__1__4_chanx_right_out; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__50_ccff_tail; + wire [0:29]cbx_1__1__50_chanx_left_out; + wire [0:29]cbx_1__1__50_chanx_right_out; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__51_ccff_tail; + wire [0:29]cbx_1__1__51_chanx_left_out; + wire [0:29]cbx_1__1__51_chanx_right_out; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__52_ccff_tail; + wire [0:29]cbx_1__1__52_chanx_left_out; + wire [0:29]cbx_1__1__52_chanx_right_out; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__53_ccff_tail; + wire [0:29]cbx_1__1__53_chanx_left_out; + wire [0:29]cbx_1__1__53_chanx_right_out; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__54_ccff_tail; + wire [0:29]cbx_1__1__54_chanx_left_out; + wire [0:29]cbx_1__1__54_chanx_right_out; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__55_ccff_tail; + wire [0:29]cbx_1__1__55_chanx_left_out; + wire [0:29]cbx_1__1__55_chanx_right_out; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__5_ccff_tail; + wire [0:29]cbx_1__1__5_chanx_left_out; + wire [0:29]cbx_1__1__5_chanx_right_out; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__6_ccff_tail; + wire [0:29]cbx_1__1__6_chanx_left_out; + wire [0:29]cbx_1__1__6_chanx_right_out; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__7_ccff_tail; + wire [0:29]cbx_1__1__7_chanx_left_out; + wire [0:29]cbx_1__1__7_chanx_right_out; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__8_ccff_tail; + wire [0:29]cbx_1__1__8_chanx_left_out; + wire [0:29]cbx_1__1__8_chanx_right_out; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__9_ccff_tail; + wire [0:29]cbx_1__1__9_chanx_left_out; + wire [0:29]cbx_1__1__9_chanx_right_out; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__0_ccff_tail; + wire [0:29]cbx_1__8__0_chanx_left_out; + wire [0:29]cbx_1__8__0_chanx_right_out; + wire cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__1_ccff_tail; + wire [0:29]cbx_1__8__1_chanx_left_out; + wire [0:29]cbx_1__8__1_chanx_right_out; + wire cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__2_ccff_tail; + wire [0:29]cbx_1__8__2_chanx_left_out; + wire [0:29]cbx_1__8__2_chanx_right_out; + wire cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__3_ccff_tail; + wire [0:29]cbx_1__8__3_chanx_left_out; + wire [0:29]cbx_1__8__3_chanx_right_out; + wire cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__4_ccff_tail; + wire [0:29]cbx_1__8__4_chanx_left_out; + wire [0:29]cbx_1__8__4_chanx_right_out; + wire cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__5_ccff_tail; + wire [0:29]cbx_1__8__5_chanx_left_out; + wire [0:29]cbx_1__8__5_chanx_right_out; + wire cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__6_ccff_tail; + wire [0:29]cbx_1__8__6_chanx_left_out; + wire [0:29]cbx_1__8__6_chanx_right_out; + wire cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__7_ccff_tail; + wire [0:29]cbx_1__8__7_chanx_left_out; + wire [0:29]cbx_1__8__7_chanx_right_out; + wire cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__0_ccff_tail; + wire [0:29]cby_0__1__0_chany_bottom_out; + wire [0:29]cby_0__1__0_chany_top_out; + wire cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__1_ccff_tail; + wire [0:29]cby_0__1__1_chany_bottom_out; + wire [0:29]cby_0__1__1_chany_top_out; + wire cby_0__1__1_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__1_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__1_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__1_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__2_ccff_tail; + wire [0:29]cby_0__1__2_chany_bottom_out; + wire [0:29]cby_0__1__2_chany_top_out; + wire cby_0__1__2_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__2_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__2_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__2_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__3_ccff_tail; + wire [0:29]cby_0__1__3_chany_bottom_out; + wire [0:29]cby_0__1__3_chany_top_out; + wire cby_0__1__3_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__3_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__3_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__3_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__4_ccff_tail; + wire [0:29]cby_0__1__4_chany_bottom_out; + wire [0:29]cby_0__1__4_chany_top_out; + wire cby_0__1__4_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__4_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__4_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__4_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__5_ccff_tail; + wire [0:29]cby_0__1__5_chany_bottom_out; + wire [0:29]cby_0__1__5_chany_top_out; + wire cby_0__1__5_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__5_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__5_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__5_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__6_ccff_tail; + wire [0:29]cby_0__1__6_chany_bottom_out; + wire [0:29]cby_0__1__6_chany_top_out; + wire cby_0__1__6_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__6_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__6_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__6_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__7_ccff_tail; + wire [0:29]cby_0__1__7_chany_bottom_out; + wire [0:29]cby_0__1__7_chany_top_out; + wire cby_0__1__7_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__7_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__7_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__7_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_1__1__0_ccff_tail; + wire [0:29]cby_1__1__0_chany_bottom_out; + wire [0:29]cby_1__1__0_chany_top_out; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__10_ccff_tail; + wire [0:29]cby_1__1__10_chany_bottom_out; + wire [0:29]cby_1__1__10_chany_top_out; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__11_ccff_tail; + wire [0:29]cby_1__1__11_chany_bottom_out; + wire [0:29]cby_1__1__11_chany_top_out; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__12_ccff_tail; + wire [0:29]cby_1__1__12_chany_bottom_out; + wire [0:29]cby_1__1__12_chany_top_out; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__13_ccff_tail; + wire [0:29]cby_1__1__13_chany_bottom_out; + wire [0:29]cby_1__1__13_chany_top_out; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__14_ccff_tail; + wire [0:29]cby_1__1__14_chany_bottom_out; + wire [0:29]cby_1__1__14_chany_top_out; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__15_ccff_tail; + wire [0:29]cby_1__1__15_chany_bottom_out; + wire [0:29]cby_1__1__15_chany_top_out; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__16_ccff_tail; + wire [0:29]cby_1__1__16_chany_bottom_out; + wire [0:29]cby_1__1__16_chany_top_out; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__17_ccff_tail; + wire [0:29]cby_1__1__17_chany_bottom_out; + wire [0:29]cby_1__1__17_chany_top_out; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__18_ccff_tail; + wire [0:29]cby_1__1__18_chany_bottom_out; + wire [0:29]cby_1__1__18_chany_top_out; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__19_ccff_tail; + wire [0:29]cby_1__1__19_chany_bottom_out; + wire [0:29]cby_1__1__19_chany_top_out; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__1_ccff_tail; + wire [0:29]cby_1__1__1_chany_bottom_out; + wire [0:29]cby_1__1__1_chany_top_out; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__20_ccff_tail; + wire [0:29]cby_1__1__20_chany_bottom_out; + wire [0:29]cby_1__1__20_chany_top_out; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__21_ccff_tail; + wire [0:29]cby_1__1__21_chany_bottom_out; + wire [0:29]cby_1__1__21_chany_top_out; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__22_ccff_tail; + wire [0:29]cby_1__1__22_chany_bottom_out; + wire [0:29]cby_1__1__22_chany_top_out; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__23_ccff_tail; + wire [0:29]cby_1__1__23_chany_bottom_out; + wire [0:29]cby_1__1__23_chany_top_out; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__24_ccff_tail; + wire [0:29]cby_1__1__24_chany_bottom_out; + wire [0:29]cby_1__1__24_chany_top_out; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__25_ccff_tail; + wire [0:29]cby_1__1__25_chany_bottom_out; + wire [0:29]cby_1__1__25_chany_top_out; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__26_ccff_tail; + wire [0:29]cby_1__1__26_chany_bottom_out; + wire [0:29]cby_1__1__26_chany_top_out; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__27_ccff_tail; + wire [0:29]cby_1__1__27_chany_bottom_out; + wire [0:29]cby_1__1__27_chany_top_out; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__28_ccff_tail; + wire [0:29]cby_1__1__28_chany_bottom_out; + wire [0:29]cby_1__1__28_chany_top_out; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__29_ccff_tail; + wire [0:29]cby_1__1__29_chany_bottom_out; + wire [0:29]cby_1__1__29_chany_top_out; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__2_ccff_tail; + wire [0:29]cby_1__1__2_chany_bottom_out; + wire [0:29]cby_1__1__2_chany_top_out; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__30_ccff_tail; + wire [0:29]cby_1__1__30_chany_bottom_out; + wire [0:29]cby_1__1__30_chany_top_out; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__31_ccff_tail; + wire [0:29]cby_1__1__31_chany_bottom_out; + wire [0:29]cby_1__1__31_chany_top_out; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__32_ccff_tail; + wire [0:29]cby_1__1__32_chany_bottom_out; + wire [0:29]cby_1__1__32_chany_top_out; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__33_ccff_tail; + wire [0:29]cby_1__1__33_chany_bottom_out; + wire [0:29]cby_1__1__33_chany_top_out; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__34_ccff_tail; + wire [0:29]cby_1__1__34_chany_bottom_out; + wire [0:29]cby_1__1__34_chany_top_out; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__35_ccff_tail; + wire [0:29]cby_1__1__35_chany_bottom_out; + wire [0:29]cby_1__1__35_chany_top_out; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__36_ccff_tail; + wire [0:29]cby_1__1__36_chany_bottom_out; + wire [0:29]cby_1__1__36_chany_top_out; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__37_ccff_tail; + wire [0:29]cby_1__1__37_chany_bottom_out; + wire [0:29]cby_1__1__37_chany_top_out; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__38_ccff_tail; + wire [0:29]cby_1__1__38_chany_bottom_out; + wire [0:29]cby_1__1__38_chany_top_out; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__39_ccff_tail; + wire [0:29]cby_1__1__39_chany_bottom_out; + wire [0:29]cby_1__1__39_chany_top_out; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__3_ccff_tail; + wire [0:29]cby_1__1__3_chany_bottom_out; + wire [0:29]cby_1__1__3_chany_top_out; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__40_ccff_tail; + wire [0:29]cby_1__1__40_chany_bottom_out; + wire [0:29]cby_1__1__40_chany_top_out; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__41_ccff_tail; + wire [0:29]cby_1__1__41_chany_bottom_out; + wire [0:29]cby_1__1__41_chany_top_out; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__42_ccff_tail; + wire [0:29]cby_1__1__42_chany_bottom_out; + wire [0:29]cby_1__1__42_chany_top_out; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__43_ccff_tail; + wire [0:29]cby_1__1__43_chany_bottom_out; + wire [0:29]cby_1__1__43_chany_top_out; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__44_ccff_tail; + wire [0:29]cby_1__1__44_chany_bottom_out; + wire [0:29]cby_1__1__44_chany_top_out; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__45_ccff_tail; + wire [0:29]cby_1__1__45_chany_bottom_out; + wire [0:29]cby_1__1__45_chany_top_out; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__46_ccff_tail; + wire [0:29]cby_1__1__46_chany_bottom_out; + wire [0:29]cby_1__1__46_chany_top_out; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__47_ccff_tail; + wire [0:29]cby_1__1__47_chany_bottom_out; + wire [0:29]cby_1__1__47_chany_top_out; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__48_ccff_tail; + wire [0:29]cby_1__1__48_chany_bottom_out; + wire [0:29]cby_1__1__48_chany_top_out; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__49_ccff_tail; + wire [0:29]cby_1__1__49_chany_bottom_out; + wire [0:29]cby_1__1__49_chany_top_out; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__4_ccff_tail; + wire [0:29]cby_1__1__4_chany_bottom_out; + wire [0:29]cby_1__1__4_chany_top_out; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__50_ccff_tail; + wire [0:29]cby_1__1__50_chany_bottom_out; + wire [0:29]cby_1__1__50_chany_top_out; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__51_ccff_tail; + wire [0:29]cby_1__1__51_chany_bottom_out; + wire [0:29]cby_1__1__51_chany_top_out; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__52_ccff_tail; + wire [0:29]cby_1__1__52_chany_bottom_out; + wire [0:29]cby_1__1__52_chany_top_out; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__53_ccff_tail; + wire [0:29]cby_1__1__53_chany_bottom_out; + wire [0:29]cby_1__1__53_chany_top_out; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__54_ccff_tail; + wire [0:29]cby_1__1__54_chany_bottom_out; + wire [0:29]cby_1__1__54_chany_top_out; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__55_ccff_tail; + wire [0:29]cby_1__1__55_chany_bottom_out; + wire [0:29]cby_1__1__55_chany_top_out; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__5_ccff_tail; + wire [0:29]cby_1__1__5_chany_bottom_out; + wire [0:29]cby_1__1__5_chany_top_out; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__6_ccff_tail; + wire [0:29]cby_1__1__6_chany_bottom_out; + wire [0:29]cby_1__1__6_chany_top_out; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__7_ccff_tail; + wire [0:29]cby_1__1__7_chany_bottom_out; + wire [0:29]cby_1__1__7_chany_top_out; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__8_ccff_tail; + wire [0:29]cby_1__1__8_chany_bottom_out; + wire [0:29]cby_1__1__8_chany_top_out; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__9_ccff_tail; + wire [0:29]cby_1__1__9_chany_bottom_out; + wire [0:29]cby_1__1__9_chany_top_out; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__0_ccff_tail; + wire [0:29]cby_8__1__0_chany_bottom_out; + wire [0:29]cby_8__1__0_chany_top_out; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__1_ccff_tail; + wire [0:29]cby_8__1__1_chany_bottom_out; + wire [0:29]cby_8__1__1_chany_top_out; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__1_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__1_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__1_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__2_ccff_tail; + wire [0:29]cby_8__1__2_chany_bottom_out; + wire [0:29]cby_8__1__2_chany_top_out; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__2_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__2_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__2_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__3_ccff_tail; + wire [0:29]cby_8__1__3_chany_bottom_out; + wire [0:29]cby_8__1__3_chany_top_out; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__3_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__3_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__3_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__4_ccff_tail; + wire [0:29]cby_8__1__4_chany_bottom_out; + wire [0:29]cby_8__1__4_chany_top_out; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__4_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__4_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__4_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__4_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__5_ccff_tail; + wire [0:29]cby_8__1__5_chany_bottom_out; + wire [0:29]cby_8__1__5_chany_top_out; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__5_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__5_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__5_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__5_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__6_ccff_tail; + wire [0:29]cby_8__1__6_chany_bottom_out; + wire [0:29]cby_8__1__6_chany_top_out; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__6_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__6_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__6_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__6_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__7_ccff_tail; + wire [0:29]cby_8__1__7_chany_bottom_out; + wire [0:29]cby_8__1__7_chany_top_out; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__7_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__7_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__7_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__7_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_head; + wire ccff_tail; + wire clk; + wire direct_interc_0_out; + wire direct_interc_100_out; + wire direct_interc_101_out; + wire direct_interc_102_out; + wire direct_interc_103_out; + wire direct_interc_104_out; + wire direct_interc_105_out; + wire direct_interc_106_out; + wire direct_interc_107_out; + wire direct_interc_108_out; + wire direct_interc_109_out; + wire direct_interc_10_out; + wire direct_interc_110_out; + wire direct_interc_111_out; + wire direct_interc_112_out; + wire direct_interc_113_out; + wire direct_interc_114_out; + wire direct_interc_115_out; + wire direct_interc_116_out; + wire direct_interc_117_out; + wire direct_interc_118_out; + wire direct_interc_119_out; + wire direct_interc_11_out; + wire direct_interc_120_out; + wire direct_interc_121_out; + wire direct_interc_122_out; + wire direct_interc_123_out; + wire direct_interc_124_out; + wire direct_interc_125_out; + wire direct_interc_126_out; + wire direct_interc_127_out; + wire direct_interc_128_out; + wire direct_interc_129_out; + wire direct_interc_12_out; + wire direct_interc_130_out; + wire direct_interc_131_out; + wire direct_interc_132_out; + wire direct_interc_133_out; + wire direct_interc_134_out; + wire direct_interc_135_out; + wire direct_interc_136_out; + wire direct_interc_137_out; + wire direct_interc_138_out; + wire direct_interc_139_out; + wire direct_interc_13_out; + wire direct_interc_140_out; + wire direct_interc_141_out; + wire direct_interc_142_out; + wire direct_interc_143_out; + wire direct_interc_144_out; + wire direct_interc_145_out; + wire direct_interc_146_out; + wire direct_interc_147_out; + wire direct_interc_148_out; + wire direct_interc_149_out; + wire direct_interc_14_out; + wire direct_interc_150_out; + wire direct_interc_151_out; + wire direct_interc_152_out; + wire direct_interc_153_out; + wire direct_interc_154_out; + wire direct_interc_155_out; + wire direct_interc_156_out; + wire direct_interc_157_out; + wire direct_interc_158_out; + wire direct_interc_159_out; + wire direct_interc_15_out; + wire direct_interc_160_out; + wire direct_interc_161_out; + wire direct_interc_162_out; + wire direct_interc_163_out; + wire direct_interc_164_out; + wire direct_interc_165_out; + wire direct_interc_166_out; + wire direct_interc_167_out; + wire direct_interc_168_out; + wire direct_interc_169_out; + wire direct_interc_16_out; + wire direct_interc_170_out; + wire direct_interc_171_out; + wire direct_interc_172_out; + wire direct_interc_173_out; + wire direct_interc_174_out; + wire direct_interc_17_out; + wire direct_interc_18_out; + wire direct_interc_19_out; + wire direct_interc_1_out; + wire direct_interc_20_out; + wire direct_interc_21_out; + wire direct_interc_22_out; + wire direct_interc_23_out; + wire direct_interc_24_out; + wire direct_interc_25_out; + wire direct_interc_26_out; + wire direct_interc_27_out; + wire direct_interc_28_out; + wire direct_interc_29_out; + wire direct_interc_2_out; + wire direct_interc_30_out; + wire direct_interc_31_out; + wire direct_interc_32_out; + wire direct_interc_33_out; + wire direct_interc_34_out; + wire direct_interc_35_out; + wire direct_interc_36_out; + wire direct_interc_37_out; + wire direct_interc_38_out; + wire direct_interc_39_out; + wire direct_interc_3_out; + wire direct_interc_40_out; + wire direct_interc_41_out; + wire direct_interc_42_out; + wire direct_interc_43_out; + wire direct_interc_44_out; + wire direct_interc_45_out; + wire direct_interc_46_out; + wire direct_interc_47_out; + wire direct_interc_48_out; + wire direct_interc_49_out; + wire direct_interc_4_out; + wire direct_interc_50_out; + wire direct_interc_51_out; + wire direct_interc_52_out; + wire direct_interc_53_out; + wire direct_interc_54_out; + wire direct_interc_55_out; + wire direct_interc_56_out; + wire direct_interc_57_out; + wire direct_interc_58_out; + wire direct_interc_59_out; + wire direct_interc_5_out; + wire direct_interc_60_out; + wire direct_interc_61_out; + wire direct_interc_62_out; + wire direct_interc_63_out; + wire direct_interc_64_out; + wire direct_interc_65_out; + wire direct_interc_66_out; + wire direct_interc_67_out; + wire direct_interc_68_out; + wire direct_interc_69_out; + wire direct_interc_6_out; + wire direct_interc_70_out; + wire direct_interc_71_out; + wire direct_interc_72_out; + wire direct_interc_73_out; + wire direct_interc_74_out; + wire direct_interc_75_out; + wire direct_interc_76_out; + wire direct_interc_77_out; + wire direct_interc_78_out; + wire direct_interc_79_out; + wire direct_interc_7_out; + wire direct_interc_80_out; + wire direct_interc_81_out; + wire direct_interc_82_out; + wire direct_interc_83_out; + wire direct_interc_84_out; + wire direct_interc_85_out; + wire direct_interc_86_out; + wire direct_interc_87_out; + wire direct_interc_88_out; + wire direct_interc_89_out; + wire direct_interc_8_out; + wire direct_interc_90_out; + wire direct_interc_91_out; + wire direct_interc_92_out; + wire direct_interc_93_out; + wire direct_interc_94_out; + wire direct_interc_95_out; + wire direct_interc_96_out; + wire direct_interc_97_out; + wire direct_interc_98_out; + wire direct_interc_99_out; + wire direct_interc_9_out; + wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire grid_clb_0_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_0_ccff_tail; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_10_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_10_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_10_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_10_ccff_tail; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_11_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_11_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_11_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_11_ccff_tail; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_12_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_12_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_12_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_12_ccff_tail; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_13_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_13_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_13_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_13_ccff_tail; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_14_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_14_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_14_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_14_ccff_tail; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_15_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_15_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_15_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_15_ccff_tail; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_16_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_16_ccff_tail; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_17_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_17_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_17_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_17_ccff_tail; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_18_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_18_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_18_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_18_ccff_tail; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_19_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_19_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_19_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_19_ccff_tail; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_sc_in_0_; + wire grid_clb_1_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_1_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_1_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_1_ccff_tail; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_20_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_20_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_20_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_20_ccff_tail; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_21_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_21_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_21_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_21_ccff_tail; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_22_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_22_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_22_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_22_ccff_tail; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_23_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_23_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_23_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_23_ccff_tail; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_24_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_24_ccff_tail; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_25_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_25_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_25_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_25_ccff_tail; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_26_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_26_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_26_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_26_ccff_tail; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_27_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_27_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_27_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_27_ccff_tail; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_28_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_28_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_28_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_28_ccff_tail; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_29_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_29_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_29_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_29_ccff_tail; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_2_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_2_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_2_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_2_ccff_tail; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_30_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_30_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_30_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_30_ccff_tail; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_31_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_31_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_31_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_31_ccff_tail; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_32_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_32_ccff_tail; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_33_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_33_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_33_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_33_ccff_tail; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_34_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_34_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_34_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_34_ccff_tail; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_35_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_35_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_35_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_35_ccff_tail; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_36_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_36_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_36_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_36_ccff_tail; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_37_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_37_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_37_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_37_ccff_tail; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_38_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_38_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_38_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_38_ccff_tail; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_39_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_39_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_39_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_39_ccff_tail; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_3_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_3_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_3_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_3_ccff_tail; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_40_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_40_ccff_tail; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_41_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_41_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_41_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_41_ccff_tail; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_42_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_42_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_42_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_42_ccff_tail; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_43_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_43_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_43_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_43_ccff_tail; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_44_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_44_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_44_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_44_ccff_tail; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_45_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_45_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_45_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_45_ccff_tail; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_46_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_46_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_46_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_46_ccff_tail; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_47_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_47_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_47_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_47_ccff_tail; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_48_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_48_ccff_tail; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_49_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_49_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_49_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_49_ccff_tail; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_4_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_4_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_4_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_4_ccff_tail; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_50_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_50_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_50_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_50_ccff_tail; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_51_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_51_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_51_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_51_ccff_tail; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_52_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_52_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_52_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_52_ccff_tail; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_53_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_53_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_53_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_53_ccff_tail; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_54_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_54_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_54_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_54_ccff_tail; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_55_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_55_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_55_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_55_ccff_tail; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_56_ccff_tail; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_57_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_57_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_57_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_57_ccff_tail; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_58_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_58_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_58_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_58_ccff_tail; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_59_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_59_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_59_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_59_ccff_tail; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_5_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_5_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_5_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_5_ccff_tail; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_60_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_60_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_60_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_60_ccff_tail; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_61_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_61_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_61_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_61_ccff_tail; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_62_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_62_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_62_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_62_ccff_tail; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_63_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_63_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_63_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_63_ccff_tail; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_6_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_6_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_6_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_6_ccff_tail; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_7_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_7_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_7_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_8_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_8_ccff_tail; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_9_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_9_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_9_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_9_ccff_tail; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_io_bottom_bottom_0_ccff_tail; + wire grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_1_ccff_tail; + wire grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_1_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_2_ccff_tail; + wire grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_2_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_3_ccff_tail; + wire grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_3_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_4_ccff_tail; + wire grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_4_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_5_ccff_tail; + wire grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_5_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_6_ccff_tail; + wire grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_6_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_7_ccff_tail; + wire grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_7_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_0_ccff_tail; + wire grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_1_ccff_tail; + wire grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_1_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_2_ccff_tail; + wire grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_2_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_3_ccff_tail; + wire grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_3_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_4_ccff_tail; + wire grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_4_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_5_ccff_tail; + wire grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_5_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_6_ccff_tail; + wire grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_6_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_7_ccff_tail; + wire grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_7_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_0_ccff_tail; + wire grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_1_ccff_tail; + wire grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_1_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_2_ccff_tail; + wire grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_2_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_3_ccff_tail; + wire grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_3_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_4_ccff_tail; + wire grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_4_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_5_ccff_tail; + wire grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_5_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_6_ccff_tail; + wire grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_6_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_7_ccff_tail; + wire grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_7_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_0_ccff_tail; + wire grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_1_ccff_tail; + wire grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_2_ccff_tail; + wire grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_3_ccff_tail; + wire grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_4_ccff_tail; + wire grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_5_ccff_tail; + wire grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_6_ccff_tail; + wire grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_7_ccff_tail; + wire pReset; + wire prog_clk; + wire sb_0__0__0_ccff_tail; + wire [0:29]sb_0__0__0_chanx_right_out; + wire [0:29]sb_0__0__0_chany_top_out; + wire sb_0__1__0_ccff_tail; + wire [0:29]sb_0__1__0_chanx_right_out; + wire [0:29]sb_0__1__0_chany_bottom_out; + wire [0:29]sb_0__1__0_chany_top_out; + wire sb_0__1__1_ccff_tail; + wire [0:29]sb_0__1__1_chanx_right_out; + wire [0:29]sb_0__1__1_chany_bottom_out; + wire [0:29]sb_0__1__1_chany_top_out; + wire sb_0__1__2_ccff_tail; + wire [0:29]sb_0__1__2_chanx_right_out; + wire [0:29]sb_0__1__2_chany_bottom_out; + wire [0:29]sb_0__1__2_chany_top_out; + wire sb_0__1__3_ccff_tail; + wire [0:29]sb_0__1__3_chanx_right_out; + wire [0:29]sb_0__1__3_chany_bottom_out; + wire [0:29]sb_0__1__3_chany_top_out; + wire sb_0__1__4_ccff_tail; + wire [0:29]sb_0__1__4_chanx_right_out; + wire [0:29]sb_0__1__4_chany_bottom_out; + wire [0:29]sb_0__1__4_chany_top_out; + wire sb_0__1__5_ccff_tail; + wire [0:29]sb_0__1__5_chanx_right_out; + wire [0:29]sb_0__1__5_chany_bottom_out; + wire [0:29]sb_0__1__5_chany_top_out; + wire sb_0__1__6_ccff_tail; + wire [0:29]sb_0__1__6_chanx_right_out; + wire [0:29]sb_0__1__6_chany_bottom_out; + wire [0:29]sb_0__1__6_chany_top_out; + wire sb_0__8__0_ccff_tail; + wire [0:29]sb_0__8__0_chanx_right_out; + wire [0:29]sb_0__8__0_chany_bottom_out; + wire sb_1__0__0_ccff_tail; + wire [0:29]sb_1__0__0_chanx_left_out; + wire [0:29]sb_1__0__0_chanx_right_out; + wire [0:29]sb_1__0__0_chany_top_out; + wire sb_1__0__1_ccff_tail; + wire [0:29]sb_1__0__1_chanx_left_out; + wire [0:29]sb_1__0__1_chanx_right_out; + wire [0:29]sb_1__0__1_chany_top_out; + wire sb_1__0__2_ccff_tail; + wire [0:29]sb_1__0__2_chanx_left_out; + wire [0:29]sb_1__0__2_chanx_right_out; + wire [0:29]sb_1__0__2_chany_top_out; + wire sb_1__0__3_ccff_tail; + wire [0:29]sb_1__0__3_chanx_left_out; + wire [0:29]sb_1__0__3_chanx_right_out; + wire [0:29]sb_1__0__3_chany_top_out; + wire sb_1__0__4_ccff_tail; + wire [0:29]sb_1__0__4_chanx_left_out; + wire [0:29]sb_1__0__4_chanx_right_out; + wire [0:29]sb_1__0__4_chany_top_out; + wire sb_1__0__5_ccff_tail; + wire [0:29]sb_1__0__5_chanx_left_out; + wire [0:29]sb_1__0__5_chanx_right_out; + wire [0:29]sb_1__0__5_chany_top_out; + wire sb_1__0__6_ccff_tail; + wire [0:29]sb_1__0__6_chanx_left_out; + wire [0:29]sb_1__0__6_chanx_right_out; + wire [0:29]sb_1__0__6_chany_top_out; + wire sb_1__1__0_ccff_tail; + wire [0:29]sb_1__1__0_chanx_left_out; + wire [0:29]sb_1__1__0_chanx_right_out; + wire [0:29]sb_1__1__0_chany_bottom_out; + wire [0:29]sb_1__1__0_chany_top_out; + wire sb_1__1__10_ccff_tail; + wire [0:29]sb_1__1__10_chanx_left_out; + wire [0:29]sb_1__1__10_chanx_right_out; + wire [0:29]sb_1__1__10_chany_bottom_out; + wire [0:29]sb_1__1__10_chany_top_out; + wire sb_1__1__11_ccff_tail; + wire [0:29]sb_1__1__11_chanx_left_out; + wire [0:29]sb_1__1__11_chanx_right_out; + wire [0:29]sb_1__1__11_chany_bottom_out; + wire [0:29]sb_1__1__11_chany_top_out; + wire sb_1__1__12_ccff_tail; + wire [0:29]sb_1__1__12_chanx_left_out; + wire [0:29]sb_1__1__12_chanx_right_out; + wire [0:29]sb_1__1__12_chany_bottom_out; + wire [0:29]sb_1__1__12_chany_top_out; + wire sb_1__1__13_ccff_tail; + wire [0:29]sb_1__1__13_chanx_left_out; + wire [0:29]sb_1__1__13_chanx_right_out; + wire [0:29]sb_1__1__13_chany_bottom_out; + wire [0:29]sb_1__1__13_chany_top_out; + wire sb_1__1__14_ccff_tail; + wire [0:29]sb_1__1__14_chanx_left_out; + wire [0:29]sb_1__1__14_chanx_right_out; + wire [0:29]sb_1__1__14_chany_bottom_out; + wire [0:29]sb_1__1__14_chany_top_out; + wire sb_1__1__15_ccff_tail; + wire [0:29]sb_1__1__15_chanx_left_out; + wire [0:29]sb_1__1__15_chanx_right_out; + wire [0:29]sb_1__1__15_chany_bottom_out; + wire [0:29]sb_1__1__15_chany_top_out; + wire sb_1__1__16_ccff_tail; + wire [0:29]sb_1__1__16_chanx_left_out; + wire [0:29]sb_1__1__16_chanx_right_out; + wire [0:29]sb_1__1__16_chany_bottom_out; + wire [0:29]sb_1__1__16_chany_top_out; + wire sb_1__1__17_ccff_tail; + wire [0:29]sb_1__1__17_chanx_left_out; + wire [0:29]sb_1__1__17_chanx_right_out; + wire [0:29]sb_1__1__17_chany_bottom_out; + wire [0:29]sb_1__1__17_chany_top_out; + wire sb_1__1__18_ccff_tail; + wire [0:29]sb_1__1__18_chanx_left_out; + wire [0:29]sb_1__1__18_chanx_right_out; + wire [0:29]sb_1__1__18_chany_bottom_out; + wire [0:29]sb_1__1__18_chany_top_out; + wire sb_1__1__19_ccff_tail; + wire [0:29]sb_1__1__19_chanx_left_out; + wire [0:29]sb_1__1__19_chanx_right_out; + wire [0:29]sb_1__1__19_chany_bottom_out; + wire [0:29]sb_1__1__19_chany_top_out; + wire sb_1__1__1_ccff_tail; + wire [0:29]sb_1__1__1_chanx_left_out; + wire [0:29]sb_1__1__1_chanx_right_out; + wire [0:29]sb_1__1__1_chany_bottom_out; + wire [0:29]sb_1__1__1_chany_top_out; + wire sb_1__1__20_ccff_tail; + wire [0:29]sb_1__1__20_chanx_left_out; + wire [0:29]sb_1__1__20_chanx_right_out; + wire [0:29]sb_1__1__20_chany_bottom_out; + wire [0:29]sb_1__1__20_chany_top_out; + wire sb_1__1__21_ccff_tail; + wire [0:29]sb_1__1__21_chanx_left_out; + wire [0:29]sb_1__1__21_chanx_right_out; + wire [0:29]sb_1__1__21_chany_bottom_out; + wire [0:29]sb_1__1__21_chany_top_out; + wire sb_1__1__22_ccff_tail; + wire [0:29]sb_1__1__22_chanx_left_out; + wire [0:29]sb_1__1__22_chanx_right_out; + wire [0:29]sb_1__1__22_chany_bottom_out; + wire [0:29]sb_1__1__22_chany_top_out; + wire sb_1__1__23_ccff_tail; + wire [0:29]sb_1__1__23_chanx_left_out; + wire [0:29]sb_1__1__23_chanx_right_out; + wire [0:29]sb_1__1__23_chany_bottom_out; + wire [0:29]sb_1__1__23_chany_top_out; + wire sb_1__1__24_ccff_tail; + wire [0:29]sb_1__1__24_chanx_left_out; + wire [0:29]sb_1__1__24_chanx_right_out; + wire [0:29]sb_1__1__24_chany_bottom_out; + wire [0:29]sb_1__1__24_chany_top_out; + wire sb_1__1__25_ccff_tail; + wire [0:29]sb_1__1__25_chanx_left_out; + wire [0:29]sb_1__1__25_chanx_right_out; + wire [0:29]sb_1__1__25_chany_bottom_out; + wire [0:29]sb_1__1__25_chany_top_out; + wire sb_1__1__26_ccff_tail; + wire [0:29]sb_1__1__26_chanx_left_out; + wire [0:29]sb_1__1__26_chanx_right_out; + wire [0:29]sb_1__1__26_chany_bottom_out; + wire [0:29]sb_1__1__26_chany_top_out; + wire sb_1__1__27_ccff_tail; + wire [0:29]sb_1__1__27_chanx_left_out; + wire [0:29]sb_1__1__27_chanx_right_out; + wire [0:29]sb_1__1__27_chany_bottom_out; + wire [0:29]sb_1__1__27_chany_top_out; + wire sb_1__1__28_ccff_tail; + wire [0:29]sb_1__1__28_chanx_left_out; + wire [0:29]sb_1__1__28_chanx_right_out; + wire [0:29]sb_1__1__28_chany_bottom_out; + wire [0:29]sb_1__1__28_chany_top_out; + wire sb_1__1__29_ccff_tail; + wire [0:29]sb_1__1__29_chanx_left_out; + wire [0:29]sb_1__1__29_chanx_right_out; + wire [0:29]sb_1__1__29_chany_bottom_out; + wire [0:29]sb_1__1__29_chany_top_out; + wire sb_1__1__2_ccff_tail; + wire [0:29]sb_1__1__2_chanx_left_out; + wire [0:29]sb_1__1__2_chanx_right_out; + wire [0:29]sb_1__1__2_chany_bottom_out; + wire [0:29]sb_1__1__2_chany_top_out; + wire sb_1__1__30_ccff_tail; + wire [0:29]sb_1__1__30_chanx_left_out; + wire [0:29]sb_1__1__30_chanx_right_out; + wire [0:29]sb_1__1__30_chany_bottom_out; + wire [0:29]sb_1__1__30_chany_top_out; + wire sb_1__1__31_ccff_tail; + wire [0:29]sb_1__1__31_chanx_left_out; + wire [0:29]sb_1__1__31_chanx_right_out; + wire [0:29]sb_1__1__31_chany_bottom_out; + wire [0:29]sb_1__1__31_chany_top_out; + wire sb_1__1__32_ccff_tail; + wire [0:29]sb_1__1__32_chanx_left_out; + wire [0:29]sb_1__1__32_chanx_right_out; + wire [0:29]sb_1__1__32_chany_bottom_out; + wire [0:29]sb_1__1__32_chany_top_out; + wire sb_1__1__33_ccff_tail; + wire [0:29]sb_1__1__33_chanx_left_out; + wire [0:29]sb_1__1__33_chanx_right_out; + wire [0:29]sb_1__1__33_chany_bottom_out; + wire [0:29]sb_1__1__33_chany_top_out; + wire sb_1__1__34_ccff_tail; + wire [0:29]sb_1__1__34_chanx_left_out; + wire [0:29]sb_1__1__34_chanx_right_out; + wire [0:29]sb_1__1__34_chany_bottom_out; + wire [0:29]sb_1__1__34_chany_top_out; + wire sb_1__1__35_ccff_tail; + wire [0:29]sb_1__1__35_chanx_left_out; + wire [0:29]sb_1__1__35_chanx_right_out; + wire [0:29]sb_1__1__35_chany_bottom_out; + wire [0:29]sb_1__1__35_chany_top_out; + wire sb_1__1__36_ccff_tail; + wire [0:29]sb_1__1__36_chanx_left_out; + wire [0:29]sb_1__1__36_chanx_right_out; + wire [0:29]sb_1__1__36_chany_bottom_out; + wire [0:29]sb_1__1__36_chany_top_out; + wire sb_1__1__37_ccff_tail; + wire [0:29]sb_1__1__37_chanx_left_out; + wire [0:29]sb_1__1__37_chanx_right_out; + wire [0:29]sb_1__1__37_chany_bottom_out; + wire [0:29]sb_1__1__37_chany_top_out; + wire sb_1__1__38_ccff_tail; + wire [0:29]sb_1__1__38_chanx_left_out; + wire [0:29]sb_1__1__38_chanx_right_out; + wire [0:29]sb_1__1__38_chany_bottom_out; + wire [0:29]sb_1__1__38_chany_top_out; + wire sb_1__1__39_ccff_tail; + wire [0:29]sb_1__1__39_chanx_left_out; + wire [0:29]sb_1__1__39_chanx_right_out; + wire [0:29]sb_1__1__39_chany_bottom_out; + wire [0:29]sb_1__1__39_chany_top_out; + wire sb_1__1__3_ccff_tail; + wire [0:29]sb_1__1__3_chanx_left_out; + wire [0:29]sb_1__1__3_chanx_right_out; + wire [0:29]sb_1__1__3_chany_bottom_out; + wire [0:29]sb_1__1__3_chany_top_out; + wire sb_1__1__40_ccff_tail; + wire [0:29]sb_1__1__40_chanx_left_out; + wire [0:29]sb_1__1__40_chanx_right_out; + wire [0:29]sb_1__1__40_chany_bottom_out; + wire [0:29]sb_1__1__40_chany_top_out; + wire sb_1__1__41_ccff_tail; + wire [0:29]sb_1__1__41_chanx_left_out; + wire [0:29]sb_1__1__41_chanx_right_out; + wire [0:29]sb_1__1__41_chany_bottom_out; + wire [0:29]sb_1__1__41_chany_top_out; + wire sb_1__1__42_ccff_tail; + wire [0:29]sb_1__1__42_chanx_left_out; + wire [0:29]sb_1__1__42_chanx_right_out; + wire [0:29]sb_1__1__42_chany_bottom_out; + wire [0:29]sb_1__1__42_chany_top_out; + wire sb_1__1__43_ccff_tail; + wire [0:29]sb_1__1__43_chanx_left_out; + wire [0:29]sb_1__1__43_chanx_right_out; + wire [0:29]sb_1__1__43_chany_bottom_out; + wire [0:29]sb_1__1__43_chany_top_out; + wire sb_1__1__44_ccff_tail; + wire [0:29]sb_1__1__44_chanx_left_out; + wire [0:29]sb_1__1__44_chanx_right_out; + wire [0:29]sb_1__1__44_chany_bottom_out; + wire [0:29]sb_1__1__44_chany_top_out; + wire sb_1__1__45_ccff_tail; + wire [0:29]sb_1__1__45_chanx_left_out; + wire [0:29]sb_1__1__45_chanx_right_out; + wire [0:29]sb_1__1__45_chany_bottom_out; + wire [0:29]sb_1__1__45_chany_top_out; + wire sb_1__1__46_ccff_tail; + wire [0:29]sb_1__1__46_chanx_left_out; + wire [0:29]sb_1__1__46_chanx_right_out; + wire [0:29]sb_1__1__46_chany_bottom_out; + wire [0:29]sb_1__1__46_chany_top_out; + wire sb_1__1__47_ccff_tail; + wire [0:29]sb_1__1__47_chanx_left_out; + wire [0:29]sb_1__1__47_chanx_right_out; + wire [0:29]sb_1__1__47_chany_bottom_out; + wire [0:29]sb_1__1__47_chany_top_out; + wire sb_1__1__48_ccff_tail; + wire [0:29]sb_1__1__48_chanx_left_out; + wire [0:29]sb_1__1__48_chanx_right_out; + wire [0:29]sb_1__1__48_chany_bottom_out; + wire [0:29]sb_1__1__48_chany_top_out; + wire sb_1__1__4_ccff_tail; + wire [0:29]sb_1__1__4_chanx_left_out; + wire [0:29]sb_1__1__4_chanx_right_out; + wire [0:29]sb_1__1__4_chany_bottom_out; + wire [0:29]sb_1__1__4_chany_top_out; + wire sb_1__1__5_ccff_tail; + wire [0:29]sb_1__1__5_chanx_left_out; + wire [0:29]sb_1__1__5_chanx_right_out; + wire [0:29]sb_1__1__5_chany_bottom_out; + wire [0:29]sb_1__1__5_chany_top_out; + wire sb_1__1__6_ccff_tail; + wire [0:29]sb_1__1__6_chanx_left_out; + wire [0:29]sb_1__1__6_chanx_right_out; + wire [0:29]sb_1__1__6_chany_bottom_out; + wire [0:29]sb_1__1__6_chany_top_out; + wire sb_1__1__7_ccff_tail; + wire [0:29]sb_1__1__7_chanx_left_out; + wire [0:29]sb_1__1__7_chanx_right_out; + wire [0:29]sb_1__1__7_chany_bottom_out; + wire [0:29]sb_1__1__7_chany_top_out; + wire sb_1__1__8_ccff_tail; + wire [0:29]sb_1__1__8_chanx_left_out; + wire [0:29]sb_1__1__8_chanx_right_out; + wire [0:29]sb_1__1__8_chany_bottom_out; + wire [0:29]sb_1__1__8_chany_top_out; + wire sb_1__1__9_ccff_tail; + wire [0:29]sb_1__1__9_chanx_left_out; + wire [0:29]sb_1__1__9_chanx_right_out; + wire [0:29]sb_1__1__9_chany_bottom_out; + wire [0:29]sb_1__1__9_chany_top_out; + wire sb_1__8__0_ccff_tail; + wire [0:29]sb_1__8__0_chanx_left_out; + wire [0:29]sb_1__8__0_chanx_right_out; + wire [0:29]sb_1__8__0_chany_bottom_out; + wire sb_1__8__1_ccff_tail; + wire [0:29]sb_1__8__1_chanx_left_out; + wire [0:29]sb_1__8__1_chanx_right_out; + wire [0:29]sb_1__8__1_chany_bottom_out; + wire sb_1__8__2_ccff_tail; + wire [0:29]sb_1__8__2_chanx_left_out; + wire [0:29]sb_1__8__2_chanx_right_out; + wire [0:29]sb_1__8__2_chany_bottom_out; + wire sb_1__8__3_ccff_tail; + wire [0:29]sb_1__8__3_chanx_left_out; + wire [0:29]sb_1__8__3_chanx_right_out; + wire [0:29]sb_1__8__3_chany_bottom_out; + wire sb_1__8__4_ccff_tail; + wire [0:29]sb_1__8__4_chanx_left_out; + wire [0:29]sb_1__8__4_chanx_right_out; + wire [0:29]sb_1__8__4_chany_bottom_out; + wire sb_1__8__5_ccff_tail; + wire [0:29]sb_1__8__5_chanx_left_out; + wire [0:29]sb_1__8__5_chanx_right_out; + wire [0:29]sb_1__8__5_chany_bottom_out; + wire sb_1__8__6_ccff_tail; + wire [0:29]sb_1__8__6_chanx_left_out; + wire [0:29]sb_1__8__6_chanx_right_out; + wire [0:29]sb_1__8__6_chany_bottom_out; + wire sb_8__0__0_ccff_tail; + wire [0:29]sb_8__0__0_chanx_left_out; + wire [0:29]sb_8__0__0_chany_top_out; + wire sb_8__1__0_ccff_tail; + wire [0:29]sb_8__1__0_chanx_left_out; + wire [0:29]sb_8__1__0_chany_bottom_out; + wire [0:29]sb_8__1__0_chany_top_out; + wire sb_8__1__1_ccff_tail; + wire [0:29]sb_8__1__1_chanx_left_out; + wire [0:29]sb_8__1__1_chany_bottom_out; + wire [0:29]sb_8__1__1_chany_top_out; + wire sb_8__1__2_ccff_tail; + wire [0:29]sb_8__1__2_chanx_left_out; + wire [0:29]sb_8__1__2_chany_bottom_out; + wire [0:29]sb_8__1__2_chany_top_out; + wire sb_8__1__3_ccff_tail; + wire [0:29]sb_8__1__3_chanx_left_out; + wire [0:29]sb_8__1__3_chany_bottom_out; + wire [0:29]sb_8__1__3_chany_top_out; + wire sb_8__1__4_ccff_tail; + wire [0:29]sb_8__1__4_chanx_left_out; + wire [0:29]sb_8__1__4_chany_bottom_out; + wire [0:29]sb_8__1__4_chany_top_out; + wire sb_8__1__5_ccff_tail; + wire [0:29]sb_8__1__5_chanx_left_out; + wire [0:29]sb_8__1__5_chany_bottom_out; + wire [0:29]sb_8__1__5_chany_top_out; + wire sb_8__1__6_ccff_tail; + wire [0:29]sb_8__1__6_chanx_left_out; + wire [0:29]sb_8__1__6_chany_bottom_out; + wire [0:29]sb_8__1__6_chany_top_out; + wire sb_8__8__0_ccff_tail; + wire [0:29]sb_8__8__0_chanx_left_out; + wire [0:29]sb_8__8__0_chany_bottom_out; + + bottom_left_tile tile_1__1_ + ( + .ccff_head(grid_io_left_left_1_ccff_tail), + .chanx_right_in(cbx_1__0__0_chanx_left_out), + .chany_top_in(cby_0__1__0_chany_bottom_out), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_3__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(sb_0__0__0_ccff_tail), + .chanx_right_out(sb_0__0__0_chanx_right_out), + .chany_top_out(sb_0__0__0_chany_top_out) + ); + left_tile tile_1__2_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(grid_io_left_left_2_ccff_tail), + .ccff_head_0(sb_0__0__0_ccff_tail), + .chanx_right_in(cbx_1__1__0_chanx_left_out), + .chany_bottom_in(sb_0__0__0_chany_top_out), + .chany_top_in_0(cby_0__1__1_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96:99]), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_0_ccff_tail), + .ccff_tail_0(sb_0__1__0_ccff_tail), + .chanx_right_out(sb_0__1__0_chanx_right_out), + .chany_bottom_out(cby_0__1__0_chany_bottom_out), + .chany_top_out_0(sb_0__1__0_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96:99]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96:99]), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_) + ); + left_tile tile_1__3_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(grid_io_left_left_3_ccff_tail), + .ccff_head_0(sb_0__1__0_ccff_tail), + .chanx_right_in(cbx_1__1__1_chanx_left_out), + .chany_bottom_in(sb_0__1__0_chany_top_out), + .chany_top_in_0(cby_0__1__2_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100:103]), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_1_ccff_tail), + .ccff_tail_0(sb_0__1__1_ccff_tail), + .chanx_right_out(sb_0__1__1_chanx_right_out), + .chany_bottom_out(cby_0__1__1_chany_bottom_out), + .chany_top_out_0(sb_0__1__1_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100:103]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100:103]), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_3__pin_inpad_0_) + ); + left_tile tile_1__4_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(grid_io_left_left_4_ccff_tail), + .ccff_head_0(sb_0__1__1_ccff_tail), + .chanx_right_in(cbx_1__1__2_chanx_left_out), + .chany_bottom_in(sb_0__1__1_chany_top_out), + .chany_top_in_0(cby_0__1__3_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104:107]), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_2_ccff_tail), + .ccff_tail_0(sb_0__1__2_ccff_tail), + .chanx_right_out(sb_0__1__2_chanx_right_out), + .chany_bottom_out(cby_0__1__2_chany_bottom_out), + .chany_top_out_0(sb_0__1__2_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104:107]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104:107]), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_3__pin_inpad_0_) + ); + left_tile tile_1__5_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(grid_io_left_left_5_ccff_tail), + .ccff_head_0(sb_0__1__2_ccff_tail), + .chanx_right_in(cbx_1__1__3_chanx_left_out), + .chany_bottom_in(sb_0__1__2_chany_top_out), + .chany_top_in_0(cby_0__1__4_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108:111]), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_3_ccff_tail), + .ccff_tail_0(sb_0__1__3_ccff_tail), + .chanx_right_out(sb_0__1__3_chanx_right_out), + .chany_bottom_out(cby_0__1__3_chany_bottom_out), + .chany_top_out_0(sb_0__1__3_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108:111]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108:111]), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_3__pin_inpad_0_) + ); + left_tile tile_1__6_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(grid_io_left_left_6_ccff_tail), + .ccff_head_0(sb_0__1__3_ccff_tail), + .chanx_right_in(cbx_1__1__4_chanx_left_out), + .chany_bottom_in(sb_0__1__3_chany_top_out), + .chany_top_in_0(cby_0__1__5_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112:115]), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_4_ccff_tail), + .ccff_tail_0(sb_0__1__4_ccff_tail), + .chanx_right_out(sb_0__1__4_chanx_right_out), + .chany_bottom_out(cby_0__1__4_chany_bottom_out), + .chany_top_out_0(sb_0__1__4_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112:115]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112:115]), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_3__pin_inpad_0_) + ); + left_tile tile_1__7_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(grid_io_left_left_7_ccff_tail), + .ccff_head_0(sb_0__1__4_ccff_tail), + .chanx_right_in(cbx_1__1__5_chanx_left_out), + .chany_bottom_in(sb_0__1__4_chany_top_out), + .chany_top_in_0(cby_0__1__6_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116:119]), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_5_ccff_tail), + .ccff_tail_0(sb_0__1__5_ccff_tail), + .chanx_right_out(sb_0__1__5_chanx_right_out), + .chany_bottom_out(cby_0__1__5_chany_bottom_out), + .chany_top_out_0(sb_0__1__5_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116:119]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116:119]), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_3__pin_inpad_0_) + ); + left_tile tile_1__8_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(sb_0__8__0_ccff_tail), + .ccff_head_0(sb_0__1__5_ccff_tail), + .chanx_right_in(cbx_1__1__6_chanx_left_out), + .chany_bottom_in(sb_0__1__5_chany_top_out), + .chany_top_in_0(cby_0__1__7_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120:123]), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_6_ccff_tail), + .ccff_tail_0(sb_0__1__6_ccff_tail), + .chanx_right_out(sb_0__1__6_chanx_right_out), + .chany_bottom_out(cby_0__1__6_chany_bottom_out), + .chany_top_out_0(sb_0__1__6_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120:123]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120:123]), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_3__pin_inpad_0_) + ); + top_left_tile tile_1__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(grid_io_top_top_0_ccff_tail), + .ccff_head_0(sb_0__1__6_ccff_tail), + .chanx_right_in(cbx_1__8__0_chanx_left_out), + .chany_bottom_in_0(sb_0__1__6_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124:127]), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_7_), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(sb_0__8__0_ccff_tail), + .ccff_tail_0(grid_io_left_left_7_ccff_tail), + .chanx_right_out(sb_0__8__0_chanx_right_out), + .chany_bottom_out_0(cby_0__1__7_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124:127]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124:127]), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_3__pin_inpad_0_) + ); + bottom_tile tile_2__1_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(ccff_head), + .ccff_head_1(grid_io_left_left_0_ccff_tail), + .chanx_left_in(sb_0__0__0_chanx_right_out), + .chanx_right_in_0(cbx_1__0__1_chanx_left_out), + .chany_top_in(cby_1__1__0_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92:95]), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_3__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_), + .ccff_tail(grid_io_bottom_bottom_7_ccff_tail), + .ccff_tail_0(cbx_1__0__0_ccff_tail), + .chanx_left_out(cbx_1__0__0_chanx_left_out), + .chanx_right_out_0(sb_1__0__0_chanx_right_out), + .chany_top_out(sb_1__0__0_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92:95]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92:95]), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_3__pin_inpad_0_) + ); + tile tile_2__2_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__0__0_ccff_tail), + .ccff_head_2(grid_clb_9_ccff_tail), + .chanx_left_in(sb_0__1__0_chanx_right_out), + .chanx_right_in_0(cbx_1__1__7_chanx_left_out), + .chany_bottom_in(sb_1__0__0_chany_top_out), + .chany_top_in_0(cby_1__1__1_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_0_ccff_tail), + .ccff_tail_0(cbx_1__1__0_ccff_tail), + .chanx_left_out(cbx_1__1__0_chanx_left_out), + .chanx_right_out_0(sb_1__1__0_chanx_right_out), + .chany_bottom_out(cby_1__1__0_chany_bottom_out), + .chany_top_out_0(sb_1__1__0_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_2__3_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__0_ccff_tail), + .ccff_head_2(grid_clb_1_ccff_tail), + .chanx_left_in(sb_0__1__1_chanx_right_out), + .chanx_right_in_0(cbx_1__1__8_chanx_left_out), + .chany_bottom_in(sb_1__1__0_chany_top_out), + .chany_top_in_0(cby_1__1__2_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_1_ccff_tail), + .ccff_tail_0(cbx_1__1__1_ccff_tail), + .chanx_left_out(cbx_1__1__1_chanx_left_out), + .chanx_right_out_0(sb_1__1__1_chanx_right_out), + .chany_bottom_out(cby_1__1__1_chany_bottom_out), + .chany_top_out_0(sb_1__1__1_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_2__4_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__1_ccff_tail), + .ccff_head_2(grid_clb_11_ccff_tail), + .chanx_left_in(sb_0__1__2_chanx_right_out), + .chanx_right_in_0(cbx_1__1__9_chanx_left_out), + .chany_bottom_in(sb_1__1__1_chany_top_out), + .chany_top_in_0(cby_1__1__3_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_2_ccff_tail), + .ccff_tail_0(cbx_1__1__2_ccff_tail), + .chanx_left_out(cbx_1__1__2_chanx_left_out), + .chanx_right_out_0(sb_1__1__2_chanx_right_out), + .chany_bottom_out(cby_1__1__2_chany_bottom_out), + .chany_top_out_0(sb_1__1__2_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_2__5_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__2_ccff_tail), + .ccff_head_2(grid_clb_3_ccff_tail), + .chanx_left_in(sb_0__1__3_chanx_right_out), + .chanx_right_in_0(cbx_1__1__10_chanx_left_out), + .chany_bottom_in(sb_1__1__2_chany_top_out), + .chany_top_in_0(cby_1__1__4_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_3_ccff_tail), + .ccff_tail_0(cbx_1__1__3_ccff_tail), + .chanx_left_out(cbx_1__1__3_chanx_left_out), + .chanx_right_out_0(sb_1__1__3_chanx_right_out), + .chany_bottom_out(cby_1__1__3_chany_bottom_out), + .chany_top_out_0(sb_1__1__3_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_2__6_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__3_ccff_tail), + .ccff_head_2(grid_clb_13_ccff_tail), + .chanx_left_in(sb_0__1__4_chanx_right_out), + .chanx_right_in_0(cbx_1__1__11_chanx_left_out), + .chany_bottom_in(sb_1__1__3_chany_top_out), + .chany_top_in_0(cby_1__1__5_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_4_ccff_tail), + .ccff_tail_0(cbx_1__1__4_ccff_tail), + .chanx_left_out(cbx_1__1__4_chanx_left_out), + .chanx_right_out_0(sb_1__1__4_chanx_right_out), + .chany_bottom_out(cby_1__1__4_chany_bottom_out), + .chany_top_out_0(sb_1__1__4_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_2__7_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__4_ccff_tail), + .ccff_head_2(grid_clb_5_ccff_tail), + .chanx_left_in(sb_0__1__5_chanx_right_out), + .chanx_right_in_0(cbx_1__1__12_chanx_left_out), + .chany_bottom_in(sb_1__1__4_chany_top_out), + .chany_top_in_0(cby_1__1__6_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_5_ccff_tail), + .ccff_tail_0(cbx_1__1__5_ccff_tail), + .chanx_left_out(cbx_1__1__5_chanx_left_out), + .chanx_right_out_0(sb_1__1__5_chanx_right_out), + .chany_bottom_out(cby_1__1__5_chany_bottom_out), + .chany_top_out_0(sb_1__1__5_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_2__8_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__5_ccff_tail), + .ccff_head_2(grid_clb_15_ccff_tail), + .chanx_left_in(sb_0__1__6_chanx_right_out), + .chanx_right_in_0(cbx_1__1__13_chanx_left_out), + .chany_bottom_in(sb_1__1__5_chany_top_out), + .chany_top_in_0(cby_1__1__7_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_6_ccff_tail), + .ccff_tail_0(cbx_1__1__6_ccff_tail), + .chanx_left_out(cbx_1__1__6_chanx_left_out), + .chanx_right_out_0(sb_1__1__6_chanx_right_out), + .chany_bottom_out(cby_1__1__6_chany_bottom_out), + .chany_top_out_0(sb_1__1__6_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_7_) + ); + top_tile tile_2__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__6_ccff_tail), + .ccff_head_2(grid_io_top_top_1_ccff_tail), + .chanx_left_in(sb_0__8__0_chanx_right_out), + .chanx_right_in_0(cbx_1__8__1_chanx_left_out), + .chany_bottom_in(sb_1__1__6_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:3]), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_7_), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_sc_in_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail), + .ccff_tail_0(grid_io_top_top_0_ccff_tail), + .chanx_left_out(cbx_1__8__0_chanx_left_out), + .chanx_right_out_0(sb_1__8__0_chanx_right_out), + .chany_bottom_out(cby_1__1__7_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:3]), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_7_) + ); + bottom_tile tile_3__1_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(grid_io_bottom_bottom_7_ccff_tail), + .ccff_head_1(grid_clb_0_ccff_tail), + .chanx_left_in(sb_1__0__0_chanx_right_out), + .chanx_right_in_0(cbx_1__0__2_chanx_left_out), + .chany_top_in(cby_1__1__8_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88:91]), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_3__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_9_), + .ccff_tail(grid_io_bottom_bottom_6_ccff_tail), + .ccff_tail_0(cbx_1__0__1_ccff_tail), + .chanx_left_out(cbx_1__0__1_chanx_left_out), + .chanx_right_out_0(sb_1__0__1_chanx_right_out), + .chany_top_out(sb_1__0__1_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88:91]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88:91]), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_3__pin_inpad_0_) + ); + tile tile_3__2_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__0__1_ccff_tail), + .ccff_head_2(grid_clb_17_ccff_tail), + .chanx_left_in(sb_1__1__0_chanx_right_out), + .chanx_right_in_0(cbx_1__1__14_chanx_left_out), + .chany_bottom_in(sb_1__0__1_chany_top_out), + .chany_top_in_0(cby_1__1__9_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_8_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_8_ccff_tail), + .ccff_tail_0(cbx_1__1__7_ccff_tail), + .chanx_left_out(cbx_1__1__7_chanx_left_out), + .chanx_right_out_0(sb_1__1__7_chanx_right_out), + .chany_bottom_out(cby_1__1__8_chany_bottom_out), + .chany_top_out_0(sb_1__1__7_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_3__3_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__7_ccff_tail), + .ccff_head_2(grid_clb_2_ccff_tail), + .chanx_left_in(sb_1__1__1_chanx_right_out), + .chanx_right_in_0(cbx_1__1__15_chanx_left_out), + .chany_bottom_in(sb_1__1__7_chany_top_out), + .chany_top_in_0(cby_1__1__10_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_9_ccff_tail), + .ccff_tail_0(cbx_1__1__8_ccff_tail), + .chanx_left_out(cbx_1__1__8_chanx_left_out), + .chanx_right_out_0(sb_1__1__8_chanx_right_out), + .chany_bottom_out(cby_1__1__9_chany_bottom_out), + .chany_top_out_0(sb_1__1__8_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_3__4_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__8_ccff_tail), + .ccff_head_2(grid_clb_19_ccff_tail), + .chanx_left_in(sb_1__1__2_chanx_right_out), + .chanx_right_in_0(cbx_1__1__16_chanx_left_out), + .chany_bottom_in(sb_1__1__8_chany_top_out), + .chany_top_in_0(cby_1__1__11_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_10_ccff_tail), + .ccff_tail_0(cbx_1__1__9_ccff_tail), + .chanx_left_out(cbx_1__1__9_chanx_left_out), + .chanx_right_out_0(sb_1__1__9_chanx_right_out), + .chany_bottom_out(cby_1__1__10_chany_bottom_out), + .chany_top_out_0(sb_1__1__9_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_3__5_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__9_ccff_tail), + .ccff_head_2(grid_clb_4_ccff_tail), + .chanx_left_in(sb_1__1__3_chanx_right_out), + .chanx_right_in_0(cbx_1__1__17_chanx_left_out), + .chany_bottom_in(sb_1__1__9_chany_top_out), + .chany_top_in_0(cby_1__1__12_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_11_ccff_tail), + .ccff_tail_0(cbx_1__1__10_ccff_tail), + .chanx_left_out(cbx_1__1__10_chanx_left_out), + .chanx_right_out_0(sb_1__1__10_chanx_right_out), + .chany_bottom_out(cby_1__1__11_chany_bottom_out), + .chany_top_out_0(sb_1__1__10_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_3__6_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__10_ccff_tail), + .ccff_head_2(grid_clb_21_ccff_tail), + .chanx_left_in(sb_1__1__4_chanx_right_out), + .chanx_right_in_0(cbx_1__1__18_chanx_left_out), + .chany_bottom_in(sb_1__1__10_chany_top_out), + .chany_top_in_0(cby_1__1__13_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_12_ccff_tail), + .ccff_tail_0(cbx_1__1__11_ccff_tail), + .chanx_left_out(cbx_1__1__11_chanx_left_out), + .chanx_right_out_0(sb_1__1__11_chanx_right_out), + .chany_bottom_out(cby_1__1__12_chany_bottom_out), + .chany_top_out_0(sb_1__1__11_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_3__7_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__11_ccff_tail), + .ccff_head_2(grid_clb_6_ccff_tail), + .chanx_left_in(sb_1__1__5_chanx_right_out), + .chanx_right_in_0(cbx_1__1__19_chanx_left_out), + .chany_bottom_in(sb_1__1__11_chany_top_out), + .chany_top_in_0(cby_1__1__14_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_13_ccff_tail), + .ccff_tail_0(cbx_1__1__12_ccff_tail), + .chanx_left_out(cbx_1__1__12_chanx_left_out), + .chanx_right_out_0(sb_1__1__12_chanx_right_out), + .chany_bottom_out(cby_1__1__13_chany_bottom_out), + .chany_top_out_0(sb_1__1__12_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_3__8_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__12_ccff_tail), + .ccff_head_2(grid_clb_23_ccff_tail), + .chanx_left_in(sb_1__1__6_chanx_right_out), + .chanx_right_in_0(cbx_1__1__20_chanx_left_out), + .chany_bottom_in(sb_1__1__12_chany_top_out), + .chany_top_in_0(cby_1__1__15_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_14_ccff_tail), + .ccff_tail_0(cbx_1__1__13_ccff_tail), + .chanx_left_out(cbx_1__1__13_chanx_left_out), + .chanx_right_out_0(sb_1__1__13_chanx_right_out), + .chany_bottom_out(cby_1__1__14_chany_bottom_out), + .chany_top_out_0(sb_1__1__13_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_) + ); + top_tile tile_3__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__13_ccff_tail), + .ccff_head_2(grid_io_top_top_2_ccff_tail), + .chanx_left_in(sb_1__8__0_chanx_right_out), + .chanx_right_in_0(cbx_1__8__2_chanx_left_out), + .chany_bottom_in(sb_1__1__13_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4:7]), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_7_), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_clb_15_ccff_tail), + .ccff_tail_0(grid_io_top_top_1_ccff_tail), + .chanx_left_out(cbx_1__8__1_chanx_left_out), + .chanx_right_out_0(sb_1__8__1_chanx_right_out), + .chany_bottom_out(cby_1__1__15_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4:7]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4:7]), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_7_) + ); + bottom_tile tile_4__1_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(grid_io_bottom_bottom_6_ccff_tail), + .ccff_head_1(grid_clb_8_ccff_tail), + .chanx_left_in(sb_1__0__1_chanx_right_out), + .chanx_right_in_0(cbx_1__0__3_chanx_left_out), + .chany_top_in(cby_1__1__16_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84:87]), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_3__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_9_), + .ccff_tail(grid_io_bottom_bottom_5_ccff_tail), + .ccff_tail_0(cbx_1__0__2_ccff_tail), + .chanx_left_out(cbx_1__0__2_chanx_left_out), + .chanx_right_out_0(sb_1__0__2_chanx_right_out), + .chany_top_out(sb_1__0__2_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84:87]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84:87]), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_3__pin_inpad_0_) + ); + tile tile_4__2_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__0__2_ccff_tail), + .ccff_head_2(grid_clb_25_ccff_tail), + .chanx_left_in(sb_1__1__7_chanx_right_out), + .chanx_right_in_0(cbx_1__1__21_chanx_left_out), + .chany_bottom_in(sb_1__0__2_chany_top_out), + .chany_top_in_0(cby_1__1__17_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_16_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_16_ccff_tail), + .ccff_tail_0(cbx_1__1__14_ccff_tail), + .chanx_left_out(cbx_1__1__14_chanx_left_out), + .chanx_right_out_0(sb_1__1__14_chanx_right_out), + .chany_bottom_out(cby_1__1__16_chany_bottom_out), + .chany_top_out_0(sb_1__1__14_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_4__3_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__14_ccff_tail), + .ccff_head_2(grid_clb_10_ccff_tail), + .chanx_left_in(sb_1__1__8_chanx_right_out), + .chanx_right_in_0(cbx_1__1__22_chanx_left_out), + .chany_bottom_in(sb_1__1__14_chany_top_out), + .chany_top_in_0(cby_1__1__18_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_17_ccff_tail), + .ccff_tail_0(cbx_1__1__15_ccff_tail), + .chanx_left_out(cbx_1__1__15_chanx_left_out), + .chanx_right_out_0(sb_1__1__15_chanx_right_out), + .chany_bottom_out(cby_1__1__17_chany_bottom_out), + .chany_top_out_0(sb_1__1__15_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_4__4_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__15_ccff_tail), + .ccff_head_2(grid_clb_27_ccff_tail), + .chanx_left_in(sb_1__1__9_chanx_right_out), + .chanx_right_in_0(cbx_1__1__23_chanx_left_out), + .chany_bottom_in(sb_1__1__15_chany_top_out), + .chany_top_in_0(cby_1__1__19_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_18_ccff_tail), + .ccff_tail_0(cbx_1__1__16_ccff_tail), + .chanx_left_out(cbx_1__1__16_chanx_left_out), + .chanx_right_out_0(sb_1__1__16_chanx_right_out), + .chany_bottom_out(cby_1__1__18_chany_bottom_out), + .chany_top_out_0(sb_1__1__16_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_4__5_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__16_ccff_tail), + .ccff_head_2(grid_clb_12_ccff_tail), + .chanx_left_in(sb_1__1__10_chanx_right_out), + .chanx_right_in_0(cbx_1__1__24_chanx_left_out), + .chany_bottom_in(sb_1__1__16_chany_top_out), + .chany_top_in_0(cby_1__1__20_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_19_ccff_tail), + .ccff_tail_0(cbx_1__1__17_ccff_tail), + .chanx_left_out(cbx_1__1__17_chanx_left_out), + .chanx_right_out_0(sb_1__1__17_chanx_right_out), + .chany_bottom_out(cby_1__1__19_chany_bottom_out), + .chany_top_out_0(sb_1__1__17_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_4__6_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__17_ccff_tail), + .ccff_head_2(grid_clb_29_ccff_tail), + .chanx_left_in(sb_1__1__11_chanx_right_out), + .chanx_right_in_0(cbx_1__1__25_chanx_left_out), + .chany_bottom_in(sb_1__1__17_chany_top_out), + .chany_top_in_0(cby_1__1__21_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_20_ccff_tail), + .ccff_tail_0(cbx_1__1__18_ccff_tail), + .chanx_left_out(cbx_1__1__18_chanx_left_out), + .chanx_right_out_0(sb_1__1__18_chanx_right_out), + .chany_bottom_out(cby_1__1__20_chany_bottom_out), + .chany_top_out_0(sb_1__1__18_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_4__7_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__18_ccff_tail), + .ccff_head_2(grid_clb_14_ccff_tail), + .chanx_left_in(sb_1__1__12_chanx_right_out), + .chanx_right_in_0(cbx_1__1__26_chanx_left_out), + .chany_bottom_in(sb_1__1__18_chany_top_out), + .chany_top_in_0(cby_1__1__22_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_21_ccff_tail), + .ccff_tail_0(cbx_1__1__19_ccff_tail), + .chanx_left_out(cbx_1__1__19_chanx_left_out), + .chanx_right_out_0(sb_1__1__19_chanx_right_out), + .chany_bottom_out(cby_1__1__21_chany_bottom_out), + .chany_top_out_0(sb_1__1__19_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_4__8_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__19_ccff_tail), + .ccff_head_2(grid_clb_31_ccff_tail), + .chanx_left_in(sb_1__1__13_chanx_right_out), + .chanx_right_in_0(cbx_1__1__27_chanx_left_out), + .chany_bottom_in(sb_1__1__19_chany_top_out), + .chany_top_in_0(cby_1__1__23_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_22_ccff_tail), + .ccff_tail_0(cbx_1__1__20_ccff_tail), + .chanx_left_out(cbx_1__1__20_chanx_left_out), + .chanx_right_out_0(sb_1__1__20_chanx_right_out), + .chany_bottom_out(cby_1__1__22_chany_bottom_out), + .chany_top_out_0(sb_1__1__20_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_) + ); + top_tile tile_4__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__20_ccff_tail), + .ccff_head_2(grid_io_top_top_3_ccff_tail), + .chanx_left_in(sb_1__8__1_chanx_right_out), + .chanx_right_in_0(cbx_1__8__3_chanx_left_out), + .chany_bottom_in(sb_1__1__20_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8:11]), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_7_), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_8_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_clb_23_ccff_tail), + .ccff_tail_0(grid_io_top_top_2_ccff_tail), + .chanx_left_out(cbx_1__8__2_chanx_left_out), + .chanx_right_out_0(sb_1__8__2_chanx_right_out), + .chany_bottom_out(cby_1__1__23_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8:11]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8:11]), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_7_) + ); + bottom_tile tile_5__1_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(grid_io_bottom_bottom_5_ccff_tail), + .ccff_head_1(grid_clb_16_ccff_tail), + .chanx_left_in(sb_1__0__2_chanx_right_out), + .chanx_right_in_0(cbx_1__0__4_chanx_left_out), + .chany_top_in(cby_1__1__24_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80:83]), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_3__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_9_), + .ccff_tail(grid_io_bottom_bottom_4_ccff_tail), + .ccff_tail_0(cbx_1__0__3_ccff_tail), + .chanx_left_out(cbx_1__0__3_chanx_left_out), + .chanx_right_out_0(sb_1__0__3_chanx_right_out), + .chany_top_out(sb_1__0__3_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80:83]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80:83]), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_3__pin_inpad_0_) + ); + tile tile_5__2_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__0__3_ccff_tail), + .ccff_head_2(grid_clb_33_ccff_tail), + .chanx_left_in(sb_1__1__14_chanx_right_out), + .chanx_right_in_0(cbx_1__1__28_chanx_left_out), + .chany_bottom_in(sb_1__0__3_chany_top_out), + .chany_top_in_0(cby_1__1__25_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_24_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_24_ccff_tail), + .ccff_tail_0(cbx_1__1__21_ccff_tail), + .chanx_left_out(cbx_1__1__21_chanx_left_out), + .chanx_right_out_0(sb_1__1__21_chanx_right_out), + .chany_bottom_out(cby_1__1__24_chany_bottom_out), + .chany_top_out_0(sb_1__1__21_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_5__3_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__21_ccff_tail), + .ccff_head_2(grid_clb_18_ccff_tail), + .chanx_left_in(sb_1__1__15_chanx_right_out), + .chanx_right_in_0(cbx_1__1__29_chanx_left_out), + .chany_bottom_in(sb_1__1__21_chany_top_out), + .chany_top_in_0(cby_1__1__26_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_25_ccff_tail), + .ccff_tail_0(cbx_1__1__22_ccff_tail), + .chanx_left_out(cbx_1__1__22_chanx_left_out), + .chanx_right_out_0(sb_1__1__22_chanx_right_out), + .chany_bottom_out(cby_1__1__25_chany_bottom_out), + .chany_top_out_0(sb_1__1__22_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_5__4_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__22_ccff_tail), + .ccff_head_2(grid_clb_35_ccff_tail), + .chanx_left_in(sb_1__1__16_chanx_right_out), + .chanx_right_in_0(cbx_1__1__30_chanx_left_out), + .chany_bottom_in(sb_1__1__22_chany_top_out), + .chany_top_in_0(cby_1__1__27_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_26_ccff_tail), + .ccff_tail_0(cbx_1__1__23_ccff_tail), + .chanx_left_out(cbx_1__1__23_chanx_left_out), + .chanx_right_out_0(sb_1__1__23_chanx_right_out), + .chany_bottom_out(cby_1__1__26_chany_bottom_out), + .chany_top_out_0(sb_1__1__23_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_5__5_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__23_ccff_tail), + .ccff_head_2(grid_clb_20_ccff_tail), + .chanx_left_in(sb_1__1__17_chanx_right_out), + .chanx_right_in_0(cbx_1__1__31_chanx_left_out), + .chany_bottom_in(sb_1__1__23_chany_top_out), + .chany_top_in_0(cby_1__1__28_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_27_ccff_tail), + .ccff_tail_0(cbx_1__1__24_ccff_tail), + .chanx_left_out(cbx_1__1__24_chanx_left_out), + .chanx_right_out_0(sb_1__1__24_chanx_right_out), + .chany_bottom_out(cby_1__1__27_chany_bottom_out), + .chany_top_out_0(sb_1__1__24_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_5__6_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__24_ccff_tail), + .ccff_head_2(grid_clb_37_ccff_tail), + .chanx_left_in(sb_1__1__18_chanx_right_out), + .chanx_right_in_0(cbx_1__1__32_chanx_left_out), + .chany_bottom_in(sb_1__1__24_chany_top_out), + .chany_top_in_0(cby_1__1__29_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_28_ccff_tail), + .ccff_tail_0(cbx_1__1__25_ccff_tail), + .chanx_left_out(cbx_1__1__25_chanx_left_out), + .chanx_right_out_0(sb_1__1__25_chanx_right_out), + .chany_bottom_out(cby_1__1__28_chany_bottom_out), + .chany_top_out_0(sb_1__1__25_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_5__7_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__25_ccff_tail), + .ccff_head_2(grid_clb_22_ccff_tail), + .chanx_left_in(sb_1__1__19_chanx_right_out), + .chanx_right_in_0(cbx_1__1__33_chanx_left_out), + .chany_bottom_in(sb_1__1__25_chany_top_out), + .chany_top_in_0(cby_1__1__30_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_29_ccff_tail), + .ccff_tail_0(cbx_1__1__26_ccff_tail), + .chanx_left_out(cbx_1__1__26_chanx_left_out), + .chanx_right_out_0(sb_1__1__26_chanx_right_out), + .chany_bottom_out(cby_1__1__29_chany_bottom_out), + .chany_top_out_0(sb_1__1__26_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_5__8_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__26_ccff_tail), + .ccff_head_2(grid_clb_39_ccff_tail), + .chanx_left_in(sb_1__1__20_chanx_right_out), + .chanx_right_in_0(cbx_1__1__34_chanx_left_out), + .chany_bottom_in(sb_1__1__26_chany_top_out), + .chany_top_in_0(cby_1__1__31_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_30_ccff_tail), + .ccff_tail_0(cbx_1__1__27_ccff_tail), + .chanx_left_out(cbx_1__1__27_chanx_left_out), + .chanx_right_out_0(sb_1__1__27_chanx_right_out), + .chany_bottom_out(cby_1__1__30_chany_bottom_out), + .chany_top_out_0(sb_1__1__27_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_) + ); + top_tile tile_5__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__27_ccff_tail), + .ccff_head_2(grid_io_top_top_4_ccff_tail), + .chanx_left_in(sb_1__8__2_chanx_right_out), + .chanx_right_in_0(cbx_1__8__4_chanx_left_out), + .chany_bottom_in(sb_1__1__27_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12:15]), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_7_), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_16_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_clb_31_ccff_tail), + .ccff_tail_0(grid_io_top_top_3_ccff_tail), + .chanx_left_out(cbx_1__8__3_chanx_left_out), + .chanx_right_out_0(sb_1__8__3_chanx_right_out), + .chany_bottom_out(cby_1__1__31_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12:15]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12:15]), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_7_) + ); + bottom_tile tile_6__1_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(grid_io_bottom_bottom_4_ccff_tail), + .ccff_head_1(grid_clb_24_ccff_tail), + .chanx_left_in(sb_1__0__3_chanx_right_out), + .chanx_right_in_0(cbx_1__0__5_chanx_left_out), + .chany_top_in(cby_1__1__32_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76:79]), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_3__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_9_), + .ccff_tail(grid_io_bottom_bottom_3_ccff_tail), + .ccff_tail_0(cbx_1__0__4_ccff_tail), + .chanx_left_out(cbx_1__0__4_chanx_left_out), + .chanx_right_out_0(sb_1__0__4_chanx_right_out), + .chany_top_out(sb_1__0__4_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76:79]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76:79]), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_3__pin_inpad_0_) + ); + tile tile_6__2_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__0__4_ccff_tail), + .ccff_head_2(grid_clb_41_ccff_tail), + .chanx_left_in(sb_1__1__21_chanx_right_out), + .chanx_right_in_0(cbx_1__1__35_chanx_left_out), + .chany_bottom_in(sb_1__0__4_chany_top_out), + .chany_top_in_0(cby_1__1__33_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_32_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_32_ccff_tail), + .ccff_tail_0(cbx_1__1__28_ccff_tail), + .chanx_left_out(cbx_1__1__28_chanx_left_out), + .chanx_right_out_0(sb_1__1__28_chanx_right_out), + .chany_bottom_out(cby_1__1__32_chany_bottom_out), + .chany_top_out_0(sb_1__1__28_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_6__3_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__28_ccff_tail), + .ccff_head_2(grid_clb_26_ccff_tail), + .chanx_left_in(sb_1__1__22_chanx_right_out), + .chanx_right_in_0(cbx_1__1__36_chanx_left_out), + .chany_bottom_in(sb_1__1__28_chany_top_out), + .chany_top_in_0(cby_1__1__34_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_33_ccff_tail), + .ccff_tail_0(cbx_1__1__29_ccff_tail), + .chanx_left_out(cbx_1__1__29_chanx_left_out), + .chanx_right_out_0(sb_1__1__29_chanx_right_out), + .chany_bottom_out(cby_1__1__33_chany_bottom_out), + .chany_top_out_0(sb_1__1__29_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_6__4_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__29_ccff_tail), + .ccff_head_2(grid_clb_43_ccff_tail), + .chanx_left_in(sb_1__1__23_chanx_right_out), + .chanx_right_in_0(cbx_1__1__37_chanx_left_out), + .chany_bottom_in(sb_1__1__29_chany_top_out), + .chany_top_in_0(cby_1__1__35_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_34_ccff_tail), + .ccff_tail_0(cbx_1__1__30_ccff_tail), + .chanx_left_out(cbx_1__1__30_chanx_left_out), + .chanx_right_out_0(sb_1__1__30_chanx_right_out), + .chany_bottom_out(cby_1__1__34_chany_bottom_out), + .chany_top_out_0(sb_1__1__30_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_6__5_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__30_ccff_tail), + .ccff_head_2(grid_clb_28_ccff_tail), + .chanx_left_in(sb_1__1__24_chanx_right_out), + .chanx_right_in_0(cbx_1__1__38_chanx_left_out), + .chany_bottom_in(sb_1__1__30_chany_top_out), + .chany_top_in_0(cby_1__1__36_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_35_ccff_tail), + .ccff_tail_0(cbx_1__1__31_ccff_tail), + .chanx_left_out(cbx_1__1__31_chanx_left_out), + .chanx_right_out_0(sb_1__1__31_chanx_right_out), + .chany_bottom_out(cby_1__1__35_chany_bottom_out), + .chany_top_out_0(sb_1__1__31_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_6__6_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__31_ccff_tail), + .ccff_head_2(grid_clb_45_ccff_tail), + .chanx_left_in(sb_1__1__25_chanx_right_out), + .chanx_right_in_0(cbx_1__1__39_chanx_left_out), + .chany_bottom_in(sb_1__1__31_chany_top_out), + .chany_top_in_0(cby_1__1__37_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_36_ccff_tail), + .ccff_tail_0(cbx_1__1__32_ccff_tail), + .chanx_left_out(cbx_1__1__32_chanx_left_out), + .chanx_right_out_0(sb_1__1__32_chanx_right_out), + .chany_bottom_out(cby_1__1__36_chany_bottom_out), + .chany_top_out_0(sb_1__1__32_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_6__7_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__32_ccff_tail), + .ccff_head_2(grid_clb_30_ccff_tail), + .chanx_left_in(sb_1__1__26_chanx_right_out), + .chanx_right_in_0(cbx_1__1__40_chanx_left_out), + .chany_bottom_in(sb_1__1__32_chany_top_out), + .chany_top_in_0(cby_1__1__38_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_37_ccff_tail), + .ccff_tail_0(cbx_1__1__33_ccff_tail), + .chanx_left_out(cbx_1__1__33_chanx_left_out), + .chanx_right_out_0(sb_1__1__33_chanx_right_out), + .chany_bottom_out(cby_1__1__37_chany_bottom_out), + .chany_top_out_0(sb_1__1__33_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_6__8_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__33_ccff_tail), + .ccff_head_2(grid_clb_47_ccff_tail), + .chanx_left_in(sb_1__1__27_chanx_right_out), + .chanx_right_in_0(cbx_1__1__41_chanx_left_out), + .chany_bottom_in(sb_1__1__33_chany_top_out), + .chany_top_in_0(cby_1__1__39_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_38_ccff_tail), + .ccff_tail_0(cbx_1__1__34_ccff_tail), + .chanx_left_out(cbx_1__1__34_chanx_left_out), + .chanx_right_out_0(sb_1__1__34_chanx_right_out), + .chany_bottom_out(cby_1__1__38_chany_bottom_out), + .chany_top_out_0(sb_1__1__34_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_) + ); + top_tile tile_6__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__34_ccff_tail), + .ccff_head_2(grid_io_top_top_5_ccff_tail), + .chanx_left_in(sb_1__8__3_chanx_right_out), + .chanx_right_in_0(cbx_1__8__5_chanx_left_out), + .chany_bottom_in(sb_1__1__34_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16:19]), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_7_), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_24_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_clb_39_ccff_tail), + .ccff_tail_0(grid_io_top_top_4_ccff_tail), + .chanx_left_out(cbx_1__8__4_chanx_left_out), + .chanx_right_out_0(sb_1__8__4_chanx_right_out), + .chany_bottom_out(cby_1__1__39_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16:19]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16:19]), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_7_) + ); + bottom_tile tile_7__1_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(grid_io_bottom_bottom_3_ccff_tail), + .ccff_head_1(grid_clb_32_ccff_tail), + .chanx_left_in(sb_1__0__4_chanx_right_out), + .chanx_right_in_0(cbx_1__0__6_chanx_left_out), + .chany_top_in(cby_1__1__40_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72:75]), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_3__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_9_), + .ccff_tail(grid_io_bottom_bottom_2_ccff_tail), + .ccff_tail_0(cbx_1__0__5_ccff_tail), + .chanx_left_out(cbx_1__0__5_chanx_left_out), + .chanx_right_out_0(sb_1__0__5_chanx_right_out), + .chany_top_out(sb_1__0__5_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72:75]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72:75]), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_3__pin_inpad_0_) + ); + tile tile_7__2_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__0__5_ccff_tail), + .ccff_head_2(grid_clb_49_ccff_tail), + .chanx_left_in(sb_1__1__28_chanx_right_out), + .chanx_right_in_0(cbx_1__1__42_chanx_left_out), + .chany_bottom_in(sb_1__0__5_chany_top_out), + .chany_top_in_0(cby_1__1__41_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_40_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_40_ccff_tail), + .ccff_tail_0(cbx_1__1__35_ccff_tail), + .chanx_left_out(cbx_1__1__35_chanx_left_out), + .chanx_right_out_0(sb_1__1__35_chanx_right_out), + .chany_bottom_out(cby_1__1__40_chany_bottom_out), + .chany_top_out_0(sb_1__1__35_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_7__3_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__35_ccff_tail), + .ccff_head_2(grid_clb_34_ccff_tail), + .chanx_left_in(sb_1__1__29_chanx_right_out), + .chanx_right_in_0(cbx_1__1__43_chanx_left_out), + .chany_bottom_in(sb_1__1__35_chany_top_out), + .chany_top_in_0(cby_1__1__42_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_41_ccff_tail), + .ccff_tail_0(cbx_1__1__36_ccff_tail), + .chanx_left_out(cbx_1__1__36_chanx_left_out), + .chanx_right_out_0(sb_1__1__36_chanx_right_out), + .chany_bottom_out(cby_1__1__41_chany_bottom_out), + .chany_top_out_0(sb_1__1__36_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_7__4_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__36_ccff_tail), + .ccff_head_2(grid_clb_51_ccff_tail), + .chanx_left_in(sb_1__1__30_chanx_right_out), + .chanx_right_in_0(cbx_1__1__44_chanx_left_out), + .chany_bottom_in(sb_1__1__36_chany_top_out), + .chany_top_in_0(cby_1__1__43_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_42_ccff_tail), + .ccff_tail_0(cbx_1__1__37_ccff_tail), + .chanx_left_out(cbx_1__1__37_chanx_left_out), + .chanx_right_out_0(sb_1__1__37_chanx_right_out), + .chany_bottom_out(cby_1__1__42_chany_bottom_out), + .chany_top_out_0(sb_1__1__37_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_7__5_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__37_ccff_tail), + .ccff_head_2(grid_clb_36_ccff_tail), + .chanx_left_in(sb_1__1__31_chanx_right_out), + .chanx_right_in_0(cbx_1__1__45_chanx_left_out), + .chany_bottom_in(sb_1__1__37_chany_top_out), + .chany_top_in_0(cby_1__1__44_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_43_ccff_tail), + .ccff_tail_0(cbx_1__1__38_ccff_tail), + .chanx_left_out(cbx_1__1__38_chanx_left_out), + .chanx_right_out_0(sb_1__1__38_chanx_right_out), + .chany_bottom_out(cby_1__1__43_chany_bottom_out), + .chany_top_out_0(sb_1__1__38_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_7__6_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__38_ccff_tail), + .ccff_head_2(grid_clb_53_ccff_tail), + .chanx_left_in(sb_1__1__32_chanx_right_out), + .chanx_right_in_0(cbx_1__1__46_chanx_left_out), + .chany_bottom_in(sb_1__1__38_chany_top_out), + .chany_top_in_0(cby_1__1__45_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_44_ccff_tail), + .ccff_tail_0(cbx_1__1__39_ccff_tail), + .chanx_left_out(cbx_1__1__39_chanx_left_out), + .chanx_right_out_0(sb_1__1__39_chanx_right_out), + .chany_bottom_out(cby_1__1__44_chany_bottom_out), + .chany_top_out_0(sb_1__1__39_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_7__7_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__39_ccff_tail), + .ccff_head_2(grid_clb_38_ccff_tail), + .chanx_left_in(sb_1__1__33_chanx_right_out), + .chanx_right_in_0(cbx_1__1__47_chanx_left_out), + .chany_bottom_in(sb_1__1__39_chany_top_out), + .chany_top_in_0(cby_1__1__46_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_45_ccff_tail), + .ccff_tail_0(cbx_1__1__40_ccff_tail), + .chanx_left_out(cbx_1__1__40_chanx_left_out), + .chanx_right_out_0(sb_1__1__40_chanx_right_out), + .chany_bottom_out(cby_1__1__45_chany_bottom_out), + .chany_top_out_0(sb_1__1__40_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_7__8_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__40_ccff_tail), + .ccff_head_2(grid_clb_55_ccff_tail), + .chanx_left_in(sb_1__1__34_chanx_right_out), + .chanx_right_in_0(cbx_1__1__48_chanx_left_out), + .chany_bottom_in(sb_1__1__40_chany_top_out), + .chany_top_in_0(cby_1__1__47_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_46_ccff_tail), + .ccff_tail_0(cbx_1__1__41_ccff_tail), + .chanx_left_out(cbx_1__1__41_chanx_left_out), + .chanx_right_out_0(sb_1__1__41_chanx_right_out), + .chany_bottom_out(cby_1__1__46_chany_bottom_out), + .chany_top_out_0(sb_1__1__41_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_) + ); + top_tile tile_7__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__41_ccff_tail), + .ccff_head_2(grid_io_top_top_6_ccff_tail), + .chanx_left_in(sb_1__8__4_chanx_right_out), + .chanx_right_in_0(cbx_1__8__6_chanx_left_out), + .chany_bottom_in(sb_1__1__41_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20:23]), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_7_), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_32_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_clb_47_ccff_tail), + .ccff_tail_0(grid_io_top_top_5_ccff_tail), + .chanx_left_out(cbx_1__8__5_chanx_left_out), + .chanx_right_out_0(sb_1__8__5_chanx_right_out), + .chany_bottom_out(cby_1__1__47_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20:23]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20:23]), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_7_) + ); + bottom_tile tile_8__1_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(grid_io_bottom_bottom_2_ccff_tail), + .ccff_head_1(grid_clb_40_ccff_tail), + .chanx_left_in(sb_1__0__5_chanx_right_out), + .chanx_right_in_0(cbx_1__0__7_chanx_left_out), + .chany_top_in(cby_1__1__48_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68:71]), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_9_), + .ccff_tail(grid_io_bottom_bottom_1_ccff_tail), + .ccff_tail_0(cbx_1__0__6_ccff_tail), + .chanx_left_out(cbx_1__0__6_chanx_left_out), + .chanx_right_out_0(sb_1__0__6_chanx_right_out), + .chany_top_out(sb_1__0__6_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68:71]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68:71]), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_3__pin_inpad_0_) + ); + tile tile_8__2_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__0__6_ccff_tail), + .ccff_head_2(grid_clb_57_ccff_tail), + .chanx_left_in(sb_1__1__35_chanx_right_out), + .chanx_right_in_0(cbx_1__1__49_chanx_left_out), + .chany_bottom_in(sb_1__0__6_chany_top_out), + .chany_top_in_0(cby_1__1__49_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_48_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_48_ccff_tail), + .ccff_tail_0(cbx_1__1__42_ccff_tail), + .chanx_left_out(cbx_1__1__42_chanx_left_out), + .chanx_right_out_0(sb_1__1__42_chanx_right_out), + .chany_bottom_out(cby_1__1__48_chany_bottom_out), + .chany_top_out_0(sb_1__1__42_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_8__3_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__42_ccff_tail), + .ccff_head_2(grid_clb_42_ccff_tail), + .chanx_left_in(sb_1__1__36_chanx_right_out), + .chanx_right_in_0(cbx_1__1__50_chanx_left_out), + .chany_bottom_in(sb_1__1__42_chany_top_out), + .chany_top_in_0(cby_1__1__50_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_49_ccff_tail), + .ccff_tail_0(cbx_1__1__43_ccff_tail), + .chanx_left_out(cbx_1__1__43_chanx_left_out), + .chanx_right_out_0(sb_1__1__43_chanx_right_out), + .chany_bottom_out(cby_1__1__49_chany_bottom_out), + .chany_top_out_0(sb_1__1__43_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_8__4_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__43_ccff_tail), + .ccff_head_2(grid_clb_59_ccff_tail), + .chanx_left_in(sb_1__1__37_chanx_right_out), + .chanx_right_in_0(cbx_1__1__51_chanx_left_out), + .chany_bottom_in(sb_1__1__43_chany_top_out), + .chany_top_in_0(cby_1__1__51_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_50_ccff_tail), + .ccff_tail_0(cbx_1__1__44_ccff_tail), + .chanx_left_out(cbx_1__1__44_chanx_left_out), + .chanx_right_out_0(sb_1__1__44_chanx_right_out), + .chany_bottom_out(cby_1__1__50_chany_bottom_out), + .chany_top_out_0(sb_1__1__44_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_8__5_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__44_ccff_tail), + .ccff_head_2(grid_clb_44_ccff_tail), + .chanx_left_in(sb_1__1__38_chanx_right_out), + .chanx_right_in_0(cbx_1__1__52_chanx_left_out), + .chany_bottom_in(sb_1__1__44_chany_top_out), + .chany_top_in_0(cby_1__1__52_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_51_ccff_tail), + .ccff_tail_0(cbx_1__1__45_ccff_tail), + .chanx_left_out(cbx_1__1__45_chanx_left_out), + .chanx_right_out_0(sb_1__1__45_chanx_right_out), + .chany_bottom_out(cby_1__1__51_chany_bottom_out), + .chany_top_out_0(sb_1__1__45_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_8__6_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__45_ccff_tail), + .ccff_head_2(grid_clb_61_ccff_tail), + .chanx_left_in(sb_1__1__39_chanx_right_out), + .chanx_right_in_0(cbx_1__1__53_chanx_left_out), + .chany_bottom_in(sb_1__1__45_chany_top_out), + .chany_top_in_0(cby_1__1__53_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_52_ccff_tail), + .ccff_tail_0(cbx_1__1__46_ccff_tail), + .chanx_left_out(cbx_1__1__46_chanx_left_out), + .chanx_right_out_0(sb_1__1__46_chanx_right_out), + .chany_bottom_out(cby_1__1__52_chany_bottom_out), + .chany_top_out_0(sb_1__1__46_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_8__7_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__46_ccff_tail), + .ccff_head_2(grid_clb_46_ccff_tail), + .chanx_left_in(sb_1__1__40_chanx_right_out), + .chanx_right_in_0(cbx_1__1__54_chanx_left_out), + .chany_bottom_in(sb_1__1__46_chany_top_out), + .chany_top_in_0(cby_1__1__54_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_53_ccff_tail), + .ccff_tail_0(cbx_1__1__47_ccff_tail), + .chanx_left_out(cbx_1__1__47_chanx_left_out), + .chanx_right_out_0(sb_1__1__47_chanx_right_out), + .chany_bottom_out(cby_1__1__53_chany_bottom_out), + .chany_top_out_0(sb_1__1__47_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_) + ); + tile tile_8__8_ + ( + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__47_ccff_tail), + .ccff_head_2(grid_clb_63_ccff_tail), + .chanx_left_in(sb_1__1__41_chanx_right_out), + .chanx_right_in_0(cbx_1__1__55_chanx_left_out), + .chany_bottom_in(sb_1__1__47_chany_top_out), + .chany_top_in_0(cby_1__1__55_chany_bottom_out), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_54_ccff_tail), + .ccff_tail_0(cbx_1__1__48_ccff_tail), + .chanx_left_out(cbx_1__1__48_chanx_left_out), + .chanx_right_out_0(sb_1__1__48_chanx_right_out), + .chany_bottom_out(cby_1__1__54_chany_bottom_out), + .chany_top_out_0(sb_1__1__48_chany_top_out), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_) + ); + top_tile tile_8__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .Test_en(Test_en), + .ccff_head_1(cbx_1__1__48_ccff_tail), + .ccff_head_2(grid_io_top_top_7_ccff_tail), + .chanx_left_in(sb_1__8__5_chanx_right_out), + .chanx_right_in_0(cbx_1__8__7_chanx_left_out), + .chany_bottom_in(sb_1__1__48_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24:27]), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_7_), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_40_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_clb_55_ccff_tail), + .ccff_tail_0(grid_io_top_top_6_ccff_tail), + .chanx_left_out(cbx_1__8__6_chanx_left_out), + .chanx_right_out_0(sb_1__8__6_chanx_right_out), + .chany_bottom_out(cby_1__1__55_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24:27]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24:27]), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_7_) + ); + bottom_right_tile tile_9__1_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(grid_io_bottom_bottom_1_ccff_tail), + .ccff_head_1(grid_clb_48_ccff_tail), + .chanx_left_in(sb_1__0__6_chanx_right_out), + .chany_top_in(cby_8__1__0_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64:67]), + .pReset(pReset), + .prog_clk(prog_clk), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_9_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_0_ccff_tail), + .ccff_tail_0(cbx_1__0__7_ccff_tail), + .chanx_left_out(cbx_1__0__7_chanx_left_out), + .chany_top_out(sb_8__0__0_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64:67]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64:67]), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_) + ); + right_tile tile_9__2_ + ( + .IO_ISOL_N(IO_ISOL_N), + .Test_en(Test_en), + .ccff_head_0_0(cbx_1__0__7_ccff_tail), + .ccff_head_1(grid_io_bottom_bottom_0_ccff_tail), + .ccff_head_2(grid_clb_56_ccff_tail), + .chanx_left_in(sb_1__1__42_chanx_right_out), + .chany_bottom_in(sb_8__0__0_chany_top_out), + .chany_top_in_0(cby_8__1__1_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60:63]), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_9_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_56_ccff_tail), + .ccff_tail_0(cbx_1__1__49_ccff_tail), + .ccff_tail_1(grid_io_right_right_7_ccff_tail), + .chanx_left_out(cbx_1__1__49_chanx_left_out), + .chany_bottom_out(cby_8__1__0_chany_bottom_out), + .chany_top_out_0(sb_8__1__0_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60:63]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60:63]), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_3__pin_inpad_0_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_) + ); + right_tile tile_9__3_ + ( + .IO_ISOL_N(IO_ISOL_N), + .Test_en(Test_en), + .ccff_head_0_0(cbx_1__1__49_ccff_tail), + .ccff_head_1(grid_io_right_right_7_ccff_tail), + .ccff_head_2(grid_clb_50_ccff_tail), + .chanx_left_in(sb_1__1__43_chanx_right_out), + .chany_bottom_in(sb_8__1__0_chany_top_out), + .chany_top_in_0(cby_8__1__2_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56:59]), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_9_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_57_ccff_tail), + .ccff_tail_0(cbx_1__1__50_ccff_tail), + .ccff_tail_1(grid_io_right_right_6_ccff_tail), + .chanx_left_out(cbx_1__1__50_chanx_left_out), + .chany_bottom_out(cby_8__1__1_chany_bottom_out), + .chany_top_out_0(sb_8__1__1_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56:59]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56:59]), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_3__pin_inpad_0_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_) + ); + right_tile tile_9__4_ + ( + .IO_ISOL_N(IO_ISOL_N), + .Test_en(Test_en), + .ccff_head_0_0(cbx_1__1__50_ccff_tail), + .ccff_head_1(grid_io_right_right_6_ccff_tail), + .ccff_head_2(grid_clb_58_ccff_tail), + .chanx_left_in(sb_1__1__44_chanx_right_out), + .chany_bottom_in(sb_8__1__1_chany_top_out), + .chany_top_in_0(cby_8__1__3_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52:55]), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_9_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_58_ccff_tail), + .ccff_tail_0(cbx_1__1__51_ccff_tail), + .ccff_tail_1(grid_io_right_right_5_ccff_tail), + .chanx_left_out(cbx_1__1__51_chanx_left_out), + .chany_bottom_out(cby_8__1__2_chany_bottom_out), + .chany_top_out_0(sb_8__1__2_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52:55]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52:55]), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_3__pin_inpad_0_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_) + ); + right_tile tile_9__5_ + ( + .IO_ISOL_N(IO_ISOL_N), + .Test_en(Test_en), + .ccff_head_0_0(cbx_1__1__51_ccff_tail), + .ccff_head_1(grid_io_right_right_5_ccff_tail), + .ccff_head_2(grid_clb_52_ccff_tail), + .chanx_left_in(sb_1__1__45_chanx_right_out), + .chany_bottom_in(sb_8__1__2_chany_top_out), + .chany_top_in_0(cby_8__1__4_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48:51]), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_9_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_59_ccff_tail), + .ccff_tail_0(cbx_1__1__52_ccff_tail), + .ccff_tail_1(grid_io_right_right_4_ccff_tail), + .chanx_left_out(cbx_1__1__52_chanx_left_out), + .chany_bottom_out(cby_8__1__3_chany_bottom_out), + .chany_top_out_0(sb_8__1__3_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48:51]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48:51]), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_3__pin_inpad_0_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_) + ); + right_tile tile_9__6_ + ( + .IO_ISOL_N(IO_ISOL_N), + .Test_en(Test_en), + .ccff_head_0_0(cbx_1__1__52_ccff_tail), + .ccff_head_1(grid_io_right_right_4_ccff_tail), + .ccff_head_2(grid_clb_60_ccff_tail), + .chanx_left_in(sb_1__1__46_chanx_right_out), + .chany_bottom_in(sb_8__1__3_chany_top_out), + .chany_top_in_0(cby_8__1__5_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44:47]), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_9_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_60_ccff_tail), + .ccff_tail_0(cbx_1__1__53_ccff_tail), + .ccff_tail_1(grid_io_right_right_3_ccff_tail), + .chanx_left_out(cbx_1__1__53_chanx_left_out), + .chany_bottom_out(cby_8__1__4_chany_bottom_out), + .chany_top_out_0(sb_8__1__4_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44:47]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44:47]), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_3__pin_inpad_0_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_) + ); + right_tile tile_9__7_ + ( + .IO_ISOL_N(IO_ISOL_N), + .Test_en(Test_en), + .ccff_head_0_0(cbx_1__1__53_ccff_tail), + .ccff_head_1(grid_io_right_right_3_ccff_tail), + .ccff_head_2(grid_clb_54_ccff_tail), + .chanx_left_in(sb_1__1__47_chanx_right_out), + .chany_bottom_in(sb_8__1__4_chany_top_out), + .chany_top_in_0(cby_8__1__6_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40:43]), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_9_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_61_ccff_tail), + .ccff_tail_0(cbx_1__1__54_ccff_tail), + .ccff_tail_1(grid_io_right_right_2_ccff_tail), + .chanx_left_out(cbx_1__1__54_chanx_left_out), + .chany_bottom_out(cby_8__1__5_chany_bottom_out), + .chany_top_out_0(sb_8__1__5_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40:43]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40:43]), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_3__pin_inpad_0_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_) + ); + right_tile tile_9__8_ + ( + .IO_ISOL_N(IO_ISOL_N), + .Test_en(Test_en), + .ccff_head_0_0(cbx_1__1__54_ccff_tail), + .ccff_head_1(grid_io_right_right_2_ccff_tail), + .ccff_head_2(grid_clb_62_ccff_tail), + .chanx_left_in(sb_1__1__48_chanx_right_out), + .chany_bottom_in(sb_8__1__5_chany_top_out), + .chany_top_in_0(cby_8__1__7_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36:39]), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_9_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(grid_clb_62_ccff_tail), + .ccff_tail_0(cbx_1__1__55_ccff_tail), + .ccff_tail_1(grid_io_right_right_1_ccff_tail), + .chanx_left_out(cbx_1__1__55_chanx_left_out), + .chany_bottom_out(cby_8__1__6_chany_bottom_out), + .chany_top_out_0(sb_8__1__6_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36:39]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36:39]), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_3__pin_inpad_0_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_) + ); + top_right_tile tile_9__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .Test_en(Test_en), + .ccff_head_0_0(cbx_1__1__55_ccff_tail), + .ccff_head_1(grid_io_right_right_1_ccff_tail), + .chanx_left_in(sb_1__8__6_chanx_right_out), + .chany_bottom_in(sb_8__1__6_chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28:31]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN_0(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32:35]), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .pReset(pReset), + .prog_clk(prog_clk), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_48_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_clb_63_ccff_tail), + .ccff_tail_0(grid_io_top_top_7_ccff_tail), + .chanx_left_out(cbx_1__8__7_chanx_left_out), + .chany_bottom_out(cby_8__1__7_chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28:31]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_0(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32:35]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28:31]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_0(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32:35]), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_7_) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD.v new file mode 100644 index 0000000..4f903f1 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD.v @@ -0,0 +1,31 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module EMBEDDED_IO_HD +( + FPGA_DIR, + FPGA_OUT, + IO_ISOL_N, + SOC_IN, + FPGA_IN, + SOC_DIR, + SOC_OUT +); + + input FPGA_DIR; + input FPGA_OUT; + input IO_ISOL_N; + input SOC_IN; + output FPGA_IN; + output SOC_DIR; + output SOC_OUT; + + wire FPGA_DIR; + wire FPGA_IN; + wire FPGA_OUT; + wire IO_ISOL_N; + wire SOC_DIR; + wire SOC_IN; + wire SOC_OUT; + +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.v new file mode 100644 index 0000000..4757823 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.v @@ -0,0 +1,33 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem +( + ccff_head, + pReset, + prog_clk, + ccff_tail, + mem_out +); + + input ccff_head; + input pReset; + input prog_clk; + output ccff_tail; + output mem_out; + + wire ccff_head; + wire ccff_tail; + wire mem_out; + wire pReset; + wire prog_clk; + +assign ccff_tail = mem_out; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .CLK(prog_clk), + .D(ccff_head), + .RESET_B(pReset), + .Q(mem_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0_.v new file mode 100644 index 0000000..b5ea2fc --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0_.v @@ -0,0 +1,102 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cbx_1__0_ +( + IO_ISOL_N, + ccff_head, + ccff_head_0, + chanx_left_in, + chanx_right_in, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + pReset, + prog_clk, + ccff_tail, + ccff_tail_0, + chanx_left_out, + chanx_right_out, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + top_width_0_height_0_subtile_0__pin_inpad_0_, + top_width_0_height_0_subtile_1__pin_inpad_0_, + top_width_0_height_0_subtile_2__pin_inpad_0_, + top_width_0_height_0_subtile_3__pin_inpad_0_ +); + + input IO_ISOL_N; + input ccff_head; + input ccff_head_0; + input [29:0]chanx_left_in; + input [29:0]chanx_right_in; + input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input pReset; + input prog_clk; + output ccff_tail; + output ccff_tail_0; + output [29:0]chanx_left_out; + output [29:0]chanx_right_out; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output top_width_0_height_0_subtile_0__pin_inpad_0_; + output top_width_0_height_0_subtile_1__pin_inpad_0_; + output top_width_0_height_0_subtile_2__pin_inpad_0_; + output top_width_0_height_0_subtile_3__pin_inpad_0_; + + wire IO_ISOL_N; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_head; + wire ccff_head_0; + wire ccff_tail; + wire ccff_tail_0; + wire [29:0]chanx_left_in; + wire [29:0]chanx_left_out; + wire [29:0]chanx_right_in; + wire [29:0]chanx_right_out; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire pReset; + wire prog_clk; + wire top_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_width_0_height_0_subtile_3__pin_inpad_0_; + + cbx_1__0__old cbx_8__0_ + ( + .ccff_head(ccff_head_0), + .chanx_left_in(chanx_left_in), + .chanx_right_in(chanx_right_in), + .pReset(pReset), + .prog_clk(prog_clk), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(ccff_tail_0), + .chanx_left_out(chanx_left_out), + .chanx_right_out(chanx_right_out) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_8__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(ccff_head), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .pReset(pReset), + .prog_clk(prog_clk), + .top_width_0_height_0_subtile_0__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), + .top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(top_width_0_height_0_subtile_3__pin_inpad_0_) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0__old.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0__old.v new file mode 100644 index 0000000..2d4c7cf --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0__old.v @@ -0,0 +1,177 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cbx_1__0__old +( + ccff_head, + chanx_left_in, + chanx_right_in, + pReset, + prog_clk, + bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_tail, + chanx_left_out, + chanx_right_out +); + + input ccff_head; + input [0:29]chanx_left_in; + input [0:29]chanx_right_in; + input pReset; + input prog_clk; + output bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + output bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + output bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + output bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + output ccff_tail; + output [0:29]chanx_left_out; + output [0:29]chanx_right_out; + + wire bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_head; + wire ccff_tail; + wire [0:29]chanx_left_in; + wire [0:29]chanx_left_out; + wire [0:29]chanx_right_in; + wire [0:29]chanx_right_out; + wire [0:3]mux_top_ipin_0_undriven_sram_inv; + wire [0:3]mux_top_ipin_1_undriven_sram_inv; + wire [0:3]mux_top_ipin_2_undriven_sram_inv; + wire [0:3]mux_top_ipin_3_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire pReset; + wire prog_clk; + +assign chanx_right_out[0] = chanx_left_in[0]; +assign chanx_right_out[1] = chanx_left_in[1]; +assign chanx_right_out[10] = chanx_left_in[10]; +assign chanx_right_out[11] = chanx_left_in[11]; +assign chanx_right_out[12] = chanx_left_in[12]; +assign chanx_right_out[13] = chanx_left_in[13]; +assign chanx_right_out[14] = chanx_left_in[14]; +assign chanx_right_out[15] = chanx_left_in[15]; +assign chanx_right_out[16] = chanx_left_in[16]; +assign chanx_right_out[17] = chanx_left_in[17]; +assign chanx_right_out[18] = chanx_left_in[18]; +assign chanx_right_out[19] = chanx_left_in[19]; +assign chanx_right_out[2] = chanx_left_in[2]; +assign chanx_right_out[20] = chanx_left_in[20]; +assign chanx_right_out[21] = chanx_left_in[21]; +assign chanx_right_out[22] = chanx_left_in[22]; +assign chanx_right_out[23] = chanx_left_in[23]; +assign chanx_right_out[24] = chanx_left_in[24]; +assign chanx_right_out[25] = chanx_left_in[25]; +assign chanx_right_out[26] = chanx_left_in[26]; +assign chanx_right_out[27] = chanx_left_in[27]; +assign chanx_right_out[28] = chanx_left_in[28]; +assign chanx_right_out[29] = chanx_left_in[29]; +assign chanx_right_out[3] = chanx_left_in[3]; +assign chanx_left_out[0] = chanx_right_in[0]; +assign chanx_left_out[1] = chanx_right_in[1]; +assign chanx_left_out[2] = chanx_right_in[2]; +assign chanx_left_out[3] = chanx_right_in[3]; +assign chanx_left_out[4] = chanx_right_in[4]; +assign chanx_left_out[5] = chanx_right_in[5]; +assign chanx_left_out[6] = chanx_right_in[6]; +assign chanx_left_out[7] = chanx_right_in[7]; +assign chanx_left_out[8] = chanx_right_in[8]; +assign chanx_left_out[9] = chanx_right_in[9]; +assign chanx_right_out[4] = chanx_left_in[4]; +assign chanx_left_out[10] = chanx_right_in[10]; +assign chanx_left_out[11] = chanx_right_in[11]; +assign chanx_left_out[12] = chanx_right_in[12]; +assign chanx_left_out[13] = chanx_right_in[13]; +assign chanx_left_out[14] = chanx_right_in[14]; +assign chanx_left_out[15] = chanx_right_in[15]; +assign chanx_left_out[16] = chanx_right_in[16]; +assign chanx_left_out[17] = chanx_right_in[17]; +assign chanx_left_out[18] = chanx_right_in[18]; +assign chanx_left_out[19] = chanx_right_in[19]; +assign chanx_right_out[5] = chanx_left_in[5]; +assign chanx_left_out[20] = chanx_right_in[20]; +assign chanx_left_out[21] = chanx_right_in[21]; +assign chanx_left_out[22] = chanx_right_in[22]; +assign chanx_left_out[23] = chanx_right_in[23]; +assign chanx_left_out[24] = chanx_right_in[24]; +assign chanx_left_out[25] = chanx_right_in[25]; +assign chanx_left_out[26] = chanx_right_in[26]; +assign chanx_left_out[27] = chanx_right_in[27]; +assign chanx_left_out[28] = chanx_right_in[28]; +assign chanx_left_out[29] = chanx_right_in[29]; +assign chanx_right_out[6] = chanx_left_in[6]; +assign chanx_right_out[7] = chanx_left_in[7]; +assign chanx_right_out[8] = chanx_left_in[8]; +assign chanx_right_out[9] = chanx_left_in[9]; + mux_tree_tapbuf_size12_mem mem_top_ipin_0 + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_1 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_2 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_3 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size12 mux_top_ipin_0 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_top_ipin_0_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_1 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_top_ipin_1_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_2 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_top_ipin_2_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_3 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21], chanx_left_in[27], chanx_right_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_top_ipin_3_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__1_.v new file mode 100644 index 0000000..6ad0f0a --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__1_.v @@ -0,0 +1,429 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cbx_1__1_ +( + ccff_head, + chanx_left_in, + chanx_right_in, + pReset, + prog_clk, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_, + ccff_tail, + chanx_left_out, + chanx_right_out +); + + input ccff_head; + input [0:29]chanx_left_in; + input [0:29]chanx_right_in; + input pReset; + input prog_clk; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + output ccff_tail; + output [0:29]chanx_left_out; + output [0:29]chanx_right_out; + + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire ccff_head; + wire ccff_tail; + wire [0:29]chanx_left_in; + wire [0:29]chanx_left_out; + wire [0:29]chanx_right_in; + wire [0:29]chanx_right_out; + wire [0:3]mux_top_ipin_0_undriven_sram_inv; + wire [0:3]mux_top_ipin_10_undriven_sram_inv; + wire [0:3]mux_top_ipin_11_undriven_sram_inv; + wire [0:3]mux_top_ipin_12_undriven_sram_inv; + wire [0:3]mux_top_ipin_13_undriven_sram_inv; + wire [0:3]mux_top_ipin_14_undriven_sram_inv; + wire [0:3]mux_top_ipin_15_undriven_sram_inv; + wire [0:3]mux_top_ipin_1_undriven_sram_inv; + wire [0:3]mux_top_ipin_2_undriven_sram_inv; + wire [0:3]mux_top_ipin_3_undriven_sram_inv; + wire [0:3]mux_top_ipin_4_undriven_sram_inv; + wire [0:3]mux_top_ipin_5_undriven_sram_inv; + wire [0:3]mux_top_ipin_6_undriven_sram_inv; + wire [0:3]mux_top_ipin_7_undriven_sram_inv; + wire [0:3]mux_top_ipin_8_undriven_sram_inv; + wire [0:3]mux_top_ipin_9_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire [0:3]mux_tree_tapbuf_size10_1_sram; + wire [0:3]mux_tree_tapbuf_size10_2_sram; + wire [0:3]mux_tree_tapbuf_size10_3_sram; + wire [0:3]mux_tree_tapbuf_size10_4_sram; + wire [0:3]mux_tree_tapbuf_size10_5_sram; + wire [0:3]mux_tree_tapbuf_size10_6_sram; + wire [0:3]mux_tree_tapbuf_size10_7_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire [0:3]mux_tree_tapbuf_size12_4_sram; + wire [0:3]mux_tree_tapbuf_size12_5_sram; + wire [0:3]mux_tree_tapbuf_size12_6_sram; + wire [0:3]mux_tree_tapbuf_size12_7_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire mux_tree_tapbuf_size12_mem_7_ccff_tail; + wire pReset; + wire prog_clk; + +assign chanx_right_out[0] = chanx_left_in[0]; +assign chanx_right_out[1] = chanx_left_in[1]; +assign chanx_right_out[10] = chanx_left_in[10]; +assign chanx_right_out[11] = chanx_left_in[11]; +assign chanx_right_out[12] = chanx_left_in[12]; +assign chanx_right_out[13] = chanx_left_in[13]; +assign chanx_right_out[14] = chanx_left_in[14]; +assign chanx_right_out[15] = chanx_left_in[15]; +assign chanx_right_out[16] = chanx_left_in[16]; +assign chanx_right_out[17] = chanx_left_in[17]; +assign chanx_right_out[18] = chanx_left_in[18]; +assign chanx_right_out[19] = chanx_left_in[19]; +assign chanx_right_out[2] = chanx_left_in[2]; +assign chanx_right_out[20] = chanx_left_in[20]; +assign chanx_right_out[21] = chanx_left_in[21]; +assign chanx_right_out[22] = chanx_left_in[22]; +assign chanx_right_out[23] = chanx_left_in[23]; +assign chanx_right_out[24] = chanx_left_in[24]; +assign chanx_right_out[25] = chanx_left_in[25]; +assign chanx_right_out[26] = chanx_left_in[26]; +assign chanx_right_out[27] = chanx_left_in[27]; +assign chanx_right_out[28] = chanx_left_in[28]; +assign chanx_right_out[29] = chanx_left_in[29]; +assign chanx_right_out[3] = chanx_left_in[3]; +assign chanx_left_out[0] = chanx_right_in[0]; +assign chanx_left_out[1] = chanx_right_in[1]; +assign chanx_left_out[2] = chanx_right_in[2]; +assign chanx_left_out[3] = chanx_right_in[3]; +assign chanx_left_out[4] = chanx_right_in[4]; +assign chanx_left_out[5] = chanx_right_in[5]; +assign chanx_left_out[6] = chanx_right_in[6]; +assign chanx_left_out[7] = chanx_right_in[7]; +assign chanx_left_out[8] = chanx_right_in[8]; +assign chanx_left_out[9] = chanx_right_in[9]; +assign chanx_right_out[4] = chanx_left_in[4]; +assign chanx_left_out[10] = chanx_right_in[10]; +assign chanx_left_out[11] = chanx_right_in[11]; +assign chanx_left_out[12] = chanx_right_in[12]; +assign chanx_left_out[13] = chanx_right_in[13]; +assign chanx_left_out[14] = chanx_right_in[14]; +assign chanx_left_out[15] = chanx_right_in[15]; +assign chanx_left_out[16] = chanx_right_in[16]; +assign chanx_left_out[17] = chanx_right_in[17]; +assign chanx_left_out[18] = chanx_right_in[18]; +assign chanx_left_out[19] = chanx_right_in[19]; +assign chanx_right_out[5] = chanx_left_in[5]; +assign chanx_left_out[20] = chanx_right_in[20]; +assign chanx_left_out[21] = chanx_right_in[21]; +assign chanx_left_out[22] = chanx_right_in[22]; +assign chanx_left_out[23] = chanx_right_in[23]; +assign chanx_left_out[24] = chanx_right_in[24]; +assign chanx_left_out[25] = chanx_right_in[25]; +assign chanx_left_out[26] = chanx_right_in[26]; +assign chanx_left_out[27] = chanx_right_in[27]; +assign chanx_left_out[28] = chanx_right_in[28]; +assign chanx_left_out[29] = chanx_right_in[29]; +assign chanx_right_out[6] = chanx_left_in[6]; +assign chanx_right_out[7] = chanx_left_in[7]; +assign chanx_right_out[8] = chanx_left_in[8]; +assign chanx_right_out[9] = chanx_left_in[9]; + mux_tree_tapbuf_size12_mem mem_top_ipin_0 + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_1 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_10 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_11 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_12 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_13 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_14 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_15 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_2 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_3 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_4 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_5 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_6 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_7 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_8 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_9 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram) + ); + mux_tree_tapbuf_size12 mux_top_ipin_0 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_top_ipin_0_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_1 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[16], chanx_right_in[16], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_top_ipin_1_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_10 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_5_sram), + .sram_inv(mux_top_ipin_10_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_11 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size10_5_sram), + .sram_inv(mux_top_ipin_11_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_12 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_6_sram), + .sram_inv(mux_top_ipin_12_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_13 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size10_6_sram), + .sram_inv(mux_top_ipin_13_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_14 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_7_sram), + .sram_inv(mux_top_ipin_14_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_15 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21]}), + .sram(mux_tree_tapbuf_size10_7_sram), + .sram_inv(mux_top_ipin_15_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_2 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_top_ipin_2_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_3 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[18], chanx_right_in[18], chanx_left_in[27], chanx_right_in[27]}), + .sram(mux_tree_tapbuf_size10_1_sram), + .sram_inv(mux_top_ipin_3_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_4 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_top_ipin_4_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_5 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[20], chanx_right_in[20], chanx_left_in[29], chanx_right_in[29]}), + .sram(mux_tree_tapbuf_size10_2_sram), + .sram_inv(mux_top_ipin_5_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_6 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_top_ipin_6_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_7 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[22], chanx_right_in[22]}), + .sram(mux_tree_tapbuf_size10_3_sram), + .sram_inv(mux_top_ipin_7_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_8 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_4_sram), + .sram_inv(mux_top_ipin_8_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_9 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size10_4_sram), + .sram_inv(mux_top_ipin_9_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8_.v new file mode 100644 index 0000000..5dc8033 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8_.v @@ -0,0 +1,161 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cbx_1__8_ +( + IO_ISOL_N, + ccff_head_0, + chanx_left_in, + chanx_right_in, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + pReset, + prog_clk, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_, + bottom_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail, + chanx_left_out, + chanx_right_out, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT +); + + input IO_ISOL_N; + input ccff_head_0; + input [29:0]chanx_left_in; + input [29:0]chanx_right_in; + input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input pReset; + input prog_clk; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + output bottom_width_0_height_0_subtile_0__pin_inpad_0_; + output bottom_width_0_height_0_subtile_1__pin_inpad_0_; + output bottom_width_0_height_0_subtile_2__pin_inpad_0_; + output bottom_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + output [29:0]chanx_left_out; + output [29:0]chanx_right_out; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + + wire IO_ISOL_N; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head_0; + wire ccff_tail; + wire ccff_tail_0; + wire [29:0]chanx_left_in; + wire [29:0]chanx_left_out; + wire [29:0]chanx_right_in; + wire [29:0]chanx_right_out; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire pReset; + wire prog_clk; + wire top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + + cbx_1__8__old cbx_1__8_ + ( + .ccff_head(ccff_head_0), + .chanx_left_in(chanx_left_in), + .chanx_right_in(chanx_right_in), + .pReset(pReset), + .prog_clk(prog_clk), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(ccff_tail_0), + .chanx_left_out(chanx_left_out), + .chanx_right_out(chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_) + ); + grid_io_top_top grid_io_top_top_1__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(ccff_tail_0), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .pReset(pReset), + .prog_clk(prog_clk), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8__old.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8__old.v new file mode 100644 index 0000000..b31d489 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8__old.v @@ -0,0 +1,513 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cbx_1__8__old +( + ccff_head, + chanx_left_in, + chanx_right_in, + pReset, + prog_clk, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_, + ccff_tail, + chanx_left_out, + chanx_right_out, + top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_ +); + + input ccff_head; + input [0:29]chanx_left_in; + input [0:29]chanx_right_in; + input pReset; + input prog_clk; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + output ccff_tail; + output [0:29]chanx_left_out; + output [0:29]chanx_right_out; + output top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + output top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + output top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + output top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire ccff_head; + wire ccff_tail; + wire [0:29]chanx_left_in; + wire [0:29]chanx_left_out; + wire [0:29]chanx_right_in; + wire [0:29]chanx_right_out; + wire [0:3]mux_bottom_ipin_0_undriven_sram_inv; + wire [0:3]mux_bottom_ipin_1_undriven_sram_inv; + wire [0:3]mux_bottom_ipin_2_undriven_sram_inv; + wire [0:3]mux_bottom_ipin_3_undriven_sram_inv; + wire [0:3]mux_top_ipin_0_undriven_sram_inv; + wire [0:3]mux_top_ipin_10_undriven_sram_inv; + wire [0:3]mux_top_ipin_11_undriven_sram_inv; + wire [0:3]mux_top_ipin_12_undriven_sram_inv; + wire [0:3]mux_top_ipin_13_undriven_sram_inv; + wire [0:3]mux_top_ipin_14_undriven_sram_inv; + wire [0:3]mux_top_ipin_15_undriven_sram_inv; + wire [0:3]mux_top_ipin_1_undriven_sram_inv; + wire [0:3]mux_top_ipin_2_undriven_sram_inv; + wire [0:3]mux_top_ipin_3_undriven_sram_inv; + wire [0:3]mux_top_ipin_4_undriven_sram_inv; + wire [0:3]mux_top_ipin_5_undriven_sram_inv; + wire [0:3]mux_top_ipin_6_undriven_sram_inv; + wire [0:3]mux_top_ipin_7_undriven_sram_inv; + wire [0:3]mux_top_ipin_8_undriven_sram_inv; + wire [0:3]mux_top_ipin_9_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire [0:3]mux_tree_tapbuf_size10_1_sram; + wire [0:3]mux_tree_tapbuf_size10_2_sram; + wire [0:3]mux_tree_tapbuf_size10_3_sram; + wire [0:3]mux_tree_tapbuf_size10_4_sram; + wire [0:3]mux_tree_tapbuf_size10_5_sram; + wire [0:3]mux_tree_tapbuf_size10_6_sram; + wire [0:3]mux_tree_tapbuf_size10_7_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_10_sram; + wire [0:3]mux_tree_tapbuf_size12_11_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire [0:3]mux_tree_tapbuf_size12_4_sram; + wire [0:3]mux_tree_tapbuf_size12_5_sram; + wire [0:3]mux_tree_tapbuf_size12_6_sram; + wire [0:3]mux_tree_tapbuf_size12_7_sram; + wire [0:3]mux_tree_tapbuf_size12_8_sram; + wire [0:3]mux_tree_tapbuf_size12_9_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_10_ccff_tail; + wire mux_tree_tapbuf_size12_mem_11_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire mux_tree_tapbuf_size12_mem_7_ccff_tail; + wire mux_tree_tapbuf_size12_mem_8_ccff_tail; + wire mux_tree_tapbuf_size12_mem_9_ccff_tail; + wire pReset; + wire prog_clk; + wire top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + +assign chanx_right_out[0] = chanx_left_in[0]; +assign chanx_right_out[1] = chanx_left_in[1]; +assign chanx_right_out[10] = chanx_left_in[10]; +assign chanx_right_out[11] = chanx_left_in[11]; +assign chanx_right_out[12] = chanx_left_in[12]; +assign chanx_right_out[13] = chanx_left_in[13]; +assign chanx_right_out[14] = chanx_left_in[14]; +assign chanx_right_out[15] = chanx_left_in[15]; +assign chanx_right_out[16] = chanx_left_in[16]; +assign chanx_right_out[17] = chanx_left_in[17]; +assign chanx_right_out[18] = chanx_left_in[18]; +assign chanx_right_out[19] = chanx_left_in[19]; +assign chanx_right_out[2] = chanx_left_in[2]; +assign chanx_right_out[20] = chanx_left_in[20]; +assign chanx_right_out[21] = chanx_left_in[21]; +assign chanx_right_out[22] = chanx_left_in[22]; +assign chanx_right_out[23] = chanx_left_in[23]; +assign chanx_right_out[24] = chanx_left_in[24]; +assign chanx_right_out[25] = chanx_left_in[25]; +assign chanx_right_out[26] = chanx_left_in[26]; +assign chanx_right_out[27] = chanx_left_in[27]; +assign chanx_right_out[28] = chanx_left_in[28]; +assign chanx_right_out[29] = chanx_left_in[29]; +assign chanx_right_out[3] = chanx_left_in[3]; +assign chanx_left_out[0] = chanx_right_in[0]; +assign chanx_left_out[1] = chanx_right_in[1]; +assign chanx_left_out[2] = chanx_right_in[2]; +assign chanx_left_out[3] = chanx_right_in[3]; +assign chanx_left_out[4] = chanx_right_in[4]; +assign chanx_left_out[5] = chanx_right_in[5]; +assign chanx_left_out[6] = chanx_right_in[6]; +assign chanx_left_out[7] = chanx_right_in[7]; +assign chanx_left_out[8] = chanx_right_in[8]; +assign chanx_left_out[9] = chanx_right_in[9]; +assign chanx_right_out[4] = chanx_left_in[4]; +assign chanx_left_out[10] = chanx_right_in[10]; +assign chanx_left_out[11] = chanx_right_in[11]; +assign chanx_left_out[12] = chanx_right_in[12]; +assign chanx_left_out[13] = chanx_right_in[13]; +assign chanx_left_out[14] = chanx_right_in[14]; +assign chanx_left_out[15] = chanx_right_in[15]; +assign chanx_left_out[16] = chanx_right_in[16]; +assign chanx_left_out[17] = chanx_right_in[17]; +assign chanx_left_out[18] = chanx_right_in[18]; +assign chanx_left_out[19] = chanx_right_in[19]; +assign chanx_right_out[5] = chanx_left_in[5]; +assign chanx_left_out[20] = chanx_right_in[20]; +assign chanx_left_out[21] = chanx_right_in[21]; +assign chanx_left_out[22] = chanx_right_in[22]; +assign chanx_left_out[23] = chanx_right_in[23]; +assign chanx_left_out[24] = chanx_right_in[24]; +assign chanx_left_out[25] = chanx_right_in[25]; +assign chanx_left_out[26] = chanx_right_in[26]; +assign chanx_left_out[27] = chanx_right_in[27]; +assign chanx_left_out[28] = chanx_right_in[28]; +assign chanx_left_out[29] = chanx_right_in[29]; +assign chanx_right_out[6] = chanx_left_in[6]; +assign chanx_right_out[7] = chanx_left_in[7]; +assign chanx_right_out[8] = chanx_left_in[8]; +assign chanx_right_out[9] = chanx_left_in[9]; + mux_tree_tapbuf_size12_mem mem_bottom_ipin_0 + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_bottom_ipin_1 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_bottom_ipin_2 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_bottom_ipin_3 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_0 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_1 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_10 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_9_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_11 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_12 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_10_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_13 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_14 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_11_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_15 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_2 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_3 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_4 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_5 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_6 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_7 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_8 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_8_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_9 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram) + ); + mux_tree_tapbuf_size12 mux_bottom_ipin_0 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_bottom_ipin_0_undriven_sram_inv), + .out(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_bottom_ipin_1 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_bottom_ipin_1_undriven_sram_inv), + .out(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_bottom_ipin_2 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_bottom_ipin_2_undriven_sram_inv), + .out(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_bottom_ipin_3 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21], chanx_left_in[27], chanx_right_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_bottom_ipin_3_undriven_sram_inv), + .out(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_0 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_4_sram), + .sram_inv(mux_top_ipin_0_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_1 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[20], chanx_right_in[20], chanx_left_in[29], chanx_right_in[29]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_top_ipin_1_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_10 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_9_sram), + .sram_inv(mux_top_ipin_10_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_11 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21]}), + .sram(mux_tree_tapbuf_size10_5_sram), + .sram_inv(mux_top_ipin_11_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_12 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_10_sram), + .sram_inv(mux_top_ipin_12_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_13 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[17], chanx_right_in[17], chanx_left_in[23], chanx_right_in[23]}), + .sram(mux_tree_tapbuf_size10_6_sram), + .sram_inv(mux_top_ipin_13_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_14 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_11_sram), + .sram_inv(mux_top_ipin_14_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_15 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size10_7_sram), + .sram_inv(mux_top_ipin_15_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_2 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_5_sram), + .sram_inv(mux_top_ipin_2_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_3 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[22], chanx_right_in[22]}), + .sram(mux_tree_tapbuf_size10_1_sram), + .sram_inv(mux_top_ipin_3_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_4 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_6_sram), + .sram_inv(mux_top_ipin_4_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_5 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size10_2_sram), + .sram_inv(mux_top_ipin_5_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_6 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_7_sram), + .sram_inv(mux_top_ipin_6_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_7 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size10_3_sram), + .sram_inv(mux_top_ipin_7_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_8 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_8_sram), + .sram_inv(mux_top_ipin_8_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_9 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size10_4_sram), + .sram_inv(mux_top_ipin_9_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1_.v new file mode 100644 index 0000000..69c1735 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1_.v @@ -0,0 +1,97 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cby_0__1_ +( + IO_ISOL_N, + ccff_head_0, + chany_bottom_in, + chany_top_in, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + pReset, + prog_clk, + ccff_tail, + chany_bottom_out, + chany_top_out, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + right_width_0_height_0_subtile_0__pin_inpad_0_, + right_width_0_height_0_subtile_1__pin_inpad_0_, + right_width_0_height_0_subtile_2__pin_inpad_0_, + right_width_0_height_0_subtile_3__pin_inpad_0_ +); + + input IO_ISOL_N; + input ccff_head_0; + input [29:0]chany_bottom_in; + input [29:0]chany_top_in; + input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input pReset; + input prog_clk; + output ccff_tail; + output [29:0]chany_bottom_out; + output [29:0]chany_top_out; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output right_width_0_height_0_subtile_0__pin_inpad_0_; + output right_width_0_height_0_subtile_1__pin_inpad_0_; + output right_width_0_height_0_subtile_2__pin_inpad_0_; + output right_width_0_height_0_subtile_3__pin_inpad_0_; + + wire IO_ISOL_N; + wire ccff_head_0; + wire ccff_tail; + wire ccff_tail_0; + wire [29:0]chany_bottom_in; + wire [29:0]chany_bottom_out; + wire [29:0]chany_top_in; + wire [29:0]chany_top_out; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire pReset; + wire prog_clk; + wire right_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_width_0_height_0_subtile_3__pin_inpad_0_; + + cby_0__1__old cby_0__1_ + ( + .ccff_head(ccff_head_0), + .chany_bottom_in(chany_bottom_in), + .chany_top_in(chany_top_in), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail_0), + .chany_bottom_out(chany_bottom_out), + .chany_top_out(chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_) + ); + grid_io_left_left grid_io_left_left_0__1_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(ccff_tail_0), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .pReset(pReset), + .prog_clk(prog_clk), + .right_width_0_height_0_subtile_0__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), + .right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(right_width_0_height_0_subtile_3__pin_inpad_0_) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1__old.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1__old.v new file mode 100644 index 0000000..798e545 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1__old.v @@ -0,0 +1,177 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cby_0__1__old +( + ccff_head, + chany_bottom_in, + chany_top_in, + pReset, + prog_clk, + ccff_tail, + chany_bottom_out, + chany_top_out, + left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_ +); + + input ccff_head; + input [0:29]chany_bottom_in; + input [0:29]chany_top_in; + input pReset; + input prog_clk; + output ccff_tail; + output [0:29]chany_bottom_out; + output [0:29]chany_top_out; + output left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + output left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + output left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + output left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + + wire ccff_head; + wire ccff_tail; + wire [0:29]chany_bottom_in; + wire [0:29]chany_bottom_out; + wire [0:29]chany_top_in; + wire [0:29]chany_top_out; + wire left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire [0:3]mux_right_ipin_0_undriven_sram_inv; + wire [0:3]mux_right_ipin_1_undriven_sram_inv; + wire [0:3]mux_right_ipin_2_undriven_sram_inv; + wire [0:3]mux_right_ipin_3_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire pReset; + wire prog_clk; + +assign chany_top_out[0] = chany_bottom_in[0]; +assign chany_top_out[1] = chany_bottom_in[1]; +assign chany_top_out[10] = chany_bottom_in[10]; +assign chany_top_out[11] = chany_bottom_in[11]; +assign chany_top_out[12] = chany_bottom_in[12]; +assign chany_top_out[13] = chany_bottom_in[13]; +assign chany_top_out[14] = chany_bottom_in[14]; +assign chany_top_out[15] = chany_bottom_in[15]; +assign chany_top_out[16] = chany_bottom_in[16]; +assign chany_top_out[17] = chany_bottom_in[17]; +assign chany_top_out[18] = chany_bottom_in[18]; +assign chany_top_out[19] = chany_bottom_in[19]; +assign chany_top_out[2] = chany_bottom_in[2]; +assign chany_top_out[20] = chany_bottom_in[20]; +assign chany_top_out[21] = chany_bottom_in[21]; +assign chany_top_out[22] = chany_bottom_in[22]; +assign chany_top_out[23] = chany_bottom_in[23]; +assign chany_top_out[24] = chany_bottom_in[24]; +assign chany_top_out[25] = chany_bottom_in[25]; +assign chany_top_out[26] = chany_bottom_in[26]; +assign chany_top_out[27] = chany_bottom_in[27]; +assign chany_top_out[28] = chany_bottom_in[28]; +assign chany_top_out[29] = chany_bottom_in[29]; +assign chany_top_out[3] = chany_bottom_in[3]; +assign chany_bottom_out[0] = chany_top_in[0]; +assign chany_bottom_out[1] = chany_top_in[1]; +assign chany_bottom_out[2] = chany_top_in[2]; +assign chany_bottom_out[3] = chany_top_in[3]; +assign chany_bottom_out[4] = chany_top_in[4]; +assign chany_bottom_out[5] = chany_top_in[5]; +assign chany_bottom_out[6] = chany_top_in[6]; +assign chany_bottom_out[7] = chany_top_in[7]; +assign chany_bottom_out[8] = chany_top_in[8]; +assign chany_bottom_out[9] = chany_top_in[9]; +assign chany_top_out[4] = chany_bottom_in[4]; +assign chany_bottom_out[10] = chany_top_in[10]; +assign chany_bottom_out[11] = chany_top_in[11]; +assign chany_bottom_out[12] = chany_top_in[12]; +assign chany_bottom_out[13] = chany_top_in[13]; +assign chany_bottom_out[14] = chany_top_in[14]; +assign chany_bottom_out[15] = chany_top_in[15]; +assign chany_bottom_out[16] = chany_top_in[16]; +assign chany_bottom_out[17] = chany_top_in[17]; +assign chany_bottom_out[18] = chany_top_in[18]; +assign chany_bottom_out[19] = chany_top_in[19]; +assign chany_top_out[5] = chany_bottom_in[5]; +assign chany_bottom_out[20] = chany_top_in[20]; +assign chany_bottom_out[21] = chany_top_in[21]; +assign chany_bottom_out[22] = chany_top_in[22]; +assign chany_bottom_out[23] = chany_top_in[23]; +assign chany_bottom_out[24] = chany_top_in[24]; +assign chany_bottom_out[25] = chany_top_in[25]; +assign chany_bottom_out[26] = chany_top_in[26]; +assign chany_bottom_out[27] = chany_top_in[27]; +assign chany_bottom_out[28] = chany_top_in[28]; +assign chany_bottom_out[29] = chany_top_in[29]; +assign chany_top_out[6] = chany_bottom_in[6]; +assign chany_top_out[7] = chany_bottom_in[7]; +assign chany_top_out[8] = chany_bottom_in[8]; +assign chany_top_out[9] = chany_bottom_in[9]; + mux_tree_tapbuf_size12_mem mem_right_ipin_0 + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_1 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_2 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_3 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size12 mux_right_ipin_0 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_right_ipin_0_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_1 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_right_ipin_1_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_2 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_right_ipin_2_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_3 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21], chany_bottom_in[27], chany_top_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_right_ipin_3_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_1__1_.v new file mode 100644 index 0000000..8e4f9ae --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_1__1_.v @@ -0,0 +1,429 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cby_1__1_ +( + ccff_head, + chany_bottom_in, + chany_top_in, + pReset, + prog_clk, + ccff_tail, + chany_bottom_out, + chany_top_out, + left_grid_right_width_0_height_0_subtile_0__pin_I4_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_ +); + + input ccff_head; + input [0:29]chany_bottom_in; + input [0:29]chany_top_in; + input pReset; + input prog_clk; + output ccff_tail; + output [0:29]chany_bottom_out; + output [0:29]chany_top_out; + output left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + + wire ccff_head; + wire ccff_tail; + wire [0:29]chany_bottom_in; + wire [0:29]chany_bottom_out; + wire [0:29]chany_top_in; + wire [0:29]chany_top_out; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire [0:3]mux_right_ipin_0_undriven_sram_inv; + wire [0:3]mux_right_ipin_10_undriven_sram_inv; + wire [0:3]mux_right_ipin_11_undriven_sram_inv; + wire [0:3]mux_right_ipin_12_undriven_sram_inv; + wire [0:3]mux_right_ipin_13_undriven_sram_inv; + wire [0:3]mux_right_ipin_14_undriven_sram_inv; + wire [0:3]mux_right_ipin_15_undriven_sram_inv; + wire [0:3]mux_right_ipin_1_undriven_sram_inv; + wire [0:3]mux_right_ipin_2_undriven_sram_inv; + wire [0:3]mux_right_ipin_3_undriven_sram_inv; + wire [0:3]mux_right_ipin_4_undriven_sram_inv; + wire [0:3]mux_right_ipin_5_undriven_sram_inv; + wire [0:3]mux_right_ipin_6_undriven_sram_inv; + wire [0:3]mux_right_ipin_7_undriven_sram_inv; + wire [0:3]mux_right_ipin_8_undriven_sram_inv; + wire [0:3]mux_right_ipin_9_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire [0:3]mux_tree_tapbuf_size10_1_sram; + wire [0:3]mux_tree_tapbuf_size10_2_sram; + wire [0:3]mux_tree_tapbuf_size10_3_sram; + wire [0:3]mux_tree_tapbuf_size10_4_sram; + wire [0:3]mux_tree_tapbuf_size10_5_sram; + wire [0:3]mux_tree_tapbuf_size10_6_sram; + wire [0:3]mux_tree_tapbuf_size10_7_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire [0:3]mux_tree_tapbuf_size12_4_sram; + wire [0:3]mux_tree_tapbuf_size12_5_sram; + wire [0:3]mux_tree_tapbuf_size12_6_sram; + wire [0:3]mux_tree_tapbuf_size12_7_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire mux_tree_tapbuf_size12_mem_7_ccff_tail; + wire pReset; + wire prog_clk; + +assign chany_top_out[0] = chany_bottom_in[0]; +assign chany_top_out[1] = chany_bottom_in[1]; +assign chany_top_out[10] = chany_bottom_in[10]; +assign chany_top_out[11] = chany_bottom_in[11]; +assign chany_top_out[12] = chany_bottom_in[12]; +assign chany_top_out[13] = chany_bottom_in[13]; +assign chany_top_out[14] = chany_bottom_in[14]; +assign chany_top_out[15] = chany_bottom_in[15]; +assign chany_top_out[16] = chany_bottom_in[16]; +assign chany_top_out[17] = chany_bottom_in[17]; +assign chany_top_out[18] = chany_bottom_in[18]; +assign chany_top_out[19] = chany_bottom_in[19]; +assign chany_top_out[2] = chany_bottom_in[2]; +assign chany_top_out[20] = chany_bottom_in[20]; +assign chany_top_out[21] = chany_bottom_in[21]; +assign chany_top_out[22] = chany_bottom_in[22]; +assign chany_top_out[23] = chany_bottom_in[23]; +assign chany_top_out[24] = chany_bottom_in[24]; +assign chany_top_out[25] = chany_bottom_in[25]; +assign chany_top_out[26] = chany_bottom_in[26]; +assign chany_top_out[27] = chany_bottom_in[27]; +assign chany_top_out[28] = chany_bottom_in[28]; +assign chany_top_out[29] = chany_bottom_in[29]; +assign chany_top_out[3] = chany_bottom_in[3]; +assign chany_bottom_out[0] = chany_top_in[0]; +assign chany_bottom_out[1] = chany_top_in[1]; +assign chany_bottom_out[2] = chany_top_in[2]; +assign chany_bottom_out[3] = chany_top_in[3]; +assign chany_bottom_out[4] = chany_top_in[4]; +assign chany_bottom_out[5] = chany_top_in[5]; +assign chany_bottom_out[6] = chany_top_in[6]; +assign chany_bottom_out[7] = chany_top_in[7]; +assign chany_bottom_out[8] = chany_top_in[8]; +assign chany_bottom_out[9] = chany_top_in[9]; +assign chany_top_out[4] = chany_bottom_in[4]; +assign chany_bottom_out[10] = chany_top_in[10]; +assign chany_bottom_out[11] = chany_top_in[11]; +assign chany_bottom_out[12] = chany_top_in[12]; +assign chany_bottom_out[13] = chany_top_in[13]; +assign chany_bottom_out[14] = chany_top_in[14]; +assign chany_bottom_out[15] = chany_top_in[15]; +assign chany_bottom_out[16] = chany_top_in[16]; +assign chany_bottom_out[17] = chany_top_in[17]; +assign chany_bottom_out[18] = chany_top_in[18]; +assign chany_bottom_out[19] = chany_top_in[19]; +assign chany_top_out[5] = chany_bottom_in[5]; +assign chany_bottom_out[20] = chany_top_in[20]; +assign chany_bottom_out[21] = chany_top_in[21]; +assign chany_bottom_out[22] = chany_top_in[22]; +assign chany_bottom_out[23] = chany_top_in[23]; +assign chany_bottom_out[24] = chany_top_in[24]; +assign chany_bottom_out[25] = chany_top_in[25]; +assign chany_bottom_out[26] = chany_top_in[26]; +assign chany_bottom_out[27] = chany_top_in[27]; +assign chany_bottom_out[28] = chany_top_in[28]; +assign chany_bottom_out[29] = chany_top_in[29]; +assign chany_top_out[6] = chany_bottom_in[6]; +assign chany_top_out[7] = chany_bottom_in[7]; +assign chany_top_out[8] = chany_bottom_in[8]; +assign chany_top_out[9] = chany_bottom_in[9]; + mux_tree_tapbuf_size12_mem mem_right_ipin_0 + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_1 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_10 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_11 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_12 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_13 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_14 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_15 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_2 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_3 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_4 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_5 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_6 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_7 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_8 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_9 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram) + ); + mux_tree_tapbuf_size12 mux_right_ipin_0 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_right_ipin_0_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_1 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_right_ipin_1_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_10 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_5_sram), + .sram_inv(mux_right_ipin_10_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_11 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size10_5_sram), + .sram_inv(mux_right_ipin_11_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_12 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_6_sram), + .sram_inv(mux_right_ipin_12_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_13 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size10_6_sram), + .sram_inv(mux_right_ipin_13_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_14 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_7_sram), + .sram_inv(mux_right_ipin_14_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_15 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21]}), + .sram(mux_tree_tapbuf_size10_7_sram), + .sram_inv(mux_right_ipin_15_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_2 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_right_ipin_2_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_3 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[27], chany_top_in[27]}), + .sram(mux_tree_tapbuf_size10_1_sram), + .sram_inv(mux_right_ipin_3_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_4 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_right_ipin_4_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_5 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[29], chany_top_in[29]}), + .sram(mux_tree_tapbuf_size10_2_sram), + .sram_inv(mux_right_ipin_5_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_6 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_right_ipin_6_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_7 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[22], chany_top_in[22]}), + .sram(mux_tree_tapbuf_size10_3_sram), + .sram_inv(mux_right_ipin_7_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_8 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_4_sram), + .sram_inv(mux_right_ipin_8_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_9 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size10_4_sram), + .sram_inv(mux_right_ipin_9_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1_.v new file mode 100644 index 0000000..37055fd --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1_.v @@ -0,0 +1,166 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cby_8__1_ +( + IO_ISOL_N, + ccff_head, + ccff_head_0, + chany_bottom_in, + chany_top_in, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + pReset, + prog_clk, + ccff_tail, + ccff_tail_0, + chany_bottom_out, + chany_top_out, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + left_grid_right_width_0_height_0_subtile_0__pin_I4_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_, + left_width_0_height_0_subtile_0__pin_inpad_0_, + left_width_0_height_0_subtile_1__pin_inpad_0_, + left_width_0_height_0_subtile_2__pin_inpad_0_, + left_width_0_height_0_subtile_3__pin_inpad_0_ +); + + input IO_ISOL_N; + input ccff_head; + input ccff_head_0; + input [29:0]chany_bottom_in; + input [29:0]chany_top_in; + input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input pReset; + input prog_clk; + output ccff_tail; + output ccff_tail_0; + output [29:0]chany_bottom_out; + output [29:0]chany_top_out; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + output left_width_0_height_0_subtile_0__pin_inpad_0_; + output left_width_0_height_0_subtile_1__pin_inpad_0_; + output left_width_0_height_0_subtile_2__pin_inpad_0_; + output left_width_0_height_0_subtile_3__pin_inpad_0_; + + wire IO_ISOL_N; + wire ccff_head; + wire ccff_head_0; + wire ccff_tail; + wire ccff_tail_0; + wire [29:0]chany_bottom_in; + wire [29:0]chany_bottom_out; + wire [29:0]chany_top_in; + wire [29:0]chany_top_out; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire left_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_width_0_height_0_subtile_3__pin_inpad_0_; + wire pReset; + wire prog_clk; + wire right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + + cby_8__1__old cby_8__8_ + ( + .ccff_head(ccff_head_0), + .chany_bottom_in(chany_bottom_in), + .chany_top_in(chany_top_in), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail_0), + .chany_bottom_out(chany_bottom_out), + .chany_top_out(chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_) + ); + grid_io_right_right grid_io_right_right_9__8_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(ccff_head), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .left_width_0_height_0_subtile_0__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), + .left_width_0_height_0_subtile_0__pin_inpad_0_(left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(left_width_0_height_0_subtile_3__pin_inpad_0_) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1__old.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1__old.v new file mode 100644 index 0000000..0b60510 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1__old.v @@ -0,0 +1,513 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cby_8__1__old +( + ccff_head, + chany_bottom_in, + chany_top_in, + pReset, + prog_clk, + ccff_tail, + chany_bottom_out, + chany_top_out, + left_grid_right_width_0_height_0_subtile_0__pin_I4_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_, + right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_ +); + + input ccff_head; + input [0:29]chany_bottom_in; + input [0:29]chany_top_in; + input pReset; + input prog_clk; + output ccff_tail; + output [0:29]chany_bottom_out; + output [0:29]chany_top_out; + output left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + output right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + output right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + output right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + output right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + + wire ccff_head; + wire ccff_tail; + wire [0:29]chany_bottom_in; + wire [0:29]chany_bottom_out; + wire [0:29]chany_top_in; + wire [0:29]chany_top_out; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire [0:3]mux_left_ipin_0_undriven_sram_inv; + wire [0:3]mux_left_ipin_1_undriven_sram_inv; + wire [0:3]mux_left_ipin_2_undriven_sram_inv; + wire [0:3]mux_left_ipin_3_undriven_sram_inv; + wire [0:3]mux_right_ipin_0_undriven_sram_inv; + wire [0:3]mux_right_ipin_10_undriven_sram_inv; + wire [0:3]mux_right_ipin_11_undriven_sram_inv; + wire [0:3]mux_right_ipin_12_undriven_sram_inv; + wire [0:3]mux_right_ipin_13_undriven_sram_inv; + wire [0:3]mux_right_ipin_14_undriven_sram_inv; + wire [0:3]mux_right_ipin_15_undriven_sram_inv; + wire [0:3]mux_right_ipin_1_undriven_sram_inv; + wire [0:3]mux_right_ipin_2_undriven_sram_inv; + wire [0:3]mux_right_ipin_3_undriven_sram_inv; + wire [0:3]mux_right_ipin_4_undriven_sram_inv; + wire [0:3]mux_right_ipin_5_undriven_sram_inv; + wire [0:3]mux_right_ipin_6_undriven_sram_inv; + wire [0:3]mux_right_ipin_7_undriven_sram_inv; + wire [0:3]mux_right_ipin_8_undriven_sram_inv; + wire [0:3]mux_right_ipin_9_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire [0:3]mux_tree_tapbuf_size10_1_sram; + wire [0:3]mux_tree_tapbuf_size10_2_sram; + wire [0:3]mux_tree_tapbuf_size10_3_sram; + wire [0:3]mux_tree_tapbuf_size10_4_sram; + wire [0:3]mux_tree_tapbuf_size10_5_sram; + wire [0:3]mux_tree_tapbuf_size10_6_sram; + wire [0:3]mux_tree_tapbuf_size10_7_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_10_sram; + wire [0:3]mux_tree_tapbuf_size12_11_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire [0:3]mux_tree_tapbuf_size12_4_sram; + wire [0:3]mux_tree_tapbuf_size12_5_sram; + wire [0:3]mux_tree_tapbuf_size12_6_sram; + wire [0:3]mux_tree_tapbuf_size12_7_sram; + wire [0:3]mux_tree_tapbuf_size12_8_sram; + wire [0:3]mux_tree_tapbuf_size12_9_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_10_ccff_tail; + wire mux_tree_tapbuf_size12_mem_11_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire mux_tree_tapbuf_size12_mem_7_ccff_tail; + wire mux_tree_tapbuf_size12_mem_8_ccff_tail; + wire mux_tree_tapbuf_size12_mem_9_ccff_tail; + wire pReset; + wire prog_clk; + wire right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + +assign chany_top_out[0] = chany_bottom_in[0]; +assign chany_top_out[1] = chany_bottom_in[1]; +assign chany_top_out[10] = chany_bottom_in[10]; +assign chany_top_out[11] = chany_bottom_in[11]; +assign chany_top_out[12] = chany_bottom_in[12]; +assign chany_top_out[13] = chany_bottom_in[13]; +assign chany_top_out[14] = chany_bottom_in[14]; +assign chany_top_out[15] = chany_bottom_in[15]; +assign chany_top_out[16] = chany_bottom_in[16]; +assign chany_top_out[17] = chany_bottom_in[17]; +assign chany_top_out[18] = chany_bottom_in[18]; +assign chany_top_out[19] = chany_bottom_in[19]; +assign chany_top_out[2] = chany_bottom_in[2]; +assign chany_top_out[20] = chany_bottom_in[20]; +assign chany_top_out[21] = chany_bottom_in[21]; +assign chany_top_out[22] = chany_bottom_in[22]; +assign chany_top_out[23] = chany_bottom_in[23]; +assign chany_top_out[24] = chany_bottom_in[24]; +assign chany_top_out[25] = chany_bottom_in[25]; +assign chany_top_out[26] = chany_bottom_in[26]; +assign chany_top_out[27] = chany_bottom_in[27]; +assign chany_top_out[28] = chany_bottom_in[28]; +assign chany_top_out[29] = chany_bottom_in[29]; +assign chany_top_out[3] = chany_bottom_in[3]; +assign chany_bottom_out[0] = chany_top_in[0]; +assign chany_bottom_out[1] = chany_top_in[1]; +assign chany_bottom_out[2] = chany_top_in[2]; +assign chany_bottom_out[3] = chany_top_in[3]; +assign chany_bottom_out[4] = chany_top_in[4]; +assign chany_bottom_out[5] = chany_top_in[5]; +assign chany_bottom_out[6] = chany_top_in[6]; +assign chany_bottom_out[7] = chany_top_in[7]; +assign chany_bottom_out[8] = chany_top_in[8]; +assign chany_bottom_out[9] = chany_top_in[9]; +assign chany_top_out[4] = chany_bottom_in[4]; +assign chany_bottom_out[10] = chany_top_in[10]; +assign chany_bottom_out[11] = chany_top_in[11]; +assign chany_bottom_out[12] = chany_top_in[12]; +assign chany_bottom_out[13] = chany_top_in[13]; +assign chany_bottom_out[14] = chany_top_in[14]; +assign chany_bottom_out[15] = chany_top_in[15]; +assign chany_bottom_out[16] = chany_top_in[16]; +assign chany_bottom_out[17] = chany_top_in[17]; +assign chany_bottom_out[18] = chany_top_in[18]; +assign chany_bottom_out[19] = chany_top_in[19]; +assign chany_top_out[5] = chany_bottom_in[5]; +assign chany_bottom_out[20] = chany_top_in[20]; +assign chany_bottom_out[21] = chany_top_in[21]; +assign chany_bottom_out[22] = chany_top_in[22]; +assign chany_bottom_out[23] = chany_top_in[23]; +assign chany_bottom_out[24] = chany_top_in[24]; +assign chany_bottom_out[25] = chany_top_in[25]; +assign chany_bottom_out[26] = chany_top_in[26]; +assign chany_bottom_out[27] = chany_top_in[27]; +assign chany_bottom_out[28] = chany_top_in[28]; +assign chany_bottom_out[29] = chany_top_in[29]; +assign chany_top_out[6] = chany_bottom_in[6]; +assign chany_top_out[7] = chany_bottom_in[7]; +assign chany_top_out[8] = chany_bottom_in[8]; +assign chany_top_out[9] = chany_bottom_in[9]; + mux_tree_tapbuf_size12_mem mem_left_ipin_0 + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_left_ipin_1 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_left_ipin_2 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_left_ipin_3 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_0 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_1 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_10 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_9_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_11 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_12 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_10_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_13 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_14 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_11_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_15 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_2 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_3 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_4 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_5 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_6 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_7 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_8 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_8_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_9 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram) + ); + mux_tree_tapbuf_size12 mux_left_ipin_0 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_left_ipin_0_undriven_sram_inv), + .out(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_left_ipin_1 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_left_ipin_1_undriven_sram_inv), + .out(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_left_ipin_2 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_left_ipin_2_undriven_sram_inv), + .out(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_left_ipin_3 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21], chany_bottom_in[27], chany_top_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_left_ipin_3_undriven_sram_inv), + .out(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_0 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_4_sram), + .sram_inv(mux_right_ipin_0_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_1 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[29], chany_top_in[29]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_right_ipin_1_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_10 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_9_sram), + .sram_inv(mux_right_ipin_10_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_11 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21]}), + .sram(mux_tree_tapbuf_size10_5_sram), + .sram_inv(mux_right_ipin_11_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_12 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_10_sram), + .sram_inv(mux_right_ipin_12_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_13 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[23], chany_top_in[23]}), + .sram(mux_tree_tapbuf_size10_6_sram), + .sram_inv(mux_right_ipin_13_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_14 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_11_sram), + .sram_inv(mux_right_ipin_14_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_15 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size10_7_sram), + .sram_inv(mux_right_ipin_15_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_2 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_5_sram), + .sram_inv(mux_right_ipin_2_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_3 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[22], chany_top_in[22]}), + .sram(mux_tree_tapbuf_size10_1_sram), + .sram_inv(mux_right_ipin_3_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_4 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_6_sram), + .sram_inv(mux_right_ipin_4_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_5 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size10_2_sram), + .sram_inv(mux_right_ipin_5_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_6 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_7_sram), + .sram_inv(mux_right_ipin_6_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_7 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size10_3_sram), + .sram_inv(mux_right_ipin_7_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_8 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_8_sram), + .sram_inv(mux_right_ipin_8_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_9 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size10_4_sram), + .sram_inv(mux_right_ipin_9_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/const0.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/const0.v new file mode 100644 index 0000000..539502b --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/const0.v @@ -0,0 +1,15 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module const0 +( + const0 +); + + output const0; + + wire \ ; + wire const0; + +assign const0 = \ ; +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/const1.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/const1.v new file mode 100644 index 0000000..515120a --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/const1.v @@ -0,0 +1,15 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module const1 +( + const1 +); + + output const1; + + wire \ ; + wire const1; + +assign const1 = \ ; +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/direct_interc.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/direct_interc.v new file mode 100644 index 0000000..304b7eb --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/direct_interc.v @@ -0,0 +1,17 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module direct_interc +( + in, + out +); + + input in; + output out; + + wire in; + wire out; + +assign out = in; +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4.v new file mode 100644 index 0000000..152e440 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4.v @@ -0,0 +1,98 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module frac_lut4 +( + in, + mode, + mode_inv, + sram, + sram_inv, + lut2_out, + lut3_out, + lut4_out +); + + input [0:3]in; + input mode; + input mode_inv; + input [0:15]sram; + input [0:15]sram_inv; + output [0:1]lut2_out; + output [0:1]lut3_out; + output lut4_out; + + wire [0:3]in; + wire [0:1]lut2_out; + wire [0:1]lut3_out; + wire lut4_out; + wire mode; + wire mode_inv; + wire sky130_fd_sc_hd__buf_2_0_X; + wire sky130_fd_sc_hd__buf_2_1_X; + wire sky130_fd_sc_hd__buf_2_2_X; + wire sky130_fd_sc_hd__buf_2_3_X; + wire sky130_fd_sc_hd__inv_1_0_Y; + wire sky130_fd_sc_hd__inv_1_1_Y; + wire sky130_fd_sc_hd__inv_1_2_Y; + wire sky130_fd_sc_hd__inv_1_3_Y; + wire sky130_fd_sc_hd__or2_1_0_X; + wire [0:15]sram; + wire [0:15]sram_inv; + + frac_lut4_mux frac_lut4_mux_0_ + ( + .in(sram), + .sram({sky130_fd_sc_hd__buf_2_0_X, sky130_fd_sc_hd__buf_2_1_X, sky130_fd_sc_hd__buf_2_2_X, sky130_fd_sc_hd__buf_2_3_X}), + .sram_inv({sky130_fd_sc_hd__inv_1_0_Y, sky130_fd_sc_hd__inv_1_1_Y, sky130_fd_sc_hd__inv_1_2_Y, sky130_fd_sc_hd__inv_1_3_Y}), + .lut2_out(lut2_out), + .lut3_out(lut3_out), + .lut4_out(lut4_out) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ + ( + .A(in[0]), + .X(sky130_fd_sc_hd__buf_2_0_X) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ + ( + .A(in[1]), + .X(sky130_fd_sc_hd__buf_2_1_X) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ + ( + .A(in[2]), + .X(sky130_fd_sc_hd__buf_2_2_X) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ + ( + .A(sky130_fd_sc_hd__or2_1_0_X), + .X(sky130_fd_sc_hd__buf_2_3_X) + ); + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ + ( + .A(in[0]), + .Y(sky130_fd_sc_hd__inv_1_0_Y) + ); + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ + ( + .A(in[1]), + .Y(sky130_fd_sc_hd__inv_1_1_Y) + ); + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ + ( + .A(in[2]), + .Y(sky130_fd_sc_hd__inv_1_2_Y) + ); + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ + ( + .A(sky130_fd_sc_hd__or2_1_0_X), + .Y(sky130_fd_sc_hd__inv_1_3_Y) + ); + sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_ + ( + .A(mode), + .B(in[3]), + .X(sky130_fd_sc_hd__or2_1_0_X) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4_mux.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4_mux.v new file mode 100644 index 0000000..971a3c8 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4_mux.v @@ -0,0 +1,185 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module frac_lut4_mux +( + in, + sram, + sram_inv, + lut2_out, + lut3_out, + lut4_out +); + + input [0:15]in; + input [0:3]sram; + input [0:3]sram_inv; + output [0:1]lut2_out; + output [0:1]lut3_out; + output lut4_out; + + wire [0:15]in; + wire [0:1]lut2_out; + wire [0:1]lut3_out; + wire lut4_out; + wire sky130_fd_sc_hd__buf_2_5_X; + wire sky130_fd_sc_hd__buf_2_6_X; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_10_X; + wire sky130_fd_sc_hd__mux2_1_11_X; + wire sky130_fd_sc_hd__mux2_1_12_X; + wire sky130_fd_sc_hd__mux2_1_13_X; + wire sky130_fd_sc_hd__mux2_1_14_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire sky130_fd_sc_hd__mux2_1_8_X; + wire sky130_fd_sc_hd__mux2_1_9_X; + wire [0:3]sram; + wire [0:3]sram_inv; + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A0(in[1]), + .A1(in[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A0(in[3]), + .A1(in[2]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A0(in[5]), + .A1(in[4]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ + ( + .A0(in[7]), + .A1(in[6]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ + ( + .A0(in[9]), + .A1(in[8]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ + ( + .A0(in[11]), + .A1(in[10]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ + ( + .A0(in[13]), + .A1(in[12]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ + ( + .A0(in[15]), + .A1(in[14]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_8_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_9_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A0(sky130_fd_sc_hd__mux2_1_5_X), + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_10_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A0(sky130_fd_sc_hd__mux2_1_7_X), + .A1(sky130_fd_sc_hd__mux2_1_6_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_11_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A0(sky130_fd_sc_hd__buf_2_6_X), + .A1(sky130_fd_sc_hd__buf_2_5_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_12_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A0(sky130_fd_sc_hd__mux2_1_11_X), + .A1(sky130_fd_sc_hd__mux2_1_10_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_13_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_13_X), + .A1(sky130_fd_sc_hd__mux2_1_12_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_14_X) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_10_X), + .X(lut2_out[0]) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ + ( + .A(sky130_fd_sc_hd__mux2_1_11_X), + .X(lut2_out[1]) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ + ( + .A(sky130_fd_sc_hd__mux2_1_12_X), + .X(lut3_out[0]) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ + ( + .A(sky130_fd_sc_hd__mux2_1_13_X), + .X(lut3_out[1]) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ + ( + .A(sky130_fd_sc_hd__mux2_1_14_X), + .X(lut4_out) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ + ( + .A(sky130_fd_sc_hd__mux2_1_8_X), + .X(sky130_fd_sc_hd__buf_2_5_X) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ + ( + .A(sky130_fd_sc_hd__mux2_1_9_X), + .X(sky130_fd_sc_hd__buf_2_6_X) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.v new file mode 100644 index 0000000..f971dfb --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.v @@ -0,0 +1,145 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem +( + ccff_head, + pReset, + prog_clk, + ccff_tail, + mem_out +); + + input ccff_head; + input pReset; + input prog_clk; + output ccff_tail; + output [0:16]mem_out; + + wire ccff_head; + wire ccff_tail; + wire [0:16]mem_out; + wire pReset; + wire prog_clk; + +assign ccff_tail = mem_out[16]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .CLK(prog_clk), + .D(ccff_head), + .RESET_B(pReset), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ + ( + .CLK(prog_clk), + .D(mem_out[9]), + .RESET_B(pReset), + .Q(mem_out[10]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ + ( + .CLK(prog_clk), + .D(mem_out[10]), + .RESET_B(pReset), + .Q(mem_out[11]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ + ( + .CLK(prog_clk), + .D(mem_out[11]), + .RESET_B(pReset), + .Q(mem_out[12]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ + ( + .CLK(prog_clk), + .D(mem_out[12]), + .RESET_B(pReset), + .Q(mem_out[13]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ + ( + .CLK(prog_clk), + .D(mem_out[13]), + .RESET_B(pReset), + .Q(mem_out[14]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ + ( + .CLK(prog_clk), + .D(mem_out[14]), + .RESET_B(pReset), + .Q(mem_out[15]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ + ( + .CLK(prog_clk), + .D(mem_out[15]), + .RESET_B(pReset), + .Q(mem_out[16]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .CLK(prog_clk), + .D(mem_out[0]), + .RESET_B(pReset), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .CLK(prog_clk), + .D(mem_out[1]), + .RESET_B(pReset), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .CLK(prog_clk), + .D(mem_out[2]), + .RESET_B(pReset), + .Q(mem_out[3]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ + ( + .CLK(prog_clk), + .D(mem_out[3]), + .RESET_B(pReset), + .Q(mem_out[4]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ + ( + .CLK(prog_clk), + .D(mem_out[4]), + .RESET_B(pReset), + .Q(mem_out[5]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ + ( + .CLK(prog_clk), + .D(mem_out[5]), + .RESET_B(pReset), + .Q(mem_out[6]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ + ( + .CLK(prog_clk), + .D(mem_out[6]), + .RESET_B(pReset), + .Q(mem_out[7]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ + ( + .CLK(prog_clk), + .D(mem_out[7]), + .RESET_B(pReset), + .Q(mem_out[8]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ + ( + .CLK(prog_clk), + .D(mem_out[8]), + .RESET_B(pReset), + .Q(mem_out[9]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_clb.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_clb.v new file mode 100644 index 0000000..07ea2e7 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_clb.v @@ -0,0 +1,226 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module grid_clb +( + Test_en, + ccff_head, + left_width_0_height_0_subtile_0__pin_clk_0_, + left_width_0_height_0_subtile_0__pin_reset_0_, + pReset, + prog_clk, + right_width_0_height_0_subtile_0__pin_I4_0_, + right_width_0_height_0_subtile_0__pin_I4_1_, + right_width_0_height_0_subtile_0__pin_I4i_0_, + right_width_0_height_0_subtile_0__pin_I4i_1_, + right_width_0_height_0_subtile_0__pin_I5_0_, + right_width_0_height_0_subtile_0__pin_I5_1_, + right_width_0_height_0_subtile_0__pin_I5i_0_, + right_width_0_height_0_subtile_0__pin_I5i_1_, + right_width_0_height_0_subtile_0__pin_I6_0_, + right_width_0_height_0_subtile_0__pin_I6_1_, + right_width_0_height_0_subtile_0__pin_I6i_0_, + right_width_0_height_0_subtile_0__pin_I6i_1_, + right_width_0_height_0_subtile_0__pin_I7_0_, + right_width_0_height_0_subtile_0__pin_I7_1_, + right_width_0_height_0_subtile_0__pin_I7i_0_, + right_width_0_height_0_subtile_0__pin_I7i_1_, + top_width_0_height_0_subtile_0__pin_I0_0_, + top_width_0_height_0_subtile_0__pin_I0_1_, + top_width_0_height_0_subtile_0__pin_I0i_0_, + top_width_0_height_0_subtile_0__pin_I0i_1_, + top_width_0_height_0_subtile_0__pin_I1_0_, + top_width_0_height_0_subtile_0__pin_I1_1_, + top_width_0_height_0_subtile_0__pin_I1i_0_, + top_width_0_height_0_subtile_0__pin_I1i_1_, + top_width_0_height_0_subtile_0__pin_I2_0_, + top_width_0_height_0_subtile_0__pin_I2_1_, + top_width_0_height_0_subtile_0__pin_I2i_0_, + top_width_0_height_0_subtile_0__pin_I2i_1_, + top_width_0_height_0_subtile_0__pin_I3_0_, + top_width_0_height_0_subtile_0__pin_I3_1_, + top_width_0_height_0_subtile_0__pin_I3i_0_, + top_width_0_height_0_subtile_0__pin_I3i_1_, + top_width_0_height_0_subtile_0__pin_cin_0_, + top_width_0_height_0_subtile_0__pin_reg_in_0_, + top_width_0_height_0_subtile_0__pin_sc_in_0_, + bottom_width_0_height_0_subtile_0__pin_cout_0_, + bottom_width_0_height_0_subtile_0__pin_reg_out_0_, + bottom_width_0_height_0_subtile_0__pin_sc_out_0_, + ccff_tail, + right_width_0_height_0_subtile_0__pin_O_10_, + right_width_0_height_0_subtile_0__pin_O_11_, + right_width_0_height_0_subtile_0__pin_O_12_, + right_width_0_height_0_subtile_0__pin_O_13_, + right_width_0_height_0_subtile_0__pin_O_14_, + right_width_0_height_0_subtile_0__pin_O_15_, + right_width_0_height_0_subtile_0__pin_O_8_, + right_width_0_height_0_subtile_0__pin_O_9_, + top_width_0_height_0_subtile_0__pin_O_0_, + top_width_0_height_0_subtile_0__pin_O_1_, + top_width_0_height_0_subtile_0__pin_O_2_, + top_width_0_height_0_subtile_0__pin_O_3_, + top_width_0_height_0_subtile_0__pin_O_4_, + top_width_0_height_0_subtile_0__pin_O_5_, + top_width_0_height_0_subtile_0__pin_O_6_, + top_width_0_height_0_subtile_0__pin_O_7_ +); + + input Test_en; + input ccff_head; + input left_width_0_height_0_subtile_0__pin_clk_0_; + input left_width_0_height_0_subtile_0__pin_reset_0_; + input pReset; + input prog_clk; + input right_width_0_height_0_subtile_0__pin_I4_0_; + input right_width_0_height_0_subtile_0__pin_I4_1_; + input right_width_0_height_0_subtile_0__pin_I4i_0_; + input right_width_0_height_0_subtile_0__pin_I4i_1_; + input right_width_0_height_0_subtile_0__pin_I5_0_; + input right_width_0_height_0_subtile_0__pin_I5_1_; + input right_width_0_height_0_subtile_0__pin_I5i_0_; + input right_width_0_height_0_subtile_0__pin_I5i_1_; + input right_width_0_height_0_subtile_0__pin_I6_0_; + input right_width_0_height_0_subtile_0__pin_I6_1_; + input right_width_0_height_0_subtile_0__pin_I6i_0_; + input right_width_0_height_0_subtile_0__pin_I6i_1_; + input right_width_0_height_0_subtile_0__pin_I7_0_; + input right_width_0_height_0_subtile_0__pin_I7_1_; + input right_width_0_height_0_subtile_0__pin_I7i_0_; + input right_width_0_height_0_subtile_0__pin_I7i_1_; + input top_width_0_height_0_subtile_0__pin_I0_0_; + input top_width_0_height_0_subtile_0__pin_I0_1_; + input top_width_0_height_0_subtile_0__pin_I0i_0_; + input top_width_0_height_0_subtile_0__pin_I0i_1_; + input top_width_0_height_0_subtile_0__pin_I1_0_; + input top_width_0_height_0_subtile_0__pin_I1_1_; + input top_width_0_height_0_subtile_0__pin_I1i_0_; + input top_width_0_height_0_subtile_0__pin_I1i_1_; + input top_width_0_height_0_subtile_0__pin_I2_0_; + input top_width_0_height_0_subtile_0__pin_I2_1_; + input top_width_0_height_0_subtile_0__pin_I2i_0_; + input top_width_0_height_0_subtile_0__pin_I2i_1_; + input top_width_0_height_0_subtile_0__pin_I3_0_; + input top_width_0_height_0_subtile_0__pin_I3_1_; + input top_width_0_height_0_subtile_0__pin_I3i_0_; + input top_width_0_height_0_subtile_0__pin_I3i_1_; + input top_width_0_height_0_subtile_0__pin_cin_0_; + input top_width_0_height_0_subtile_0__pin_reg_in_0_; + input top_width_0_height_0_subtile_0__pin_sc_in_0_; + output bottom_width_0_height_0_subtile_0__pin_cout_0_; + output bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + output bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + output ccff_tail; + output right_width_0_height_0_subtile_0__pin_O_10_; + output right_width_0_height_0_subtile_0__pin_O_11_; + output right_width_0_height_0_subtile_0__pin_O_12_; + output right_width_0_height_0_subtile_0__pin_O_13_; + output right_width_0_height_0_subtile_0__pin_O_14_; + output right_width_0_height_0_subtile_0__pin_O_15_; + output right_width_0_height_0_subtile_0__pin_O_8_; + output right_width_0_height_0_subtile_0__pin_O_9_; + output top_width_0_height_0_subtile_0__pin_O_0_; + output top_width_0_height_0_subtile_0__pin_O_1_; + output top_width_0_height_0_subtile_0__pin_O_2_; + output top_width_0_height_0_subtile_0__pin_O_3_; + output top_width_0_height_0_subtile_0__pin_O_4_; + output top_width_0_height_0_subtile_0__pin_O_5_; + output top_width_0_height_0_subtile_0__pin_O_6_; + output top_width_0_height_0_subtile_0__pin_O_7_; + + wire Test_en; + wire bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire ccff_head; + wire ccff_tail; + wire left_width_0_height_0_subtile_0__pin_clk_0_; + wire left_width_0_height_0_subtile_0__pin_reset_0_; + wire pReset; + wire prog_clk; + wire right_width_0_height_0_subtile_0__pin_I4_0_; + wire right_width_0_height_0_subtile_0__pin_I4_1_; + wire right_width_0_height_0_subtile_0__pin_I4i_0_; + wire right_width_0_height_0_subtile_0__pin_I4i_1_; + wire right_width_0_height_0_subtile_0__pin_I5_0_; + wire right_width_0_height_0_subtile_0__pin_I5_1_; + wire right_width_0_height_0_subtile_0__pin_I5i_0_; + wire right_width_0_height_0_subtile_0__pin_I5i_1_; + wire right_width_0_height_0_subtile_0__pin_I6_0_; + wire right_width_0_height_0_subtile_0__pin_I6_1_; + wire right_width_0_height_0_subtile_0__pin_I6i_0_; + wire right_width_0_height_0_subtile_0__pin_I6i_1_; + wire right_width_0_height_0_subtile_0__pin_I7_0_; + wire right_width_0_height_0_subtile_0__pin_I7_1_; + wire right_width_0_height_0_subtile_0__pin_I7i_0_; + wire right_width_0_height_0_subtile_0__pin_I7i_1_; + wire right_width_0_height_0_subtile_0__pin_O_10_; + wire right_width_0_height_0_subtile_0__pin_O_11_; + wire right_width_0_height_0_subtile_0__pin_O_12_; + wire right_width_0_height_0_subtile_0__pin_O_13_; + wire right_width_0_height_0_subtile_0__pin_O_14_; + wire right_width_0_height_0_subtile_0__pin_O_15_; + wire right_width_0_height_0_subtile_0__pin_O_8_; + wire right_width_0_height_0_subtile_0__pin_O_9_; + wire top_width_0_height_0_subtile_0__pin_I0_0_; + wire top_width_0_height_0_subtile_0__pin_I0_1_; + wire top_width_0_height_0_subtile_0__pin_I0i_0_; + wire top_width_0_height_0_subtile_0__pin_I0i_1_; + wire top_width_0_height_0_subtile_0__pin_I1_0_; + wire top_width_0_height_0_subtile_0__pin_I1_1_; + wire top_width_0_height_0_subtile_0__pin_I1i_0_; + wire top_width_0_height_0_subtile_0__pin_I1i_1_; + wire top_width_0_height_0_subtile_0__pin_I2_0_; + wire top_width_0_height_0_subtile_0__pin_I2_1_; + wire top_width_0_height_0_subtile_0__pin_I2i_0_; + wire top_width_0_height_0_subtile_0__pin_I2i_1_; + wire top_width_0_height_0_subtile_0__pin_I3_0_; + wire top_width_0_height_0_subtile_0__pin_I3_1_; + wire top_width_0_height_0_subtile_0__pin_I3i_0_; + wire top_width_0_height_0_subtile_0__pin_I3i_1_; + wire top_width_0_height_0_subtile_0__pin_O_0_; + wire top_width_0_height_0_subtile_0__pin_O_1_; + wire top_width_0_height_0_subtile_0__pin_O_2_; + wire top_width_0_height_0_subtile_0__pin_O_3_; + wire top_width_0_height_0_subtile_0__pin_O_4_; + wire top_width_0_height_0_subtile_0__pin_O_5_; + wire top_width_0_height_0_subtile_0__pin_O_6_; + wire top_width_0_height_0_subtile_0__pin_O_7_; + wire top_width_0_height_0_subtile_0__pin_cin_0_; + wire top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire top_width_0_height_0_subtile_0__pin_sc_in_0_; + + logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 + ( + .Test_en(Test_en), + .ccff_head(ccff_head), + .clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}), + .clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}), + .clb_I1({top_width_0_height_0_subtile_0__pin_I1_0_, top_width_0_height_0_subtile_0__pin_I1_1_}), + .clb_I1i({top_width_0_height_0_subtile_0__pin_I1i_0_, top_width_0_height_0_subtile_0__pin_I1i_1_}), + .clb_I2({top_width_0_height_0_subtile_0__pin_I2_0_, top_width_0_height_0_subtile_0__pin_I2_1_}), + .clb_I2i({top_width_0_height_0_subtile_0__pin_I2i_0_, top_width_0_height_0_subtile_0__pin_I2i_1_}), + .clb_I3({top_width_0_height_0_subtile_0__pin_I3_0_, top_width_0_height_0_subtile_0__pin_I3_1_}), + .clb_I3i({top_width_0_height_0_subtile_0__pin_I3i_0_, top_width_0_height_0_subtile_0__pin_I3i_1_}), + .clb_I4({right_width_0_height_0_subtile_0__pin_I4_0_, right_width_0_height_0_subtile_0__pin_I4_1_}), + .clb_I4i({right_width_0_height_0_subtile_0__pin_I4i_0_, right_width_0_height_0_subtile_0__pin_I4i_1_}), + .clb_I5({right_width_0_height_0_subtile_0__pin_I5_0_, right_width_0_height_0_subtile_0__pin_I5_1_}), + .clb_I5i({right_width_0_height_0_subtile_0__pin_I5i_0_, right_width_0_height_0_subtile_0__pin_I5i_1_}), + .clb_I6({right_width_0_height_0_subtile_0__pin_I6_0_, right_width_0_height_0_subtile_0__pin_I6_1_}), + .clb_I6i({right_width_0_height_0_subtile_0__pin_I6i_0_, right_width_0_height_0_subtile_0__pin_I6i_1_}), + .clb_I7({right_width_0_height_0_subtile_0__pin_I7_0_, right_width_0_height_0_subtile_0__pin_I7_1_}), + .clb_I7i({right_width_0_height_0_subtile_0__pin_I7i_0_, right_width_0_height_0_subtile_0__pin_I7i_1_}), + .clb_cin(top_width_0_height_0_subtile_0__pin_cin_0_), + .clb_clk(left_width_0_height_0_subtile_0__pin_clk_0_), + .clb_reg_in(top_width_0_height_0_subtile_0__pin_reg_in_0_), + .clb_reset(left_width_0_height_0_subtile_0__pin_reset_0_), + .clb_sc_in(top_width_0_height_0_subtile_0__pin_sc_in_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .clb_O({top_width_0_height_0_subtile_0__pin_O_0_, top_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, top_width_0_height_0_subtile_0__pin_O_3_, top_width_0_height_0_subtile_0__pin_O_4_, top_width_0_height_0_subtile_0__pin_O_5_, top_width_0_height_0_subtile_0__pin_O_6_, top_width_0_height_0_subtile_0__pin_O_7_, right_width_0_height_0_subtile_0__pin_O_8_, right_width_0_height_0_subtile_0__pin_O_9_, right_width_0_height_0_subtile_0__pin_O_10_, right_width_0_height_0_subtile_0__pin_O_11_, right_width_0_height_0_subtile_0__pin_O_12_, right_width_0_height_0_subtile_0__pin_O_13_, right_width_0_height_0_subtile_0__pin_O_14_, right_width_0_height_0_subtile_0__pin_O_15_}), + .clb_cout(bottom_width_0_height_0_subtile_0__pin_cout_0_), + .clb_reg_out(bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .clb_sc_out(bottom_width_0_height_0_subtile_0__pin_sc_out_0_) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_bottom_bottom.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_bottom_bottom.v new file mode 100644 index 0000000..896916d --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_bottom_bottom.v @@ -0,0 +1,113 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module grid_io_bottom_bottom +( + IO_ISOL_N, + ccff_head, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + pReset, + prog_clk, + top_width_0_height_0_subtile_0__pin_outpad_0_, + top_width_0_height_0_subtile_1__pin_outpad_0_, + top_width_0_height_0_subtile_2__pin_outpad_0_, + top_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_tail, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + top_width_0_height_0_subtile_0__pin_inpad_0_, + top_width_0_height_0_subtile_1__pin_inpad_0_, + top_width_0_height_0_subtile_2__pin_inpad_0_, + top_width_0_height_0_subtile_3__pin_inpad_0_ +); + + input IO_ISOL_N; + input ccff_head; + input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input pReset; + input prog_clk; + input top_width_0_height_0_subtile_0__pin_outpad_0_; + input top_width_0_height_0_subtile_1__pin_outpad_0_; + input top_width_0_height_0_subtile_2__pin_outpad_0_; + input top_width_0_height_0_subtile_3__pin_outpad_0_; + output ccff_tail; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output top_width_0_height_0_subtile_0__pin_inpad_0_; + output top_width_0_height_0_subtile_1__pin_inpad_0_; + output top_width_0_height_0_subtile_2__pin_inpad_0_; + output top_width_0_height_0_subtile_3__pin_inpad_0_; + + wire IO_ISOL_N; + wire ccff_head; + wire ccff_tail; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire logical_tile_io_mode_io__0_ccff_tail; + wire logical_tile_io_mode_io__1_ccff_tail; + wire logical_tile_io_mode_io__2_ccff_tail; + wire pReset; + wire prog_clk; + wire top_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_width_0_height_0_subtile_0__pin_outpad_0_; + wire top_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_width_0_height_0_subtile_1__pin_outpad_0_; + wire top_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_width_0_height_0_subtile_2__pin_outpad_0_; + wire top_width_0_height_0_subtile_3__pin_inpad_0_; + wire top_width_0_height_0_subtile_3__pin_outpad_0_; + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(ccff_head), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]), + .io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]), + .io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]), + .io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]), + .io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]), + .io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]), + .io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]), + .io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]), + .io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_left_left.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_left_left.v new file mode 100644 index 0000000..9883717 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_left_left.v @@ -0,0 +1,113 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module grid_io_left_left +( + IO_ISOL_N, + ccff_head, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + pReset, + prog_clk, + right_width_0_height_0_subtile_0__pin_outpad_0_, + right_width_0_height_0_subtile_1__pin_outpad_0_, + right_width_0_height_0_subtile_2__pin_outpad_0_, + right_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_tail, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + right_width_0_height_0_subtile_0__pin_inpad_0_, + right_width_0_height_0_subtile_1__pin_inpad_0_, + right_width_0_height_0_subtile_2__pin_inpad_0_, + right_width_0_height_0_subtile_3__pin_inpad_0_ +); + + input IO_ISOL_N; + input ccff_head; + input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input pReset; + input prog_clk; + input right_width_0_height_0_subtile_0__pin_outpad_0_; + input right_width_0_height_0_subtile_1__pin_outpad_0_; + input right_width_0_height_0_subtile_2__pin_outpad_0_; + input right_width_0_height_0_subtile_3__pin_outpad_0_; + output ccff_tail; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output right_width_0_height_0_subtile_0__pin_inpad_0_; + output right_width_0_height_0_subtile_1__pin_inpad_0_; + output right_width_0_height_0_subtile_2__pin_inpad_0_; + output right_width_0_height_0_subtile_3__pin_inpad_0_; + + wire IO_ISOL_N; + wire ccff_head; + wire ccff_tail; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire logical_tile_io_mode_io__0_ccff_tail; + wire logical_tile_io_mode_io__1_ccff_tail; + wire logical_tile_io_mode_io__2_ccff_tail; + wire pReset; + wire prog_clk; + wire right_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_width_0_height_0_subtile_0__pin_outpad_0_; + wire right_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_width_0_height_0_subtile_1__pin_outpad_0_; + wire right_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_width_0_height_0_subtile_2__pin_outpad_0_; + wire right_width_0_height_0_subtile_3__pin_inpad_0_; + wire right_width_0_height_0_subtile_3__pin_outpad_0_; + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(ccff_head), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]), + .io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]), + .io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]), + .io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]), + .io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]), + .io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]), + .io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]), + .io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]), + .io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_right_right.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_right_right.v new file mode 100644 index 0000000..726a666 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_right_right.v @@ -0,0 +1,113 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module grid_io_right_right +( + IO_ISOL_N, + ccff_head, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + left_width_0_height_0_subtile_0__pin_outpad_0_, + left_width_0_height_0_subtile_1__pin_outpad_0_, + left_width_0_height_0_subtile_2__pin_outpad_0_, + left_width_0_height_0_subtile_3__pin_outpad_0_, + pReset, + prog_clk, + ccff_tail, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + left_width_0_height_0_subtile_0__pin_inpad_0_, + left_width_0_height_0_subtile_1__pin_inpad_0_, + left_width_0_height_0_subtile_2__pin_inpad_0_, + left_width_0_height_0_subtile_3__pin_inpad_0_ +); + + input IO_ISOL_N; + input ccff_head; + input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input left_width_0_height_0_subtile_0__pin_outpad_0_; + input left_width_0_height_0_subtile_1__pin_outpad_0_; + input left_width_0_height_0_subtile_2__pin_outpad_0_; + input left_width_0_height_0_subtile_3__pin_outpad_0_; + input pReset; + input prog_clk; + output ccff_tail; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output left_width_0_height_0_subtile_0__pin_inpad_0_; + output left_width_0_height_0_subtile_1__pin_inpad_0_; + output left_width_0_height_0_subtile_2__pin_inpad_0_; + output left_width_0_height_0_subtile_3__pin_inpad_0_; + + wire IO_ISOL_N; + wire ccff_head; + wire ccff_tail; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire left_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_width_0_height_0_subtile_0__pin_outpad_0_; + wire left_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_width_0_height_0_subtile_1__pin_outpad_0_; + wire left_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_width_0_height_0_subtile_2__pin_outpad_0_; + wire left_width_0_height_0_subtile_3__pin_inpad_0_; + wire left_width_0_height_0_subtile_3__pin_outpad_0_; + wire logical_tile_io_mode_io__0_ccff_tail; + wire logical_tile_io_mode_io__1_ccff_tail; + wire logical_tile_io_mode_io__2_ccff_tail; + wire pReset; + wire prog_clk; + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(ccff_head), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]), + .io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]), + .io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]), + .io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]), + .io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]), + .io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]), + .io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]), + .io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]), + .io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_top_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_top_top.v new file mode 100644 index 0000000..51b2e73 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_top_top.v @@ -0,0 +1,113 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module grid_io_top_top +( + IO_ISOL_N, + bottom_width_0_height_0_subtile_0__pin_outpad_0_, + bottom_width_0_height_0_subtile_1__pin_outpad_0_, + bottom_width_0_height_0_subtile_2__pin_outpad_0_, + bottom_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_head, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + pReset, + prog_clk, + bottom_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT +); + + input IO_ISOL_N; + input bottom_width_0_height_0_subtile_0__pin_outpad_0_; + input bottom_width_0_height_0_subtile_1__pin_outpad_0_; + input bottom_width_0_height_0_subtile_2__pin_outpad_0_; + input bottom_width_0_height_0_subtile_3__pin_outpad_0_; + input ccff_head; + input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input pReset; + input prog_clk; + output bottom_width_0_height_0_subtile_0__pin_inpad_0_; + output bottom_width_0_height_0_subtile_1__pin_inpad_0_; + output bottom_width_0_height_0_subtile_2__pin_inpad_0_; + output bottom_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + + wire IO_ISOL_N; + wire bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_head; + wire ccff_tail; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire logical_tile_io_mode_io__0_ccff_tail; + wire logical_tile_io_mode_io__1_ccff_tail; + wire logical_tile_io_mode_io__2_ccff_tail; + wire pReset; + wire prog_clk; + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(ccff_head), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]), + .io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]), + .io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]), + .io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]), + .io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]), + .io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]), + .io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]), + .io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]), + .io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_clb_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_clb_.v new file mode 100644 index 0000000..3249ee0 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_clb_.v @@ -0,0 +1,810 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_clb_ +( + Test_en, + ccff_head, + clb_I0, + clb_I0i, + clb_I1, + clb_I1i, + clb_I2, + clb_I2i, + clb_I3, + clb_I3i, + clb_I4, + clb_I4i, + clb_I5, + clb_I5i, + clb_I6, + clb_I6i, + clb_I7, + clb_I7i, + clb_cin, + clb_clk, + clb_reg_in, + clb_reset, + clb_sc_in, + pReset, + prog_clk, + ccff_tail, + clb_O, + clb_cout, + clb_reg_out, + clb_sc_out +); + + input Test_en; + input ccff_head; + input [0:1]clb_I0; + input [0:1]clb_I0i; + input [0:1]clb_I1; + input [0:1]clb_I1i; + input [0:1]clb_I2; + input [0:1]clb_I2i; + input [0:1]clb_I3; + input [0:1]clb_I3i; + input [0:1]clb_I4; + input [0:1]clb_I4i; + input [0:1]clb_I5; + input [0:1]clb_I5i; + input [0:1]clb_I6; + input [0:1]clb_I6i; + input [0:1]clb_I7; + input [0:1]clb_I7i; + input clb_cin; + input clb_clk; + input clb_reg_in; + input clb_reset; + input clb_sc_in; + input pReset; + input prog_clk; + output ccff_tail; + output [0:15]clb_O; + output clb_cout; + output clb_reg_out; + output clb_sc_out; + + wire Test_en; + wire ccff_head; + wire ccff_tail; + wire [0:1]clb_I0; + wire [0:1]clb_I0i; + wire [0:1]clb_I1; + wire [0:1]clb_I1i; + wire [0:1]clb_I2; + wire [0:1]clb_I2i; + wire [0:1]clb_I3; + wire [0:1]clb_I3i; + wire [0:1]clb_I4; + wire [0:1]clb_I4i; + wire [0:1]clb_I5; + wire [0:1]clb_I5i; + wire [0:1]clb_I6; + wire [0:1]clb_I6i; + wire [0:1]clb_I7; + wire [0:1]clb_I7i; + wire [0:15]clb_O; + wire clb_cin; + wire clb_clk; + wire clb_cout; + wire clb_reg_in; + wire clb_reg_out; + wire clb_reset; + wire clb_sc_in; + wire clb_sc_out; + wire direct_interc_19_out; + wire direct_interc_20_out; + wire direct_interc_21_out; + wire direct_interc_22_out; + wire direct_interc_23_out; + wire direct_interc_24_out; + wire direct_interc_25_out; + wire direct_interc_26_out; + wire direct_interc_27_out; + wire direct_interc_28_out; + wire direct_interc_29_out; + wire direct_interc_30_out; + wire direct_interc_31_out; + wire direct_interc_32_out; + wire direct_interc_33_out; + wire direct_interc_34_out; + wire direct_interc_35_out; + wire direct_interc_36_out; + wire direct_interc_37_out; + wire direct_interc_38_out; + wire direct_interc_39_out; + wire direct_interc_40_out; + wire direct_interc_41_out; + wire direct_interc_42_out; + wire direct_interc_43_out; + wire direct_interc_44_out; + wire direct_interc_45_out; + wire direct_interc_46_out; + wire direct_interc_47_out; + wire direct_interc_48_out; + wire direct_interc_49_out; + wire direct_interc_50_out; + wire direct_interc_51_out; + wire direct_interc_52_out; + wire direct_interc_53_out; + wire direct_interc_54_out; + wire direct_interc_55_out; + wire direct_interc_56_out; + wire direct_interc_57_out; + wire direct_interc_58_out; + wire direct_interc_59_out; + wire direct_interc_60_out; + wire direct_interc_61_out; + wire direct_interc_62_out; + wire direct_interc_63_out; + wire direct_interc_64_out; + wire direct_interc_65_out; + wire direct_interc_66_out; + wire direct_interc_67_out; + wire direct_interc_68_out; + wire direct_interc_69_out; + wire direct_interc_70_out; + wire direct_interc_71_out; + wire direct_interc_72_out; + wire direct_interc_73_out; + wire direct_interc_74_out; + wire direct_interc_75_out; + wire direct_interc_76_out; + wire direct_interc_77_out; + wire direct_interc_78_out; + wire direct_interc_79_out; + wire direct_interc_80_out; + wire direct_interc_81_out; + wire direct_interc_82_out; + wire direct_interc_83_out; + wire direct_interc_84_out; + wire direct_interc_85_out; + wire direct_interc_86_out; + wire direct_interc_87_out; + wire direct_interc_88_out; + wire direct_interc_89_out; + wire direct_interc_90_out; + wire logical_tile_clb_mode_default__fle_0_ccff_tail; + wire logical_tile_clb_mode_default__fle_0_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_0_fle_out; + wire logical_tile_clb_mode_default__fle_0_fle_reg_out; + wire logical_tile_clb_mode_default__fle_0_fle_sc_out; + wire logical_tile_clb_mode_default__fle_1_ccff_tail; + wire logical_tile_clb_mode_default__fle_1_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_1_fle_out; + wire logical_tile_clb_mode_default__fle_1_fle_reg_out; + wire logical_tile_clb_mode_default__fle_1_fle_sc_out; + wire logical_tile_clb_mode_default__fle_2_ccff_tail; + wire logical_tile_clb_mode_default__fle_2_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_2_fle_out; + wire logical_tile_clb_mode_default__fle_2_fle_reg_out; + wire logical_tile_clb_mode_default__fle_2_fle_sc_out; + wire logical_tile_clb_mode_default__fle_3_ccff_tail; + wire logical_tile_clb_mode_default__fle_3_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_3_fle_out; + wire logical_tile_clb_mode_default__fle_3_fle_reg_out; + wire logical_tile_clb_mode_default__fle_3_fle_sc_out; + wire logical_tile_clb_mode_default__fle_4_ccff_tail; + wire logical_tile_clb_mode_default__fle_4_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_4_fle_out; + wire logical_tile_clb_mode_default__fle_4_fle_reg_out; + wire logical_tile_clb_mode_default__fle_4_fle_sc_out; + wire logical_tile_clb_mode_default__fle_5_ccff_tail; + wire logical_tile_clb_mode_default__fle_5_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_5_fle_out; + wire logical_tile_clb_mode_default__fle_5_fle_reg_out; + wire logical_tile_clb_mode_default__fle_5_fle_sc_out; + wire logical_tile_clb_mode_default__fle_6_ccff_tail; + wire logical_tile_clb_mode_default__fle_6_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_6_fle_out; + wire logical_tile_clb_mode_default__fle_6_fle_reg_out; + wire logical_tile_clb_mode_default__fle_6_fle_sc_out; + wire logical_tile_clb_mode_default__fle_7_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_7_fle_out; + wire logical_tile_clb_mode_default__fle_7_fle_reg_out; + wire logical_tile_clb_mode_default__fle_7_fle_sc_out; + wire pReset; + wire prog_clk; + + direct_interc direct_interc_0_ + ( + .in(logical_tile_clb_mode_default__fle_0_fle_out[1]), + .out(clb_O[0]) + ); + direct_interc direct_interc_10_ + ( + .in(logical_tile_clb_mode_default__fle_5_fle_out[1]), + .out(clb_O[10]) + ); + direct_interc direct_interc_11_ + ( + .in(logical_tile_clb_mode_default__fle_5_fle_out[0]), + .out(clb_O[11]) + ); + direct_interc direct_interc_12_ + ( + .in(logical_tile_clb_mode_default__fle_6_fle_out[1]), + .out(clb_O[12]) + ); + direct_interc direct_interc_13_ + ( + .in(logical_tile_clb_mode_default__fle_6_fle_out[0]), + .out(clb_O[13]) + ); + direct_interc direct_interc_14_ + ( + .in(logical_tile_clb_mode_default__fle_7_fle_out[1]), + .out(clb_O[14]) + ); + direct_interc direct_interc_15_ + ( + .in(logical_tile_clb_mode_default__fle_7_fle_out[0]), + .out(clb_O[15]) + ); + direct_interc direct_interc_16_ + ( + .in(logical_tile_clb_mode_default__fle_7_fle_reg_out), + .out(clb_reg_out) + ); + direct_interc direct_interc_17_ + ( + .in(logical_tile_clb_mode_default__fle_7_fle_sc_out), + .out(clb_sc_out) + ); + direct_interc direct_interc_18_ + ( + .in(logical_tile_clb_mode_default__fle_7_fle_cout), + .out(clb_cout) + ); + direct_interc direct_interc_19_ + ( + .in(clb_I0[0]), + .out(direct_interc_19_out) + ); + direct_interc direct_interc_1_ + ( + .in(logical_tile_clb_mode_default__fle_0_fle_out[0]), + .out(clb_O[1]) + ); + direct_interc direct_interc_20_ + ( + .in(clb_I0[1]), + .out(direct_interc_20_out) + ); + direct_interc direct_interc_21_ + ( + .in(clb_I0i[0]), + .out(direct_interc_21_out) + ); + direct_interc direct_interc_22_ + ( + .in(clb_I0i[1]), + .out(direct_interc_22_out) + ); + direct_interc direct_interc_23_ + ( + .in(clb_reg_in), + .out(direct_interc_23_out) + ); + direct_interc direct_interc_24_ + ( + .in(clb_sc_in), + .out(direct_interc_24_out) + ); + direct_interc direct_interc_25_ + ( + .in(clb_cin), + .out(direct_interc_25_out) + ); + direct_interc direct_interc_26_ + ( + .in(clb_reset), + .out(direct_interc_26_out) + ); + direct_interc direct_interc_27_ + ( + .in(clb_clk), + .out(direct_interc_27_out) + ); + direct_interc direct_interc_28_ + ( + .in(clb_I1[0]), + .out(direct_interc_28_out) + ); + direct_interc direct_interc_29_ + ( + .in(clb_I1[1]), + .out(direct_interc_29_out) + ); + direct_interc direct_interc_2_ + ( + .in(logical_tile_clb_mode_default__fle_1_fle_out[1]), + .out(clb_O[2]) + ); + direct_interc direct_interc_30_ + ( + .in(clb_I1i[0]), + .out(direct_interc_30_out) + ); + direct_interc direct_interc_31_ + ( + .in(clb_I1i[1]), + .out(direct_interc_31_out) + ); + direct_interc direct_interc_32_ + ( + .in(logical_tile_clb_mode_default__fle_0_fle_reg_out), + .out(direct_interc_32_out) + ); + direct_interc direct_interc_33_ + ( + .in(logical_tile_clb_mode_default__fle_0_fle_sc_out), + .out(direct_interc_33_out) + ); + direct_interc direct_interc_34_ + ( + .in(logical_tile_clb_mode_default__fle_0_fle_cout), + .out(direct_interc_34_out) + ); + direct_interc direct_interc_35_ + ( + .in(clb_reset), + .out(direct_interc_35_out) + ); + direct_interc direct_interc_36_ + ( + .in(clb_clk), + .out(direct_interc_36_out) + ); + direct_interc direct_interc_37_ + ( + .in(clb_I2[0]), + .out(direct_interc_37_out) + ); + direct_interc direct_interc_38_ + ( + .in(clb_I2[1]), + .out(direct_interc_38_out) + ); + direct_interc direct_interc_39_ + ( + .in(clb_I2i[0]), + .out(direct_interc_39_out) + ); + direct_interc direct_interc_3_ + ( + .in(logical_tile_clb_mode_default__fle_1_fle_out[0]), + .out(clb_O[3]) + ); + direct_interc direct_interc_40_ + ( + .in(clb_I2i[1]), + .out(direct_interc_40_out) + ); + direct_interc direct_interc_41_ + ( + .in(logical_tile_clb_mode_default__fle_1_fle_reg_out), + .out(direct_interc_41_out) + ); + direct_interc direct_interc_42_ + ( + .in(logical_tile_clb_mode_default__fle_1_fle_sc_out), + .out(direct_interc_42_out) + ); + direct_interc direct_interc_43_ + ( + .in(logical_tile_clb_mode_default__fle_1_fle_cout), + .out(direct_interc_43_out) + ); + direct_interc direct_interc_44_ + ( + .in(clb_reset), + .out(direct_interc_44_out) + ); + direct_interc direct_interc_45_ + ( + .in(clb_clk), + .out(direct_interc_45_out) + ); + direct_interc direct_interc_46_ + ( + .in(clb_I3[0]), + .out(direct_interc_46_out) + ); + direct_interc direct_interc_47_ + ( + .in(clb_I3[1]), + .out(direct_interc_47_out) + ); + direct_interc direct_interc_48_ + ( + .in(clb_I3i[0]), + .out(direct_interc_48_out) + ); + direct_interc direct_interc_49_ + ( + .in(clb_I3i[1]), + .out(direct_interc_49_out) + ); + direct_interc direct_interc_4_ + ( + .in(logical_tile_clb_mode_default__fle_2_fle_out[1]), + .out(clb_O[4]) + ); + direct_interc direct_interc_50_ + ( + .in(logical_tile_clb_mode_default__fle_2_fle_reg_out), + .out(direct_interc_50_out) + ); + direct_interc direct_interc_51_ + ( + .in(logical_tile_clb_mode_default__fle_2_fle_sc_out), + .out(direct_interc_51_out) + ); + direct_interc direct_interc_52_ + ( + .in(logical_tile_clb_mode_default__fle_2_fle_cout), + .out(direct_interc_52_out) + ); + direct_interc direct_interc_53_ + ( + .in(clb_reset), + .out(direct_interc_53_out) + ); + direct_interc direct_interc_54_ + ( + .in(clb_clk), + .out(direct_interc_54_out) + ); + direct_interc direct_interc_55_ + ( + .in(clb_I4[0]), + .out(direct_interc_55_out) + ); + direct_interc direct_interc_56_ + ( + .in(clb_I4[1]), + .out(direct_interc_56_out) + ); + direct_interc direct_interc_57_ + ( + .in(clb_I4i[0]), + .out(direct_interc_57_out) + ); + direct_interc direct_interc_58_ + ( + .in(clb_I4i[1]), + .out(direct_interc_58_out) + ); + direct_interc direct_interc_59_ + ( + .in(logical_tile_clb_mode_default__fle_3_fle_reg_out), + .out(direct_interc_59_out) + ); + direct_interc direct_interc_5_ + ( + .in(logical_tile_clb_mode_default__fle_2_fle_out[0]), + .out(clb_O[5]) + ); + direct_interc direct_interc_60_ + ( + .in(logical_tile_clb_mode_default__fle_3_fle_sc_out), + .out(direct_interc_60_out) + ); + direct_interc direct_interc_61_ + ( + .in(logical_tile_clb_mode_default__fle_3_fle_cout), + .out(direct_interc_61_out) + ); + direct_interc direct_interc_62_ + ( + .in(clb_reset), + .out(direct_interc_62_out) + ); + direct_interc direct_interc_63_ + ( + .in(clb_clk), + .out(direct_interc_63_out) + ); + direct_interc direct_interc_64_ + ( + .in(clb_I5[0]), + .out(direct_interc_64_out) + ); + direct_interc direct_interc_65_ + ( + .in(clb_I5[1]), + .out(direct_interc_65_out) + ); + direct_interc direct_interc_66_ + ( + .in(clb_I5i[0]), + .out(direct_interc_66_out) + ); + direct_interc direct_interc_67_ + ( + .in(clb_I5i[1]), + .out(direct_interc_67_out) + ); + direct_interc direct_interc_68_ + ( + .in(logical_tile_clb_mode_default__fle_4_fle_reg_out), + .out(direct_interc_68_out) + ); + direct_interc direct_interc_69_ + ( + .in(logical_tile_clb_mode_default__fle_4_fle_sc_out), + .out(direct_interc_69_out) + ); + direct_interc direct_interc_6_ + ( + .in(logical_tile_clb_mode_default__fle_3_fle_out[1]), + .out(clb_O[6]) + ); + direct_interc direct_interc_70_ + ( + .in(logical_tile_clb_mode_default__fle_4_fle_cout), + .out(direct_interc_70_out) + ); + direct_interc direct_interc_71_ + ( + .in(clb_reset), + .out(direct_interc_71_out) + ); + direct_interc direct_interc_72_ + ( + .in(clb_clk), + .out(direct_interc_72_out) + ); + direct_interc direct_interc_73_ + ( + .in(clb_I6[0]), + .out(direct_interc_73_out) + ); + direct_interc direct_interc_74_ + ( + .in(clb_I6[1]), + .out(direct_interc_74_out) + ); + direct_interc direct_interc_75_ + ( + .in(clb_I6i[0]), + .out(direct_interc_75_out) + ); + direct_interc direct_interc_76_ + ( + .in(clb_I6i[1]), + .out(direct_interc_76_out) + ); + direct_interc direct_interc_77_ + ( + .in(logical_tile_clb_mode_default__fle_5_fle_reg_out), + .out(direct_interc_77_out) + ); + direct_interc direct_interc_78_ + ( + .in(logical_tile_clb_mode_default__fle_5_fle_sc_out), + .out(direct_interc_78_out) + ); + direct_interc direct_interc_79_ + ( + .in(logical_tile_clb_mode_default__fle_5_fle_cout), + .out(direct_interc_79_out) + ); + direct_interc direct_interc_7_ + ( + .in(logical_tile_clb_mode_default__fle_3_fle_out[0]), + .out(clb_O[7]) + ); + direct_interc direct_interc_80_ + ( + .in(clb_reset), + .out(direct_interc_80_out) + ); + direct_interc direct_interc_81_ + ( + .in(clb_clk), + .out(direct_interc_81_out) + ); + direct_interc direct_interc_82_ + ( + .in(clb_I7[0]), + .out(direct_interc_82_out) + ); + direct_interc direct_interc_83_ + ( + .in(clb_I7[1]), + .out(direct_interc_83_out) + ); + direct_interc direct_interc_84_ + ( + .in(clb_I7i[0]), + .out(direct_interc_84_out) + ); + direct_interc direct_interc_85_ + ( + .in(clb_I7i[1]), + .out(direct_interc_85_out) + ); + direct_interc direct_interc_86_ + ( + .in(logical_tile_clb_mode_default__fle_6_fle_reg_out), + .out(direct_interc_86_out) + ); + direct_interc direct_interc_87_ + ( + .in(logical_tile_clb_mode_default__fle_6_fle_sc_out), + .out(direct_interc_87_out) + ); + direct_interc direct_interc_88_ + ( + .in(logical_tile_clb_mode_default__fle_6_fle_cout), + .out(direct_interc_88_out) + ); + direct_interc direct_interc_89_ + ( + .in(clb_reset), + .out(direct_interc_89_out) + ); + direct_interc direct_interc_8_ + ( + .in(logical_tile_clb_mode_default__fle_4_fle_out[1]), + .out(clb_O[8]) + ); + direct_interc direct_interc_90_ + ( + .in(clb_clk), + .out(direct_interc_90_out) + ); + direct_interc direct_interc_9_ + ( + .in(logical_tile_clb_mode_default__fle_4_fle_out[0]), + .out(clb_O[9]) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 + ( + .Test_en(Test_en), + .ccff_head(ccff_head), + .fle_cin(direct_interc_25_out), + .fle_clk(direct_interc_27_out), + .fle_in({direct_interc_19_out, direct_interc_20_out, direct_interc_21_out, direct_interc_22_out}), + .fle_reg_in(direct_interc_23_out), + .fle_reset(direct_interc_26_out), + .fle_sc_in(direct_interc_24_out), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail), + .fle_cout(logical_tile_clb_mode_default__fle_0_fle_cout), + .fle_out(logical_tile_clb_mode_default__fle_0_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_0_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_0_fle_sc_out) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 + ( + .Test_en(Test_en), + .ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail), + .fle_cin(direct_interc_34_out), + .fle_clk(direct_interc_36_out), + .fle_in({direct_interc_28_out, direct_interc_29_out, direct_interc_30_out, direct_interc_31_out}), + .fle_reg_in(direct_interc_32_out), + .fle_reset(direct_interc_35_out), + .fle_sc_in(direct_interc_33_out), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail), + .fle_cout(logical_tile_clb_mode_default__fle_1_fle_cout), + .fle_out(logical_tile_clb_mode_default__fle_1_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_1_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_1_fle_sc_out) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 + ( + .Test_en(Test_en), + .ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail), + .fle_cin(direct_interc_43_out), + .fle_clk(direct_interc_45_out), + .fle_in({direct_interc_37_out, direct_interc_38_out, direct_interc_39_out, direct_interc_40_out}), + .fle_reg_in(direct_interc_41_out), + .fle_reset(direct_interc_44_out), + .fle_sc_in(direct_interc_42_out), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail), + .fle_cout(logical_tile_clb_mode_default__fle_2_fle_cout), + .fle_out(logical_tile_clb_mode_default__fle_2_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_2_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_2_fle_sc_out) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 + ( + .Test_en(Test_en), + .ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail), + .fle_cin(direct_interc_52_out), + .fle_clk(direct_interc_54_out), + .fle_in({direct_interc_46_out, direct_interc_47_out, direct_interc_48_out, direct_interc_49_out}), + .fle_reg_in(direct_interc_50_out), + .fle_reset(direct_interc_53_out), + .fle_sc_in(direct_interc_51_out), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail), + .fle_cout(logical_tile_clb_mode_default__fle_3_fle_cout), + .fle_out(logical_tile_clb_mode_default__fle_3_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_3_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_3_fle_sc_out) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 + ( + .Test_en(Test_en), + .ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail), + .fle_cin(direct_interc_61_out), + .fle_clk(direct_interc_63_out), + .fle_in({direct_interc_55_out, direct_interc_56_out, direct_interc_57_out, direct_interc_58_out}), + .fle_reg_in(direct_interc_59_out), + .fle_reset(direct_interc_62_out), + .fle_sc_in(direct_interc_60_out), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail), + .fle_cout(logical_tile_clb_mode_default__fle_4_fle_cout), + .fle_out(logical_tile_clb_mode_default__fle_4_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_4_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_4_fle_sc_out) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 + ( + .Test_en(Test_en), + .ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail), + .fle_cin(direct_interc_70_out), + .fle_clk(direct_interc_72_out), + .fle_in({direct_interc_64_out, direct_interc_65_out, direct_interc_66_out, direct_interc_67_out}), + .fle_reg_in(direct_interc_68_out), + .fle_reset(direct_interc_71_out), + .fle_sc_in(direct_interc_69_out), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail), + .fle_cout(logical_tile_clb_mode_default__fle_5_fle_cout), + .fle_out(logical_tile_clb_mode_default__fle_5_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_5_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_5_fle_sc_out) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 + ( + .Test_en(Test_en), + .ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail), + .fle_cin(direct_interc_79_out), + .fle_clk(direct_interc_81_out), + .fle_in({direct_interc_73_out, direct_interc_74_out, direct_interc_75_out, direct_interc_76_out}), + .fle_reg_in(direct_interc_77_out), + .fle_reset(direct_interc_80_out), + .fle_sc_in(direct_interc_78_out), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail), + .fle_cout(logical_tile_clb_mode_default__fle_6_fle_cout), + .fle_out(logical_tile_clb_mode_default__fle_6_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_6_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_6_fle_sc_out) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 + ( + .Test_en(Test_en), + .ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail), + .fle_cin(direct_interc_88_out), + .fle_clk(direct_interc_90_out), + .fle_in({direct_interc_82_out, direct_interc_83_out, direct_interc_84_out, direct_interc_85_out}), + .fle_reg_in(direct_interc_86_out), + .fle_reset(direct_interc_89_out), + .fle_sc_in(direct_interc_87_out), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .fle_cout(logical_tile_clb_mode_default__fle_7_fle_cout), + .fle_out(logical_tile_clb_mode_default__fle_7_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_7_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_7_fle_sc_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle.v new file mode 100644 index 0000000..8c042cc --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle.v @@ -0,0 +1,156 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle +( + Test_en, + ccff_head, + fle_cin, + fle_clk, + fle_in, + fle_reg_in, + fle_reset, + fle_sc_in, + pReset, + prog_clk, + ccff_tail, + fle_cout, + fle_out, + fle_reg_out, + fle_sc_out +); + + input Test_en; + input ccff_head; + input fle_cin; + input fle_clk; + input [0:3]fle_in; + input fle_reg_in; + input fle_reset; + input fle_sc_in; + input pReset; + input prog_clk; + output ccff_tail; + output fle_cout; + output [0:1]fle_out; + output fle_reg_out; + output fle_sc_out; + + wire Test_en; + wire ccff_head; + wire ccff_tail; + wire direct_interc_10_out; + wire direct_interc_11_out; + wire direct_interc_12_out; + wire direct_interc_13_out; + wire direct_interc_5_out; + wire direct_interc_6_out; + wire direct_interc_7_out; + wire direct_interc_8_out; + wire direct_interc_9_out; + wire fle_cin; + wire fle_clk; + wire fle_cout; + wire [0:3]fle_in; + wire [0:1]fle_out; + wire fle_reg_in; + wire fle_reg_out; + wire fle_reset; + wire fle_sc_in; + wire fle_sc_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout; + wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out; + wire pReset; + wire prog_clk; + + direct_interc direct_interc_0_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0]), + .out(fle_out[0]) + ); + direct_interc direct_interc_10_ + ( + .in(fle_sc_in), + .out(direct_interc_10_out) + ); + direct_interc direct_interc_11_ + ( + .in(fle_cin), + .out(direct_interc_11_out) + ); + direct_interc direct_interc_12_ + ( + .in(fle_reset), + .out(direct_interc_12_out) + ); + direct_interc direct_interc_13_ + ( + .in(fle_clk), + .out(direct_interc_13_out) + ); + direct_interc direct_interc_1_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[1]), + .out(fle_out[1]) + ); + direct_interc direct_interc_2_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out), + .out(fle_reg_out) + ); + direct_interc direct_interc_3_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out), + .out(fle_sc_out) + ); + direct_interc direct_interc_4_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout), + .out(fle_cout) + ); + direct_interc direct_interc_5_ + ( + .in(fle_in[0]), + .out(direct_interc_5_out) + ); + direct_interc direct_interc_6_ + ( + .in(fle_in[1]), + .out(direct_interc_6_out) + ); + direct_interc direct_interc_7_ + ( + .in(fle_in[2]), + .out(direct_interc_7_out) + ); + direct_interc direct_interc_8_ + ( + .in(fle_in[3]), + .out(direct_interc_8_out) + ); + direct_interc direct_interc_9_ + ( + .in(fle_reg_in), + .out(direct_interc_9_out) + ); + logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 + ( + .Test_en(Test_en), + .ccff_head(ccff_head), + .fabric_cin(direct_interc_11_out), + .fabric_clk(direct_interc_13_out), + .fabric_in({direct_interc_5_out, direct_interc_6_out, direct_interc_7_out, direct_interc_8_out}), + .fabric_reg_in(direct_interc_9_out), + .fabric_reset(direct_interc_12_out), + .fabric_sc_in(direct_interc_10_out), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .fabric_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout), + .fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out), + .fabric_reg_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out), + .fabric_sc_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric.v new file mode 100644 index 0000000..3328140 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric.v @@ -0,0 +1,243 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle_mode_physical__fabric +( + Test_en, + ccff_head, + fabric_cin, + fabric_clk, + fabric_in, + fabric_reg_in, + fabric_reset, + fabric_sc_in, + pReset, + prog_clk, + ccff_tail, + fabric_cout, + fabric_out, + fabric_reg_out, + fabric_sc_out +); + + input Test_en; + input ccff_head; + input fabric_cin; + input fabric_clk; + input [0:3]fabric_in; + input fabric_reg_in; + input fabric_reset; + input fabric_sc_in; + input pReset; + input prog_clk; + output ccff_tail; + output fabric_cout; + output [0:1]fabric_out; + output fabric_reg_out; + output fabric_sc_out; + + wire Test_en; + wire ccff_head; + wire ccff_tail; + wire direct_interc_10_out; + wire direct_interc_11_out; + wire direct_interc_12_out; + wire direct_interc_13_out; + wire direct_interc_3_out; + wire direct_interc_4_out; + wire direct_interc_5_out; + wire direct_interc_6_out; + wire direct_interc_7_out; + wire direct_interc_8_out; + wire direct_interc_9_out; + wire fabric_cin; + wire fabric_clk; + wire fabric_cout; + wire [0:3]fabric_in; + wire [0:1]fabric_out; + wire fabric_reg_in; + wire fabric_reg_out; + wire fabric_reset; + wire fabric_sc_in; + wire fabric_sc_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout; + wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out; + wire [0:1]mux_fabric_out_0_undriven_sram_inv; + wire [0:1]mux_fabric_out_1_undriven_sram_inv; + wire [0:1]mux_ff_0_D_0_undriven_sram_inv; + wire [0:1]mux_ff_1_D_0_undriven_sram_inv; + wire [0:1]mux_tree_size2_0_sram; + wire [0:1]mux_tree_size2_1_sram; + wire mux_tree_size2_2_out; + wire [0:1]mux_tree_size2_2_sram; + wire mux_tree_size2_3_out; + wire [0:1]mux_tree_size2_3_sram; + wire mux_tree_size2_mem_0_ccff_tail; + wire mux_tree_size2_mem_1_ccff_tail; + wire mux_tree_size2_mem_2_ccff_tail; + wire pReset; + wire prog_clk; + + direct_interc direct_interc_0_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q), + .out(fabric_reg_out) + ); + direct_interc direct_interc_10_ + ( + .in(fabric_clk), + .out(direct_interc_10_out) + ); + direct_interc direct_interc_11_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q), + .out(direct_interc_11_out) + ); + direct_interc direct_interc_12_ + ( + .in(fabric_reset), + .out(direct_interc_12_out) + ); + direct_interc direct_interc_13_ + ( + .in(fabric_clk), + .out(direct_interc_13_out) + ); + direct_interc direct_interc_1_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q), + .out(fabric_sc_out) + ); + direct_interc direct_interc_2_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout), + .out(fabric_cout) + ); + direct_interc direct_interc_3_ + ( + .in(fabric_in[0]), + .out(direct_interc_3_out) + ); + direct_interc direct_interc_4_ + ( + .in(fabric_in[1]), + .out(direct_interc_4_out) + ); + direct_interc direct_interc_5_ + ( + .in(fabric_in[2]), + .out(direct_interc_5_out) + ); + direct_interc direct_interc_6_ + ( + .in(fabric_in[3]), + .out(direct_interc_6_out) + ); + direct_interc direct_interc_7_ + ( + .in(fabric_cin), + .out(direct_interc_7_out) + ); + direct_interc direct_interc_8_ + ( + .in(fabric_sc_in), + .out(direct_interc_8_out) + ); + direct_interc direct_interc_9_ + ( + .in(fabric_reset), + .out(direct_interc_9_out) + ); + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 + ( + .Test_en(Test_en), + .ff_D(mux_tree_size2_2_out), + .ff_DI(direct_interc_8_out), + .ff_clk(direct_interc_10_out), + .ff_reset(direct_interc_9_out), + .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q) + ); + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 + ( + .Test_en(Test_en), + .ff_D(mux_tree_size2_3_out), + .ff_DI(direct_interc_11_out), + .ff_clk(direct_interc_13_out), + .ff_reset(direct_interc_12_out), + .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q) + ); + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 + ( + .ccff_head(ccff_head), + .frac_logic_cin(direct_interc_7_out), + .frac_logic_in({direct_interc_3_out, direct_interc_4_out, direct_interc_5_out, direct_interc_6_out}), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail), + .frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout), + .frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out) + ); + mux_tree_size2_mem mem_fabric_out_0 + ( + .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_size2_mem_0_ccff_tail), + .mem_out(mux_tree_size2_0_sram) + ); + mux_tree_size2_mem mem_fabric_out_1 + ( + .ccff_head(mux_tree_size2_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_size2_mem_1_ccff_tail), + .mem_out(mux_tree_size2_1_sram) + ); + mux_tree_size2_mem mem_ff_0_D_0 + ( + .ccff_head(mux_tree_size2_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_size2_mem_2_ccff_tail), + .mem_out(mux_tree_size2_2_sram) + ); + mux_tree_size2_mem mem_ff_1_D_0 + ( + .ccff_head(mux_tree_size2_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_size2_3_sram) + ); + mux_tree_size2 mux_fabric_out_0 + ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}), + .sram(mux_tree_size2_0_sram), + .sram_inv(mux_fabric_out_0_undriven_sram_inv), + .out(fabric_out[0]) + ); + mux_tree_size2 mux_fabric_out_1 + ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}), + .sram(mux_tree_size2_1_sram), + .sram_inv(mux_fabric_out_1_undriven_sram_inv), + .out(fabric_out[1]) + ); + mux_tree_size2 mux_ff_0_D_0 + ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_reg_in}), + .sram(mux_tree_size2_2_sram), + .sram_inv(mux_ff_0_D_0_undriven_sram_inv), + .out(mux_tree_size2_2_out) + ); + mux_tree_size2 mux_ff_1_D_0 + ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q}), + .sram(mux_tree_size2_3_sram), + .sram_inv(mux_ff_1_D_0_undriven_sram_inv), + .out(mux_tree_size2_3_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v new file mode 100644 index 0000000..7bb0f9e --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v @@ -0,0 +1,37 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff +( + Test_en, + ff_D, + ff_DI, + ff_clk, + ff_reset, + ff_Q +); + + input Test_en; + input ff_D; + input ff_DI; + input ff_clk; + input ff_reset; + output ff_Q; + + wire Test_en; + wire ff_D; + wire ff_DI; + wire ff_Q; + wire ff_clk; + wire ff_reset; + + sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ + ( + .CLK(ff_clk), + .D(ff_D), + .RESET_B(ff_reset), + .SCD(ff_DI), + .SCE(Test_en), + .Q(ff_Q) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v new file mode 100644 index 0000000..e01a31d --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v @@ -0,0 +1,139 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic +( + ccff_head, + frac_logic_cin, + frac_logic_in, + pReset, + prog_clk, + ccff_tail, + frac_logic_cout, + frac_logic_out +); + + input ccff_head; + input frac_logic_cin; + input [0:3]frac_logic_in; + input pReset; + input prog_clk; + output ccff_tail; + output frac_logic_cout; + output [0:1]frac_logic_out; + + wire ccff_head; + wire ccff_tail; + wire direct_interc_2_out; + wire direct_interc_3_out; + wire direct_interc_4_out; + wire direct_interc_5_out; + wire direct_interc_6_out; + wire direct_interc_7_out; + wire frac_logic_cin; + wire frac_logic_cout; + wire [0:3]frac_logic_in; + wire [0:1]frac_logic_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail; + wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out; + wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out; + wire [0:1]mux_frac_logic_out_0_undriven_sram_inv; + wire [0:1]mux_frac_lut4_0_in_2_undriven_sram_inv; + wire [0:1]mux_tree_size2_0_sram; + wire mux_tree_size2_1_out; + wire [0:1]mux_tree_size2_1_sram; + wire mux_tree_size2_mem_0_ccff_tail; + wire pReset; + wire prog_clk; + + direct_interc direct_interc_0_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]), + .out(frac_logic_out[1]) + ); + direct_interc direct_interc_1_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout), + .out(frac_logic_cout) + ); + direct_interc direct_interc_2_ + ( + .in(frac_logic_in[0]), + .out(direct_interc_2_out) + ); + direct_interc direct_interc_3_ + ( + .in(frac_logic_in[1]), + .out(direct_interc_3_out) + ); + direct_interc direct_interc_4_ + ( + .in(frac_logic_in[3]), + .out(direct_interc_4_out) + ); + direct_interc direct_interc_5_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[1]), + .out(direct_interc_5_out) + ); + direct_interc direct_interc_6_ + ( + .in(frac_logic_cin), + .out(direct_interc_6_out) + ); + direct_interc direct_interc_7_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[0]), + .out(direct_interc_7_out) + ); + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 + ( + .carry_follower_a(direct_interc_5_out), + .carry_follower_b(direct_interc_6_out), + .carry_follower_cin(direct_interc_7_out), + .carry_follower_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout) + ); + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 + ( + .ccff_head(ccff_head), + .frac_lut4_in({direct_interc_2_out, direct_interc_3_out, mux_tree_size2_1_out, direct_interc_4_out}), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail), + .frac_lut4_lut2_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out), + .frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out), + .frac_lut4_lut4_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out) + ); + mux_tree_size2_mem mem_frac_logic_out_0 + ( + .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_size2_mem_0_ccff_tail), + .mem_out(mux_tree_size2_0_sram) + ); + mux_tree_size2_mem mem_frac_lut4_0_in_2 + ( + .ccff_head(mux_tree_size2_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_size2_1_sram) + ); + mux_tree_size2 mux_frac_logic_out_0 + ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}), + .sram(mux_tree_size2_0_sram), + .sram_inv(mux_frac_logic_out_0_undriven_sram_inv), + .out(frac_logic_out[0]) + ); + mux_tree_size2 mux_frac_lut4_0_in_2 + ( + .in({frac_logic_cin, frac_logic_in[2]}), + .sram(mux_tree_size2_1_sram), + .sram_inv(mux_frac_lut4_0_in_2_undriven_sram_inv), + .out(mux_tree_size2_1_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v new file mode 100644 index 0000000..5264e03 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v @@ -0,0 +1,29 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower +( + carry_follower_a, + carry_follower_b, + carry_follower_cin, + carry_follower_cout +); + + input carry_follower_a; + input carry_follower_b; + input carry_follower_cin; + output carry_follower_cout; + + wire carry_follower_a; + wire carry_follower_b; + wire carry_follower_cin; + wire carry_follower_cout; + + sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_ + ( + .A0(carry_follower_a), + .A1(carry_follower_b), + .S(carry_follower_cin), + .X(carry_follower_cout) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v new file mode 100644 index 0000000..3d49b1f --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v @@ -0,0 +1,57 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 +( + ccff_head, + frac_lut4_in, + pReset, + prog_clk, + ccff_tail, + frac_lut4_lut2_out, + frac_lut4_lut3_out, + frac_lut4_lut4_out +); + + input ccff_head; + input [0:3]frac_lut4_in; + input pReset; + input prog_clk; + output ccff_tail; + output [0:1]frac_lut4_lut2_out; + output [0:1]frac_lut4_lut3_out; + output frac_lut4_lut4_out; + + wire ccff_head; + wire ccff_tail; + wire frac_lut4_0__undriven_mode_inv; + wire [0:15]frac_lut4_0__undriven_sram_inv; + wire frac_lut4_0_mode; + wire [0:15]frac_lut4_0_sram; + wire [0:3]frac_lut4_in; + wire [0:1]frac_lut4_lut2_out; + wire [0:1]frac_lut4_lut3_out; + wire frac_lut4_lut4_out; + wire pReset; + wire prog_clk; + + frac_lut4 frac_lut4_0_ + ( + .in(frac_lut4_in), + .mode(frac_lut4_0_mode), + .mode_inv(frac_lut4_0__undriven_mode_inv), + .sram(frac_lut4_0_sram), + .sram_inv(frac_lut4_0__undriven_sram_inv), + .lut2_out(frac_lut4_lut2_out), + .lut3_out(frac_lut4_lut3_out), + .lut4_out(frac_lut4_lut4_out) + ); + frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out({frac_lut4_0_sram[0], frac_lut4_0_sram[1], frac_lut4_0_sram[2], frac_lut4_0_sram[3], frac_lut4_0_sram[4], frac_lut4_0_sram[5], frac_lut4_0_sram[6], frac_lut4_0_sram[7], frac_lut4_0_sram[8], frac_lut4_0_sram[9], frac_lut4_0_sram[10], frac_lut4_0_sram[11], frac_lut4_0_sram[12], frac_lut4_0_sram[13], frac_lut4_0_sram[14], frac_lut4_0_sram[15], frac_lut4_0_mode}) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_io_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_io_.v new file mode 100644 index 0000000..8f186ab --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_io_.v @@ -0,0 +1,65 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_io_mode_io_ +( + IO_ISOL_N, + ccff_head, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + io_outpad, + pReset, + prog_clk, + ccff_tail, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + io_inpad +); + + input IO_ISOL_N; + input ccff_head; + input gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input io_outpad; + input pReset; + input prog_clk; + output ccff_tail; + output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output io_inpad; + + wire IO_ISOL_N; + wire ccff_head; + wire ccff_tail; + wire direct_interc_1_out; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire io_inpad; + wire io_outpad; + wire logical_tile_io_mode_physical__iopad_0_iopad_inpad; + wire pReset; + wire prog_clk; + + direct_interc direct_interc_0_ + ( + .in(logical_tile_io_mode_physical__iopad_0_iopad_inpad), + .out(io_inpad) + ); + direct_interc direct_interc_1_ + ( + .in(io_outpad), + .out(direct_interc_1_out) + ); + logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(ccff_head), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .iopad_outpad(direct_interc_1_out), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), + .iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_physical__iopad.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_physical__iopad.v new file mode 100644 index 0000000..d73ea95 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_physical__iopad.v @@ -0,0 +1,59 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_io_mode_physical__iopad +( + IO_ISOL_N, + ccff_head, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + iopad_outpad, + pReset, + prog_clk, + ccff_tail, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + iopad_inpad +); + + input IO_ISOL_N; + input ccff_head; + input gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input iopad_outpad; + input pReset; + input prog_clk; + output ccff_tail; + output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output iopad_inpad; + + wire EMBEDDED_IO_HD_0_en; + wire IO_ISOL_N; + wire ccff_head; + wire ccff_tail; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire iopad_inpad; + wire iopad_outpad; + wire pReset; + wire prog_clk; + + EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ + ( + .FPGA_DIR(EMBEDDED_IO_HD_0_en), + .FPGA_OUT(iopad_outpad), + .IO_ISOL_N(IO_ISOL_N), + .SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .FPGA_IN(iopad_inpad), + .SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT) + ); + EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(EMBEDDED_IO_HD_0_en) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_size2.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_size2.v new file mode 100644 index 0000000..122c833 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_size2.v @@ -0,0 +1,42 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_size2 +( + in, + sram, + sram_inv, + out +); + + input [0:1]in; + input [0:1]sram; + input [0:1]sram_inv; + output out; + + wire const1_0_const1; + wire [0:1]in; + wire out; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire [0:1]sram; + wire [0:1]sram_inv; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A0(in[1]), + .A1(in[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A0(const1_0_const1), + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .S(sram[1]), + .X(out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_size2_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_size2_mem.v new file mode 100644 index 0000000..d5ba29e --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_size2_mem.v @@ -0,0 +1,40 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_size2_mem +( + ccff_head, + pReset, + prog_clk, + ccff_tail, + mem_out +); + + input ccff_head; + input pReset; + input prog_clk; + output ccff_tail; + output [0:1]mem_out; + + wire ccff_head; + wire ccff_tail; + wire [0:1]mem_out; + wire pReset; + wire prog_clk; + +assign ccff_tail = mem_out[1]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .CLK(prog_clk), + .D(ccff_head), + .RESET_B(pReset), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .CLK(prog_clk), + .D(mem_out[0]), + .RESET_B(pReset), + .Q(mem_out[1]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size10.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size10.v new file mode 100644 index 0000000..8fe75a6 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size10.v @@ -0,0 +1,112 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size10 +( + in, + sram, + sram_inv, + out +); + + input [0:9]in; + input [0:3]sram; + input [0:3]sram_inv; + output out; + + wire const1_0_const1; + wire [0:9]in; + wire out; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire sky130_fd_sc_hd__mux2_1_8_X; + wire sky130_fd_sc_hd__mux2_1_9_X; + wire [0:3]sram; + wire [0:3]sram_inv; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A0(in[1]), + .A1(in[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A0(in[3]), + .A1(in[2]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A0(in[5]), + .A1(in[4]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A0(in[6]), + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A0(in[8]), + .A1(in[7]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A0(const1_0_const1), + .A1(in[9]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_4_X), + .A1(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A0(sky130_fd_sc_hd__mux2_1_6_X), + .A1(sky130_fd_sc_hd__mux2_1_5_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_8_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_8_X), + .A1(sky130_fd_sc_hd__mux2_1_7_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_9_X) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_9_X), + .X(out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size10_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size10_mem.v new file mode 100644 index 0000000..1cae90e --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size10_mem.v @@ -0,0 +1,54 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size10_mem +( + ccff_head, + pReset, + prog_clk, + ccff_tail, + mem_out +); + + input ccff_head; + input pReset; + input prog_clk; + output ccff_tail; + output [0:3]mem_out; + + wire ccff_head; + wire ccff_tail; + wire [0:3]mem_out; + wire pReset; + wire prog_clk; + +assign ccff_tail = mem_out[3]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .CLK(prog_clk), + .D(ccff_head), + .RESET_B(pReset), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .CLK(prog_clk), + .D(mem_out[0]), + .RESET_B(pReset), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .CLK(prog_clk), + .D(mem_out[1]), + .RESET_B(pReset), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .CLK(prog_clk), + .D(mem_out[2]), + .RESET_B(pReset), + .Q(mem_out[3]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size11.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size11.v new file mode 100644 index 0000000..86464d2 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size11.v @@ -0,0 +1,120 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size11 +( + in, + sram, + sram_inv, + out +); + + input [0:10]in; + input [0:3]sram; + input [0:3]sram_inv; + output out; + + wire const1_0_const1; + wire [0:10]in; + wire out; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_10_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire sky130_fd_sc_hd__mux2_1_8_X; + wire sky130_fd_sc_hd__mux2_1_9_X; + wire [0:3]sram; + wire [0:3]sram_inv; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A0(in[1]), + .A1(in[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A0(in[3]), + .A1(in[2]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A0(in[5]), + .A1(in[4]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ + ( + .A0(in[7]), + .A1(in[6]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A0(in[9]), + .A1(in[8]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A0(const1_0_const1), + .A1(in[10]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_5_X), + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_8_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A0(sky130_fd_sc_hd__mux2_1_7_X), + .A1(sky130_fd_sc_hd__mux2_1_6_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_9_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_9_X), + .A1(sky130_fd_sc_hd__mux2_1_8_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_10_X) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_10_X), + .X(out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size11_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size11_mem.v new file mode 100644 index 0000000..43bcce1 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size11_mem.v @@ -0,0 +1,54 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size11_mem +( + ccff_head, + pReset, + prog_clk, + ccff_tail, + mem_out +); + + input ccff_head; + input pReset; + input prog_clk; + output ccff_tail; + output [0:3]mem_out; + + wire ccff_head; + wire ccff_tail; + wire [0:3]mem_out; + wire pReset; + wire prog_clk; + +assign ccff_tail = mem_out[3]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .CLK(prog_clk), + .D(ccff_head), + .RESET_B(pReset), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .CLK(prog_clk), + .D(mem_out[0]), + .RESET_B(pReset), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .CLK(prog_clk), + .D(mem_out[1]), + .RESET_B(pReset), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .CLK(prog_clk), + .D(mem_out[2]), + .RESET_B(pReset), + .Q(mem_out[3]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size12.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size12.v new file mode 100644 index 0000000..67d0f4f --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size12.v @@ -0,0 +1,128 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size12 +( + in, + sram, + sram_inv, + out +); + + input [0:11]in; + input [0:3]sram; + input [0:3]sram_inv; + output out; + + wire const1_0_const1; + wire [0:11]in; + wire out; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_10_X; + wire sky130_fd_sc_hd__mux2_1_11_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire sky130_fd_sc_hd__mux2_1_8_X; + wire sky130_fd_sc_hd__mux2_1_9_X; + wire [0:3]sram; + wire [0:3]sram_inv; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A0(in[1]), + .A1(in[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A0(in[3]), + .A1(in[2]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A0(in[5]), + .A1(in[4]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ + ( + .A0(in[7]), + .A1(in[6]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ + ( + .A0(in[9]), + .A1(in[8]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A0(in[10]), + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A0(const1_0_const1), + .A1(in[11]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_8_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_6_X), + .A1(sky130_fd_sc_hd__mux2_1_5_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_9_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A0(sky130_fd_sc_hd__mux2_1_8_X), + .A1(sky130_fd_sc_hd__mux2_1_7_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_10_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_10_X), + .A1(sky130_fd_sc_hd__mux2_1_9_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_11_X) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_11_X), + .X(out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size12_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size12_mem.v new file mode 100644 index 0000000..5a0fdc8 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size12_mem.v @@ -0,0 +1,54 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size12_mem +( + ccff_head, + pReset, + prog_clk, + ccff_tail, + mem_out +); + + input ccff_head; + input pReset; + input prog_clk; + output ccff_tail; + output [0:3]mem_out; + + wire ccff_head; + wire ccff_tail; + wire [0:3]mem_out; + wire pReset; + wire prog_clk; + +assign ccff_tail = mem_out[3]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .CLK(prog_clk), + .D(ccff_head), + .RESET_B(pReset), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .CLK(prog_clk), + .D(mem_out[0]), + .RESET_B(pReset), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .CLK(prog_clk), + .D(mem_out[1]), + .RESET_B(pReset), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .CLK(prog_clk), + .D(mem_out[2]), + .RESET_B(pReset), + .Q(mem_out[3]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size2.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size2.v new file mode 100644 index 0000000..bb813d1 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size2.v @@ -0,0 +1,48 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size2 +( + in, + sram, + sram_inv, + out +); + + input [0:1]in; + input [0:1]sram; + input [0:1]sram_inv; + output out; + + wire const1_0_const1; + wire [0:1]in; + wire out; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire [0:1]sram; + wire [0:1]sram_inv; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A0(in[1]), + .A1(in[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A0(const1_0_const1), + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_1_X), + .X(out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size2_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size2_mem.v new file mode 100644 index 0000000..447f320 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size2_mem.v @@ -0,0 +1,40 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size2_mem +( + ccff_head, + pReset, + prog_clk, + ccff_tail, + mem_out +); + + input ccff_head; + input pReset; + input prog_clk; + output ccff_tail; + output [0:1]mem_out; + + wire ccff_head; + wire ccff_tail; + wire [0:1]mem_out; + wire pReset; + wire prog_clk; + +assign ccff_tail = mem_out[1]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .CLK(prog_clk), + .D(ccff_head), + .RESET_B(pReset), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .CLK(prog_clk), + .D(mem_out[0]), + .RESET_B(pReset), + .Q(mem_out[1]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size3.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size3.v new file mode 100644 index 0000000..51878f7 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size3.v @@ -0,0 +1,56 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size3 +( + in, + sram, + sram_inv, + out +); + + input [0:2]in; + input [0:1]sram; + input [0:1]sram_inv; + output out; + + wire const1_0_const1; + wire [0:2]in; + wire out; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire [0:1]sram; + wire [0:1]sram_inv; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A0(in[1]), + .A1(in[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A0(const1_0_const1), + .A1(in[2]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_2_X), + .X(out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size3_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size3_mem.v new file mode 100644 index 0000000..9e955a2 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size3_mem.v @@ -0,0 +1,40 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size3_mem +( + ccff_head, + pReset, + prog_clk, + ccff_tail, + mem_out +); + + input ccff_head; + input pReset; + input prog_clk; + output ccff_tail; + output [0:1]mem_out; + + wire ccff_head; + wire ccff_tail; + wire [0:1]mem_out; + wire pReset; + wire prog_clk; + +assign ccff_tail = mem_out[1]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .CLK(prog_clk), + .D(ccff_head), + .RESET_B(pReset), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .CLK(prog_clk), + .D(mem_out[0]), + .RESET_B(pReset), + .Q(mem_out[1]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size4.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size4.v new file mode 100644 index 0000000..8c3ae9a --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size4.v @@ -0,0 +1,64 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size4 +( + in, + sram, + sram_inv, + out +); + + input [0:3]in; + input [0:2]sram; + input [0:2]sram_inv; + output out; + + wire const1_0_const1; + wire [0:3]in; + wire out; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire [0:2]sram; + wire [0:2]sram_inv; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A0(in[1]), + .A1(in[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A0(in[2]), + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A0(const1_0_const1), + .A1(in[3]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_2_X), + .A1(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_3_X), + .X(out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size4_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size4_mem.v new file mode 100644 index 0000000..28fb4f3 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size4_mem.v @@ -0,0 +1,47 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size4_mem +( + ccff_head, + pReset, + prog_clk, + ccff_tail, + mem_out +); + + input ccff_head; + input pReset; + input prog_clk; + output ccff_tail; + output [0:2]mem_out; + + wire ccff_head; + wire ccff_tail; + wire [0:2]mem_out; + wire pReset; + wire prog_clk; + +assign ccff_tail = mem_out[2]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .CLK(prog_clk), + .D(ccff_head), + .RESET_B(pReset), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .CLK(prog_clk), + .D(mem_out[0]), + .RESET_B(pReset), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .CLK(prog_clk), + .D(mem_out[1]), + .RESET_B(pReset), + .Q(mem_out[2]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size5.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size5.v new file mode 100644 index 0000000..8225c99 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size5.v @@ -0,0 +1,72 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size5 +( + in, + sram, + sram_inv, + out +); + + input [0:4]in; + input [0:2]sram; + input [0:2]sram_inv; + output out; + + wire const1_0_const1; + wire [0:4]in; + wire out; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire [0:2]sram; + wire [0:2]sram_inv; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A0(in[1]), + .A1(in[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A0(in[3]), + .A1(in[2]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A0(const1_0_const1), + .A1(in[4]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_4_X), + .X(out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size5_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size5_mem.v new file mode 100644 index 0000000..285b187 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size5_mem.v @@ -0,0 +1,47 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size5_mem +( + ccff_head, + pReset, + prog_clk, + ccff_tail, + mem_out +); + + input ccff_head; + input pReset; + input prog_clk; + output ccff_tail; + output [0:2]mem_out; + + wire ccff_head; + wire ccff_tail; + wire [0:2]mem_out; + wire pReset; + wire prog_clk; + +assign ccff_tail = mem_out[2]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .CLK(prog_clk), + .D(ccff_head), + .RESET_B(pReset), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .CLK(prog_clk), + .D(mem_out[0]), + .RESET_B(pReset), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .CLK(prog_clk), + .D(mem_out[1]), + .RESET_B(pReset), + .Q(mem_out[2]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size6.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size6.v new file mode 100644 index 0000000..de04b01 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size6.v @@ -0,0 +1,80 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size6 +( + in, + sram, + sram_inv, + out +); + + input [0:5]in; + input [0:2]sram; + input [0:2]sram_inv; + output out; + + wire const1_0_const1; + wire [0:5]in; + wire out; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire [0:2]sram; + wire [0:2]sram_inv; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A0(in[1]), + .A1(in[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A0(in[3]), + .A1(in[2]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A0(in[5]), + .A1(in[4]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A0(const1_0_const1), + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_4_X), + .A1(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_5_X), + .X(out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size6_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size6_mem.v new file mode 100644 index 0000000..248ae26 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size6_mem.v @@ -0,0 +1,47 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size6_mem +( + ccff_head, + pReset, + prog_clk, + ccff_tail, + mem_out +); + + input ccff_head; + input pReset; + input prog_clk; + output ccff_tail; + output [0:2]mem_out; + + wire ccff_head; + wire ccff_tail; + wire [0:2]mem_out; + wire pReset; + wire prog_clk; + +assign ccff_tail = mem_out[2]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .CLK(prog_clk), + .D(ccff_head), + .RESET_B(pReset), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .CLK(prog_clk), + .D(mem_out[0]), + .RESET_B(pReset), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .CLK(prog_clk), + .D(mem_out[1]), + .RESET_B(pReset), + .Q(mem_out[2]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size7.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size7.v new file mode 100644 index 0000000..72e1e57 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size7.v @@ -0,0 +1,88 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size7 +( + in, + sram, + sram_inv, + out +); + + input [0:6]in; + input [0:2]sram; + input [0:2]sram_inv; + output out; + + wire const1_0_const1; + wire [0:6]in; + wire out; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire [0:2]sram; + wire [0:2]sram_inv; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A0(in[1]), + .A1(in[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A0(in[3]), + .A1(in[2]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A0(in[5]), + .A1(in[4]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ + ( + .A0(const1_0_const1), + .A1(in[6]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_5_X), + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_6_X), + .X(out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size7_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size7_mem.v new file mode 100644 index 0000000..dabe18a --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size7_mem.v @@ -0,0 +1,47 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size7_mem +( + ccff_head, + pReset, + prog_clk, + ccff_tail, + mem_out +); + + input ccff_head; + input pReset; + input prog_clk; + output ccff_tail; + output [0:2]mem_out; + + wire ccff_head; + wire ccff_tail; + wire [0:2]mem_out; + wire pReset; + wire prog_clk; + +assign ccff_tail = mem_out[2]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .CLK(prog_clk), + .D(ccff_head), + .RESET_B(pReset), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .CLK(prog_clk), + .D(mem_out[0]), + .RESET_B(pReset), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .CLK(prog_clk), + .D(mem_out[1]), + .RESET_B(pReset), + .Q(mem_out[2]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size8.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size8.v new file mode 100644 index 0000000..0be523b --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size8.v @@ -0,0 +1,96 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size8 +( + in, + sram, + sram_inv, + out +); + + input [0:7]in; + input [0:3]sram; + input [0:3]sram_inv; + output out; + + wire const1_0_const1; + wire [0:7]in; + wire out; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire [0:3]sram; + wire [0:3]sram_inv; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A0(in[1]), + .A1(in[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A0(in[2]), + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A0(in[4]), + .A1(in[3]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A0(in[6]), + .A1(in[5]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A0(const1_0_const1), + .A1(in[7]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_2_X), + .A1(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A0(sky130_fd_sc_hd__mux2_1_4_X), + .A1(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_6_X), + .A1(sky130_fd_sc_hd__mux2_1_5_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_7_X), + .X(out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size8_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size8_mem.v new file mode 100644 index 0000000..83a9937 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size8_mem.v @@ -0,0 +1,54 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size8_mem +( + ccff_head, + pReset, + prog_clk, + ccff_tail, + mem_out +); + + input ccff_head; + input pReset; + input prog_clk; + output ccff_tail; + output [0:3]mem_out; + + wire ccff_head; + wire ccff_tail; + wire [0:3]mem_out; + wire pReset; + wire prog_clk; + +assign ccff_tail = mem_out[3]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .CLK(prog_clk), + .D(ccff_head), + .RESET_B(pReset), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .CLK(prog_clk), + .D(mem_out[0]), + .RESET_B(pReset), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .CLK(prog_clk), + .D(mem_out[1]), + .RESET_B(pReset), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .CLK(prog_clk), + .D(mem_out[2]), + .RESET_B(pReset), + .Q(mem_out[3]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size9.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size9.v new file mode 100644 index 0000000..ff33fd5 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size9.v @@ -0,0 +1,104 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size9 +( + in, + sram, + sram_inv, + out +); + + input [0:8]in; + input [0:3]sram; + input [0:3]sram_inv; + output out; + + wire const1_0_const1; + wire [0:8]in; + wire out; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire sky130_fd_sc_hd__mux2_1_8_X; + wire [0:3]sram; + wire [0:3]sram_inv; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A0(in[1]), + .A1(in[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A0(in[3]), + .A1(in[2]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A0(in[5]), + .A1(in[4]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A0(in[7]), + .A1(in[6]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A0(const1_0_const1), + .A1(in[8]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A0(sky130_fd_sc_hd__mux2_1_5_X), + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A0(sky130_fd_sc_hd__mux2_1_7_X), + .A1(sky130_fd_sc_hd__mux2_1_6_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_8_X) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_8_X), + .X(out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size9_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size9_mem.v new file mode 100644 index 0000000..9e4aa9a --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size9_mem.v @@ -0,0 +1,54 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size9_mem +( + ccff_head, + pReset, + prog_clk, + ccff_tail, + mem_out +); + + input ccff_head; + input pReset; + input prog_clk; + output ccff_tail; + output [0:3]mem_out; + + wire ccff_head; + wire ccff_tail; + wire [0:3]mem_out; + wire pReset; + wire prog_clk; + +assign ccff_tail = mem_out[3]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .CLK(prog_clk), + .D(ccff_head), + .RESET_B(pReset), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .CLK(prog_clk), + .D(mem_out[0]), + .RESET_B(pReset), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .CLK(prog_clk), + .D(mem_out[1]), + .RESET_B(pReset), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .CLK(prog_clk), + .D(mem_out[2]), + .RESET_B(pReset), + .Q(mem_out[3]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__0_.v new file mode 100644 index 0000000..4643af3 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__0_.v @@ -0,0 +1,729 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_0__0_ +( + ccff_head, + chanx_right_in, + chany_top_in, + pReset, + prog_clk, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail, + chanx_right_out, + chany_top_out +); + + input ccff_head; + input [0:29]chanx_right_in; + input [0:29]chany_top_in; + input pReset; + input prog_clk; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + output [0:29]chanx_right_out; + output [0:29]chany_top_out; + + wire ccff_head; + wire ccff_tail; + wire [0:29]chanx_right_in; + wire [0:29]chanx_right_out; + wire [0:29]chany_top_in; + wire [0:29]chany_top_out; + wire [0:1]mux_right_track_0_undriven_sram_inv; + wire [0:1]mux_right_track_10_undriven_sram_inv; + wire [0:1]mux_right_track_12_undriven_sram_inv; + wire [0:1]mux_right_track_14_undriven_sram_inv; + wire [0:1]mux_right_track_16_undriven_sram_inv; + wire [0:1]mux_right_track_18_undriven_sram_inv; + wire [0:1]mux_right_track_28_undriven_sram_inv; + wire [0:1]mux_right_track_2_undriven_sram_inv; + wire [0:1]mux_right_track_30_undriven_sram_inv; + wire [0:1]mux_right_track_32_undriven_sram_inv; + wire [0:1]mux_right_track_34_undriven_sram_inv; + wire [0:1]mux_right_track_44_undriven_sram_inv; + wire [0:1]mux_right_track_46_undriven_sram_inv; + wire [0:1]mux_right_track_48_undriven_sram_inv; + wire [0:1]mux_right_track_4_undriven_sram_inv; + wire [0:1]mux_right_track_50_undriven_sram_inv; + wire [0:1]mux_right_track_6_undriven_sram_inv; + wire [0:1]mux_right_track_8_undriven_sram_inv; + wire [0:1]mux_top_track_0_undriven_sram_inv; + wire [0:1]mux_top_track_10_undriven_sram_inv; + wire [0:1]mux_top_track_12_undriven_sram_inv; + wire [0:1]mux_top_track_14_undriven_sram_inv; + wire [0:1]mux_top_track_16_undriven_sram_inv; + wire [0:1]mux_top_track_18_undriven_sram_inv; + wire [0:1]mux_top_track_28_undriven_sram_inv; + wire [0:1]mux_top_track_2_undriven_sram_inv; + wire [0:1]mux_top_track_30_undriven_sram_inv; + wire [0:1]mux_top_track_32_undriven_sram_inv; + wire [0:1]mux_top_track_34_undriven_sram_inv; + wire [0:1]mux_top_track_44_undriven_sram_inv; + wire [0:1]mux_top_track_46_undriven_sram_inv; + wire [0:1]mux_top_track_48_undriven_sram_inv; + wire [0:1]mux_top_track_4_undriven_sram_inv; + wire [0:1]mux_top_track_50_undriven_sram_inv; + wire [0:1]mux_top_track_6_undriven_sram_inv; + wire [0:1]mux_top_track_8_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_11_sram; + wire [0:1]mux_tree_tapbuf_size2_12_sram; + wire [0:1]mux_tree_tapbuf_size2_13_sram; + wire [0:1]mux_tree_tapbuf_size2_14_sram; + wire [0:1]mux_tree_tapbuf_size2_15_sram; + wire [0:1]mux_tree_tapbuf_size2_16_sram; + wire [0:1]mux_tree_tapbuf_size2_17_sram; + wire [0:1]mux_tree_tapbuf_size2_18_sram; + wire [0:1]mux_tree_tapbuf_size2_19_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_20_sram; + wire [0:1]mux_tree_tapbuf_size2_21_sram; + wire [0:1]mux_tree_tapbuf_size2_22_sram; + wire [0:1]mux_tree_tapbuf_size2_23_sram; + wire [0:1]mux_tree_tapbuf_size2_24_sram; + wire [0:1]mux_tree_tapbuf_size2_25_sram; + wire [0:1]mux_tree_tapbuf_size2_26_sram; + wire [0:1]mux_tree_tapbuf_size2_27_sram; + wire [0:1]mux_tree_tapbuf_size2_28_sram; + wire [0:1]mux_tree_tapbuf_size2_29_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_30_sram; + wire [0:1]mux_tree_tapbuf_size2_31_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire mux_tree_tapbuf_size2_mem_19_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_20_ccff_tail; + wire mux_tree_tapbuf_size2_mem_21_ccff_tail; + wire mux_tree_tapbuf_size2_mem_22_ccff_tail; + wire mux_tree_tapbuf_size2_mem_23_ccff_tail; + wire mux_tree_tapbuf_size2_mem_24_ccff_tail; + wire mux_tree_tapbuf_size2_mem_25_ccff_tail; + wire mux_tree_tapbuf_size2_mem_26_ccff_tail; + wire mux_tree_tapbuf_size2_mem_27_ccff_tail; + wire mux_tree_tapbuf_size2_mem_28_ccff_tail; + wire mux_tree_tapbuf_size2_mem_29_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_30_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire pReset; + wire prog_clk; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + +assign chanx_right_out[10] = chany_top_in[9]; +assign chanx_right_out[11] = chany_top_in[10]; +assign chanx_right_out[28] = chany_top_in[27]; +assign chanx_right_out[29] = chany_top_in[28]; +assign chany_top_out[29] = chanx_right_in[0]; +assign chany_top_out[10] = chanx_right_in[11]; +assign chany_top_out[11] = chanx_right_in[12]; +assign chany_top_out[12] = chanx_right_in[13]; +assign chany_top_out[13] = chanx_right_in[14]; +assign chany_top_out[18] = chanx_right_in[19]; +assign chany_top_out[19] = chanx_right_in[20]; +assign chany_top_out[20] = chanx_right_in[21]; +assign chanx_right_out[12] = chany_top_in[11]; +assign chany_top_out[21] = chanx_right_in[22]; +assign chany_top_out[26] = chanx_right_in[27]; +assign chany_top_out[27] = chanx_right_in[28]; +assign chany_top_out[28] = chanx_right_in[29]; +assign chanx_right_out[13] = chany_top_in[12]; +assign chanx_right_out[18] = chany_top_in[17]; +assign chanx_right_out[19] = chany_top_in[18]; +assign chanx_right_out[20] = chany_top_in[19]; +assign chanx_right_out[21] = chany_top_in[20]; +assign chanx_right_out[26] = chany_top_in[25]; +assign chanx_right_out[27] = chany_top_in[26]; + mux_tree_tapbuf_size3_mem mem_right_track_0 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_10 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_12 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_14 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_16 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_18 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_2 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_28 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_30 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_25_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_32 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_26_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_34 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_27_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_4 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_44 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_28_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_28_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_46 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_28_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_29_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_29_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_48 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_29_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_30_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_30_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_50 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_30_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_31_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_6 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_8 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_0 + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_10 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_12 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_14 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_16 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_18 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_2 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_28 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_30 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_32 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_34 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_4 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_44 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_46 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_48 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_50 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_6 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_8 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size3 mux_right_track_0 + ( + .in({chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size2 mux_right_track_10 + ( + .in({chany_top_in[4], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_19_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size2 mux_right_track_12 + ( + .in({chany_top_in[5], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_20_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size2 mux_right_track_14 + ( + .in({chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram), + .sram_inv(mux_right_track_14_undriven_sram_inv), + .out(chanx_right_out[7]) + ); + mux_tree_tapbuf_size2 mux_right_track_16 + ( + .in({chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_22_sram), + .sram_inv(mux_right_track_16_undriven_sram_inv), + .out(chanx_right_out[8]) + ); + mux_tree_tapbuf_size2 mux_right_track_18 + ( + .in({chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_23_sram), + .sram_inv(mux_right_track_18_undriven_sram_inv), + .out(chanx_right_out[9]) + ); + mux_tree_tapbuf_size2 mux_right_track_2 + ( + .in({chany_top_in[0], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_16_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size2 mux_right_track_28 + ( + .in({chany_top_in[13], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_24_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size2 mux_right_track_30 + ( + .in({chany_top_in[14], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_25_sram), + .sram_inv(mux_right_track_30_undriven_sram_inv), + .out(chanx_right_out[15]) + ); + mux_tree_tapbuf_size2 mux_right_track_32 + ( + .in({chany_top_in[15], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_26_sram), + .sram_inv(mux_right_track_32_undriven_sram_inv), + .out(chanx_right_out[16]) + ); + mux_tree_tapbuf_size2 mux_right_track_34 + ( + .in({chany_top_in[16], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_27_sram), + .sram_inv(mux_right_track_34_undriven_sram_inv), + .out(chanx_right_out[17]) + ); + mux_tree_tapbuf_size2 mux_right_track_4 + ( + .in({chany_top_in[1], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_17_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size2 mux_right_track_44 + ( + .in({chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_28_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size2 mux_right_track_46 + ( + .in({chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_29_sram), + .sram_inv(mux_right_track_46_undriven_sram_inv), + .out(chanx_right_out[23]) + ); + mux_tree_tapbuf_size2 mux_right_track_48 + ( + .in({chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_30_sram), + .sram_inv(mux_right_track_48_undriven_sram_inv), + .out(chanx_right_out[24]) + ); + mux_tree_tapbuf_size2 mux_right_track_50 + ( + .in({chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_31_sram), + .sram_inv(mux_right_track_50_undriven_sram_inv), + .out(chanx_right_out[25]) + ); + mux_tree_tapbuf_size3 mux_right_track_6 + ( + .in({chany_top_in[2], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size2 mux_right_track_8 + ( + .in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_18_sram), + .sram_inv(mux_right_track_8_undriven_sram_inv), + .out(chanx_right_out[4]) + ); + mux_tree_tapbuf_size3 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[1]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size2 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[6]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size2 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[7]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size2 mux_top_track_14 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[8]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_top_track_14_undriven_sram_inv), + .out(chany_top_out[7]) + ); + mux_tree_tapbuf_size2 mux_top_track_16 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[9]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_top_track_16_undriven_sram_inv), + .out(chany_top_out[8]) + ); + mux_tree_tapbuf_size2 mux_top_track_18 + ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[10]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_top_track_18_undriven_sram_inv), + .out(chany_top_out[9]) + ); + mux_tree_tapbuf_size2 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[2]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size2 mux_top_track_28 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[15]}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size2 mux_top_track_30 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[16]}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_top_track_30_undriven_sram_inv), + .out(chany_top_out[15]) + ); + mux_tree_tapbuf_size2 mux_top_track_32 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[17]}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_top_track_32_undriven_sram_inv), + .out(chany_top_out[16]) + ); + mux_tree_tapbuf_size2 mux_top_track_34 + ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[18]}), + .sram(mux_tree_tapbuf_size2_11_sram), + .sram_inv(mux_top_track_34_undriven_sram_inv), + .out(chany_top_out[17]) + ); + mux_tree_tapbuf_size2 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[3]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size2 mux_top_track_44 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[23]}), + .sram(mux_tree_tapbuf_size2_12_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size2 mux_top_track_46 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size2_13_sram), + .sram_inv(mux_top_track_46_undriven_sram_inv), + .out(chany_top_out[23]) + ); + mux_tree_tapbuf_size2 mux_top_track_48 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size2_14_sram), + .sram_inv(mux_top_track_48_undriven_sram_inv), + .out(chany_top_out[24]) + ); + mux_tree_tapbuf_size2 mux_top_track_50 + ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size2_15_sram), + .sram_inv(mux_top_track_50_undriven_sram_inv), + .out(chany_top_out[25]) + ); + mux_tree_tapbuf_size3 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[4]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); + mux_tree_tapbuf_size2 mux_top_track_8 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[5]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_top_track_8_undriven_sram_inv), + .out(chany_top_out[4]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__1_.v new file mode 100644 index 0000000..ac1ec14 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__1_.v @@ -0,0 +1,1026 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_0__1_ +( + bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chanx_right_in, + chany_bottom_in, + chany_top_in, + pReset, + prog_clk, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail, + chanx_right_out, + chany_bottom_out, + chany_top_out +); + + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + input ccff_head; + input [0:29]chanx_right_in; + input [0:29]chany_bottom_in; + input [0:29]chany_top_in; + input pReset; + input prog_clk; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + output [0:29]chanx_right_out; + output [0:29]chany_bottom_out; + output [0:29]chany_top_out; + + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head; + wire ccff_tail; + wire [0:29]chanx_right_in; + wire [0:29]chanx_right_out; + wire [0:29]chany_bottom_in; + wire [0:29]chany_bottom_out; + wire [0:29]chany_top_in; + wire [0:29]chany_top_out; + wire [0:2]mux_bottom_track_11_undriven_sram_inv; + wire [0:2]mux_bottom_track_13_undriven_sram_inv; + wire [0:2]mux_bottom_track_1_undriven_sram_inv; + wire [0:2]mux_bottom_track_21_undriven_sram_inv; + wire [0:2]mux_bottom_track_29_undriven_sram_inv; + wire [0:2]mux_bottom_track_37_undriven_sram_inv; + wire [0:2]mux_bottom_track_3_undriven_sram_inv; + wire [0:2]mux_bottom_track_45_undriven_sram_inv; + wire [0:1]mux_bottom_track_53_undriven_sram_inv; + wire [0:2]mux_bottom_track_5_undriven_sram_inv; + wire [0:2]mux_bottom_track_7_undriven_sram_inv; + wire [0:2]mux_right_track_0_undriven_sram_inv; + wire [0:2]mux_right_track_10_undriven_sram_inv; + wire [0:2]mux_right_track_12_undriven_sram_inv; + wire [0:2]mux_right_track_14_undriven_sram_inv; + wire [0:2]mux_right_track_16_undriven_sram_inv; + wire [0:2]mux_right_track_18_undriven_sram_inv; + wire [0:2]mux_right_track_20_undriven_sram_inv; + wire [0:2]mux_right_track_22_undriven_sram_inv; + wire [0:1]mux_right_track_24_undriven_sram_inv; + wire [0:1]mux_right_track_26_undriven_sram_inv; + wire [0:1]mux_right_track_28_undriven_sram_inv; + wire [0:2]mux_right_track_2_undriven_sram_inv; + wire [0:1]mux_right_track_30_undriven_sram_inv; + wire [0:1]mux_right_track_32_undriven_sram_inv; + wire [0:1]mux_right_track_34_undriven_sram_inv; + wire [0:2]mux_right_track_36_undriven_sram_inv; + wire [0:1]mux_right_track_38_undriven_sram_inv; + wire [0:1]mux_right_track_40_undriven_sram_inv; + wire [0:1]mux_right_track_44_undriven_sram_inv; + wire [0:1]mux_right_track_46_undriven_sram_inv; + wire [0:1]mux_right_track_48_undriven_sram_inv; + wire [0:2]mux_right_track_4_undriven_sram_inv; + wire [0:1]mux_right_track_50_undriven_sram_inv; + wire [0:1]mux_right_track_52_undriven_sram_inv; + wire [0:1]mux_right_track_54_undriven_sram_inv; + wire [0:1]mux_right_track_56_undriven_sram_inv; + wire [0:2]mux_right_track_6_undriven_sram_inv; + wire [0:2]mux_right_track_8_undriven_sram_inv; + wire [0:2]mux_top_track_0_undriven_sram_inv; + wire [0:2]mux_top_track_10_undriven_sram_inv; + wire [0:2]mux_top_track_12_undriven_sram_inv; + wire [0:2]mux_top_track_20_undriven_sram_inv; + wire [0:2]mux_top_track_28_undriven_sram_inv; + wire [0:2]mux_top_track_2_undriven_sram_inv; + wire [0:2]mux_top_track_36_undriven_sram_inv; + wire [0:1]mux_top_track_44_undriven_sram_inv; + wire [0:2]mux_top_track_4_undriven_sram_inv; + wire [0:2]mux_top_track_52_undriven_sram_inv; + wire [0:2]mux_top_track_6_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire [0:1]mux_tree_tapbuf_size3_7_sram; + wire [0:1]mux_tree_tapbuf_size3_8_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire mux_tree_tapbuf_size3_mem_7_ccff_tail; + wire [0:2]mux_tree_tapbuf_size4_0_sram; + wire [0:2]mux_tree_tapbuf_size4_1_sram; + wire [0:2]mux_tree_tapbuf_size4_2_sram; + wire [0:2]mux_tree_tapbuf_size4_3_sram; + wire [0:2]mux_tree_tapbuf_size4_4_sram; + wire [0:2]mux_tree_tapbuf_size4_5_sram; + wire [0:2]mux_tree_tapbuf_size4_6_sram; + wire [0:2]mux_tree_tapbuf_size4_7_sram; + wire [0:2]mux_tree_tapbuf_size4_8_sram; + wire [0:2]mux_tree_tapbuf_size4_9_sram; + wire mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire mux_tree_tapbuf_size4_mem_4_ccff_tail; + wire mux_tree_tapbuf_size4_mem_5_ccff_tail; + wire mux_tree_tapbuf_size4_mem_6_ccff_tail; + wire mux_tree_tapbuf_size4_mem_7_ccff_tail; + wire mux_tree_tapbuf_size4_mem_8_ccff_tail; + wire mux_tree_tapbuf_size4_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire [0:2]mux_tree_tapbuf_size5_5_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire mux_tree_tapbuf_size5_mem_5_ccff_tail; + wire [0:2]mux_tree_tapbuf_size6_0_sram; + wire [0:2]mux_tree_tapbuf_size6_10_sram; + wire [0:2]mux_tree_tapbuf_size6_11_sram; + wire [0:2]mux_tree_tapbuf_size6_1_sram; + wire [0:2]mux_tree_tapbuf_size6_2_sram; + wire [0:2]mux_tree_tapbuf_size6_3_sram; + wire [0:2]mux_tree_tapbuf_size6_4_sram; + wire [0:2]mux_tree_tapbuf_size6_5_sram; + wire [0:2]mux_tree_tapbuf_size6_6_sram; + wire [0:2]mux_tree_tapbuf_size6_7_sram; + wire [0:2]mux_tree_tapbuf_size6_8_sram; + wire [0:2]mux_tree_tapbuf_size6_9_sram; + wire mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire mux_tree_tapbuf_size6_mem_10_ccff_tail; + wire mux_tree_tapbuf_size6_mem_11_ccff_tail; + wire mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire mux_tree_tapbuf_size6_mem_7_ccff_tail; + wire mux_tree_tapbuf_size6_mem_8_ccff_tail; + wire mux_tree_tapbuf_size6_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size7_0_sram; + wire [0:2]mux_tree_tapbuf_size7_1_sram; + wire [0:2]mux_tree_tapbuf_size7_2_sram; + wire [0:2]mux_tree_tapbuf_size7_3_sram; + wire [0:2]mux_tree_tapbuf_size7_4_sram; + wire mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire mux_tree_tapbuf_size7_mem_4_ccff_tail; + wire pReset; + wire prog_clk; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + +assign chany_bottom_out[4] = chany_top_in[3]; +assign chany_bottom_out[7] = chany_top_in[6]; +assign chany_bottom_out[19] = chany_top_in[18]; +assign chany_bottom_out[20] = chany_top_in[19]; +assign chany_bottom_out[21] = chany_top_in[20]; +assign chany_bottom_out[23] = chany_top_in[22]; +assign chany_bottom_out[24] = chany_top_in[23]; +assign chany_bottom_out[25] = chany_top_in[24]; +assign chany_bottom_out[27] = chany_top_in[26]; +assign chany_bottom_out[28] = chany_top_in[27]; +assign chany_bottom_out[29] = chany_top_in[28]; +assign chany_top_out[4] = chany_bottom_in[3]; +assign chany_bottom_out[8] = chany_top_in[7]; +assign chany_top_out[7] = chany_bottom_in[6]; +assign chany_top_out[8] = chany_bottom_in[7]; +assign chany_top_out[9] = chany_bottom_in[8]; +assign chany_top_out[11] = chany_bottom_in[10]; +assign chany_top_out[12] = chany_bottom_in[11]; +assign chany_top_out[13] = chany_bottom_in[12]; +assign chany_top_out[15] = chany_bottom_in[14]; +assign chany_top_out[16] = chany_bottom_in[15]; +assign chany_top_out[17] = chany_bottom_in[16]; +assign chanx_right_out[21] = chany_bottom_in[17]; +assign chany_bottom_out[9] = chany_top_in[8]; +assign chany_top_out[19] = chany_bottom_in[18]; +assign chany_top_out[20] = chany_bottom_in[19]; +assign chany_top_out[21] = chany_bottom_in[20]; +assign chany_top_out[23] = chany_bottom_in[22]; +assign chany_top_out[24] = chany_bottom_in[23]; +assign chany_top_out[25] = chany_bottom_in[24]; +assign chany_top_out[27] = chany_bottom_in[26]; +assign chany_top_out[28] = chany_bottom_in[27]; +assign chany_top_out[29] = chany_bottom_in[28]; +assign chany_bottom_out[11] = chany_top_in[10]; +assign chany_bottom_out[12] = chany_top_in[11]; +assign chany_bottom_out[13] = chany_top_in[12]; +assign chany_bottom_out[15] = chany_top_in[14]; +assign chany_bottom_out[16] = chany_top_in[15]; +assign chany_bottom_out[17] = chany_top_in[16]; + mux_tree_tapbuf_size6_mem mem_bottom_track_1 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram) + ); + mux_tree_tapbuf_size7_mem mem_bottom_track_11 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_13 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_21 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_29 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_11_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_3 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_37 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_45 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_9_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_5 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_53 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram) + ); + mux_tree_tapbuf_size7_mem mem_bottom_track_7 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_0 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_10 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_12 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_14 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_16 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_18 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_2 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_20 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_6_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_22 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_7_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_24 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_26 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_28 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_30 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_32 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_34 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_36 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_38 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_4 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_40 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_44 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_46 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_48 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_50 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_52 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_54 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_56 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_6 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_8 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram) + ); + mux_tree_tapbuf_size7_mem mem_top_track_0 + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram) + ); + mux_tree_tapbuf_size7_mem mem_top_track_10 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_12 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_2 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_20 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_28 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size4_mem mem_top_track_36 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_4 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_44 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size4_mem mem_top_track_52 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram) + ); + mux_tree_tapbuf_size7_mem mem_top_track_6 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram) + ); + mux_tree_tapbuf_size6 mux_bottom_track_1 + ( + .in({chany_top_in[3], chany_top_in[19], chanx_right_in[9], chanx_right_in[20], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_7_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size7 mux_bottom_track_11 + ( + .in({chany_top_in[10], chany_top_in[24], chanx_right_in[5], chanx_right_in[16], chanx_right_in[27], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_4_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_13 + ( + .in({chany_top_in[11], chany_top_in[26], chanx_right_in[4], chanx_right_in[15], chanx_right_in[26], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_9_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_21 + ( + .in({chany_top_in[12], chany_top_in[27], chanx_right_in[3], chanx_right_in[14], chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_10_sram), + .sram_inv(mux_bottom_track_21_undriven_sram_inv), + .out(chany_bottom_out[10]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_29 + ( + .in({chany_top_in[14], chany_top_in[28], chanx_right_in[2], chanx_right_in[13], chanx_right_in[24], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_11_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_3 + ( + .in({chany_top_in[6], chany_top_in[20], chanx_right_in[8], chanx_right_in[19], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_37 + ( + .in({chany_top_in[15], chanx_right_in[1], chanx_right_in[12], chanx_right_in[23], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_5_sram), + .sram_inv(mux_bottom_track_37_undriven_sram_inv), + .out(chany_bottom_out[18]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_45 + ( + .in({chany_top_in[16], chanx_right_in[0], chanx_right_in[11], chanx_right_in[22]}), + .sram(mux_tree_tapbuf_size4_9_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_5 + ( + .in({chany_top_in[7], chany_top_in[22], chanx_right_in[7], chanx_right_in[18], chanx_right_in[29], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_8_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_53 + ( + .in({chany_top_in[18], chanx_right_in[10], chanx_right_in[21]}), + .sram(mux_tree_tapbuf_size3_8_sram), + .sram_inv(mux_bottom_track_53_undriven_sram_inv), + .out(chany_bottom_out[26]) + ); + mux_tree_tapbuf_size7 mux_bottom_track_7 + ( + .in({chany_top_in[8], chany_top_in[23], chanx_right_in[6], chanx_right_in[17], chanx_right_in[28], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_3_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size5 mux_right_track_0 + ( + .in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[3]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size5 mux_right_track_10 + ( + .in({chany_top_in[5], chany_top_in[11], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[11]}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size4 mux_right_track_12 + ( + .in({chany_top_in[9], chany_top_in[12], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[12]}), + .sram(mux_tree_tapbuf_size4_2_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size4 mux_right_track_14 + ( + .in({chany_top_in[13], chany_top_in[14], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[14]}), + .sram(mux_tree_tapbuf_size4_3_sram), + .sram_inv(mux_right_track_14_undriven_sram_inv), + .out(chanx_right_out[7]) + ); + mux_tree_tapbuf_size4 mux_right_track_16 + ( + .in({chany_top_in[15], chany_top_in[17], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[15]}), + .sram(mux_tree_tapbuf_size4_4_sram), + .sram_inv(mux_right_track_16_undriven_sram_inv), + .out(chanx_right_out[8]) + ); + mux_tree_tapbuf_size4 mux_right_track_18 + ( + .in({chany_top_in[16], chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[16]}), + .sram(mux_tree_tapbuf_size4_5_sram), + .sram_inv(mux_right_track_18_undriven_sram_inv), + .out(chanx_right_out[9]) + ); + mux_tree_tapbuf_size6 mux_right_track_2 + ( + .in({chany_top_in[0], chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[6]}), + .sram(mux_tree_tapbuf_size6_4_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size4 mux_right_track_20 + ( + .in({chany_top_in[18], chany_top_in[25], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[18]}), + .sram(mux_tree_tapbuf_size4_6_sram), + .sram_inv(mux_right_track_20_undriven_sram_inv), + .out(chanx_right_out[10]) + ); + mux_tree_tapbuf_size4 mux_right_track_22 + ( + .in({chany_top_in[19], chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[19]}), + .sram(mux_tree_tapbuf_size4_7_sram), + .sram_inv(mux_right_track_22_undriven_sram_inv), + .out(chanx_right_out[11]) + ); + mux_tree_tapbuf_size3 mux_right_track_24 + ( + .in({chany_top_in[20], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[20]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_right_track_24_undriven_sram_inv), + .out(chanx_right_out[12]) + ); + mux_tree_tapbuf_size3 mux_right_track_26 + ( + .in({chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[22]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_right_track_26_undriven_sram_inv), + .out(chanx_right_out[13]) + ); + mux_tree_tapbuf_size3 mux_right_track_28 + ( + .in({chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[23]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size3 mux_right_track_30 + ( + .in({chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[24]}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_right_track_30_undriven_sram_inv), + .out(chanx_right_out[15]) + ); + mux_tree_tapbuf_size3 mux_right_track_32 + ( + .in({chany_top_in[26], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[26]}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_right_track_32_undriven_sram_inv), + .out(chanx_right_out[16]) + ); + mux_tree_tapbuf_size3 mux_right_track_34 + ( + .in({chany_top_in[27], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[27]}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_right_track_34_undriven_sram_inv), + .out(chanx_right_out[17]) + ); + mux_tree_tapbuf_size4 mux_right_track_36 + ( + .in({chany_top_in[28], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[28], chany_bottom_in[29]}), + .sram(mux_tree_tapbuf_size4_8_sram), + .sram_inv(mux_right_track_36_undriven_sram_inv), + .out(chanx_right_out[18]) + ); + mux_tree_tapbuf_size2 mux_right_track_38 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[25]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_right_track_38_undriven_sram_inv), + .out(chanx_right_out[19]) + ); + mux_tree_tapbuf_size5 mux_right_track_4 + ( + .in({chany_top_in[1], chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[7]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size2 mux_right_track_40 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[21]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_right_track_40_undriven_sram_inv), + .out(chanx_right_out[20]) + ); + mux_tree_tapbuf_size2 mux_right_track_44 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[13]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size2 mux_right_track_46 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[9]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_right_track_46_undriven_sram_inv), + .out(chanx_right_out[23]) + ); + mux_tree_tapbuf_size2 mux_right_track_48 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[5]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_right_track_48_undriven_sram_inv), + .out(chanx_right_out[24]) + ); + mux_tree_tapbuf_size3 mux_right_track_50 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[4]}), + .sram(mux_tree_tapbuf_size3_7_sram), + .sram_inv(mux_right_track_50_undriven_sram_inv), + .out(chanx_right_out[25]) + ); + mux_tree_tapbuf_size2 mux_right_track_52 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[2]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_right_track_52_undriven_sram_inv), + .out(chanx_right_out[26]) + ); + mux_tree_tapbuf_size2 mux_right_track_54 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[1]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_right_track_54_undriven_sram_inv), + .out(chanx_right_out[27]) + ); + mux_tree_tapbuf_size2 mux_right_track_56 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[0]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_right_track_56_undriven_sram_inv), + .out(chanx_right_out[28]) + ); + mux_tree_tapbuf_size6 mux_right_track_6 + ( + .in({chany_top_in[2], chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[8]}), + .sram(mux_tree_tapbuf_size6_5_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size6 mux_right_track_8 + ( + .in({chany_top_in[4], chany_top_in[10], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[10]}), + .sram(mux_tree_tapbuf_size6_6_sram), + .sram_inv(mux_right_track_8_undriven_sram_inv), + .out(chanx_right_out[4]) + ); + mux_tree_tapbuf_size7 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[1], chanx_right_in[12], chanx_right_in[23], chany_bottom_in[3], chany_bottom_in[19]}), + .sram(mux_tree_tapbuf_size7_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size7 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[5], chanx_right_in[16], chanx_right_in[27], chany_bottom_in[10], chany_bottom_in[24]}), + .sram(mux_tree_tapbuf_size7_2_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size6 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[6], chanx_right_in[17], chanx_right_in[28], chany_bottom_in[11], chany_bottom_in[26]}), + .sram(mux_tree_tapbuf_size6_2_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size6 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[2], chanx_right_in[13], chanx_right_in[24], chany_bottom_in[6], chany_bottom_in[20]}), + .sram(mux_tree_tapbuf_size6_0_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size6 mux_top_track_20 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[7], chanx_right_in[18], chanx_right_in[29], chany_bottom_in[12], chany_bottom_in[27]}), + .sram(mux_tree_tapbuf_size6_3_sram), + .sram_inv(mux_top_track_20_undriven_sram_inv), + .out(chany_top_out[10]) + ); + mux_tree_tapbuf_size5 mux_top_track_28 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[8], chanx_right_in[19], chany_bottom_in[14], chany_bottom_in[28]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size4 mux_top_track_36 + ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[9], chanx_right_in[20], chany_bottom_in[15]}), + .sram(mux_tree_tapbuf_size4_0_sram), + .sram_inv(mux_top_track_36_undriven_sram_inv), + .out(chany_top_out[18]) + ); + mux_tree_tapbuf_size6 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[3], chanx_right_in[14], chanx_right_in[25], chany_bottom_in[7], chany_bottom_in[22]}), + .sram(mux_tree_tapbuf_size6_1_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size3 mux_top_track_44 + ( + .in({chanx_right_in[10], chanx_right_in[21], chany_bottom_in[16]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size4 mux_top_track_52 + ( + .in({chanx_right_in[0], chanx_right_in[11], chanx_right_in[22], chany_bottom_in[18]}), + .sram(mux_tree_tapbuf_size4_1_sram), + .sram_inv(mux_top_track_52_undriven_sram_inv), + .out(chany_top_out[26]) + ); + mux_tree_tapbuf_size7 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[4], chanx_right_in[15], chanx_right_in[26], chany_bottom_in[8], chany_bottom_in[23]}), + .sram(mux_tree_tapbuf_size7_1_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__8_.v new file mode 100644 index 0000000..413e5de --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__8_.v @@ -0,0 +1,957 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_0__8_ +( + bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chanx_right_in, + chany_bottom_in, + pReset, + prog_clk, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail, + chanx_right_out, + chany_bottom_out +); + + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + input ccff_head; + input [0:29]chanx_right_in; + input [0:29]chany_bottom_in; + input pReset; + input prog_clk; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + output [0:29]chanx_right_out; + output [0:29]chany_bottom_out; + + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head; + wire ccff_tail; + wire [0:29]chanx_right_in; + wire [0:29]chanx_right_out; + wire [0:29]chany_bottom_in; + wire [0:29]chany_bottom_out; + wire [0:1]mux_bottom_track_11_undriven_sram_inv; + wire [0:1]mux_bottom_track_13_undriven_sram_inv; + wire [0:1]mux_bottom_track_15_undriven_sram_inv; + wire [0:1]mux_bottom_track_17_undriven_sram_inv; + wire [0:1]mux_bottom_track_19_undriven_sram_inv; + wire [0:1]mux_bottom_track_1_undriven_sram_inv; + wire [0:1]mux_bottom_track_29_undriven_sram_inv; + wire [0:1]mux_bottom_track_31_undriven_sram_inv; + wire [0:1]mux_bottom_track_33_undriven_sram_inv; + wire [0:1]mux_bottom_track_35_undriven_sram_inv; + wire [0:1]mux_bottom_track_3_undriven_sram_inv; + wire [0:1]mux_bottom_track_45_undriven_sram_inv; + wire [0:1]mux_bottom_track_47_undriven_sram_inv; + wire [0:1]mux_bottom_track_49_undriven_sram_inv; + wire [0:1]mux_bottom_track_51_undriven_sram_inv; + wire [0:1]mux_bottom_track_5_undriven_sram_inv; + wire [0:1]mux_bottom_track_7_undriven_sram_inv; + wire [0:1]mux_bottom_track_9_undriven_sram_inv; + wire [0:2]mux_right_track_0_undriven_sram_inv; + wire [0:2]mux_right_track_10_undriven_sram_inv; + wire [0:1]mux_right_track_12_undriven_sram_inv; + wire [0:1]mux_right_track_14_undriven_sram_inv; + wire [0:1]mux_right_track_16_undriven_sram_inv; + wire [0:1]mux_right_track_18_undriven_sram_inv; + wire [0:1]mux_right_track_20_undriven_sram_inv; + wire [0:1]mux_right_track_22_undriven_sram_inv; + wire [0:1]mux_right_track_24_undriven_sram_inv; + wire [0:1]mux_right_track_26_undriven_sram_inv; + wire [0:1]mux_right_track_28_undriven_sram_inv; + wire [0:2]mux_right_track_2_undriven_sram_inv; + wire [0:1]mux_right_track_30_undriven_sram_inv; + wire [0:1]mux_right_track_32_undriven_sram_inv; + wire [0:1]mux_right_track_34_undriven_sram_inv; + wire [0:1]mux_right_track_36_undriven_sram_inv; + wire [0:1]mux_right_track_38_undriven_sram_inv; + wire [0:1]mux_right_track_40_undriven_sram_inv; + wire [0:1]mux_right_track_42_undriven_sram_inv; + wire [0:1]mux_right_track_44_undriven_sram_inv; + wire [0:1]mux_right_track_46_undriven_sram_inv; + wire [0:1]mux_right_track_48_undriven_sram_inv; + wire [0:2]mux_right_track_4_undriven_sram_inv; + wire [0:1]mux_right_track_50_undriven_sram_inv; + wire [0:1]mux_right_track_52_undriven_sram_inv; + wire [0:1]mux_right_track_54_undriven_sram_inv; + wire [0:1]mux_right_track_56_undriven_sram_inv; + wire [0:1]mux_right_track_58_undriven_sram_inv; + wire [0:2]mux_right_track_6_undriven_sram_inv; + wire [0:2]mux_right_track_8_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_11_sram; + wire [0:1]mux_tree_tapbuf_size2_12_sram; + wire [0:1]mux_tree_tapbuf_size2_13_sram; + wire [0:1]mux_tree_tapbuf_size2_14_sram; + wire [0:1]mux_tree_tapbuf_size2_15_sram; + wire [0:1]mux_tree_tapbuf_size2_16_sram; + wire [0:1]mux_tree_tapbuf_size2_17_sram; + wire [0:1]mux_tree_tapbuf_size2_18_sram; + wire [0:1]mux_tree_tapbuf_size2_19_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_20_sram; + wire [0:1]mux_tree_tapbuf_size2_21_sram; + wire [0:1]mux_tree_tapbuf_size2_22_sram; + wire [0:1]mux_tree_tapbuf_size2_23_sram; + wire [0:1]mux_tree_tapbuf_size2_24_sram; + wire [0:1]mux_tree_tapbuf_size2_25_sram; + wire [0:1]mux_tree_tapbuf_size2_26_sram; + wire [0:1]mux_tree_tapbuf_size2_27_sram; + wire [0:1]mux_tree_tapbuf_size2_28_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire mux_tree_tapbuf_size2_mem_19_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_20_ccff_tail; + wire mux_tree_tapbuf_size2_mem_21_ccff_tail; + wire mux_tree_tapbuf_size2_mem_22_ccff_tail; + wire mux_tree_tapbuf_size2_mem_23_ccff_tail; + wire mux_tree_tapbuf_size2_mem_24_ccff_tail; + wire mux_tree_tapbuf_size2_mem_25_ccff_tail; + wire mux_tree_tapbuf_size2_mem_26_ccff_tail; + wire mux_tree_tapbuf_size2_mem_27_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_10_sram; + wire [0:1]mux_tree_tapbuf_size3_11_sram; + wire [0:1]mux_tree_tapbuf_size3_12_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire [0:1]mux_tree_tapbuf_size3_7_sram; + wire [0:1]mux_tree_tapbuf_size3_8_sram; + wire [0:1]mux_tree_tapbuf_size3_9_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_10_ccff_tail; + wire mux_tree_tapbuf_size3_mem_11_ccff_tail; + wire mux_tree_tapbuf_size3_mem_12_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire mux_tree_tapbuf_size3_mem_7_ccff_tail; + wire mux_tree_tapbuf_size3_mem_8_ccff_tail; + wire mux_tree_tapbuf_size3_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire [0:2]mux_tree_tapbuf_size5_5_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire mux_tree_tapbuf_size5_mem_5_ccff_tail; + wire pReset; + wire prog_clk; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + +assign chany_bottom_out[28] = chanx_right_in[0]; +assign chany_bottom_out[27] = chanx_right_in[1]; +assign chany_bottom_out[10] = chanx_right_in[18]; +assign chany_bottom_out[29] = chanx_right_in[29]; +assign chany_bottom_out[26] = chanx_right_in[2]; +assign chany_bottom_out[21] = chanx_right_in[7]; +assign chany_bottom_out[20] = chanx_right_in[8]; +assign chany_bottom_out[19] = chanx_right_in[9]; +assign chany_bottom_out[18] = chanx_right_in[10]; +assign chany_bottom_out[13] = chanx_right_in[15]; +assign chany_bottom_out[12] = chanx_right_in[16]; +assign chany_bottom_out[11] = chanx_right_in[17]; + mux_tree_tapbuf_size3_mem mem_bottom_track_1 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_11 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_13 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_15 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_17 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_19 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_29 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_3 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_31 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_33 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_35 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_45 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_25_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_47 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_26_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_49 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_27_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_5 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_51 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_28_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_7 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_12_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_9 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_0 + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_10 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_12 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_14 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_16 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_18 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_2 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_20 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_22 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_24 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_26 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_28 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_30 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_32 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_34 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_36 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_38 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_4 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_40 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_42 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_44 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_46 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_48 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_50 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_52 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_54 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_56 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_58 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_6 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_8 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size3 mux_bottom_track_1 + ( + .in({chanx_right_in[28], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_11_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_11 + ( + .in({chanx_right_in[23], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_16_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_13 + ( + .in({chanx_right_in[22], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_17_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_15 + ( + .in({chanx_right_in[21], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_18_sram), + .sram_inv(mux_bottom_track_15_undriven_sram_inv), + .out(chany_bottom_out[7]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_17 + ( + .in({chanx_right_in[20], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_19_sram), + .sram_inv(mux_bottom_track_17_undriven_sram_inv), + .out(chany_bottom_out[8]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_19 + ( + .in({chanx_right_in[19], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_20_sram), + .sram_inv(mux_bottom_track_19_undriven_sram_inv), + .out(chany_bottom_out[9]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_29 + ( + .in({chanx_right_in[14], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_3 + ( + .in({chanx_right_in[27], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_13_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_31 + ( + .in({chanx_right_in[13], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_22_sram), + .sram_inv(mux_bottom_track_31_undriven_sram_inv), + .out(chany_bottom_out[15]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_33 + ( + .in({chanx_right_in[12], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_23_sram), + .sram_inv(mux_bottom_track_33_undriven_sram_inv), + .out(chany_bottom_out[16]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_35 + ( + .in({chanx_right_in[11], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_24_sram), + .sram_inv(mux_bottom_track_35_undriven_sram_inv), + .out(chany_bottom_out[17]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_45 + ( + .in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_25_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_47 + ( + .in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_26_sram), + .sram_inv(mux_bottom_track_47_undriven_sram_inv), + .out(chany_bottom_out[23]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_49 + ( + .in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_27_sram), + .sram_inv(mux_bottom_track_49_undriven_sram_inv), + .out(chany_bottom_out[24]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_5 + ( + .in({chanx_right_in[26], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_14_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_51 + ( + .in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_28_sram), + .sram_inv(mux_bottom_track_51_undriven_sram_inv), + .out(chany_bottom_out[25]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_7 + ( + .in({chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_12_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_9 + ( + .in({chanx_right_in[24], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_15_sram), + .sram_inv(mux_bottom_track_9_undriven_sram_inv), + .out(chany_bottom_out[4]) + ); + mux_tree_tapbuf_size5 mux_right_track_0 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[28]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size5 mux_right_track_10 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[23]}), + .sram(mux_tree_tapbuf_size5_5_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size3 mux_right_track_12 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[22]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size3 mux_right_track_14 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[21]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_right_track_14_undriven_sram_inv), + .out(chanx_right_out[7]) + ); + mux_tree_tapbuf_size3 mux_right_track_16 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[20]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_right_track_16_undriven_sram_inv), + .out(chanx_right_out[8]) + ); + mux_tree_tapbuf_size2 mux_right_track_18 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[19]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_right_track_18_undriven_sram_inv), + .out(chanx_right_out[9]) + ); + mux_tree_tapbuf_size5 mux_right_track_2 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[27]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size2 mux_right_track_20 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[18]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_right_track_20_undriven_sram_inv), + .out(chanx_right_out[10]) + ); + mux_tree_tapbuf_size2 mux_right_track_22 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[17]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_right_track_22_undriven_sram_inv), + .out(chanx_right_out[11]) + ); + mux_tree_tapbuf_size2 mux_right_track_24 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[16]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_right_track_24_undriven_sram_inv), + .out(chanx_right_out[12]) + ); + mux_tree_tapbuf_size2 mux_right_track_26 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[15]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_right_track_26_undriven_sram_inv), + .out(chanx_right_out[13]) + ); + mux_tree_tapbuf_size3 mux_right_track_28 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[14]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size3 mux_right_track_30 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[13]}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_right_track_30_undriven_sram_inv), + .out(chanx_right_out[15]) + ); + mux_tree_tapbuf_size3 mux_right_track_32 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[12]}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_right_track_32_undriven_sram_inv), + .out(chanx_right_out[16]) + ); + mux_tree_tapbuf_size3 mux_right_track_34 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[11]}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_right_track_34_undriven_sram_inv), + .out(chanx_right_out[17]) + ); + mux_tree_tapbuf_size2 mux_right_track_36 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[10]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_right_track_36_undriven_sram_inv), + .out(chanx_right_out[18]) + ); + mux_tree_tapbuf_size2 mux_right_track_38 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[9]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_right_track_38_undriven_sram_inv), + .out(chanx_right_out[19]) + ); + mux_tree_tapbuf_size5 mux_right_track_4 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[26]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size2 mux_right_track_40 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[8]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_right_track_40_undriven_sram_inv), + .out(chanx_right_out[20]) + ); + mux_tree_tapbuf_size2 mux_right_track_42 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[7]}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_right_track_42_undriven_sram_inv), + .out(chanx_right_out[21]) + ); + mux_tree_tapbuf_size3 mux_right_track_44 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[6]}), + .sram(mux_tree_tapbuf_size3_7_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size3 mux_right_track_46 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[5]}), + .sram(mux_tree_tapbuf_size3_8_sram), + .sram_inv(mux_right_track_46_undriven_sram_inv), + .out(chanx_right_out[23]) + ); + mux_tree_tapbuf_size3 mux_right_track_48 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[4]}), + .sram(mux_tree_tapbuf_size3_9_sram), + .sram_inv(mux_right_track_48_undriven_sram_inv), + .out(chanx_right_out[24]) + ); + mux_tree_tapbuf_size2 mux_right_track_50 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[3]}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_right_track_50_undriven_sram_inv), + .out(chanx_right_out[25]) + ); + mux_tree_tapbuf_size2 mux_right_track_52 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[2]}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_right_track_52_undriven_sram_inv), + .out(chanx_right_out[26]) + ); + mux_tree_tapbuf_size2 mux_right_track_54 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[1]}), + .sram(mux_tree_tapbuf_size2_11_sram), + .sram_inv(mux_right_track_54_undriven_sram_inv), + .out(chanx_right_out[27]) + ); + mux_tree_tapbuf_size2 mux_right_track_56 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[0]}), + .sram(mux_tree_tapbuf_size2_12_sram), + .sram_inv(mux_right_track_56_undriven_sram_inv), + .out(chanx_right_out[28]) + ); + mux_tree_tapbuf_size3 mux_right_track_58 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[29]}), + .sram(mux_tree_tapbuf_size3_10_sram), + .sram_inv(mux_right_track_58_undriven_sram_inv), + .out(chanx_right_out[29]) + ); + mux_tree_tapbuf_size5 mux_right_track_6 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[25]}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size5 mux_right_track_8 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[24]}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_right_track_8_undriven_sram_inv), + .out(chanx_right_out[4]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__0_.v new file mode 100644 index 0000000..1636d61 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__0_.v @@ -0,0 +1,993 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_1__0_ +( + ccff_head, + chanx_left_in, + chanx_right_in, + chany_top_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + pReset, + prog_clk, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + ccff_tail, + chanx_left_out, + chanx_right_out, + chany_top_out +); + + input ccff_head; + input [0:29]chanx_left_in; + input [0:29]chanx_right_in; + input [0:29]chany_top_in; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + input pReset; + input prog_clk; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + output ccff_tail; + output [0:29]chanx_left_out; + output [0:29]chanx_right_out; + output [0:29]chany_top_out; + + wire ccff_head; + wire ccff_tail; + wire [0:29]chanx_left_in; + wire [0:29]chanx_left_out; + wire [0:29]chanx_right_in; + wire [0:29]chanx_right_out; + wire [0:29]chany_top_in; + wire [0:29]chany_top_out; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire [0:2]mux_left_track_11_undriven_sram_inv; + wire [0:2]mux_left_track_13_undriven_sram_inv; + wire [0:2]mux_left_track_1_undriven_sram_inv; + wire [0:2]mux_left_track_21_undriven_sram_inv; + wire [0:2]mux_left_track_29_undriven_sram_inv; + wire [0:2]mux_left_track_37_undriven_sram_inv; + wire [0:2]mux_left_track_3_undriven_sram_inv; + wire [0:2]mux_left_track_45_undriven_sram_inv; + wire [0:2]mux_left_track_53_undriven_sram_inv; + wire [0:2]mux_left_track_5_undriven_sram_inv; + wire [0:2]mux_left_track_7_undriven_sram_inv; + wire [0:2]mux_right_track_0_undriven_sram_inv; + wire [0:2]mux_right_track_10_undriven_sram_inv; + wire [0:2]mux_right_track_12_undriven_sram_inv; + wire [0:2]mux_right_track_20_undriven_sram_inv; + wire [0:2]mux_right_track_28_undriven_sram_inv; + wire [0:2]mux_right_track_2_undriven_sram_inv; + wire [0:2]mux_right_track_36_undriven_sram_inv; + wire [0:1]mux_right_track_44_undriven_sram_inv; + wire [0:2]mux_right_track_4_undriven_sram_inv; + wire [0:1]mux_right_track_52_undriven_sram_inv; + wire [0:2]mux_right_track_6_undriven_sram_inv; + wire [0:2]mux_top_track_0_undriven_sram_inv; + wire [0:2]mux_top_track_10_undriven_sram_inv; + wire [0:2]mux_top_track_12_undriven_sram_inv; + wire [0:2]mux_top_track_14_undriven_sram_inv; + wire [0:2]mux_top_track_16_undriven_sram_inv; + wire [0:2]mux_top_track_18_undriven_sram_inv; + wire [0:1]mux_top_track_20_undriven_sram_inv; + wire [0:1]mux_top_track_22_undriven_sram_inv; + wire [0:1]mux_top_track_24_undriven_sram_inv; + wire [0:1]mux_top_track_26_undriven_sram_inv; + wire [0:1]mux_top_track_28_undriven_sram_inv; + wire [0:2]mux_top_track_2_undriven_sram_inv; + wire [0:1]mux_top_track_30_undriven_sram_inv; + wire [0:1]mux_top_track_32_undriven_sram_inv; + wire [0:1]mux_top_track_34_undriven_sram_inv; + wire [0:1]mux_top_track_36_undriven_sram_inv; + wire [0:1]mux_top_track_40_undriven_sram_inv; + wire [0:1]mux_top_track_42_undriven_sram_inv; + wire [0:1]mux_top_track_44_undriven_sram_inv; + wire [0:1]mux_top_track_46_undriven_sram_inv; + wire [0:1]mux_top_track_48_undriven_sram_inv; + wire [0:2]mux_top_track_4_undriven_sram_inv; + wire [0:1]mux_top_track_50_undriven_sram_inv; + wire [0:1]mux_top_track_58_undriven_sram_inv; + wire [0:2]mux_top_track_6_undriven_sram_inv; + wire [0:2]mux_top_track_8_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire [0:2]mux_tree_tapbuf_size4_0_sram; + wire [0:2]mux_tree_tapbuf_size4_1_sram; + wire [0:2]mux_tree_tapbuf_size4_2_sram; + wire [0:2]mux_tree_tapbuf_size4_3_sram; + wire [0:2]mux_tree_tapbuf_size4_4_sram; + wire [0:2]mux_tree_tapbuf_size4_5_sram; + wire mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire mux_tree_tapbuf_size4_mem_4_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire [0:2]mux_tree_tapbuf_size5_5_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire mux_tree_tapbuf_size5_mem_5_ccff_tail; + wire [0:2]mux_tree_tapbuf_size6_0_sram; + wire [0:2]mux_tree_tapbuf_size6_10_sram; + wire [0:2]mux_tree_tapbuf_size6_11_sram; + wire [0:2]mux_tree_tapbuf_size6_12_sram; + wire [0:2]mux_tree_tapbuf_size6_1_sram; + wire [0:2]mux_tree_tapbuf_size6_2_sram; + wire [0:2]mux_tree_tapbuf_size6_3_sram; + wire [0:2]mux_tree_tapbuf_size6_4_sram; + wire [0:2]mux_tree_tapbuf_size6_5_sram; + wire [0:2]mux_tree_tapbuf_size6_6_sram; + wire [0:2]mux_tree_tapbuf_size6_7_sram; + wire [0:2]mux_tree_tapbuf_size6_8_sram; + wire [0:2]mux_tree_tapbuf_size6_9_sram; + wire mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire mux_tree_tapbuf_size6_mem_10_ccff_tail; + wire mux_tree_tapbuf_size6_mem_11_ccff_tail; + wire mux_tree_tapbuf_size6_mem_12_ccff_tail; + wire mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire mux_tree_tapbuf_size6_mem_7_ccff_tail; + wire mux_tree_tapbuf_size6_mem_8_ccff_tail; + wire mux_tree_tapbuf_size6_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size7_0_sram; + wire [0:2]mux_tree_tapbuf_size7_1_sram; + wire [0:2]mux_tree_tapbuf_size7_2_sram; + wire [0:2]mux_tree_tapbuf_size7_3_sram; + wire [0:2]mux_tree_tapbuf_size7_4_sram; + wire mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire mux_tree_tapbuf_size7_mem_4_ccff_tail; + wire pReset; + wire prog_clk; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + +assign chany_top_out[19] = top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; +assign chanx_left_out[4] = chanx_right_in[3]; +assign chanx_left_out[17] = chanx_right_in[16]; +assign chanx_left_out[19] = chanx_right_in[18]; +assign chanx_left_out[20] = chanx_right_in[19]; +assign chanx_left_out[21] = chanx_right_in[20]; +assign chanx_left_out[23] = chanx_right_in[22]; +assign chanx_left_out[24] = chanx_right_in[23]; +assign chanx_left_out[25] = chanx_right_in[24]; +assign chanx_left_out[27] = chanx_right_in[26]; +assign chanx_left_out[28] = chanx_right_in[27]; +assign chanx_left_out[29] = chanx_right_in[28]; +assign chanx_left_out[7] = chanx_right_in[6]; +assign chany_top_out[28] = chanx_left_in[2]; +assign chanx_right_out[4] = chanx_left_in[3]; +assign chany_top_out[27] = chanx_left_in[4]; +assign chany_top_out[26] = chanx_left_in[5]; +assign chanx_right_out[7] = chanx_left_in[6]; +assign chanx_right_out[8] = chanx_left_in[7]; +assign chanx_right_out[9] = chanx_left_in[8]; +assign chanx_right_out[11] = chanx_left_in[10]; +assign chanx_right_out[12] = chanx_left_in[11]; +assign chanx_right_out[13] = chanx_left_in[12]; +assign chanx_left_out[8] = chanx_right_in[7]; +assign chanx_right_out[15] = chanx_left_in[14]; +assign chanx_right_out[16] = chanx_left_in[15]; +assign chanx_right_out[17] = chanx_left_in[16]; +assign chanx_right_out[19] = chanx_left_in[18]; +assign chanx_right_out[20] = chanx_left_in[19]; +assign chanx_right_out[21] = chanx_left_in[20]; +assign chanx_right_out[23] = chanx_left_in[22]; +assign chanx_right_out[24] = chanx_left_in[23]; +assign chanx_right_out[25] = chanx_left_in[24]; +assign chanx_right_out[27] = chanx_left_in[26]; +assign chanx_left_out[9] = chanx_right_in[8]; +assign chanx_right_out[28] = chanx_left_in[27]; +assign chanx_right_out[29] = chanx_left_in[28]; +assign chanx_left_out[11] = chanx_right_in[10]; +assign chanx_left_out[12] = chanx_right_in[11]; +assign chanx_left_out[13] = chanx_right_in[12]; +assign chanx_left_out[15] = chanx_right_in[14]; +assign chanx_left_out[16] = chanx_right_in[15]; + mux_tree_tapbuf_size7_mem mem_left_track_1 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram) + ); + mux_tree_tapbuf_size7_mem mem_left_track_11 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_13 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_21 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_11_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_29 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_12_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_3 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_37 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_12_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_45 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_5 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_53 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_7 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_0 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram) + ); + mux_tree_tapbuf_size7_mem mem_right_track_10 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_12 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_2 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_20 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_28 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_36 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_4 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_44 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_52 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size7_mem mem_right_track_6 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram) + ); + mux_tree_tapbuf_size7_mem mem_top_track_0 + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_10 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size4_mem mem_top_track_12 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram) + ); + mux_tree_tapbuf_size4_mem mem_top_track_14 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram) + ); + mux_tree_tapbuf_size4_mem mem_top_track_16 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram) + ); + mux_tree_tapbuf_size4_mem mem_top_track_18 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_2 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_20 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_22 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_24 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_26 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_28 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_30 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_32 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_34 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_36 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_4 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_40 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_42 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_44 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_46 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_48 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_50 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_58 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_6 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_8 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram) + ); + mux_tree_tapbuf_size7 mux_left_track_1 + ( + .in({chany_top_in[0], chany_top_in[11], chany_top_in[22], chanx_right_in[3], chanx_right_in[19], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_3_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size7 mux_left_track_11 + ( + .in({chany_top_in[7], chany_top_in[18], chany_top_in[29], chanx_right_in[10], chanx_right_in[24], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_4_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size6 mux_left_track_13 + ( + .in({chany_top_in[6], chany_top_in[17], chany_top_in[28], chanx_right_in[11], chanx_right_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_10_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size6 mux_left_track_21 + ( + .in({chany_top_in[5], chany_top_in[16], chany_top_in[27], chanx_right_in[12], chanx_right_in[27], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_11_sram), + .sram_inv(mux_left_track_21_undriven_sram_inv), + .out(chanx_left_out[10]) + ); + mux_tree_tapbuf_size6 mux_left_track_29 + ( + .in({chany_top_in[4], chany_top_in[15], chany_top_in[26], chanx_right_in[14], chanx_right_in[28], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_12_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size5 mux_left_track_3 + ( + .in({chany_top_in[10], chany_top_in[21], chanx_right_in[6], chanx_right_in[20], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size5 mux_left_track_37 + ( + .in({chany_top_in[3], chany_top_in[14], chany_top_in[25], chanx_right_in[15], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_5_sram), + .sram_inv(mux_left_track_37_undriven_sram_inv), + .out(chanx_left_out[18]) + ); + mux_tree_tapbuf_size4 mux_left_track_45 + ( + .in({chany_top_in[2], chany_top_in[13], chany_top_in[24], chanx_right_in[16]}), + .sram(mux_tree_tapbuf_size4_4_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size5 mux_left_track_5 + ( + .in({chany_top_in[9], chany_top_in[20], chanx_right_in[7], chanx_right_in[22], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size4 mux_left_track_53 + ( + .in({chany_top_in[1], chany_top_in[12], chany_top_in[23], chanx_right_in[18]}), + .sram(mux_tree_tapbuf_size4_5_sram), + .sram_inv(mux_left_track_53_undriven_sram_inv), + .out(chanx_left_out[26]) + ); + mux_tree_tapbuf_size6 mux_left_track_7 + ( + .in({chany_top_in[8], chany_top_in[19], chanx_right_in[8], chanx_right_in[23], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_9_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size6 mux_right_track_0 + ( + .in({chany_top_in[10], chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size6_3_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size7 mux_right_track_10 + ( + .in({chany_top_in[3], chany_top_in[14], chany_top_in[25], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size7_2_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size6 mux_right_track_12 + ( + .in({chany_top_in[4], chany_top_in[15], chany_top_in[26], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[11], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size6_6_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size6 mux_right_track_2 + ( + .in({chany_top_in[0], chany_top_in[11], chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size6_4_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size6 mux_right_track_20 + ( + .in({chany_top_in[5], chany_top_in[16], chany_top_in[27], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size6_7_sram), + .sram_inv(mux_right_track_20_undriven_sram_inv), + .out(chanx_right_out[10]) + ); + mux_tree_tapbuf_size6 mux_right_track_28 + ( + .in({chany_top_in[6], chany_top_in[17], chany_top_in[28], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size6_8_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size5 mux_right_track_36 + ( + .in({chany_top_in[7], chany_top_in[18], chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_right_track_36_undriven_sram_inv), + .out(chanx_right_out[18]) + ); + mux_tree_tapbuf_size6 mux_right_track_4 + ( + .in({chany_top_in[1], chany_top_in[12], chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size6_5_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size3 mux_right_track_44 + ( + .in({chany_top_in[8], chany_top_in[19], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size3 mux_right_track_52 + ( + .in({chany_top_in[9], chany_top_in[20], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_right_track_52_undriven_sram_inv), + .out(chanx_right_out[26]) + ); + mux_tree_tapbuf_size7 mux_right_track_6 + ( + .in({chany_top_in[2], chany_top_in[13], chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size7_1_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size7 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[1], chanx_right_in[3], chanx_left_in[0], chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size7_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size5 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[11], chanx_right_in[13], chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size4 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_right_in[12], chanx_right_in[17], chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size4_0_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size4 mux_top_track_14 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_right_in[14], chanx_right_in[21], chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size4_1_sram), + .sram_inv(mux_top_track_14_undriven_sram_inv), + .out(chany_top_out[7]) + ); + mux_tree_tapbuf_size4 mux_top_track_16 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_right_in[15], chanx_right_in[25], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size4_2_sram), + .sram_inv(mux_top_track_16_undriven_sram_inv), + .out(chany_top_out[8]) + ); + mux_tree_tapbuf_size4 mux_top_track_18 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_right_in[16], chanx_right_in[29], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size4_3_sram), + .sram_inv(mux_top_track_18_undriven_sram_inv), + .out(chany_top_out[9]) + ); + mux_tree_tapbuf_size6 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[2], chanx_right_in[6], chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size6_0_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size3 mux_top_track_20 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_right_in[18], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_top_track_20_undriven_sram_inv), + .out(chany_top_out[10]) + ); + mux_tree_tapbuf_size3 mux_top_track_22 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[19], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_top_track_22_undriven_sram_inv), + .out(chany_top_out[11]) + ); + mux_tree_tapbuf_size3 mux_top_track_24 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[20], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_top_track_24_undriven_sram_inv), + .out(chany_top_out[12]) + ); + mux_tree_tapbuf_size3 mux_top_track_26 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[22], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_top_track_26_undriven_sram_inv), + .out(chany_top_out[13]) + ); + mux_tree_tapbuf_size2 mux_top_track_28 + ( + .in({chanx_right_in[23], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size2 mux_top_track_30 + ( + .in({chanx_right_in[24], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_top_track_30_undriven_sram_inv), + .out(chany_top_out[15]) + ); + mux_tree_tapbuf_size2 mux_top_track_32 + ( + .in({chanx_right_in[26], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_top_track_32_undriven_sram_inv), + .out(chany_top_out[16]) + ); + mux_tree_tapbuf_size2 mux_top_track_34 + ( + .in({chanx_right_in[27], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_top_track_34_undriven_sram_inv), + .out(chany_top_out[17]) + ); + mux_tree_tapbuf_size3 mux_top_track_36 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_right_in[28], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_top_track_36_undriven_sram_inv), + .out(chany_top_out[18]) + ); + mux_tree_tapbuf_size5 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[4], chanx_right_in[7], chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size2 mux_top_track_40 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_top_track_40_undriven_sram_inv), + .out(chany_top_out[20]) + ); + mux_tree_tapbuf_size2 mux_top_track_42 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_top_track_42_undriven_sram_inv), + .out(chany_top_out[21]) + ); + mux_tree_tapbuf_size2 mux_top_track_44 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size2 mux_top_track_46 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_top_track_46_undriven_sram_inv), + .out(chany_top_out[23]) + ); + mux_tree_tapbuf_size2 mux_top_track_48 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_top_track_48_undriven_sram_inv), + .out(chany_top_out[24]) + ); + mux_tree_tapbuf_size2 mux_top_track_50 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_top_track_50_undriven_sram_inv), + .out(chany_top_out[25]) + ); + mux_tree_tapbuf_size2 mux_top_track_58 + ( + .in({chanx_right_in[0], chanx_left_in[1]}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_top_track_58_undriven_sram_inv), + .out(chany_top_out[29]) + ); + mux_tree_tapbuf_size6 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[5], chanx_right_in[8], chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size6_1_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); + mux_tree_tapbuf_size6 mux_top_track_8 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[9], chanx_right_in[10], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size6_2_sram), + .sram_inv(mux_top_track_8_undriven_sram_inv), + .out(chany_top_out[4]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__1_.v new file mode 100644 index 0000000..0092db3 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__1_.v @@ -0,0 +1,1009 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_1__1_ +( + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + ccff_head, + chanx_left_in, + chanx_right_in, + chany_bottom_in, + chany_top_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + pReset, + prog_clk, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + ccff_tail, + chanx_left_out, + chanx_right_out, + chany_bottom_out, + chany_top_out +); + + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input ccff_head; + input [0:29]chanx_left_in; + input [0:29]chanx_right_in; + input [0:29]chany_bottom_in; + input [0:29]chany_top_in; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input pReset; + input prog_clk; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + output ccff_tail; + output [0:29]chanx_left_out; + output [0:29]chanx_right_out; + output [0:29]chany_bottom_out; + output [0:29]chany_top_out; + + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire ccff_head; + wire ccff_tail; + wire [0:29]chanx_left_in; + wire [0:29]chanx_left_out; + wire [0:29]chanx_right_in; + wire [0:29]chanx_right_out; + wire [0:29]chany_bottom_in; + wire [0:29]chany_bottom_out; + wire [0:29]chany_top_in; + wire [0:29]chany_top_out; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire [0:3]mux_bottom_track_11_undriven_sram_inv; + wire [0:3]mux_bottom_track_13_undriven_sram_inv; + wire [0:3]mux_bottom_track_1_undriven_sram_inv; + wire [0:3]mux_bottom_track_21_undriven_sram_inv; + wire [0:3]mux_bottom_track_29_undriven_sram_inv; + wire [0:2]mux_bottom_track_37_undriven_sram_inv; + wire [0:3]mux_bottom_track_3_undriven_sram_inv; + wire [0:2]mux_bottom_track_45_undriven_sram_inv; + wire [0:2]mux_bottom_track_53_undriven_sram_inv; + wire [0:3]mux_bottom_track_5_undriven_sram_inv; + wire [0:3]mux_bottom_track_7_undriven_sram_inv; + wire [0:3]mux_left_track_11_undriven_sram_inv; + wire [0:3]mux_left_track_13_undriven_sram_inv; + wire [0:3]mux_left_track_1_undriven_sram_inv; + wire [0:3]mux_left_track_21_undriven_sram_inv; + wire [0:3]mux_left_track_29_undriven_sram_inv; + wire [0:2]mux_left_track_37_undriven_sram_inv; + wire [0:3]mux_left_track_3_undriven_sram_inv; + wire [0:2]mux_left_track_45_undriven_sram_inv; + wire [0:2]mux_left_track_53_undriven_sram_inv; + wire [0:3]mux_left_track_5_undriven_sram_inv; + wire [0:3]mux_left_track_7_undriven_sram_inv; + wire [0:3]mux_right_track_0_undriven_sram_inv; + wire [0:3]mux_right_track_10_undriven_sram_inv; + wire [0:3]mux_right_track_12_undriven_sram_inv; + wire [0:3]mux_right_track_20_undriven_sram_inv; + wire [0:3]mux_right_track_28_undriven_sram_inv; + wire [0:3]mux_right_track_2_undriven_sram_inv; + wire [0:2]mux_right_track_36_undriven_sram_inv; + wire [0:2]mux_right_track_44_undriven_sram_inv; + wire [0:3]mux_right_track_4_undriven_sram_inv; + wire [0:2]mux_right_track_52_undriven_sram_inv; + wire [0:3]mux_right_track_6_undriven_sram_inv; + wire [0:3]mux_top_track_0_undriven_sram_inv; + wire [0:3]mux_top_track_10_undriven_sram_inv; + wire [0:3]mux_top_track_12_undriven_sram_inv; + wire [0:3]mux_top_track_20_undriven_sram_inv; + wire [0:3]mux_top_track_28_undriven_sram_inv; + wire [0:3]mux_top_track_2_undriven_sram_inv; + wire [0:2]mux_top_track_36_undriven_sram_inv; + wire [0:2]mux_top_track_44_undriven_sram_inv; + wire [0:3]mux_top_track_4_undriven_sram_inv; + wire [0:2]mux_top_track_52_undriven_sram_inv; + wire [0:3]mux_top_track_6_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire [0:3]mux_tree_tapbuf_size10_10_sram; + wire [0:3]mux_tree_tapbuf_size10_11_sram; + wire [0:3]mux_tree_tapbuf_size10_1_sram; + wire [0:3]mux_tree_tapbuf_size10_2_sram; + wire [0:3]mux_tree_tapbuf_size10_3_sram; + wire [0:3]mux_tree_tapbuf_size10_4_sram; + wire [0:3]mux_tree_tapbuf_size10_5_sram; + wire [0:3]mux_tree_tapbuf_size10_6_sram; + wire [0:3]mux_tree_tapbuf_size10_7_sram; + wire [0:3]mux_tree_tapbuf_size10_8_sram; + wire [0:3]mux_tree_tapbuf_size10_9_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire mux_tree_tapbuf_size10_mem_10_ccff_tail; + wire mux_tree_tapbuf_size10_mem_11_ccff_tail; + wire mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire mux_tree_tapbuf_size10_mem_7_ccff_tail; + wire mux_tree_tapbuf_size10_mem_8_ccff_tail; + wire mux_tree_tapbuf_size10_mem_9_ccff_tail; + wire [0:3]mux_tree_tapbuf_size11_0_sram; + wire [0:3]mux_tree_tapbuf_size11_1_sram; + wire [0:3]mux_tree_tapbuf_size11_2_sram; + wire [0:3]mux_tree_tapbuf_size11_3_sram; + wire [0:3]mux_tree_tapbuf_size11_4_sram; + wire [0:3]mux_tree_tapbuf_size11_5_sram; + wire [0:3]mux_tree_tapbuf_size11_6_sram; + wire [0:3]mux_tree_tapbuf_size11_7_sram; + wire mux_tree_tapbuf_size11_mem_0_ccff_tail; + wire mux_tree_tapbuf_size11_mem_1_ccff_tail; + wire mux_tree_tapbuf_size11_mem_2_ccff_tail; + wire mux_tree_tapbuf_size11_mem_3_ccff_tail; + wire mux_tree_tapbuf_size11_mem_4_ccff_tail; + wire mux_tree_tapbuf_size11_mem_5_ccff_tail; + wire mux_tree_tapbuf_size11_mem_6_ccff_tail; + wire mux_tree_tapbuf_size11_mem_7_ccff_tail; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire [0:3]mux_tree_tapbuf_size12_4_sram; + wire [0:3]mux_tree_tapbuf_size12_5_sram; + wire [0:3]mux_tree_tapbuf_size12_6_sram; + wire [0:3]mux_tree_tapbuf_size12_7_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire mux_tree_tapbuf_size12_mem_7_ccff_tail; + wire [0:2]mux_tree_tapbuf_size6_0_sram; + wire [0:2]mux_tree_tapbuf_size6_10_sram; + wire [0:2]mux_tree_tapbuf_size6_11_sram; + wire [0:2]mux_tree_tapbuf_size6_1_sram; + wire [0:2]mux_tree_tapbuf_size6_2_sram; + wire [0:2]mux_tree_tapbuf_size6_3_sram; + wire [0:2]mux_tree_tapbuf_size6_4_sram; + wire [0:2]mux_tree_tapbuf_size6_5_sram; + wire [0:2]mux_tree_tapbuf_size6_6_sram; + wire [0:2]mux_tree_tapbuf_size6_7_sram; + wire [0:2]mux_tree_tapbuf_size6_8_sram; + wire [0:2]mux_tree_tapbuf_size6_9_sram; + wire mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire mux_tree_tapbuf_size6_mem_10_ccff_tail; + wire mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire mux_tree_tapbuf_size6_mem_7_ccff_tail; + wire mux_tree_tapbuf_size6_mem_8_ccff_tail; + wire mux_tree_tapbuf_size6_mem_9_ccff_tail; + wire [0:3]mux_tree_tapbuf_size9_0_sram; + wire [0:3]mux_tree_tapbuf_size9_1_sram; + wire [0:3]mux_tree_tapbuf_size9_2_sram; + wire [0:3]mux_tree_tapbuf_size9_3_sram; + wire mux_tree_tapbuf_size9_mem_0_ccff_tail; + wire mux_tree_tapbuf_size9_mem_1_ccff_tail; + wire mux_tree_tapbuf_size9_mem_2_ccff_tail; + wire mux_tree_tapbuf_size9_mem_3_ccff_tail; + wire pReset; + wire prog_clk; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + +assign chany_bottom_out[4] = chany_top_in[3]; +assign chany_bottom_out[7] = chany_top_in[6]; +assign chany_bottom_out[19] = chany_top_in[18]; +assign chany_bottom_out[20] = chany_top_in[19]; +assign chany_bottom_out[21] = chany_top_in[20]; +assign chany_bottom_out[23] = chany_top_in[22]; +assign chany_bottom_out[24] = chany_top_in[23]; +assign chany_bottom_out[25] = chany_top_in[24]; +assign chany_bottom_out[27] = chany_top_in[26]; +assign chany_bottom_out[28] = chany_top_in[27]; +assign chany_bottom_out[29] = chany_top_in[28]; +assign chanx_left_out[4] = chanx_right_in[3]; +assign chany_bottom_out[8] = chany_top_in[7]; +assign chanx_left_out[7] = chanx_right_in[6]; +assign chanx_left_out[8] = chanx_right_in[7]; +assign chanx_left_out[9] = chanx_right_in[8]; +assign chanx_left_out[11] = chanx_right_in[10]; +assign chanx_left_out[12] = chanx_right_in[11]; +assign chanx_left_out[13] = chanx_right_in[12]; +assign chanx_left_out[15] = chanx_right_in[14]; +assign chanx_left_out[16] = chanx_right_in[15]; +assign chanx_left_out[17] = chanx_right_in[16]; +assign chanx_left_out[19] = chanx_right_in[18]; +assign chany_bottom_out[9] = chany_top_in[8]; +assign chanx_left_out[20] = chanx_right_in[19]; +assign chanx_left_out[21] = chanx_right_in[20]; +assign chanx_left_out[23] = chanx_right_in[22]; +assign chanx_left_out[24] = chanx_right_in[23]; +assign chanx_left_out[25] = chanx_right_in[24]; +assign chanx_left_out[27] = chanx_right_in[26]; +assign chanx_left_out[28] = chanx_right_in[27]; +assign chanx_left_out[29] = chanx_right_in[28]; +assign chany_top_out[4] = chany_bottom_in[3]; +assign chany_top_out[7] = chany_bottom_in[6]; +assign chany_bottom_out[11] = chany_top_in[10]; +assign chany_top_out[8] = chany_bottom_in[7]; +assign chany_top_out[9] = chany_bottom_in[8]; +assign chany_top_out[11] = chany_bottom_in[10]; +assign chany_top_out[12] = chany_bottom_in[11]; +assign chany_top_out[13] = chany_bottom_in[12]; +assign chany_top_out[15] = chany_bottom_in[14]; +assign chany_top_out[16] = chany_bottom_in[15]; +assign chany_top_out[17] = chany_bottom_in[16]; +assign chany_top_out[19] = chany_bottom_in[18]; +assign chany_top_out[20] = chany_bottom_in[19]; +assign chany_bottom_out[12] = chany_top_in[11]; +assign chany_top_out[21] = chany_bottom_in[20]; +assign chany_top_out[23] = chany_bottom_in[22]; +assign chany_top_out[24] = chany_bottom_in[23]; +assign chany_top_out[25] = chany_bottom_in[24]; +assign chany_top_out[27] = chany_bottom_in[26]; +assign chany_top_out[28] = chany_bottom_in[27]; +assign chany_top_out[29] = chany_bottom_in[28]; +assign chanx_right_out[4] = chanx_left_in[3]; +assign chanx_right_out[7] = chanx_left_in[6]; +assign chanx_right_out[8] = chanx_left_in[7]; +assign chany_bottom_out[13] = chany_top_in[12]; +assign chanx_right_out[9] = chanx_left_in[8]; +assign chanx_right_out[11] = chanx_left_in[10]; +assign chanx_right_out[12] = chanx_left_in[11]; +assign chanx_right_out[13] = chanx_left_in[12]; +assign chanx_right_out[15] = chanx_left_in[14]; +assign chanx_right_out[16] = chanx_left_in[15]; +assign chanx_right_out[17] = chanx_left_in[16]; +assign chanx_right_out[19] = chanx_left_in[18]; +assign chanx_right_out[20] = chanx_left_in[19]; +assign chanx_right_out[21] = chanx_left_in[20]; +assign chany_bottom_out[15] = chany_top_in[14]; +assign chanx_right_out[23] = chanx_left_in[22]; +assign chanx_right_out[24] = chanx_left_in[23]; +assign chanx_right_out[25] = chanx_left_in[24]; +assign chanx_right_out[27] = chanx_left_in[26]; +assign chanx_right_out[28] = chanx_left_in[27]; +assign chanx_right_out[29] = chanx_left_in[28]; +assign chany_bottom_out[16] = chany_top_in[15]; +assign chany_bottom_out[17] = chany_top_in[16]; + mux_tree_tapbuf_size11_mem mem_bottom_track_1 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size11_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_4_sram) + ); + mux_tree_tapbuf_size12_mem mem_bottom_track_11 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram) + ); + mux_tree_tapbuf_size10_mem mem_bottom_track_13 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram) + ); + mux_tree_tapbuf_size10_mem mem_bottom_track_21 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_8_sram) + ); + mux_tree_tapbuf_size9_mem mem_bottom_track_29 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_2_sram) + ); + mux_tree_tapbuf_size11_mem mem_bottom_track_3 + ( + .ccff_head(mux_tree_tapbuf_size11_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size11_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_5_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_37 + ( + .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_45 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram) + ); + mux_tree_tapbuf_size10_mem mem_bottom_track_5 + ( + .ccff_head(mux_tree_tapbuf_size11_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_53 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram) + ); + mux_tree_tapbuf_size12_mem mem_bottom_track_7 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram) + ); + mux_tree_tapbuf_size11_mem mem_left_track_1 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size11_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_6_sram) + ); + mux_tree_tapbuf_size12_mem mem_left_track_11 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram) + ); + mux_tree_tapbuf_size10_mem mem_left_track_13 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_10_sram) + ); + mux_tree_tapbuf_size10_mem mem_left_track_21 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_11_sram) + ); + mux_tree_tapbuf_size9_mem mem_left_track_29 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_3_sram) + ); + mux_tree_tapbuf_size11_mem mem_left_track_3 + ( + .ccff_head(mux_tree_tapbuf_size11_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size11_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_7_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_37 + ( + .ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_45 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram) + ); + mux_tree_tapbuf_size10_mem mem_left_track_5 + ( + .ccff_head(mux_tree_tapbuf_size11_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_9_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_53 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size6_11_sram) + ); + mux_tree_tapbuf_size12_mem mem_left_track_7 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram) + ); + mux_tree_tapbuf_size11_mem mem_right_track_0 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_track_10 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_track_12 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram) + ); + mux_tree_tapbuf_size11_mem mem_right_track_2 + ( + .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_3_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_track_20 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram) + ); + mux_tree_tapbuf_size9_mem mem_right_track_28 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_36 + ( + .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_track_4 + ( + .ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_44 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_52 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_track_6 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size11_mem mem_top_track_0 + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_track_10 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_track_12 + ( + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram) + ); + mux_tree_tapbuf_size11_mem mem_top_track_2 + ( + .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_1_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_track_20 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram) + ); + mux_tree_tapbuf_size9_mem mem_top_track_28 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_36 + ( + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_track_4 + ( + .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_44 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_52 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_track_6 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size11 mux_bottom_track_1 + ( + .in({chany_top_in[3], chany_top_in[19], chanx_right_in[3], chanx_right_in[19], chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[1], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size11_4_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size12 mux_bottom_track_11 + ( + .in({chany_top_in[10], chany_top_in[24], chanx_right_in[9], chanx_right_in[10], chanx_right_in[24], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[9], chanx_left_in[10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size12_5_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size10 mux_bottom_track_13 + ( + .in({chany_top_in[11], chany_top_in[26], chanx_right_in[5], chanx_right_in[11], chanx_right_in[26], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[11], chanx_left_in[13], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size10_7_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size10 mux_bottom_track_21 + ( + .in({chany_top_in[12], chany_top_in[27], chanx_right_in[4], chanx_right_in[12], chanx_right_in[27], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[12], chanx_left_in[17], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size10_8_sram), + .sram_inv(mux_bottom_track_21_undriven_sram_inv), + .out(chany_bottom_out[10]) + ); + mux_tree_tapbuf_size9 mux_bottom_track_29 + ( + .in({chany_top_in[14], chany_top_in[28], chanx_right_in[2], chanx_right_in[14], chanx_right_in[28], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[14], chanx_left_in[21], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size9_2_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size11 mux_bottom_track_3 + ( + .in({chany_top_in[6], chany_top_in[20], chanx_right_in[6], chanx_right_in[20], chanx_right_in[21], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[2], chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size11_5_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_37 + ( + .in({chany_top_in[15], chanx_right_in[1], chanx_right_in[15], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[15], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size6_6_sram), + .sram_inv(mux_bottom_track_37_undriven_sram_inv), + .out(chany_bottom_out[18]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_45 + ( + .in({chany_top_in[16], chanx_right_in[0], chanx_right_in[16], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[16], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size6_7_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size10 mux_bottom_track_5 + ( + .in({chany_top_in[7], chany_top_in[22], chanx_right_in[7], chanx_right_in[17], chanx_right_in[22], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[4], chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size10_6_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_53 + ( + .in({chany_top_in[18], chanx_right_in[18], chanx_right_in[29], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[0], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size6_8_sram), + .sram_inv(mux_bottom_track_53_undriven_sram_inv), + .out(chany_bottom_out[26]) + ); + mux_tree_tapbuf_size12 mux_bottom_track_7 + ( + .in({chany_top_in[8], chany_top_in[23], chanx_right_in[8], chanx_right_in[13], chanx_right_in[23], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[5], chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size12_4_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size11 mux_left_track_1 + ( + .in({chany_top_in[0], chany_top_in[3], chany_top_in[19], chanx_right_in[3], chanx_right_in[19], chany_bottom_in[3], chany_bottom_in[19], chany_bottom_in[29], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size11_6_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size12 mux_left_track_11 + ( + .in({chany_top_in[10], chany_top_in[17], chany_top_in[24], chanx_right_in[10], chanx_right_in[24], chany_bottom_in[4], chany_bottom_in[10], chany_bottom_in[24], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size12_7_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size10 mux_left_track_13 + ( + .in({chany_top_in[11], chany_top_in[13], chany_top_in[26], chanx_right_in[11], chanx_right_in[26], chany_bottom_in[5], chany_bottom_in[11], chany_bottom_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size10_10_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size10 mux_left_track_21 + ( + .in({chany_top_in[9], chany_top_in[12], chany_top_in[27], chanx_right_in[12], chanx_right_in[27], chany_bottom_in[9], chany_bottom_in[12], chany_bottom_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size10_11_sram), + .sram_inv(mux_left_track_21_undriven_sram_inv), + .out(chanx_left_out[10]) + ); + mux_tree_tapbuf_size9 mux_left_track_29 + ( + .in({chany_top_in[5], chany_top_in[14], chany_top_in[28], chanx_right_in[14], chanx_right_in[28], chany_bottom_in[13], chany_bottom_in[14], chany_bottom_in[28], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size9_3_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size11 mux_left_track_3 + ( + .in({chany_top_in[6], chany_top_in[20], chany_top_in[29], chanx_right_in[6], chanx_right_in[20], chany_bottom_in[0], chany_bottom_in[6], chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size11_7_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size6 mux_left_track_37 + ( + .in({chany_top_in[4], chany_top_in[15], chanx_right_in[15], chany_bottom_in[15], chany_bottom_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size6_9_sram), + .sram_inv(mux_left_track_37_undriven_sram_inv), + .out(chanx_left_out[18]) + ); + mux_tree_tapbuf_size6 mux_left_track_45 + ( + .in({chany_top_in[2], chany_top_in[16], chanx_right_in[16], chany_bottom_in[16], chany_bottom_in[21], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size6_10_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size10 mux_left_track_5 + ( + .in({chany_top_in[7], chany_top_in[22], chany_top_in[25], chanx_right_in[7], chanx_right_in[22], chany_bottom_in[1], chany_bottom_in[7], chany_bottom_in[22], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size10_9_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size6 mux_left_track_53 + ( + .in({chany_top_in[1], chany_top_in[18], chanx_right_in[18], chany_bottom_in[18], chany_bottom_in[25], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size6_11_sram), + .sram_inv(mux_left_track_53_undriven_sram_inv), + .out(chanx_left_out[26]) + ); + mux_tree_tapbuf_size12 mux_left_track_7 + ( + .in({chany_top_in[8], chany_top_in[21], chany_top_in[23], chanx_right_in[8], chanx_right_in[23], chany_bottom_in[2], chany_bottom_in[8], chany_bottom_in[23], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size12_6_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size11 mux_right_track_0 + ( + .in({chany_top_in[3], chany_top_in[19], chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[3], chany_bottom_in[19], chany_bottom_in[25], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size11_2_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size12 mux_right_track_10 + ( + .in({chany_top_in[4], chany_top_in[10], chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[9], chany_bottom_in[10], chany_bottom_in[24], chanx_left_in[10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size10 mux_right_track_12 + ( + .in({chany_top_in[5], chany_top_in[11], chany_top_in[26], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[5], chany_bottom_in[11], chany_bottom_in[26], chanx_left_in[11], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size10_4_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size11 mux_right_track_2 + ( + .in({chany_top_in[0], chany_top_in[6], chany_top_in[20], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[6], chany_bottom_in[20], chany_bottom_in[21], chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size11_3_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size10 mux_right_track_20 + ( + .in({chany_top_in[9], chany_top_in[12], chany_top_in[27], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[4], chany_bottom_in[12], chany_bottom_in[27], chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size10_5_sram), + .sram_inv(mux_right_track_20_undriven_sram_inv), + .out(chanx_right_out[10]) + ); + mux_tree_tapbuf_size9 mux_right_track_28 + ( + .in({chany_top_in[13], chany_top_in[14], chany_top_in[28], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[2], chany_bottom_in[14], chany_bottom_in[28], chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size9_1_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size6 mux_right_track_36 + ( + .in({chany_top_in[15], chany_top_in[17], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[1], chany_bottom_in[15], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size6_3_sram), + .sram_inv(mux_right_track_36_undriven_sram_inv), + .out(chanx_right_out[18]) + ); + mux_tree_tapbuf_size10 mux_right_track_4 + ( + .in({chany_top_in[1], chany_top_in[7], chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[7], chany_bottom_in[17], chany_bottom_in[22], chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size10_3_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size6 mux_right_track_44 + ( + .in({chany_top_in[16], chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[0], chany_bottom_in[16], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size6_4_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size6 mux_right_track_52 + ( + .in({chany_top_in[18], chany_top_in[25], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[18], chany_bottom_in[29], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size6_5_sram), + .sram_inv(mux_right_track_52_undriven_sram_inv), + .out(chanx_right_out[26]) + ); + mux_tree_tapbuf_size12 mux_right_track_6 + ( + .in({chany_top_in[2], chany_top_in[8], chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[8], chany_bottom_in[13], chany_bottom_in[23], chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size11 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[1], chanx_right_in[3], chanx_right_in[19], chany_bottom_in[3], chany_bottom_in[19], chanx_left_in[0], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size11_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size12 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[9], chanx_right_in[10], chanx_right_in[24], chany_bottom_in[10], chany_bottom_in[24], chanx_left_in[10], chanx_left_in[17], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size10 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[11], chanx_right_in[13], chanx_right_in[26], chany_bottom_in[11], chany_bottom_in[26], chanx_left_in[11], chanx_left_in[13], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size10_1_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size11 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[2], chanx_right_in[6], chanx_right_in[20], chany_bottom_in[6], chany_bottom_in[20], chanx_left_in[6], chanx_left_in[20], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size11_1_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size10 mux_top_track_20 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[12], chanx_right_in[17], chanx_right_in[27], chany_bottom_in[12], chany_bottom_in[27], chanx_left_in[9], chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size10_2_sram), + .sram_inv(mux_top_track_20_undriven_sram_inv), + .out(chany_top_out[10]) + ); + mux_tree_tapbuf_size9 mux_top_track_28 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_right_in[14], chanx_right_in[21], chanx_right_in[28], chany_bottom_in[14], chany_bottom_in[28], chanx_left_in[5], chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size9_0_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size6 mux_top_track_36 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_right_in[15], chanx_right_in[25], chany_bottom_in[15], chanx_left_in[4], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size6_0_sram), + .sram_inv(mux_top_track_36_undriven_sram_inv), + .out(chany_top_out[18]) + ); + mux_tree_tapbuf_size10 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[4], chanx_right_in[7], chanx_right_in[22], chany_bottom_in[7], chany_bottom_in[22], chanx_left_in[7], chanx_left_in[22], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size6 mux_top_track_44 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_right_in[16], chanx_right_in[29], chany_bottom_in[16], chanx_left_in[2], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size6_1_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size6 mux_top_track_52 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[0], chanx_right_in[18], chany_bottom_in[18], chanx_left_in[1], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size6_2_sram), + .sram_inv(mux_top_track_52_undriven_sram_inv), + .out(chany_top_out[26]) + ); + mux_tree_tapbuf_size12 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[5], chanx_right_in[8], chanx_right_in[23], chany_bottom_in[8], chany_bottom_in[23], chanx_left_in[8], chanx_left_in[21], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__8_.v new file mode 100644 index 0000000..1826c3c --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__8_.v @@ -0,0 +1,1041 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_1__8_ +( + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + ccff_head, + chanx_left_in, + chanx_right_in, + chany_bottom_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + pReset, + prog_clk, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail, + chanx_left_out, + chanx_right_out, + chany_bottom_out +); + + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input ccff_head; + input [0:29]chanx_left_in; + input [0:29]chanx_right_in; + input [0:29]chany_bottom_in; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + input pReset; + input prog_clk; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + output [0:29]chanx_left_out; + output [0:29]chanx_right_out; + output [0:29]chany_bottom_out; + + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire ccff_head; + wire ccff_tail; + wire [0:29]chanx_left_in; + wire [0:29]chanx_left_out; + wire [0:29]chanx_right_in; + wire [0:29]chanx_right_out; + wire [0:29]chany_bottom_in; + wire [0:29]chany_bottom_out; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire [0:2]mux_bottom_track_11_undriven_sram_inv; + wire [0:2]mux_bottom_track_13_undriven_sram_inv; + wire [0:2]mux_bottom_track_15_undriven_sram_inv; + wire [0:2]mux_bottom_track_17_undriven_sram_inv; + wire [0:2]mux_bottom_track_19_undriven_sram_inv; + wire [0:2]mux_bottom_track_1_undriven_sram_inv; + wire [0:1]mux_bottom_track_21_undriven_sram_inv; + wire [0:1]mux_bottom_track_23_undriven_sram_inv; + wire [0:1]mux_bottom_track_25_undriven_sram_inv; + wire [0:1]mux_bottom_track_27_undriven_sram_inv; + wire [0:1]mux_bottom_track_29_undriven_sram_inv; + wire [0:1]mux_bottom_track_31_undriven_sram_inv; + wire [0:1]mux_bottom_track_33_undriven_sram_inv; + wire [0:1]mux_bottom_track_35_undriven_sram_inv; + wire [0:2]mux_bottom_track_37_undriven_sram_inv; + wire [0:1]mux_bottom_track_39_undriven_sram_inv; + wire [0:2]mux_bottom_track_3_undriven_sram_inv; + wire [0:1]mux_bottom_track_41_undriven_sram_inv; + wire [0:1]mux_bottom_track_43_undriven_sram_inv; + wire [0:1]mux_bottom_track_45_undriven_sram_inv; + wire [0:1]mux_bottom_track_47_undriven_sram_inv; + wire [0:1]mux_bottom_track_49_undriven_sram_inv; + wire [0:1]mux_bottom_track_51_undriven_sram_inv; + wire [0:2]mux_bottom_track_5_undriven_sram_inv; + wire [0:2]mux_bottom_track_7_undriven_sram_inv; + wire [0:2]mux_bottom_track_9_undriven_sram_inv; + wire [0:3]mux_left_track_11_undriven_sram_inv; + wire [0:2]mux_left_track_13_undriven_sram_inv; + wire [0:3]mux_left_track_1_undriven_sram_inv; + wire [0:2]mux_left_track_21_undriven_sram_inv; + wire [0:2]mux_left_track_29_undriven_sram_inv; + wire [0:2]mux_left_track_37_undriven_sram_inv; + wire [0:3]mux_left_track_3_undriven_sram_inv; + wire [0:2]mux_left_track_45_undriven_sram_inv; + wire [0:2]mux_left_track_53_undriven_sram_inv; + wire [0:3]mux_left_track_5_undriven_sram_inv; + wire [0:3]mux_left_track_7_undriven_sram_inv; + wire [0:3]mux_right_track_0_undriven_sram_inv; + wire [0:3]mux_right_track_10_undriven_sram_inv; + wire [0:2]mux_right_track_12_undriven_sram_inv; + wire [0:2]mux_right_track_20_undriven_sram_inv; + wire [0:2]mux_right_track_28_undriven_sram_inv; + wire [0:3]mux_right_track_2_undriven_sram_inv; + wire [0:2]mux_right_track_36_undriven_sram_inv; + wire [0:2]mux_right_track_44_undriven_sram_inv; + wire [0:3]mux_right_track_4_undriven_sram_inv; + wire [0:2]mux_right_track_52_undriven_sram_inv; + wire [0:3]mux_right_track_6_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size11_0_sram; + wire [0:3]mux_tree_tapbuf_size11_1_sram; + wire [0:3]mux_tree_tapbuf_size11_2_sram; + wire [0:3]mux_tree_tapbuf_size11_3_sram; + wire mux_tree_tapbuf_size11_mem_0_ccff_tail; + wire mux_tree_tapbuf_size11_mem_1_ccff_tail; + wire mux_tree_tapbuf_size11_mem_2_ccff_tail; + wire mux_tree_tapbuf_size11_mem_3_ccff_tail; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire [0:2]mux_tree_tapbuf_size4_0_sram; + wire [0:2]mux_tree_tapbuf_size4_1_sram; + wire [0:2]mux_tree_tapbuf_size4_2_sram; + wire [0:2]mux_tree_tapbuf_size4_3_sram; + wire [0:2]mux_tree_tapbuf_size4_4_sram; + wire mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire mux_tree_tapbuf_size4_mem_4_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire [0:2]mux_tree_tapbuf_size6_0_sram; + wire [0:2]mux_tree_tapbuf_size6_1_sram; + wire [0:2]mux_tree_tapbuf_size6_2_sram; + wire [0:2]mux_tree_tapbuf_size6_3_sram; + wire [0:2]mux_tree_tapbuf_size6_4_sram; + wire [0:2]mux_tree_tapbuf_size6_5_sram; + wire [0:2]mux_tree_tapbuf_size6_6_sram; + wire mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire [0:2]mux_tree_tapbuf_size7_0_sram; + wire [0:2]mux_tree_tapbuf_size7_1_sram; + wire [0:2]mux_tree_tapbuf_size7_2_sram; + wire [0:2]mux_tree_tapbuf_size7_3_sram; + wire [0:2]mux_tree_tapbuf_size7_4_sram; + wire [0:2]mux_tree_tapbuf_size7_5_sram; + wire mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire mux_tree_tapbuf_size7_mem_4_ccff_tail; + wire mux_tree_tapbuf_size7_mem_5_ccff_tail; + wire [0:3]mux_tree_tapbuf_size8_0_sram; + wire [0:3]mux_tree_tapbuf_size8_1_sram; + wire [0:3]mux_tree_tapbuf_size8_2_sram; + wire mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire mux_tree_tapbuf_size8_mem_2_ccff_tail; + wire [0:3]mux_tree_tapbuf_size9_0_sram; + wire [0:3]mux_tree_tapbuf_size9_1_sram; + wire [0:3]mux_tree_tapbuf_size9_2_sram; + wire mux_tree_tapbuf_size9_mem_0_ccff_tail; + wire mux_tree_tapbuf_size9_mem_1_ccff_tail; + wire mux_tree_tapbuf_size9_mem_2_ccff_tail; + wire pReset; + wire prog_clk; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + +assign chany_bottom_out[28] = chanx_right_in[0]; +assign chany_bottom_out[27] = chanx_right_in[1]; +assign chanx_left_out[15] = chanx_right_in[14]; +assign chanx_left_out[16] = chanx_right_in[15]; +assign chanx_left_out[17] = chanx_right_in[16]; +assign chanx_left_out[19] = chanx_right_in[18]; +assign chanx_left_out[20] = chanx_right_in[19]; +assign chanx_left_out[21] = chanx_right_in[20]; +assign chanx_left_out[23] = chanx_right_in[22]; +assign chanx_left_out[24] = chanx_right_in[23]; +assign chanx_left_out[25] = chanx_right_in[24]; +assign chanx_left_out[27] = chanx_right_in[26]; +assign chany_bottom_out[26] = chanx_right_in[2]; +assign chanx_left_out[28] = chanx_right_in[27]; +assign chanx_left_out[29] = chanx_right_in[28]; +assign chany_bottom_out[29] = chanx_left_in[0]; +assign chanx_right_out[4] = chanx_left_in[3]; +assign chanx_right_out[7] = chanx_left_in[6]; +assign chanx_right_out[8] = chanx_left_in[7]; +assign chanx_right_out[9] = chanx_left_in[8]; +assign chanx_right_out[11] = chanx_left_in[10]; +assign chanx_right_out[12] = chanx_left_in[11]; +assign chanx_right_out[13] = chanx_left_in[12]; +assign chanx_left_out[4] = chanx_right_in[3]; +assign chanx_right_out[15] = chanx_left_in[14]; +assign chanx_right_out[16] = chanx_left_in[15]; +assign chanx_right_out[17] = chanx_left_in[16]; +assign chanx_right_out[19] = chanx_left_in[18]; +assign chanx_right_out[20] = chanx_left_in[19]; +assign chanx_right_out[21] = chanx_left_in[20]; +assign chanx_right_out[23] = chanx_left_in[22]; +assign chanx_right_out[24] = chanx_left_in[23]; +assign chanx_right_out[25] = chanx_left_in[24]; +assign chanx_right_out[27] = chanx_left_in[26]; +assign chanx_left_out[7] = chanx_right_in[6]; +assign chanx_right_out[28] = chanx_left_in[27]; +assign chanx_right_out[29] = chanx_left_in[28]; +assign chanx_left_out[8] = chanx_right_in[7]; +assign chanx_left_out[9] = chanx_right_in[8]; +assign chanx_left_out[11] = chanx_right_in[10]; +assign chanx_left_out[12] = chanx_right_in[11]; +assign chanx_left_out[13] = chanx_right_in[12]; + mux_tree_tapbuf_size6_mem mem_bottom_track_1 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_11 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_13 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_15 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_17 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_19 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_21 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_23 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_25 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_27 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_29 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_3 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_31 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_33 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_35 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_37 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_39 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_41 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_43 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_45 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_47 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_49 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_5 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_51 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_7 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_9 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram) + ); + mux_tree_tapbuf_size8_mem mem_left_track_1 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_2_sram) + ); + mux_tree_tapbuf_size11_mem mem_left_track_11 + ( + .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_3_sram) + ); + mux_tree_tapbuf_size7_mem mem_left_track_13 + ( + .ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram) + ); + mux_tree_tapbuf_size7_mem mem_left_track_21 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram) + ); + mux_tree_tapbuf_size7_mem mem_left_track_29 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_5_sram) + ); + mux_tree_tapbuf_size9_mem mem_left_track_3 + ( + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_37 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_45 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size9_mem mem_left_track_5 + ( + .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_53 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size11_mem mem_left_track_7 + ( + .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_2_sram) + ); + mux_tree_tapbuf_size8_mem mem_right_track_0 + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_0_sram) + ); + mux_tree_tapbuf_size11_mem mem_right_track_10 + ( + .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_1_sram) + ); + mux_tree_tapbuf_size7_mem mem_right_track_12 + ( + .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram) + ); + mux_tree_tapbuf_size8_mem mem_right_track_2 + ( + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_1_sram) + ); + mux_tree_tapbuf_size7_mem mem_right_track_20 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram) + ); + mux_tree_tapbuf_size7_mem mem_right_track_28 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_36 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram) + ); + mux_tree_tapbuf_size9_mem mem_right_track_4 + ( + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_44 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_52 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size11_mem mem_right_track_6 + ( + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_0_sram) + ); + mux_tree_tapbuf_size6 mux_bottom_track_1 + ( + .in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[1], chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size6_2_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_11 + ( + .in({chanx_right_in[11], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[11], chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_13 + ( + .in({chanx_right_in[12], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[12], chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size4_0_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_15 + ( + .in({chanx_right_in[14], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[14], chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size4_1_sram), + .sram_inv(mux_bottom_track_15_undriven_sram_inv), + .out(chany_bottom_out[7]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_17 + ( + .in({chanx_right_in[15], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[15], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size4_2_sram), + .sram_inv(mux_bottom_track_17_undriven_sram_inv), + .out(chany_bottom_out[8]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_19 + ( + .in({chanx_right_in[16], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[16], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size4_3_sram), + .sram_inv(mux_bottom_track_19_undriven_sram_inv), + .out(chany_bottom_out[9]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_21 + ( + .in({chanx_right_in[18], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_bottom_track_21_undriven_sram_inv), + .out(chany_bottom_out[10]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_23 + ( + .in({chanx_right_in[19], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_bottom_track_23_undriven_sram_inv), + .out(chany_bottom_out[11]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_25 + ( + .in({chanx_right_in[20], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_bottom_track_25_undriven_sram_inv), + .out(chany_bottom_out[12]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_27 + ( + .in({chanx_right_in[22], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_bottom_track_27_undriven_sram_inv), + .out(chany_bottom_out[13]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_29 + ( + .in({chanx_right_in[23], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_3 + ( + .in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[2], chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size6_3_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_31 + ( + .in({chanx_right_in[24], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_bottom_track_31_undriven_sram_inv), + .out(chany_bottom_out[15]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_33 + ( + .in({chanx_right_in[26], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_bottom_track_33_undriven_sram_inv), + .out(chany_bottom_out[16]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_35 + ( + .in({chanx_right_in[27], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_bottom_track_35_undriven_sram_inv), + .out(chany_bottom_out[17]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_37 + ( + .in({chanx_right_in[28], chanx_right_in[29], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size4_4_sram), + .sram_inv(mux_bottom_track_37_undriven_sram_inv), + .out(chany_bottom_out[18]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_39 + ( + .in({chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_bottom_track_39_undriven_sram_inv), + .out(chany_bottom_out[19]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_41 + ( + .in({chanx_right_in[21], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_bottom_track_41_undriven_sram_inv), + .out(chany_bottom_out[20]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_43 + ( + .in({chanx_right_in[17], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_bottom_track_43_undriven_sram_inv), + .out(chany_bottom_out[21]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_45 + ( + .in({chanx_right_in[13], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_47 + ( + .in({chanx_right_in[9], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_bottom_track_47_undriven_sram_inv), + .out(chany_bottom_out[23]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_49 + ( + .in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_bottom_track_49_undriven_sram_inv), + .out(chany_bottom_out[24]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_5 + ( + .in({chanx_right_in[7], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[4], chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_51 + ( + .in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_bottom_track_51_undriven_sram_inv), + .out(chany_bottom_out[25]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_7 + ( + .in({chanx_right_in[8], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[5], chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size6_4_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_9 + ( + .in({chanx_right_in[10], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[9], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size6_5_sram), + .sram_inv(mux_bottom_track_9_undriven_sram_inv), + .out(chany_bottom_out[4]) + ); + mux_tree_tapbuf_size8 mux_left_track_1 + ( + .in({chanx_right_in[3], chanx_right_in[19], chany_bottom_in[10], chany_bottom_in[21], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size8_2_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size11 mux_left_track_11 + ( + .in({chanx_right_in[10], chanx_right_in[24], chany_bottom_in[3], chany_bottom_in[14], chany_bottom_in[25], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size11_3_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size7 mux_left_track_13 + ( + .in({chanx_right_in[11], chanx_right_in[26], chany_bottom_in[4], chany_bottom_in[15], chany_bottom_in[26], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size7_3_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size7 mux_left_track_21 + ( + .in({chanx_right_in[12], chanx_right_in[27], chany_bottom_in[5], chany_bottom_in[16], chany_bottom_in[27], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size7_4_sram), + .sram_inv(mux_left_track_21_undriven_sram_inv), + .out(chanx_left_out[10]) + ); + mux_tree_tapbuf_size7 mux_left_track_29 + ( + .in({chanx_right_in[14], chanx_right_in[28], chany_bottom_in[6], chany_bottom_in[17], chany_bottom_in[28], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size7_5_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size9 mux_left_track_3 + ( + .in({chanx_right_in[6], chanx_right_in[20], chany_bottom_in[0], chany_bottom_in[11], chany_bottom_in[22], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size9_1_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size6 mux_left_track_37 + ( + .in({chanx_right_in[15], chany_bottom_in[7], chany_bottom_in[18], chany_bottom_in[29], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size6_6_sram), + .sram_inv(mux_left_track_37_undriven_sram_inv), + .out(chanx_left_out[18]) + ); + mux_tree_tapbuf_size5 mux_left_track_45 + ( + .in({chanx_right_in[16], chany_bottom_in[8], chany_bottom_in[19], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size9 mux_left_track_5 + ( + .in({chanx_right_in[7], chanx_right_in[22], chany_bottom_in[1], chany_bottom_in[12], chany_bottom_in[23], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size9_2_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size5 mux_left_track_53 + ( + .in({chanx_right_in[18], chany_bottom_in[9], chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_left_track_53_undriven_sram_inv), + .out(chanx_left_out[26]) + ); + mux_tree_tapbuf_size11 mux_left_track_7 + ( + .in({chanx_right_in[8], chanx_right_in[23], chany_bottom_in[2], chany_bottom_in[13], chany_bottom_in[24], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size11_2_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size8 mux_right_track_0 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[9], chany_bottom_in[20], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size8_0_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size11 mux_right_track_10 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[5], chany_bottom_in[16], chany_bottom_in[27], chanx_left_in[10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size11_1_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size7 mux_right_track_12 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[4], chany_bottom_in[15], chany_bottom_in[26], chanx_left_in[11], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size7_0_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size8 mux_right_track_2 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[8], chany_bottom_in[19], chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size8_1_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size7 mux_right_track_20 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[3], chany_bottom_in[14], chany_bottom_in[25], chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size7_1_sram), + .sram_inv(mux_right_track_20_undriven_sram_inv), + .out(chanx_right_out[10]) + ); + mux_tree_tapbuf_size7 mux_right_track_28 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[2], chany_bottom_in[13], chany_bottom_in[24], chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size7_2_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size6 mux_right_track_36 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[1], chany_bottom_in[12], chany_bottom_in[23], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size6_0_sram), + .sram_inv(mux_right_track_36_undriven_sram_inv), + .out(chanx_right_out[18]) + ); + mux_tree_tapbuf_size9 mux_right_track_4 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[7], chany_bottom_in[18], chany_bottom_in[29], chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size9_0_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size6 mux_right_track_44 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[0], chany_bottom_in[11], chany_bottom_in[22], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size6_1_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size5 mux_right_track_52 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[10], chany_bottom_in[21], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_right_track_52_undriven_sram_inv), + .out(chanx_right_out[26]) + ); + mux_tree_tapbuf_size11 mux_right_track_6 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[6], chany_bottom_in[17], chany_bottom_in[28], chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size11_0_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__0_.v new file mode 100644 index 0000000..1ac66eb --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__0_.v @@ -0,0 +1,889 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_8__0_ +( + ccff_head, + chanx_left_in, + chany_top_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + pReset, + prog_clk, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail, + chanx_left_out, + chany_top_out +); + + input ccff_head; + input [0:29]chanx_left_in; + input [0:29]chany_top_in; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + input pReset; + input prog_clk; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + output [0:29]chanx_left_out; + output [0:29]chany_top_out; + + wire ccff_head; + wire ccff_tail; + wire [0:29]chanx_left_in; + wire [0:29]chanx_left_out; + wire [0:29]chany_top_in; + wire [0:29]chany_top_out; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire [0:1]mux_left_track_11_undriven_sram_inv; + wire [0:1]mux_left_track_13_undriven_sram_inv; + wire [0:1]mux_left_track_15_undriven_sram_inv; + wire [0:1]mux_left_track_17_undriven_sram_inv; + wire [0:1]mux_left_track_19_undriven_sram_inv; + wire [0:1]mux_left_track_1_undriven_sram_inv; + wire [0:1]mux_left_track_29_undriven_sram_inv; + wire [0:1]mux_left_track_31_undriven_sram_inv; + wire [0:1]mux_left_track_33_undriven_sram_inv; + wire [0:1]mux_left_track_35_undriven_sram_inv; + wire [0:1]mux_left_track_3_undriven_sram_inv; + wire [0:1]mux_left_track_45_undriven_sram_inv; + wire [0:1]mux_left_track_47_undriven_sram_inv; + wire [0:1]mux_left_track_49_undriven_sram_inv; + wire [0:1]mux_left_track_51_undriven_sram_inv; + wire [0:1]mux_left_track_5_undriven_sram_inv; + wire [0:1]mux_left_track_7_undriven_sram_inv; + wire [0:1]mux_left_track_9_undriven_sram_inv; + wire [0:2]mux_top_track_0_undriven_sram_inv; + wire [0:2]mux_top_track_10_undriven_sram_inv; + wire [0:1]mux_top_track_12_undriven_sram_inv; + wire [0:1]mux_top_track_14_undriven_sram_inv; + wire [0:1]mux_top_track_16_undriven_sram_inv; + wire [0:1]mux_top_track_18_undriven_sram_inv; + wire [0:1]mux_top_track_20_undriven_sram_inv; + wire [0:1]mux_top_track_22_undriven_sram_inv; + wire [0:1]mux_top_track_24_undriven_sram_inv; + wire [0:1]mux_top_track_26_undriven_sram_inv; + wire [0:1]mux_top_track_28_undriven_sram_inv; + wire [0:2]mux_top_track_2_undriven_sram_inv; + wire [0:1]mux_top_track_30_undriven_sram_inv; + wire [0:1]mux_top_track_32_undriven_sram_inv; + wire [0:1]mux_top_track_34_undriven_sram_inv; + wire [0:1]mux_top_track_36_undriven_sram_inv; + wire [0:1]mux_top_track_38_undriven_sram_inv; + wire [0:1]mux_top_track_40_undriven_sram_inv; + wire [0:1]mux_top_track_42_undriven_sram_inv; + wire [0:1]mux_top_track_44_undriven_sram_inv; + wire [0:1]mux_top_track_46_undriven_sram_inv; + wire [0:1]mux_top_track_48_undriven_sram_inv; + wire [0:2]mux_top_track_4_undriven_sram_inv; + wire [0:1]mux_top_track_50_undriven_sram_inv; + wire [0:2]mux_top_track_6_undriven_sram_inv; + wire [0:2]mux_top_track_8_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_11_sram; + wire [0:1]mux_tree_tapbuf_size2_12_sram; + wire [0:1]mux_tree_tapbuf_size2_13_sram; + wire [0:1]mux_tree_tapbuf_size2_14_sram; + wire [0:1]mux_tree_tapbuf_size2_15_sram; + wire [0:1]mux_tree_tapbuf_size2_16_sram; + wire [0:1]mux_tree_tapbuf_size2_17_sram; + wire [0:1]mux_tree_tapbuf_size2_18_sram; + wire [0:1]mux_tree_tapbuf_size2_19_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_20_sram; + wire [0:1]mux_tree_tapbuf_size2_21_sram; + wire [0:1]mux_tree_tapbuf_size2_22_sram; + wire [0:1]mux_tree_tapbuf_size2_23_sram; + wire [0:1]mux_tree_tapbuf_size2_24_sram; + wire [0:1]mux_tree_tapbuf_size2_25_sram; + wire [0:1]mux_tree_tapbuf_size2_26_sram; + wire [0:1]mux_tree_tapbuf_size2_27_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire mux_tree_tapbuf_size2_mem_19_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_20_ccff_tail; + wire mux_tree_tapbuf_size2_mem_21_ccff_tail; + wire mux_tree_tapbuf_size2_mem_22_ccff_tail; + wire mux_tree_tapbuf_size2_mem_23_ccff_tail; + wire mux_tree_tapbuf_size2_mem_24_ccff_tail; + wire mux_tree_tapbuf_size2_mem_25_ccff_tail; + wire mux_tree_tapbuf_size2_mem_26_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire [0:1]mux_tree_tapbuf_size3_7_sram; + wire [0:1]mux_tree_tapbuf_size3_8_sram; + wire [0:1]mux_tree_tapbuf_size3_9_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire mux_tree_tapbuf_size3_mem_7_ccff_tail; + wire mux_tree_tapbuf_size3_mem_8_ccff_tail; + wire mux_tree_tapbuf_size3_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire [0:2]mux_tree_tapbuf_size5_5_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire mux_tree_tapbuf_size5_mem_5_ccff_tail; + wire pReset; + wire prog_clk; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + +assign chanx_left_out[29] = chany_top_in[1]; +assign chanx_left_out[28] = chany_top_in[2]; +assign chanx_left_out[11] = chany_top_in[19]; +assign chanx_left_out[10] = chany_top_in[20]; +assign chany_top_out[29] = chanx_left_in[1]; +assign chany_top_out[28] = chanx_left_in[2]; +assign chany_top_out[27] = chanx_left_in[3]; +assign chany_top_out[26] = chanx_left_in[4]; +assign chanx_left_out[27] = chany_top_in[3]; +assign chanx_left_out[26] = chany_top_in[4]; +assign chanx_left_out[21] = chany_top_in[9]; +assign chanx_left_out[20] = chany_top_in[10]; +assign chanx_left_out[19] = chany_top_in[11]; +assign chanx_left_out[18] = chany_top_in[12]; +assign chanx_left_out[13] = chany_top_in[17]; +assign chanx_left_out[12] = chany_top_in[18]; + mux_tree_tapbuf_size3_mem mem_left_track_1 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_11 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_13 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_15 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_17 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_19 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_29 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_3 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_31 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_33 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_35 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_45 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_47 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_25_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_49 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_26_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_5 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_51 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_27_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_7 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_9 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_0 + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_10 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_12 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_14 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_16 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_18 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_2 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_20 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_22 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_24 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_26 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_28 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_30 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_32 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_34 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_36 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_38 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_4 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_40 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_42 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_44 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_46 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_48 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_50 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_6 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_8 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size3 mux_left_track_1 + ( + .in({chany_top_in[0], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_8_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size2 mux_left_track_11 + ( + .in({chany_top_in[25], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_15_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size2 mux_left_track_13 + ( + .in({chany_top_in[24], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_16_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size2 mux_left_track_15 + ( + .in({chany_top_in[23], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_17_sram), + .sram_inv(mux_left_track_15_undriven_sram_inv), + .out(chanx_left_out[7]) + ); + mux_tree_tapbuf_size2 mux_left_track_17 + ( + .in({chany_top_in[22], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_18_sram), + .sram_inv(mux_left_track_17_undriven_sram_inv), + .out(chanx_left_out[8]) + ); + mux_tree_tapbuf_size2 mux_left_track_19 + ( + .in({chany_top_in[21], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_19_sram), + .sram_inv(mux_left_track_19_undriven_sram_inv), + .out(chanx_left_out[9]) + ); + mux_tree_tapbuf_size2 mux_left_track_29 + ( + .in({chany_top_in[16], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_20_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size2 mux_left_track_3 + ( + .in({chany_top_in[29], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_12_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size2 mux_left_track_31 + ( + .in({chany_top_in[15], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram), + .sram_inv(mux_left_track_31_undriven_sram_inv), + .out(chanx_left_out[15]) + ); + mux_tree_tapbuf_size2 mux_left_track_33 + ( + .in({chany_top_in[14], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_22_sram), + .sram_inv(mux_left_track_33_undriven_sram_inv), + .out(chanx_left_out[16]) + ); + mux_tree_tapbuf_size2 mux_left_track_35 + ( + .in({chany_top_in[13], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_23_sram), + .sram_inv(mux_left_track_35_undriven_sram_inv), + .out(chanx_left_out[17]) + ); + mux_tree_tapbuf_size2 mux_left_track_45 + ( + .in({chany_top_in[8], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_24_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size2 mux_left_track_47 + ( + .in({chany_top_in[7], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_25_sram), + .sram_inv(mux_left_track_47_undriven_sram_inv), + .out(chanx_left_out[23]) + ); + mux_tree_tapbuf_size2 mux_left_track_49 + ( + .in({chany_top_in[6], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_26_sram), + .sram_inv(mux_left_track_49_undriven_sram_inv), + .out(chanx_left_out[24]) + ); + mux_tree_tapbuf_size2 mux_left_track_5 + ( + .in({chany_top_in[28], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_13_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size2 mux_left_track_51 + ( + .in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_27_sram), + .sram_inv(mux_left_track_51_undriven_sram_inv), + .out(chanx_left_out[25]) + ); + mux_tree_tapbuf_size3 mux_left_track_7 + ( + .in({chany_top_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_9_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size2 mux_left_track_9 + ( + .in({chany_top_in[26], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_14_sram), + .sram_inv(mux_left_track_9_undriven_sram_inv), + .out(chanx_left_out[4]) + ); + mux_tree_tapbuf_size5 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[0]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size5 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size5_5_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size3 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size3 mux_top_track_14 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_top_track_14_undriven_sram_inv), + .out(chany_top_out[7]) + ); + mux_tree_tapbuf_size3 mux_top_track_16 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_top_track_16_undriven_sram_inv), + .out(chany_top_out[8]) + ); + mux_tree_tapbuf_size3 mux_top_track_18 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_top_track_18_undriven_sram_inv), + .out(chany_top_out[9]) + ); + mux_tree_tapbuf_size5 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size2 mux_top_track_20 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_top_track_20_undriven_sram_inv), + .out(chany_top_out[10]) + ); + mux_tree_tapbuf_size2 mux_top_track_22 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_top_track_22_undriven_sram_inv), + .out(chany_top_out[11]) + ); + mux_tree_tapbuf_size2 mux_top_track_24 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_top_track_24_undriven_sram_inv), + .out(chany_top_out[12]) + ); + mux_tree_tapbuf_size2 mux_top_track_26 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_top_track_26_undriven_sram_inv), + .out(chany_top_out[13]) + ); + mux_tree_tapbuf_size2 mux_top_track_28 + ( + .in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size2 mux_top_track_30 + ( + .in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_top_track_30_undriven_sram_inv), + .out(chany_top_out[15]) + ); + mux_tree_tapbuf_size2 mux_top_track_32 + ( + .in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_top_track_32_undriven_sram_inv), + .out(chany_top_out[16]) + ); + mux_tree_tapbuf_size2 mux_top_track_34 + ( + .in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_top_track_34_undriven_sram_inv), + .out(chany_top_out[17]) + ); + mux_tree_tapbuf_size2 mux_top_track_36 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_top_track_36_undriven_sram_inv), + .out(chany_top_out[18]) + ); + mux_tree_tapbuf_size2 mux_top_track_38 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_top_track_38_undriven_sram_inv), + .out(chany_top_out[19]) + ); + mux_tree_tapbuf_size5 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size2 mux_top_track_40 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_top_track_40_undriven_sram_inv), + .out(chany_top_out[20]) + ); + mux_tree_tapbuf_size2 mux_top_track_42 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size2_11_sram), + .sram_inv(mux_top_track_42_undriven_sram_inv), + .out(chany_top_out[21]) + ); + mux_tree_tapbuf_size3 mux_top_track_44 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size3 mux_top_track_46 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_top_track_46_undriven_sram_inv), + .out(chany_top_out[23]) + ); + mux_tree_tapbuf_size3 mux_top_track_48 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_top_track_48_undriven_sram_inv), + .out(chany_top_out[24]) + ); + mux_tree_tapbuf_size3 mux_top_track_50 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[5]}), + .sram(mux_tree_tapbuf_size3_7_sram), + .sram_inv(mux_top_track_50_undriven_sram_inv), + .out(chany_top_out[25]) + ); + mux_tree_tapbuf_size5 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); + mux_tree_tapbuf_size5 mux_top_track_8 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_top_track_8_undriven_sram_inv), + .out(chany_top_out[4]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__1_.v new file mode 100644 index 0000000..1350585 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__1_.v @@ -0,0 +1,1058 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_8__1_ +( + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chanx_left_in, + chany_bottom_in, + chany_top_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + pReset, + prog_clk, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail, + chanx_left_out, + chany_bottom_out, + chany_top_out +); + + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + input ccff_head; + input [0:29]chanx_left_in; + input [0:29]chany_bottom_in; + input [0:29]chany_top_in; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input pReset; + input prog_clk; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + output [0:29]chanx_left_out; + output [0:29]chany_bottom_out; + output [0:29]chany_top_out; + + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head; + wire ccff_tail; + wire [0:29]chanx_left_in; + wire [0:29]chanx_left_out; + wire [0:29]chany_bottom_in; + wire [0:29]chany_bottom_out; + wire [0:29]chany_top_in; + wire [0:29]chany_top_out; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire [0:3]mux_bottom_track_11_undriven_sram_inv; + wire [0:2]mux_bottom_track_13_undriven_sram_inv; + wire [0:3]mux_bottom_track_1_undriven_sram_inv; + wire [0:2]mux_bottom_track_21_undriven_sram_inv; + wire [0:2]mux_bottom_track_29_undriven_sram_inv; + wire [0:2]mux_bottom_track_37_undriven_sram_inv; + wire [0:3]mux_bottom_track_3_undriven_sram_inv; + wire [0:2]mux_bottom_track_45_undriven_sram_inv; + wire [0:2]mux_bottom_track_53_undriven_sram_inv; + wire [0:3]mux_bottom_track_5_undriven_sram_inv; + wire [0:3]mux_bottom_track_7_undriven_sram_inv; + wire [0:2]mux_left_track_11_undriven_sram_inv; + wire [0:2]mux_left_track_13_undriven_sram_inv; + wire [0:2]mux_left_track_15_undriven_sram_inv; + wire [0:2]mux_left_track_17_undriven_sram_inv; + wire [0:2]mux_left_track_19_undriven_sram_inv; + wire [0:2]mux_left_track_1_undriven_sram_inv; + wire [0:2]mux_left_track_21_undriven_sram_inv; + wire [0:2]mux_left_track_23_undriven_sram_inv; + wire [0:1]mux_left_track_25_undriven_sram_inv; + wire [0:1]mux_left_track_27_undriven_sram_inv; + wire [0:1]mux_left_track_29_undriven_sram_inv; + wire [0:1]mux_left_track_31_undriven_sram_inv; + wire [0:1]mux_left_track_33_undriven_sram_inv; + wire [0:1]mux_left_track_35_undriven_sram_inv; + wire [0:1]mux_left_track_37_undriven_sram_inv; + wire [0:2]mux_left_track_3_undriven_sram_inv; + wire [0:1]mux_left_track_41_undriven_sram_inv; + wire [0:1]mux_left_track_45_undriven_sram_inv; + wire [0:1]mux_left_track_47_undriven_sram_inv; + wire [0:1]mux_left_track_49_undriven_sram_inv; + wire [0:1]mux_left_track_51_undriven_sram_inv; + wire [0:1]mux_left_track_53_undriven_sram_inv; + wire [0:1]mux_left_track_55_undriven_sram_inv; + wire [0:1]mux_left_track_57_undriven_sram_inv; + wire [0:2]mux_left_track_5_undriven_sram_inv; + wire [0:2]mux_left_track_7_undriven_sram_inv; + wire [0:2]mux_left_track_9_undriven_sram_inv; + wire [0:3]mux_top_track_0_undriven_sram_inv; + wire [0:3]mux_top_track_10_undriven_sram_inv; + wire [0:2]mux_top_track_12_undriven_sram_inv; + wire [0:2]mux_top_track_20_undriven_sram_inv; + wire [0:2]mux_top_track_28_undriven_sram_inv; + wire [0:3]mux_top_track_2_undriven_sram_inv; + wire [0:2]mux_top_track_36_undriven_sram_inv; + wire [0:2]mux_top_track_44_undriven_sram_inv; + wire [0:3]mux_top_track_4_undriven_sram_inv; + wire [0:2]mux_top_track_52_undriven_sram_inv; + wire [0:3]mux_top_track_6_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:3]mux_tree_tapbuf_size11_0_sram; + wire [0:3]mux_tree_tapbuf_size11_1_sram; + wire [0:3]mux_tree_tapbuf_size11_2_sram; + wire mux_tree_tapbuf_size11_mem_0_ccff_tail; + wire mux_tree_tapbuf_size11_mem_1_ccff_tail; + wire mux_tree_tapbuf_size11_mem_2_ccff_tail; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire [0:1]mux_tree_tapbuf_size3_7_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire mux_tree_tapbuf_size3_mem_7_ccff_tail; + wire [0:2]mux_tree_tapbuf_size4_0_sram; + wire [0:2]mux_tree_tapbuf_size4_1_sram; + wire [0:2]mux_tree_tapbuf_size4_2_sram; + wire [0:2]mux_tree_tapbuf_size4_3_sram; + wire [0:2]mux_tree_tapbuf_size4_4_sram; + wire [0:2]mux_tree_tapbuf_size4_5_sram; + wire mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire mux_tree_tapbuf_size4_mem_4_ccff_tail; + wire mux_tree_tapbuf_size4_mem_5_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire [0:2]mux_tree_tapbuf_size6_0_sram; + wire [0:2]mux_tree_tapbuf_size6_1_sram; + wire [0:2]mux_tree_tapbuf_size6_2_sram; + wire [0:2]mux_tree_tapbuf_size6_3_sram; + wire [0:2]mux_tree_tapbuf_size6_4_sram; + wire [0:2]mux_tree_tapbuf_size6_5_sram; + wire [0:2]mux_tree_tapbuf_size6_6_sram; + wire [0:2]mux_tree_tapbuf_size6_7_sram; + wire [0:2]mux_tree_tapbuf_size6_8_sram; + wire mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire mux_tree_tapbuf_size6_mem_7_ccff_tail; + wire mux_tree_tapbuf_size6_mem_8_ccff_tail; + wire [0:2]mux_tree_tapbuf_size7_0_sram; + wire [0:2]mux_tree_tapbuf_size7_1_sram; + wire [0:2]mux_tree_tapbuf_size7_2_sram; + wire [0:2]mux_tree_tapbuf_size7_3_sram; + wire [0:2]mux_tree_tapbuf_size7_4_sram; + wire mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire mux_tree_tapbuf_size7_mem_4_ccff_tail; + wire [0:3]mux_tree_tapbuf_size8_0_sram; + wire [0:3]mux_tree_tapbuf_size8_1_sram; + wire mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:3]mux_tree_tapbuf_size9_0_sram; + wire [0:3]mux_tree_tapbuf_size9_1_sram; + wire [0:3]mux_tree_tapbuf_size9_2_sram; + wire [0:3]mux_tree_tapbuf_size9_3_sram; + wire mux_tree_tapbuf_size9_mem_0_ccff_tail; + wire mux_tree_tapbuf_size9_mem_1_ccff_tail; + wire mux_tree_tapbuf_size9_mem_2_ccff_tail; + wire mux_tree_tapbuf_size9_mem_3_ccff_tail; + wire pReset; + wire prog_clk; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + +assign chanx_left_out[29] = chany_top_in[1]; +assign chany_bottom_out[4] = chany_top_in[3]; +assign chany_bottom_out[17] = chany_top_in[16]; +assign chany_bottom_out[19] = chany_top_in[18]; +assign chany_bottom_out[20] = chany_top_in[19]; +assign chany_bottom_out[21] = chany_top_in[20]; +assign chany_bottom_out[23] = chany_top_in[22]; +assign chany_bottom_out[24] = chany_top_in[23]; +assign chany_bottom_out[25] = chany_top_in[24]; +assign chanx_left_out[21] = chany_top_in[25]; +assign chany_bottom_out[27] = chany_top_in[26]; +assign chany_bottom_out[28] = chany_top_in[27]; +assign chany_bottom_out[7] = chany_top_in[6]; +assign chany_bottom_out[29] = chany_top_in[28]; +assign chany_top_out[4] = chany_bottom_in[3]; +assign chany_top_out[7] = chany_bottom_in[6]; +assign chany_top_out[8] = chany_bottom_in[7]; +assign chany_top_out[9] = chany_bottom_in[8]; +assign chany_top_out[11] = chany_bottom_in[10]; +assign chany_top_out[12] = chany_bottom_in[11]; +assign chany_top_out[13] = chany_bottom_in[12]; +assign chany_top_out[15] = chany_bottom_in[14]; +assign chany_top_out[16] = chany_bottom_in[15]; +assign chany_bottom_out[8] = chany_top_in[7]; +assign chany_top_out[17] = chany_bottom_in[16]; +assign chany_top_out[19] = chany_bottom_in[18]; +assign chany_top_out[20] = chany_bottom_in[19]; +assign chany_top_out[21] = chany_bottom_in[20]; +assign chany_top_out[23] = chany_bottom_in[22]; +assign chany_top_out[24] = chany_bottom_in[23]; +assign chany_top_out[25] = chany_bottom_in[24]; +assign chany_top_out[27] = chany_bottom_in[26]; +assign chany_top_out[28] = chany_bottom_in[27]; +assign chany_top_out[29] = chany_bottom_in[28]; +assign chany_bottom_out[9] = chany_top_in[8]; +assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; +assign chany_bottom_out[11] = chany_top_in[10]; +assign chany_bottom_out[12] = chany_top_in[11]; +assign chany_bottom_out[13] = chany_top_in[12]; +assign chany_bottom_out[15] = chany_top_in[14]; +assign chany_bottom_out[16] = chany_top_in[15]; + mux_tree_tapbuf_size9_mem mem_bottom_track_1 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_1_sram) + ); + mux_tree_tapbuf_size11_mem mem_bottom_track_11 + ( + .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_2_sram) + ); + mux_tree_tapbuf_size7_mem mem_bottom_track_13 + ( + .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram) + ); + mux_tree_tapbuf_size7_mem mem_bottom_track_21 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_29 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram) + ); + mux_tree_tapbuf_size9_mem mem_bottom_track_3 + ( + .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_37 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_45 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size9_mem mem_bottom_track_5 + ( + .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_3_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_53 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram) + ); + mux_tree_tapbuf_size11_mem mem_bottom_track_7 + ( + .ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_1 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_11 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_13 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_15 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_17 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_19 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_21 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_23 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_25 + ( + .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_27 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_29 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_3 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_31 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_33 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_35 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_37 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_41 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_45 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_47 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_49 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_5 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_51 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_53 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_55 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_57 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_7 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_9 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram) + ); + mux_tree_tapbuf_size9_mem mem_top_track_0 + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_0_sram) + ); + mux_tree_tapbuf_size11_mem mem_top_track_10 + ( + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_0_sram) + ); + mux_tree_tapbuf_size7_mem mem_top_track_12 + ( + .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram) + ); + mux_tree_tapbuf_size8_mem mem_top_track_2 + ( + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_0_sram) + ); + mux_tree_tapbuf_size7_mem mem_top_track_20 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram) + ); + mux_tree_tapbuf_size7_mem mem_top_track_28 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_36 + ( + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram) + ); + mux_tree_tapbuf_size8_mem mem_top_track_4 + ( + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_44 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_52 + ( + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_track_6 + ( + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size9 mux_bottom_track_1 + ( + .in({chany_top_in[3], chany_top_in[19], bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[1], chanx_left_in[12], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size9_1_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size11 mux_bottom_track_11 + ( + .in({chany_top_in[10], chany_top_in[24], bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[5], chanx_left_in[16], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size11_2_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size7 mux_bottom_track_13 + ( + .in({chany_top_in[11], chany_top_in[26], bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[6], chanx_left_in[17], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size7_3_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size7 mux_bottom_track_21 + ( + .in({chany_top_in[12], chany_top_in[27], bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[7], chanx_left_in[18], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size7_4_sram), + .sram_inv(mux_bottom_track_21_undriven_sram_inv), + .out(chany_bottom_out[10]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_29 + ( + .in({chany_top_in[14], chany_top_in[28], bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[8], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size6_3_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size9 mux_bottom_track_3 + ( + .in({chany_top_in[6], chany_top_in[20], bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[2], chanx_left_in[13], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size9_2_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_37 + ( + .in({chany_top_in[15], bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[9], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_bottom_track_37_undriven_sram_inv), + .out(chany_bottom_out[18]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_45 + ( + .in({chany_top_in[16], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[10], chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size9 mux_bottom_track_5 + ( + .in({chany_top_in[7], chany_top_in[22], bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[3], chanx_left_in[14], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size9_3_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_53 + ( + .in({chany_top_in[18], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[0], chanx_left_in[11], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size6_4_sram), + .sram_inv(mux_bottom_track_53_undriven_sram_inv), + .out(chany_bottom_out[26]) + ); + mux_tree_tapbuf_size11 mux_bottom_track_7 + ( + .in({chany_top_in[8], chany_top_in[23], bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[4], chanx_left_in[15], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size11_1_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size6 mux_left_track_1 + ( + .in({chany_top_in[0], chany_top_in[3], chany_bottom_in[3], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size6_5_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size5 mux_left_track_11 + ( + .in({chany_top_in[11], chany_bottom_in[5], chany_bottom_in[11], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size4 mux_left_track_13 + ( + .in({chany_top_in[12], chany_bottom_in[9], chany_bottom_in[12], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size4_0_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size4 mux_left_track_15 + ( + .in({chany_top_in[14], chany_bottom_in[13], chany_bottom_in[14], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size4_1_sram), + .sram_inv(mux_left_track_15_undriven_sram_inv), + .out(chanx_left_out[7]) + ); + mux_tree_tapbuf_size4 mux_left_track_17 + ( + .in({chany_top_in[15], chany_bottom_in[15], chany_bottom_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size4_2_sram), + .sram_inv(mux_left_track_17_undriven_sram_inv), + .out(chanx_left_out[8]) + ); + mux_tree_tapbuf_size4 mux_left_track_19 + ( + .in({chany_top_in[16], chany_bottom_in[16], chany_bottom_in[21], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size4_3_sram), + .sram_inv(mux_left_track_19_undriven_sram_inv), + .out(chanx_left_out[9]) + ); + mux_tree_tapbuf_size4 mux_left_track_21 + ( + .in({chany_top_in[18], chany_bottom_in[18], chany_bottom_in[25], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size4_4_sram), + .sram_inv(mux_left_track_21_undriven_sram_inv), + .out(chanx_left_out[10]) + ); + mux_tree_tapbuf_size4 mux_left_track_23 + ( + .in({chany_top_in[19], chany_bottom_in[19], chany_bottom_in[29], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size4_5_sram), + .sram_inv(mux_left_track_23_undriven_sram_inv), + .out(chanx_left_out[11]) + ); + mux_tree_tapbuf_size3 mux_left_track_25 + ( + .in({chany_top_in[20], chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_left_track_25_undriven_sram_inv), + .out(chanx_left_out[12]) + ); + mux_tree_tapbuf_size3 mux_left_track_27 + ( + .in({chany_top_in[22], chany_bottom_in[22], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_left_track_27_undriven_sram_inv), + .out(chanx_left_out[13]) + ); + mux_tree_tapbuf_size3 mux_left_track_29 + ( + .in({chany_top_in[23], chany_bottom_in[23], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size6 mux_left_track_3 + ( + .in({chany_top_in[6], chany_bottom_in[0], chany_bottom_in[6], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size6_6_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size3 mux_left_track_31 + ( + .in({chany_top_in[24], chany_bottom_in[24], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_left_track_31_undriven_sram_inv), + .out(chanx_left_out[15]) + ); + mux_tree_tapbuf_size3 mux_left_track_33 + ( + .in({chany_top_in[26], chany_bottom_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_left_track_33_undriven_sram_inv), + .out(chanx_left_out[16]) + ); + mux_tree_tapbuf_size3 mux_left_track_35 + ( + .in({chany_top_in[27], chany_bottom_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_left_track_35_undriven_sram_inv), + .out(chanx_left_out[17]) + ); + mux_tree_tapbuf_size3 mux_left_track_37 + ( + .in({chany_top_in[28], chany_bottom_in[28], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_left_track_37_undriven_sram_inv), + .out(chanx_left_out[18]) + ); + mux_tree_tapbuf_size2 mux_left_track_41 + ( + .in({chany_top_in[29], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_left_track_41_undriven_sram_inv), + .out(chanx_left_out[20]) + ); + mux_tree_tapbuf_size2 mux_left_track_45 + ( + .in({chany_top_in[21], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size2 mux_left_track_47 + ( + .in({chany_top_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_left_track_47_undriven_sram_inv), + .out(chanx_left_out[23]) + ); + mux_tree_tapbuf_size2 mux_left_track_49 + ( + .in({chany_top_in[13], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_left_track_49_undriven_sram_inv), + .out(chanx_left_out[24]) + ); + mux_tree_tapbuf_size5 mux_left_track_5 + ( + .in({chany_top_in[7], chany_bottom_in[1], chany_bottom_in[7], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size3 mux_left_track_51 + ( + .in({chany_top_in[9], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_7_sram), + .sram_inv(mux_left_track_51_undriven_sram_inv), + .out(chanx_left_out[25]) + ); + mux_tree_tapbuf_size2 mux_left_track_53 + ( + .in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_left_track_53_undriven_sram_inv), + .out(chanx_left_out[26]) + ); + mux_tree_tapbuf_size2 mux_left_track_55 + ( + .in({chany_top_in[4], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_left_track_55_undriven_sram_inv), + .out(chanx_left_out[27]) + ); + mux_tree_tapbuf_size2 mux_left_track_57 + ( + .in({chany_top_in[2], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_left_track_57_undriven_sram_inv), + .out(chanx_left_out[28]) + ); + mux_tree_tapbuf_size6 mux_left_track_7 + ( + .in({chany_top_in[8], chany_bottom_in[2], chany_bottom_in[8], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size6_7_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size6 mux_left_track_9 + ( + .in({chany_top_in[10], chany_bottom_in[4], chany_bottom_in[10], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size6_8_sram), + .sram_inv(mux_left_track_9_undriven_sram_inv), + .out(chanx_left_out[4]) + ); + mux_tree_tapbuf_size9 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chany_bottom_in[3], chany_bottom_in[19], chanx_left_in[0], chanx_left_in[11], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size9_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size11 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[10], chany_bottom_in[24], chanx_left_in[7], chanx_left_in[18], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size11_0_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size7 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chany_bottom_in[11], chany_bottom_in[26], chanx_left_in[6], chanx_left_in[17], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size7_0_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size8 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[6], chany_bottom_in[20], chanx_left_in[10], chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size8_0_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size7 mux_top_track_20 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chany_bottom_in[12], chany_bottom_in[27], chanx_left_in[5], chanx_left_in[16], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size7_1_sram), + .sram_inv(mux_top_track_20_undriven_sram_inv), + .out(chany_top_out[10]) + ); + mux_tree_tapbuf_size7 mux_top_track_28 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chany_bottom_in[14], chany_bottom_in[28], chanx_left_in[4], chanx_left_in[15], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size7_2_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size6 mux_top_track_36 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chany_bottom_in[15], chanx_left_in[3], chanx_left_in[14], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size6_0_sram), + .sram_inv(mux_top_track_36_undriven_sram_inv), + .out(chany_top_out[18]) + ); + mux_tree_tapbuf_size8 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[7], chany_bottom_in[22], chanx_left_in[9], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size8_1_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size6 mux_top_track_44 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[16], chanx_left_in[2], chanx_left_in[13], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size6_1_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size6 mux_top_track_52 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[18], chanx_left_in[1], chanx_left_in[12], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size6_2_sram), + .sram_inv(mux_top_track_52_undriven_sram_inv), + .out(chany_top_out[26]) + ); + mux_tree_tapbuf_size10 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[8], chany_bottom_in[23], chanx_left_in[8], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__8_.v new file mode 100644 index 0000000..4d3b2cf --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__8_.v @@ -0,0 +1,1117 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_8__8_ +( + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chanx_left_in, + chany_bottom_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + pReset, + prog_clk, + ccff_tail, + chanx_left_out, + chany_bottom_out +); + + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + input ccff_head; + input [0:29]chanx_left_in; + input [0:29]chany_bottom_in; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + input pReset; + input prog_clk; + output ccff_tail; + output [0:29]chanx_left_out; + output [0:29]chany_bottom_out; + + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head; + wire ccff_tail; + wire [0:29]chanx_left_in; + wire [0:29]chanx_left_out; + wire [0:29]chany_bottom_in; + wire [0:29]chany_bottom_out; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire [0:2]mux_bottom_track_11_undriven_sram_inv; + wire [0:1]mux_bottom_track_13_undriven_sram_inv; + wire [0:1]mux_bottom_track_15_undriven_sram_inv; + wire [0:1]mux_bottom_track_17_undriven_sram_inv; + wire [0:1]mux_bottom_track_19_undriven_sram_inv; + wire [0:2]mux_bottom_track_1_undriven_sram_inv; + wire [0:1]mux_bottom_track_21_undriven_sram_inv; + wire [0:1]mux_bottom_track_23_undriven_sram_inv; + wire [0:1]mux_bottom_track_25_undriven_sram_inv; + wire [0:1]mux_bottom_track_27_undriven_sram_inv; + wire [0:1]mux_bottom_track_29_undriven_sram_inv; + wire [0:1]mux_bottom_track_31_undriven_sram_inv; + wire [0:1]mux_bottom_track_33_undriven_sram_inv; + wire [0:1]mux_bottom_track_35_undriven_sram_inv; + wire [0:2]mux_bottom_track_3_undriven_sram_inv; + wire [0:1]mux_bottom_track_45_undriven_sram_inv; + wire [0:1]mux_bottom_track_47_undriven_sram_inv; + wire [0:1]mux_bottom_track_49_undriven_sram_inv; + wire [0:1]mux_bottom_track_51_undriven_sram_inv; + wire [0:1]mux_bottom_track_53_undriven_sram_inv; + wire [0:1]mux_bottom_track_55_undriven_sram_inv; + wire [0:1]mux_bottom_track_57_undriven_sram_inv; + wire [0:1]mux_bottom_track_59_undriven_sram_inv; + wire [0:2]mux_bottom_track_5_undriven_sram_inv; + wire [0:2]mux_bottom_track_7_undriven_sram_inv; + wire [0:2]mux_bottom_track_9_undriven_sram_inv; + wire [0:2]mux_left_track_11_undriven_sram_inv; + wire [0:1]mux_left_track_13_undriven_sram_inv; + wire [0:1]mux_left_track_15_undriven_sram_inv; + wire [0:1]mux_left_track_17_undriven_sram_inv; + wire [0:1]mux_left_track_19_undriven_sram_inv; + wire [0:2]mux_left_track_1_undriven_sram_inv; + wire [0:1]mux_left_track_21_undriven_sram_inv; + wire [0:1]mux_left_track_23_undriven_sram_inv; + wire [0:1]mux_left_track_25_undriven_sram_inv; + wire [0:1]mux_left_track_27_undriven_sram_inv; + wire [0:1]mux_left_track_29_undriven_sram_inv; + wire [0:1]mux_left_track_31_undriven_sram_inv; + wire [0:1]mux_left_track_33_undriven_sram_inv; + wire [0:1]mux_left_track_35_undriven_sram_inv; + wire [0:1]mux_left_track_37_undriven_sram_inv; + wire [0:1]mux_left_track_39_undriven_sram_inv; + wire [0:2]mux_left_track_3_undriven_sram_inv; + wire [0:1]mux_left_track_41_undriven_sram_inv; + wire [0:1]mux_left_track_43_undriven_sram_inv; + wire [0:1]mux_left_track_45_undriven_sram_inv; + wire [0:1]mux_left_track_47_undriven_sram_inv; + wire [0:1]mux_left_track_49_undriven_sram_inv; + wire [0:1]mux_left_track_51_undriven_sram_inv; + wire [0:1]mux_left_track_53_undriven_sram_inv; + wire [0:1]mux_left_track_55_undriven_sram_inv; + wire [0:1]mux_left_track_57_undriven_sram_inv; + wire [0:1]mux_left_track_59_undriven_sram_inv; + wire [0:2]mux_left_track_5_undriven_sram_inv; + wire [0:2]mux_left_track_7_undriven_sram_inv; + wire [0:2]mux_left_track_9_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_11_sram; + wire [0:1]mux_tree_tapbuf_size2_12_sram; + wire [0:1]mux_tree_tapbuf_size2_13_sram; + wire [0:1]mux_tree_tapbuf_size2_14_sram; + wire [0:1]mux_tree_tapbuf_size2_15_sram; + wire [0:1]mux_tree_tapbuf_size2_16_sram; + wire [0:1]mux_tree_tapbuf_size2_17_sram; + wire [0:1]mux_tree_tapbuf_size2_18_sram; + wire [0:1]mux_tree_tapbuf_size2_19_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_20_sram; + wire [0:1]mux_tree_tapbuf_size2_21_sram; + wire [0:1]mux_tree_tapbuf_size2_22_sram; + wire [0:1]mux_tree_tapbuf_size2_23_sram; + wire [0:1]mux_tree_tapbuf_size2_24_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire mux_tree_tapbuf_size2_mem_19_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_20_ccff_tail; + wire mux_tree_tapbuf_size2_mem_21_ccff_tail; + wire mux_tree_tapbuf_size2_mem_22_ccff_tail; + wire mux_tree_tapbuf_size2_mem_23_ccff_tail; + wire mux_tree_tapbuf_size2_mem_24_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_10_sram; + wire [0:1]mux_tree_tapbuf_size3_11_sram; + wire [0:1]mux_tree_tapbuf_size3_12_sram; + wire [0:1]mux_tree_tapbuf_size3_13_sram; + wire [0:1]mux_tree_tapbuf_size3_14_sram; + wire [0:1]mux_tree_tapbuf_size3_15_sram; + wire [0:1]mux_tree_tapbuf_size3_16_sram; + wire [0:1]mux_tree_tapbuf_size3_17_sram; + wire [0:1]mux_tree_tapbuf_size3_18_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire [0:1]mux_tree_tapbuf_size3_7_sram; + wire [0:1]mux_tree_tapbuf_size3_8_sram; + wire [0:1]mux_tree_tapbuf_size3_9_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_10_ccff_tail; + wire mux_tree_tapbuf_size3_mem_11_ccff_tail; + wire mux_tree_tapbuf_size3_mem_12_ccff_tail; + wire mux_tree_tapbuf_size3_mem_13_ccff_tail; + wire mux_tree_tapbuf_size3_mem_14_ccff_tail; + wire mux_tree_tapbuf_size3_mem_15_ccff_tail; + wire mux_tree_tapbuf_size3_mem_16_ccff_tail; + wire mux_tree_tapbuf_size3_mem_17_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire mux_tree_tapbuf_size3_mem_7_ccff_tail; + wire mux_tree_tapbuf_size3_mem_8_ccff_tail; + wire mux_tree_tapbuf_size3_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_10_sram; + wire [0:2]mux_tree_tapbuf_size5_11_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire [0:2]mux_tree_tapbuf_size5_5_sram; + wire [0:2]mux_tree_tapbuf_size5_6_sram; + wire [0:2]mux_tree_tapbuf_size5_7_sram; + wire [0:2]mux_tree_tapbuf_size5_8_sram; + wire [0:2]mux_tree_tapbuf_size5_9_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_10_ccff_tail; + wire mux_tree_tapbuf_size5_mem_11_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire mux_tree_tapbuf_size5_mem_5_ccff_tail; + wire mux_tree_tapbuf_size5_mem_6_ccff_tail; + wire mux_tree_tapbuf_size5_mem_7_ccff_tail; + wire mux_tree_tapbuf_size5_mem_8_ccff_tail; + wire mux_tree_tapbuf_size5_mem_9_ccff_tail; + wire pReset; + wire prog_clk; + +assign chany_bottom_out[18] = chanx_left_in[19]; +assign chany_bottom_out[19] = chanx_left_in[20]; +assign chany_bottom_out[20] = chanx_left_in[21]; +assign chany_bottom_out[21] = chanx_left_in[22]; + mux_tree_tapbuf_size5_mem mem_bottom_track_1 + ( + .ccff_head(ccff_head), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_11 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_13 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_15 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_17 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_19 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_21 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_23 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_25 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_27 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_29 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_3 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_31 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_33 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_35 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_45 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_47 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_49 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_5 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_51 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_53 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_55 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_57 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_59 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_7 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_9 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_1 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_6_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_11 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_10_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_11_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_13 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_11_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_15 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_17 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_19 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_21 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_23 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_25 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_27 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_29 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_3 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_6_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_7_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_31 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_12_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_33 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_13_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_35 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_14_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_37 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_14_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_39 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_41 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_43 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_45 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_15_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_47 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_15_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_16_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_49 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_16_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size3_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_17_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_5 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_7_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_51 + ( + .ccff_head(mux_tree_tapbuf_size3_mem_17_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_53 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_55 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_57 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_59 + ( + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size3_18_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_7 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_8_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_9_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_9 + ( + .ccff_head(mux_tree_tapbuf_size5_mem_9_ccff_tail), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(mux_tree_tapbuf_size5_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_10_sram) + ); + mux_tree_tapbuf_size5 mux_bottom_track_1 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[1]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_11 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size5_5_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_13 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_15 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_bottom_track_15_undriven_sram_inv), + .out(chany_bottom_out[7]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_17 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_bottom_track_17_undriven_sram_inv), + .out(chany_bottom_out[8]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_19 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_bottom_track_19_undriven_sram_inv), + .out(chany_bottom_out[9]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_21 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_bottom_track_21_undriven_sram_inv), + .out(chany_bottom_out[10]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_23 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_bottom_track_23_undriven_sram_inv), + .out(chany_bottom_out[11]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_25 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_bottom_track_25_undriven_sram_inv), + .out(chany_bottom_out[12]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_27 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_bottom_track_27_undriven_sram_inv), + .out(chany_bottom_out[13]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_29 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_3 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[2]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_31 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_bottom_track_31_undriven_sram_inv), + .out(chany_bottom_out[15]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_33 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_bottom_track_33_undriven_sram_inv), + .out(chany_bottom_out[16]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_35 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_bottom_track_35_undriven_sram_inv), + .out(chany_bottom_out[17]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_45 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_47 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_bottom_track_47_undriven_sram_inv), + .out(chany_bottom_out[23]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_49 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_bottom_track_49_undriven_sram_inv), + .out(chany_bottom_out[24]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_5 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_51 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size3_7_sram), + .sram_inv(mux_bottom_track_51_undriven_sram_inv), + .out(chany_bottom_out[25]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_53 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_bottom_track_53_undriven_sram_inv), + .out(chany_bottom_out[26]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_55 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_bottom_track_55_undriven_sram_inv), + .out(chany_bottom_out[27]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_57 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_bottom_track_57_undriven_sram_inv), + .out(chany_bottom_out[28]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_59 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[0]}), + .sram(mux_tree_tapbuf_size2_11_sram), + .sram_inv(mux_bottom_track_59_undriven_sram_inv), + .out(chany_bottom_out[29]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_7 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[4]}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_9 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[5]}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_bottom_track_9_undriven_sram_inv), + .out(chany_bottom_out[4]) + ); + mux_tree_tapbuf_size5 mux_left_track_1 + ( + .in({chany_bottom_in[29], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_6_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size5 mux_left_track_11 + ( + .in({chany_bottom_in[4], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size5_11_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size3 mux_left_track_13 + ( + .in({chany_bottom_in[5], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_8_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size3 mux_left_track_15 + ( + .in({chany_bottom_in[6], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size3_9_sram), + .sram_inv(mux_left_track_15_undriven_sram_inv), + .out(chanx_left_out[7]) + ); + mux_tree_tapbuf_size3 mux_left_track_17 + ( + .in({chany_bottom_in[7], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_10_sram), + .sram_inv(mux_left_track_17_undriven_sram_inv), + .out(chanx_left_out[8]) + ); + mux_tree_tapbuf_size2 mux_left_track_19 + ( + .in({chany_bottom_in[8], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_12_sram), + .sram_inv(mux_left_track_19_undriven_sram_inv), + .out(chanx_left_out[9]) + ); + mux_tree_tapbuf_size2 mux_left_track_21 + ( + .in({chany_bottom_in[9], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_13_sram), + .sram_inv(mux_left_track_21_undriven_sram_inv), + .out(chanx_left_out[10]) + ); + mux_tree_tapbuf_size2 mux_left_track_23 + ( + .in({chany_bottom_in[10], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_14_sram), + .sram_inv(mux_left_track_23_undriven_sram_inv), + .out(chanx_left_out[11]) + ); + mux_tree_tapbuf_size2 mux_left_track_25 + ( + .in({chany_bottom_in[11], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_15_sram), + .sram_inv(mux_left_track_25_undriven_sram_inv), + .out(chanx_left_out[12]) + ); + mux_tree_tapbuf_size2 mux_left_track_27 + ( + .in({chany_bottom_in[12], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size2_16_sram), + .sram_inv(mux_left_track_27_undriven_sram_inv), + .out(chanx_left_out[13]) + ); + mux_tree_tapbuf_size3 mux_left_track_29 + ( + .in({chany_bottom_in[13], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_11_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size5 mux_left_track_3 + ( + .in({chany_bottom_in[0], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size5_7_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size3 mux_left_track_31 + ( + .in({chany_bottom_in[14], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size3_12_sram), + .sram_inv(mux_left_track_31_undriven_sram_inv), + .out(chanx_left_out[15]) + ); + mux_tree_tapbuf_size3 mux_left_track_33 + ( + .in({chany_bottom_in[15], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_13_sram), + .sram_inv(mux_left_track_33_undriven_sram_inv), + .out(chanx_left_out[16]) + ); + mux_tree_tapbuf_size3 mux_left_track_35 + ( + .in({chany_bottom_in[16], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_14_sram), + .sram_inv(mux_left_track_35_undriven_sram_inv), + .out(chanx_left_out[17]) + ); + mux_tree_tapbuf_size2 mux_left_track_37 + ( + .in({chany_bottom_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_17_sram), + .sram_inv(mux_left_track_37_undriven_sram_inv), + .out(chanx_left_out[18]) + ); + mux_tree_tapbuf_size2 mux_left_track_39 + ( + .in({chany_bottom_in[18], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_18_sram), + .sram_inv(mux_left_track_39_undriven_sram_inv), + .out(chanx_left_out[19]) + ); + mux_tree_tapbuf_size2 mux_left_track_41 + ( + .in({chany_bottom_in[19], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_19_sram), + .sram_inv(mux_left_track_41_undriven_sram_inv), + .out(chanx_left_out[20]) + ); + mux_tree_tapbuf_size2 mux_left_track_43 + ( + .in({chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size2_20_sram), + .sram_inv(mux_left_track_43_undriven_sram_inv), + .out(chanx_left_out[21]) + ); + mux_tree_tapbuf_size3 mux_left_track_45 + ( + .in({chany_bottom_in[21], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_15_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size3 mux_left_track_47 + ( + .in({chany_bottom_in[22], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size3_16_sram), + .sram_inv(mux_left_track_47_undriven_sram_inv), + .out(chanx_left_out[23]) + ); + mux_tree_tapbuf_size3 mux_left_track_49 + ( + .in({chany_bottom_in[23], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_17_sram), + .sram_inv(mux_left_track_49_undriven_sram_inv), + .out(chanx_left_out[24]) + ); + mux_tree_tapbuf_size5 mux_left_track_5 + ( + .in({chany_bottom_in[1], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size5_8_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size2 mux_left_track_51 + ( + .in({chany_bottom_in[24], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram), + .sram_inv(mux_left_track_51_undriven_sram_inv), + .out(chanx_left_out[25]) + ); + mux_tree_tapbuf_size2 mux_left_track_53 + ( + .in({chany_bottom_in[25], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_22_sram), + .sram_inv(mux_left_track_53_undriven_sram_inv), + .out(chanx_left_out[26]) + ); + mux_tree_tapbuf_size2 mux_left_track_55 + ( + .in({chany_bottom_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_23_sram), + .sram_inv(mux_left_track_55_undriven_sram_inv), + .out(chanx_left_out[27]) + ); + mux_tree_tapbuf_size2 mux_left_track_57 + ( + .in({chany_bottom_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_24_sram), + .sram_inv(mux_left_track_57_undriven_sram_inv), + .out(chanx_left_out[28]) + ); + mux_tree_tapbuf_size3 mux_left_track_59 + ( + .in({chany_bottom_in[28], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_18_sram), + .sram_inv(mux_left_track_59_undriven_sram_inv), + .out(chanx_left_out[29]) + ); + mux_tree_tapbuf_size5 mux_left_track_7 + ( + .in({chany_bottom_in[2], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_9_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size5 mux_left_track_9 + ( + .in({chany_bottom_in[3], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size5_10_sram), + .sram_inv(mux_left_track_9_undriven_sram_inv), + .out(chanx_left_out[4]) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__buf_2.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__buf_2.v new file mode 100644 index 0000000..59f024a --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__buf_2.v @@ -0,0 +1,16 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sky130_fd_sc_hd__buf_2 +( + A, + X +); + + input A; + output X; + + wire A; + wire X; + +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__buf_4.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__buf_4.v new file mode 100644 index 0000000..67a9d33 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__buf_4.v @@ -0,0 +1,16 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sky130_fd_sc_hd__buf_4 +( + A, + X +); + + input A; + output X; + + wire A; + wire X; + +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__dfrtp_1.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__dfrtp_1.v new file mode 100644 index 0000000..d7ebaf1 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__dfrtp_1.v @@ -0,0 +1,22 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sky130_fd_sc_hd__dfrtp_1 +( + CLK, + D, + RESET_B, + Q +); + + input CLK; + input D; + input RESET_B; + output Q; + + wire CLK; + wire D; + wire Q; + wire RESET_B; + +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__inv_1.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__inv_1.v new file mode 100644 index 0000000..9a346c7 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__inv_1.v @@ -0,0 +1,16 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sky130_fd_sc_hd__inv_1 +( + A, + Y +); + + input A; + output Y; + + wire A; + wire Y; + +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__inv_2.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__inv_2.v new file mode 100644 index 0000000..23e363e --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__inv_2.v @@ -0,0 +1,16 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sky130_fd_sc_hd__inv_2 +( + A, + Y +); + + input A; + output Y; + + wire A; + wire Y; + +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__mux2_1.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__mux2_1.v new file mode 100644 index 0000000..8a7269f --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__mux2_1.v @@ -0,0 +1,22 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sky130_fd_sc_hd__mux2_1 +( + A0, + A1, + S, + X +); + + input A0; + input A1; + input S; + output X; + + wire A0; + wire A1; + wire S; + wire X; + +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__mux2_1_wrapper.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__mux2_1_wrapper.v new file mode 100644 index 0000000..5ec7a3a --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__mux2_1_wrapper.v @@ -0,0 +1,22 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sky130_fd_sc_hd__mux2_1_wrapper +( + A0, + A1, + S, + X +); + + input A0; + input A1; + input S; + output X; + + wire A0; + wire A1; + wire S; + wire X; + +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__or2_1.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__or2_1.v new file mode 100644 index 0000000..8fa647f --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__or2_1.v @@ -0,0 +1,19 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sky130_fd_sc_hd__or2_1 +( + A, + B, + X +); + + input A; + input B; + output X; + + wire A; + wire B; + wire X; + +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__sdfrtp_1.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__sdfrtp_1.v new file mode 100644 index 0000000..0288267 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sky130_fd_sc_hd__sdfrtp_1.v @@ -0,0 +1,28 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sky130_fd_sc_hd__sdfrtp_1 +( + CLK, + D, + RESET_B, + SCD, + SCE, + Q +); + + input CLK; + input D; + input RESET_B; + input SCD; + input SCE; + output Q; + + wire CLK; + wire D; + wire Q; + wire RESET_B; + wire SCD; + wire SCE; + +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_left_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_left_tile.v new file mode 100644 index 0000000..f03df8a --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_left_tile.v @@ -0,0 +1,77 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module bottom_left_tile +( + ccff_head, + chanx_right_in, + chany_top_in, + pReset, + prog_clk, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail, + chanx_right_out, + chany_top_out +); + + input ccff_head; + input [29:0]chanx_right_in; + input [29:0]chany_top_in; + input pReset; + input prog_clk; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + output [29:0]chanx_right_out; + output [29:0]chany_top_out; + + wire ccff_head; + wire ccff_tail; + wire [29:0]chanx_right_in; + wire [29:0]chanx_right_out; + wire [29:0]chany_top_in; + wire [29:0]chany_top_out; + wire pReset; + wire prog_clk; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + + sb_0__0_ sb_0__0_ + ( + .ccff_head(ccff_head), + .chanx_right_in(chanx_right_in), + .chany_top_in(chany_top_in), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail), + .chanx_right_out(chanx_right_out), + .chany_top_out(chany_top_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_right_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_right_tile.v new file mode 100644 index 0000000..ca20c14 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_right_tile.v @@ -0,0 +1,151 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module bottom_right_tile +( + IO_ISOL_N, + ccff_head, + ccff_head_1, + chanx_left_in, + chany_top_in, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + pReset, + prog_clk, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail, + ccff_tail_0, + chanx_left_out, + chany_top_out, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + top_width_0_height_0_subtile_0__pin_inpad_0_, + top_width_0_height_0_subtile_1__pin_inpad_0_, + top_width_0_height_0_subtile_2__pin_inpad_0_, + top_width_0_height_0_subtile_3__pin_inpad_0_ +); + + input IO_ISOL_N; + input ccff_head; + input ccff_head_1; + input [29:0]chanx_left_in; + input [29:0]chany_top_in; + input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input pReset; + input prog_clk; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + output ccff_tail_0; + output [29:0]chanx_left_out; + output [29:0]chany_top_out; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output top_width_0_height_0_subtile_0__pin_inpad_0_; + output top_width_0_height_0_subtile_1__pin_inpad_0_; + output top_width_0_height_0_subtile_2__pin_inpad_0_; + output top_width_0_height_0_subtile_3__pin_inpad_0_; + + wire IO_ISOL_N; + wire ccff_head; + wire ccff_head_1; + wire ccff_tail; + wire ccff_tail_0; + wire ccff_tail_1; + wire [29:0]chanx_left_in; + wire [29:0]chanx_left_out; + wire [29:0]chanx_left_out_0; + wire [29:0]chanx_right_out; + wire [29:0]chany_top_in; + wire [29:0]chany_top_out; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire pReset; + wire prog_clk; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire top_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_width_0_height_0_subtile_3__pin_inpad_0_; + + cbx_1__0_ cbx_8__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(ccff_head), + .ccff_head_0(ccff_tail_1), + .chanx_left_in(chanx_left_in), + .chanx_right_in(chanx_left_out_0), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .ccff_tail_0(ccff_tail_0), + .chanx_left_out(chanx_left_out), + .chanx_right_out(chanx_right_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), + .top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(top_width_0_height_0_subtile_3__pin_inpad_0_) + ); + sb_8__0_ sb_8__0_ + ( + .ccff_head(ccff_head_1), + .chanx_left_in(chanx_right_out), + .chany_top_in(chany_top_in), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(top_width_0_height_0_subtile_3__pin_inpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail_1), + .chanx_left_out(chanx_left_out_0), + .chany_top_out(chany_top_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_tile.v new file mode 100644 index 0000000..987bd4e --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_tile.v @@ -0,0 +1,159 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module bottom_tile +( + IO_ISOL_N, + ccff_head, + ccff_head_1, + chanx_left_in, + chanx_right_in_0, + chany_top_in, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + pReset, + prog_clk, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + ccff_tail, + ccff_tail_0, + chanx_left_out, + chanx_right_out_0, + chany_top_out, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + top_width_0_height_0_subtile_0__pin_inpad_0_, + top_width_0_height_0_subtile_1__pin_inpad_0_, + top_width_0_height_0_subtile_2__pin_inpad_0_, + top_width_0_height_0_subtile_3__pin_inpad_0_ +); + + input IO_ISOL_N; + input ccff_head; + input ccff_head_1; + input [29:0]chanx_left_in; + input [29:0]chanx_right_in_0; + input [29:0]chany_top_in; + input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input pReset; + input prog_clk; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + output ccff_tail; + output ccff_tail_0; + output [29:0]chanx_left_out; + output [29:0]chanx_right_out_0; + output [29:0]chany_top_out; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output top_width_0_height_0_subtile_0__pin_inpad_0_; + output top_width_0_height_0_subtile_1__pin_inpad_0_; + output top_width_0_height_0_subtile_2__pin_inpad_0_; + output top_width_0_height_0_subtile_3__pin_inpad_0_; + + wire IO_ISOL_N; + wire ccff_head; + wire ccff_head_1; + wire ccff_tail; + wire ccff_tail_0; + wire ccff_tail_1; + wire [29:0]chanx_left_in; + wire [29:0]chanx_left_out; + wire [29:0]chanx_left_out_0; + wire [29:0]chanx_right_in_0; + wire [29:0]chanx_right_out; + wire [29:0]chanx_right_out_0; + wire [29:0]chany_top_in; + wire [29:0]chany_top_out; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire pReset; + wire prog_clk; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire top_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_width_0_height_0_subtile_3__pin_inpad_0_; + + cbx_1__0_ cbx_1__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(ccff_head), + .ccff_head_0(ccff_tail_1), + .chanx_left_in(chanx_left_in), + .chanx_right_in(chanx_left_out_0), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .ccff_tail_0(ccff_tail_0), + .chanx_left_out(chanx_left_out), + .chanx_right_out(chanx_right_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), + .top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(top_width_0_height_0_subtile_3__pin_inpad_0_) + ); + sb_1__0_ sb_1__0_ + ( + .ccff_head(ccff_head_1), + .chanx_left_in(chanx_right_out), + .chanx_right_in(chanx_right_in_0), + .chany_top_in(chany_top_in), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(top_width_0_height_0_subtile_3__pin_inpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_), + .ccff_tail(ccff_tail_1), + .chanx_left_out(chanx_left_out_0), + .chanx_right_out(chanx_right_out_0), + .chany_top_out(chany_top_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/left_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/left_tile.v new file mode 100644 index 0000000..7666f02 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/left_tile.v @@ -0,0 +1,156 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module left_tile +( + IO_ISOL_N, + ccff_head, + ccff_head_0, + chanx_right_in, + chany_bottom_in, + chany_top_in_0, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + pReset, + prog_clk, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail, + ccff_tail_0, + chanx_right_out, + chany_bottom_out, + chany_top_out_0, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + right_width_0_height_0_subtile_0__pin_inpad_0_, + right_width_0_height_0_subtile_1__pin_inpad_0_, + right_width_0_height_0_subtile_2__pin_inpad_0_, + right_width_0_height_0_subtile_3__pin_inpad_0_ +); + + input IO_ISOL_N; + input ccff_head; + input ccff_head_0; + input [29:0]chanx_right_in; + input [29:0]chany_bottom_in; + input [29:0]chany_top_in_0; + input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input pReset; + input prog_clk; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + output ccff_tail_0; + output [29:0]chanx_right_out; + output [29:0]chany_bottom_out; + output [29:0]chany_top_out_0; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output right_width_0_height_0_subtile_0__pin_inpad_0_; + output right_width_0_height_0_subtile_1__pin_inpad_0_; + output right_width_0_height_0_subtile_2__pin_inpad_0_; + output right_width_0_height_0_subtile_3__pin_inpad_0_; + + wire IO_ISOL_N; + wire ccff_head; + wire ccff_head_0; + wire ccff_tail; + wire ccff_tail_0; + wire [29:0]chanx_right_in; + wire [29:0]chanx_right_out; + wire [29:0]chany_bottom_in; + wire [29:0]chany_bottom_out; + wire [29:0]chany_bottom_out_0; + wire [29:0]chany_top_in_0; + wire [29:0]chany_top_out; + wire [29:0]chany_top_out_0; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire pReset; + wire prog_clk; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire right_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_width_0_height_0_subtile_3__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + + cby_0__1_ cby_0__1_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head_0(ccff_head_0), + .chany_bottom_in(chany_bottom_in), + .chany_top_in(chany_bottom_out_0), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail), + .chany_bottom_out(chany_bottom_out), + .chany_top_out(chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), + .right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(right_width_0_height_0_subtile_3__pin_inpad_0_) + ); + sb_0__1_ sb_0__1_ + ( + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(ccff_head), + .chanx_right_in(chanx_right_in), + .chany_bottom_in(chany_top_out), + .chany_top_in(chany_top_in_0), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail_0), + .chanx_right_out(chanx_right_out), + .chany_bottom_out(chany_bottom_out_0), + .chany_top_out(chany_top_out_0) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/right_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/right_tile.v new file mode 100644 index 0000000..74f8d7a --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/right_tile.v @@ -0,0 +1,398 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module right_tile +( + IO_ISOL_N, + Test_en, + ccff_head_0_0, + ccff_head_1, + ccff_head_2, + chanx_left_in, + chany_bottom_in, + chany_top_in_0, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + left_width_0_height_0_subtile_0__pin_clk_0_, + left_width_0_height_0_subtile_0__pin_reset_0_, + pReset, + prog_clk, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + top_width_0_height_0_subtile_0__pin_cin_0_, + top_width_0_height_0_subtile_0__pin_reg_in_0_, + top_width_0_height_0_subtile_0__pin_sc_in_0_, + bottom_width_0_height_0_subtile_0__pin_cout_0_, + bottom_width_0_height_0_subtile_0__pin_reg_out_0_, + bottom_width_0_height_0_subtile_0__pin_sc_out_0_, + ccff_tail, + ccff_tail_0, + ccff_tail_1, + chanx_left_out, + chany_bottom_out, + chany_top_out_0, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + left_width_0_height_0_subtile_0__pin_inpad_0_, + left_width_0_height_0_subtile_1__pin_inpad_0_, + left_width_0_height_0_subtile_2__pin_inpad_0_, + left_width_0_height_0_subtile_3__pin_inpad_0_, + right_width_0_height_0_subtile_0__pin_O_10_, + right_width_0_height_0_subtile_0__pin_O_11_, + right_width_0_height_0_subtile_0__pin_O_12_, + right_width_0_height_0_subtile_0__pin_O_13_, + right_width_0_height_0_subtile_0__pin_O_14_, + right_width_0_height_0_subtile_0__pin_O_15_, + right_width_0_height_0_subtile_0__pin_O_8_, + right_width_0_height_0_subtile_0__pin_O_9_, + top_width_0_height_0_subtile_0__pin_O_0_, + top_width_0_height_0_subtile_0__pin_O_1_, + top_width_0_height_0_subtile_0__pin_O_2_, + top_width_0_height_0_subtile_0__pin_O_3_, + top_width_0_height_0_subtile_0__pin_O_4_, + top_width_0_height_0_subtile_0__pin_O_5_, + top_width_0_height_0_subtile_0__pin_O_6_, + top_width_0_height_0_subtile_0__pin_O_7_ +); + + input IO_ISOL_N; + input Test_en; + input ccff_head_0_0; + input ccff_head_1; + input ccff_head_2; + input [29:0]chanx_left_in; + input [29:0]chany_bottom_in; + input [29:0]chany_top_in_0; + input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input left_width_0_height_0_subtile_0__pin_clk_0_; + input left_width_0_height_0_subtile_0__pin_reset_0_; + input pReset; + input prog_clk; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + input top_width_0_height_0_subtile_0__pin_cin_0_; + input top_width_0_height_0_subtile_0__pin_reg_in_0_; + input top_width_0_height_0_subtile_0__pin_sc_in_0_; + output bottom_width_0_height_0_subtile_0__pin_cout_0_; + output bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + output bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + output ccff_tail; + output ccff_tail_0; + output ccff_tail_1; + output [29:0]chanx_left_out; + output [29:0]chany_bottom_out; + output [29:0]chany_top_out_0; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output left_width_0_height_0_subtile_0__pin_inpad_0_; + output left_width_0_height_0_subtile_1__pin_inpad_0_; + output left_width_0_height_0_subtile_2__pin_inpad_0_; + output left_width_0_height_0_subtile_3__pin_inpad_0_; + output right_width_0_height_0_subtile_0__pin_O_10_; + output right_width_0_height_0_subtile_0__pin_O_11_; + output right_width_0_height_0_subtile_0__pin_O_12_; + output right_width_0_height_0_subtile_0__pin_O_13_; + output right_width_0_height_0_subtile_0__pin_O_14_; + output right_width_0_height_0_subtile_0__pin_O_15_; + output right_width_0_height_0_subtile_0__pin_O_8_; + output right_width_0_height_0_subtile_0__pin_O_9_; + output top_width_0_height_0_subtile_0__pin_O_0_; + output top_width_0_height_0_subtile_0__pin_O_1_; + output top_width_0_height_0_subtile_0__pin_O_2_; + output top_width_0_height_0_subtile_0__pin_O_3_; + output top_width_0_height_0_subtile_0__pin_O_4_; + output top_width_0_height_0_subtile_0__pin_O_5_; + output top_width_0_height_0_subtile_0__pin_O_6_; + output top_width_0_height_0_subtile_0__pin_O_7_; + + wire IO_ISOL_N; + wire Test_en; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire ccff_head_0_0; + wire ccff_head_1; + wire ccff_head_2; + wire ccff_tail; + wire ccff_tail_0; + wire ccff_tail_0_0; + wire ccff_tail_1; + wire ccff_tail_2; + wire [29:0]chanx_left_in; + wire [29:0]chanx_left_out; + wire [29:0]chanx_left_out_0; + wire [29:0]chanx_right_out; + wire [29:0]chany_bottom_in; + wire [29:0]chany_bottom_out; + wire [29:0]chany_bottom_out_0; + wire [29:0]chany_top_in_0; + wire [29:0]chany_top_out; + wire [29:0]chany_top_out_0; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire left_width_0_height_0_subtile_0__pin_clk_0_; + wire left_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_width_0_height_0_subtile_0__pin_reset_0_; + wire left_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_width_0_height_0_subtile_3__pin_inpad_0_; + wire pReset; + wire prog_clk; + wire right_width_0_height_0_subtile_0__pin_O_10_; + wire right_width_0_height_0_subtile_0__pin_O_11_; + wire right_width_0_height_0_subtile_0__pin_O_12_; + wire right_width_0_height_0_subtile_0__pin_O_13_; + wire right_width_0_height_0_subtile_0__pin_O_14_; + wire right_width_0_height_0_subtile_0__pin_O_15_; + wire right_width_0_height_0_subtile_0__pin_O_8_; + wire right_width_0_height_0_subtile_0__pin_O_9_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire top_width_0_height_0_subtile_0__pin_O_0_; + wire top_width_0_height_0_subtile_0__pin_O_1_; + wire top_width_0_height_0_subtile_0__pin_O_2_; + wire top_width_0_height_0_subtile_0__pin_O_3_; + wire top_width_0_height_0_subtile_0__pin_O_4_; + wire top_width_0_height_0_subtile_0__pin_O_5_; + wire top_width_0_height_0_subtile_0__pin_O_6_; + wire top_width_0_height_0_subtile_0__pin_O_7_; + wire top_width_0_height_0_subtile_0__pin_cin_0_; + wire top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire top_width_0_height_0_subtile_0__pin_sc_in_0_; + + cbx_1__1_ cbx_8__1_ + ( + .ccff_head(ccff_tail_2), + .chanx_left_in(chanx_left_in), + .chanx_right_in(chanx_left_out_0), + .pReset(pReset), + .prog_clk(prog_clk), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(ccff_tail_0), + .chanx_left_out(chanx_left_out), + .chanx_right_out(chanx_right_out) + ); + cby_8__1_ cby_8__1_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(ccff_head_1), + .ccff_head_0(ccff_head_0_0), + .chany_bottom_in(chany_bottom_in), + .chany_top_in(chany_bottom_out_0), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail_1), + .ccff_tail_0(ccff_tail_0_0), + .chany_bottom_out(chany_bottom_out), + .chany_top_out(chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_inpad_0_(left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(left_width_0_height_0_subtile_3__pin_inpad_0_) + ); + grid_clb grid_clb_8__1_ + ( + .Test_en(Test_en), + .ccff_head(ccff_tail_0_0), + .left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_), + .left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_cin_0_(top_width_0_height_0_subtile_0__pin_cin_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(top_width_0_height_0_subtile_0__pin_sc_in_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(ccff_tail), + .right_width_0_height_0_subtile_0__pin_O_10_(right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(top_width_0_height_0_subtile_0__pin_O_7_) + ); + sb_8__1_ sb_8__1_ + ( + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(ccff_head_2), + .chanx_left_in(chanx_right_out), + .chany_bottom_in(chany_top_out), + .chany_top_in(chany_top_in_0), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(top_width_0_height_0_subtile_0__pin_O_7_), + .pReset(pReset), + .prog_clk(prog_clk), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail_2), + .chanx_left_out(chanx_left_out_0), + .chany_bottom_out(chany_bottom_out_0), + .chany_top_out(chany_top_out_0) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/tile.v new file mode 100644 index 0000000..622f1f0 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/tile.v @@ -0,0 +1,378 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module tile +( + Test_en, + ccff_head_1, + ccff_head_2, + chanx_left_in, + chanx_right_in_0, + chany_bottom_in, + chany_top_in_0, + left_width_0_height_0_subtile_0__pin_clk_0_, + left_width_0_height_0_subtile_0__pin_reset_0_, + pReset, + prog_clk, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_width_0_height_0_subtile_0__pin_cin_0_, + top_width_0_height_0_subtile_0__pin_reg_in_0_, + top_width_0_height_0_subtile_0__pin_sc_in_0_, + bottom_width_0_height_0_subtile_0__pin_cout_0_, + bottom_width_0_height_0_subtile_0__pin_reg_out_0_, + bottom_width_0_height_0_subtile_0__pin_sc_out_0_, + ccff_tail, + ccff_tail_0, + chanx_left_out, + chanx_right_out_0, + chany_bottom_out, + chany_top_out_0, + right_width_0_height_0_subtile_0__pin_O_10_, + right_width_0_height_0_subtile_0__pin_O_11_, + right_width_0_height_0_subtile_0__pin_O_12_, + right_width_0_height_0_subtile_0__pin_O_13_, + right_width_0_height_0_subtile_0__pin_O_14_, + right_width_0_height_0_subtile_0__pin_O_15_, + right_width_0_height_0_subtile_0__pin_O_8_, + right_width_0_height_0_subtile_0__pin_O_9_, + top_width_0_height_0_subtile_0__pin_O_0_, + top_width_0_height_0_subtile_0__pin_O_1_, + top_width_0_height_0_subtile_0__pin_O_2_, + top_width_0_height_0_subtile_0__pin_O_3_, + top_width_0_height_0_subtile_0__pin_O_4_, + top_width_0_height_0_subtile_0__pin_O_5_, + top_width_0_height_0_subtile_0__pin_O_6_, + top_width_0_height_0_subtile_0__pin_O_7_ +); + + input Test_en; + input ccff_head_1; + input ccff_head_2; + input [29:0]chanx_left_in; + input [29:0]chanx_right_in_0; + input [29:0]chany_bottom_in; + input [29:0]chany_top_in_0; + input left_width_0_height_0_subtile_0__pin_clk_0_; + input left_width_0_height_0_subtile_0__pin_reset_0_; + input pReset; + input prog_clk; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input top_width_0_height_0_subtile_0__pin_cin_0_; + input top_width_0_height_0_subtile_0__pin_reg_in_0_; + input top_width_0_height_0_subtile_0__pin_sc_in_0_; + output bottom_width_0_height_0_subtile_0__pin_cout_0_; + output bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + output bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + output ccff_tail; + output ccff_tail_0; + output [29:0]chanx_left_out; + output [29:0]chanx_right_out_0; + output [29:0]chany_bottom_out; + output [29:0]chany_top_out_0; + output right_width_0_height_0_subtile_0__pin_O_10_; + output right_width_0_height_0_subtile_0__pin_O_11_; + output right_width_0_height_0_subtile_0__pin_O_12_; + output right_width_0_height_0_subtile_0__pin_O_13_; + output right_width_0_height_0_subtile_0__pin_O_14_; + output right_width_0_height_0_subtile_0__pin_O_15_; + output right_width_0_height_0_subtile_0__pin_O_8_; + output right_width_0_height_0_subtile_0__pin_O_9_; + output top_width_0_height_0_subtile_0__pin_O_0_; + output top_width_0_height_0_subtile_0__pin_O_1_; + output top_width_0_height_0_subtile_0__pin_O_2_; + output top_width_0_height_0_subtile_0__pin_O_3_; + output top_width_0_height_0_subtile_0__pin_O_4_; + output top_width_0_height_0_subtile_0__pin_O_5_; + output top_width_0_height_0_subtile_0__pin_O_6_; + output top_width_0_height_0_subtile_0__pin_O_7_; + + wire Test_en; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire ccff_head_1; + wire ccff_head_2; + wire ccff_tail; + wire ccff_tail_0; + wire ccff_tail_1; + wire ccff_tail_2; + wire [29:0]chanx_left_in; + wire [29:0]chanx_left_out; + wire [29:0]chanx_left_out_0; + wire [29:0]chanx_right_in_0; + wire [29:0]chanx_right_out; + wire [29:0]chanx_right_out_0; + wire [29:0]chany_bottom_in; + wire [29:0]chany_bottom_out; + wire [29:0]chany_bottom_out_0; + wire [29:0]chany_top_in_0; + wire [29:0]chany_top_out; + wire [29:0]chany_top_out_0; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire left_width_0_height_0_subtile_0__pin_clk_0_; + wire left_width_0_height_0_subtile_0__pin_reset_0_; + wire pReset; + wire prog_clk; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire right_width_0_height_0_subtile_0__pin_O_10_; + wire right_width_0_height_0_subtile_0__pin_O_11_; + wire right_width_0_height_0_subtile_0__pin_O_12_; + wire right_width_0_height_0_subtile_0__pin_O_13_; + wire right_width_0_height_0_subtile_0__pin_O_14_; + wire right_width_0_height_0_subtile_0__pin_O_15_; + wire right_width_0_height_0_subtile_0__pin_O_8_; + wire right_width_0_height_0_subtile_0__pin_O_9_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire top_width_0_height_0_subtile_0__pin_O_0_; + wire top_width_0_height_0_subtile_0__pin_O_1_; + wire top_width_0_height_0_subtile_0__pin_O_2_; + wire top_width_0_height_0_subtile_0__pin_O_3_; + wire top_width_0_height_0_subtile_0__pin_O_4_; + wire top_width_0_height_0_subtile_0__pin_O_5_; + wire top_width_0_height_0_subtile_0__pin_O_6_; + wire top_width_0_height_0_subtile_0__pin_O_7_; + wire top_width_0_height_0_subtile_0__pin_cin_0_; + wire top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire top_width_0_height_0_subtile_0__pin_sc_in_0_; + + cbx_1__1_ cbx_1__1_ + ( + .ccff_head(ccff_tail_2), + .chanx_left_in(chanx_left_in), + .chanx_right_in(chanx_left_out_0), + .pReset(pReset), + .prog_clk(prog_clk), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(ccff_tail_0), + .chanx_left_out(chanx_left_out), + .chanx_right_out(chanx_right_out) + ); + cby_1__1_ cby_1__1_ + ( + .ccff_head(ccff_head_1), + .chany_bottom_in(chany_bottom_in), + .chany_top_in(chany_bottom_out_0), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail_1), + .chany_bottom_out(chany_bottom_out), + .chany_top_out(chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_) + ); + grid_clb grid_clb_1__1_ + ( + .Test_en(Test_en), + .ccff_head(ccff_tail_1), + .left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_), + .left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_cin_0_(top_width_0_height_0_subtile_0__pin_cin_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(top_width_0_height_0_subtile_0__pin_sc_in_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(ccff_tail), + .right_width_0_height_0_subtile_0__pin_O_10_(right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(top_width_0_height_0_subtile_0__pin_O_7_) + ); + sb_1__1_ sb_1__1_ + ( + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(right_width_0_height_0_subtile_0__pin_O_9_), + .ccff_head(ccff_head_2), + .chanx_left_in(chanx_right_out), + .chanx_right_in(chanx_right_in_0), + .chany_bottom_in(chany_top_out), + .chany_top_in(chany_top_in_0), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(top_width_0_height_0_subtile_0__pin_O_7_), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_), + .ccff_tail(ccff_tail_2), + .chanx_left_out(chanx_left_out_0), + .chanx_right_out(chanx_right_out_0), + .chany_bottom_out(chany_bottom_out_0), + .chany_top_out(chany_top_out_0) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_left_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_left_tile.v new file mode 100644 index 0000000..bc3bfcd --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_left_tile.v @@ -0,0 +1,148 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module top_left_tile +( + IO_ISOL_N, + ccff_head, + ccff_head_0, + chanx_right_in, + chany_bottom_in_0, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + pReset, + prog_clk, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail, + ccff_tail_0, + chanx_right_out, + chany_bottom_out_0, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + right_width_0_height_0_subtile_0__pin_inpad_0_, + right_width_0_height_0_subtile_1__pin_inpad_0_, + right_width_0_height_0_subtile_2__pin_inpad_0_, + right_width_0_height_0_subtile_3__pin_inpad_0_ +); + + input IO_ISOL_N; + input ccff_head; + input ccff_head_0; + input [29:0]chanx_right_in; + input [29:0]chany_bottom_in_0; + input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input pReset; + input prog_clk; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + output ccff_tail_0; + output [29:0]chanx_right_out; + output [29:0]chany_bottom_out_0; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output right_width_0_height_0_subtile_0__pin_inpad_0_; + output right_width_0_height_0_subtile_1__pin_inpad_0_; + output right_width_0_height_0_subtile_2__pin_inpad_0_; + output right_width_0_height_0_subtile_3__pin_inpad_0_; + + wire IO_ISOL_N; + wire ccff_head; + wire ccff_head_0; + wire ccff_tail; + wire ccff_tail_0; + wire [29:0]chanx_right_in; + wire [29:0]chanx_right_out; + wire [29:0]chany_bottom_in_0; + wire [29:0]chany_bottom_out; + wire [29:0]chany_bottom_out_0; + wire [29:0]chany_top_out; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire pReset; + wire prog_clk; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire right_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_width_0_height_0_subtile_3__pin_inpad_0_; + + cby_0__1_ cby_0__8_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head_0(ccff_head_0), + .chany_bottom_in(chany_bottom_in_0), + .chany_top_in(chany_bottom_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail_0), + .chany_bottom_out(chany_bottom_out_0), + .chany_top_out(chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), + .right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(right_width_0_height_0_subtile_3__pin_inpad_0_) + ); + sb_0__8_ sb_0__8_ + ( + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(ccff_head), + .chanx_right_in(chanx_right_in), + .chany_bottom_in(chany_top_out), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail), + .chanx_right_out(chanx_right_out), + .chany_bottom_out(chany_bottom_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_right_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_right_tile.v new file mode 100644 index 0000000..7a1f8fc --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_right_tile.v @@ -0,0 +1,370 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module top_right_tile +( + IO_ISOL_N, + Test_en, + ccff_head_0_0, + ccff_head_1, + chanx_left_in, + chany_bottom_in, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN_0, + left_width_0_height_0_subtile_0__pin_clk_0_, + left_width_0_height_0_subtile_0__pin_reset_0_, + pReset, + prog_clk, + top_width_0_height_0_subtile_0__pin_cin_0_, + top_width_0_height_0_subtile_0__pin_reg_in_0_, + top_width_0_height_0_subtile_0__pin_sc_in_0_, + bottom_width_0_height_0_subtile_0__pin_cout_0_, + bottom_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_width_0_height_0_subtile_0__pin_reg_out_0_, + bottom_width_0_height_0_subtile_0__pin_sc_out_0_, + bottom_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail, + ccff_tail_0, + chanx_left_out, + chany_bottom_out, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_0, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_0, + left_width_0_height_0_subtile_0__pin_inpad_0_, + left_width_0_height_0_subtile_1__pin_inpad_0_, + left_width_0_height_0_subtile_2__pin_inpad_0_, + left_width_0_height_0_subtile_3__pin_inpad_0_, + right_width_0_height_0_subtile_0__pin_O_10_, + right_width_0_height_0_subtile_0__pin_O_11_, + right_width_0_height_0_subtile_0__pin_O_12_, + right_width_0_height_0_subtile_0__pin_O_13_, + right_width_0_height_0_subtile_0__pin_O_14_, + right_width_0_height_0_subtile_0__pin_O_15_, + right_width_0_height_0_subtile_0__pin_O_8_, + right_width_0_height_0_subtile_0__pin_O_9_, + top_width_0_height_0_subtile_0__pin_O_0_, + top_width_0_height_0_subtile_0__pin_O_1_, + top_width_0_height_0_subtile_0__pin_O_2_, + top_width_0_height_0_subtile_0__pin_O_3_, + top_width_0_height_0_subtile_0__pin_O_4_, + top_width_0_height_0_subtile_0__pin_O_5_, + top_width_0_height_0_subtile_0__pin_O_6_, + top_width_0_height_0_subtile_0__pin_O_7_ +); + + input IO_ISOL_N; + input Test_en; + input ccff_head_0_0; + input ccff_head_1; + input [29:0]chanx_left_in; + input [29:0]chany_bottom_in; + input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN_0; + input left_width_0_height_0_subtile_0__pin_clk_0_; + input left_width_0_height_0_subtile_0__pin_reset_0_; + input pReset; + input prog_clk; + input top_width_0_height_0_subtile_0__pin_cin_0_; + input top_width_0_height_0_subtile_0__pin_reg_in_0_; + input top_width_0_height_0_subtile_0__pin_sc_in_0_; + output bottom_width_0_height_0_subtile_0__pin_cout_0_; + output bottom_width_0_height_0_subtile_0__pin_inpad_0_; + output bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + output bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + output bottom_width_0_height_0_subtile_1__pin_inpad_0_; + output bottom_width_0_height_0_subtile_2__pin_inpad_0_; + output bottom_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + output ccff_tail_0; + output [29:0]chanx_left_out; + output [29:0]chany_bottom_out; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_0; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_0; + output left_width_0_height_0_subtile_0__pin_inpad_0_; + output left_width_0_height_0_subtile_1__pin_inpad_0_; + output left_width_0_height_0_subtile_2__pin_inpad_0_; + output left_width_0_height_0_subtile_3__pin_inpad_0_; + output right_width_0_height_0_subtile_0__pin_O_10_; + output right_width_0_height_0_subtile_0__pin_O_11_; + output right_width_0_height_0_subtile_0__pin_O_12_; + output right_width_0_height_0_subtile_0__pin_O_13_; + output right_width_0_height_0_subtile_0__pin_O_14_; + output right_width_0_height_0_subtile_0__pin_O_15_; + output right_width_0_height_0_subtile_0__pin_O_8_; + output right_width_0_height_0_subtile_0__pin_O_9_; + output top_width_0_height_0_subtile_0__pin_O_0_; + output top_width_0_height_0_subtile_0__pin_O_1_; + output top_width_0_height_0_subtile_0__pin_O_2_; + output top_width_0_height_0_subtile_0__pin_O_3_; + output top_width_0_height_0_subtile_0__pin_O_4_; + output top_width_0_height_0_subtile_0__pin_O_5_; + output top_width_0_height_0_subtile_0__pin_O_6_; + output top_width_0_height_0_subtile_0__pin_O_7_; + + wire IO_ISOL_N; + wire Test_en; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head_0_0; + wire ccff_head_1; + wire ccff_tail; + wire ccff_tail_0; + wire ccff_tail_0_0; + wire ccff_tail_1; + wire ccff_tail_2; + wire [29:0]chanx_left_in; + wire [29:0]chanx_left_out; + wire [29:0]chanx_left_out_0; + wire [29:0]chanx_right_out; + wire [29:0]chany_bottom_in; + wire [29:0]chany_bottom_out; + wire [29:0]chany_bottom_out_0; + wire [29:0]chany_top_out; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_0; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN_0; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_0; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire left_width_0_height_0_subtile_0__pin_clk_0_; + wire left_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_width_0_height_0_subtile_0__pin_reset_0_; + wire left_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_width_0_height_0_subtile_3__pin_inpad_0_; + wire pReset; + wire prog_clk; + wire right_width_0_height_0_subtile_0__pin_O_10_; + wire right_width_0_height_0_subtile_0__pin_O_11_; + wire right_width_0_height_0_subtile_0__pin_O_12_; + wire right_width_0_height_0_subtile_0__pin_O_13_; + wire right_width_0_height_0_subtile_0__pin_O_14_; + wire right_width_0_height_0_subtile_0__pin_O_15_; + wire right_width_0_height_0_subtile_0__pin_O_8_; + wire right_width_0_height_0_subtile_0__pin_O_9_; + wire top_width_0_height_0_subtile_0__pin_O_0_; + wire top_width_0_height_0_subtile_0__pin_O_1_; + wire top_width_0_height_0_subtile_0__pin_O_2_; + wire top_width_0_height_0_subtile_0__pin_O_3_; + wire top_width_0_height_0_subtile_0__pin_O_4_; + wire top_width_0_height_0_subtile_0__pin_O_5_; + wire top_width_0_height_0_subtile_0__pin_O_6_; + wire top_width_0_height_0_subtile_0__pin_O_7_; + wire top_width_0_height_0_subtile_0__pin_cin_0_; + wire top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire top_width_0_height_0_subtile_0__pin_sc_in_0_; + + cbx_1__8_ cbx_8__8_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head_0(ccff_tail_2), + .chanx_left_in(chanx_left_in), + .chanx_right_in(chanx_left_out_0), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .pReset(pReset), + .prog_clk(prog_clk), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail_0), + .chanx_left_out(chanx_left_out), + .chanx_right_out(chanx_right_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT) + ); + cby_8__1_ cby_8__8_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head(ccff_head_1), + .ccff_head_0(ccff_head_0_0), + .chany_bottom_in(chany_bottom_in), + .chany_top_in(chany_bottom_out_0), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN_0), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail_1), + .ccff_tail_0(ccff_tail_0_0), + .chany_bottom_out(chany_bottom_out), + .chany_top_out(chany_top_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_0), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_0), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_inpad_0_(left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(left_width_0_height_0_subtile_3__pin_inpad_0_) + ); + grid_clb grid_clb_8__8_ + ( + .Test_en(Test_en), + .ccff_head(ccff_tail_0_0), + .left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_), + .left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_cin_0_(top_width_0_height_0_subtile_0__pin_cin_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(top_width_0_height_0_subtile_0__pin_sc_in_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(ccff_tail), + .right_width_0_height_0_subtile_0__pin_O_10_(right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(top_width_0_height_0_subtile_0__pin_O_7_) + ); + sb_8__8_ sb_8__8_ + ( + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(ccff_tail_1), + .chanx_left_in(chanx_right_out), + .chany_bottom_in(chany_top_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(top_width_0_height_0_subtile_0__pin_O_7_), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail_2), + .chanx_left_out(chanx_left_out_0), + .chany_bottom_out(chany_bottom_out_0) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v new file mode 100644 index 0000000..44b8c6e --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v @@ -0,0 +1,390 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module top_tile +( + IO_ISOL_N, + Test_en, + ccff_head_1, + ccff_head_2, + chanx_left_in, + chanx_right_in_0, + chany_bottom_in, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + left_width_0_height_0_subtile_0__pin_clk_0_, + left_width_0_height_0_subtile_0__pin_reset_0_, + pReset, + prog_clk, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + top_width_0_height_0_subtile_0__pin_cin_0_, + top_width_0_height_0_subtile_0__pin_reg_in_0_, + top_width_0_height_0_subtile_0__pin_sc_in_0_, + bottom_width_0_height_0_subtile_0__pin_cout_0_, + bottom_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_width_0_height_0_subtile_0__pin_reg_out_0_, + bottom_width_0_height_0_subtile_0__pin_sc_out_0_, + bottom_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail, + ccff_tail_0, + chanx_left_out, + chanx_right_out_0, + chany_bottom_out, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + right_width_0_height_0_subtile_0__pin_O_10_, + right_width_0_height_0_subtile_0__pin_O_11_, + right_width_0_height_0_subtile_0__pin_O_12_, + right_width_0_height_0_subtile_0__pin_O_13_, + right_width_0_height_0_subtile_0__pin_O_14_, + right_width_0_height_0_subtile_0__pin_O_15_, + right_width_0_height_0_subtile_0__pin_O_8_, + right_width_0_height_0_subtile_0__pin_O_9_, + top_width_0_height_0_subtile_0__pin_O_0_, + top_width_0_height_0_subtile_0__pin_O_1_, + top_width_0_height_0_subtile_0__pin_O_2_, + top_width_0_height_0_subtile_0__pin_O_3_, + top_width_0_height_0_subtile_0__pin_O_4_, + top_width_0_height_0_subtile_0__pin_O_5_, + top_width_0_height_0_subtile_0__pin_O_6_, + top_width_0_height_0_subtile_0__pin_O_7_ +); + + input IO_ISOL_N; + input Test_en; + input ccff_head_1; + input ccff_head_2; + input [29:0]chanx_left_in; + input [29:0]chanx_right_in_0; + input [29:0]chany_bottom_in; + input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + input left_width_0_height_0_subtile_0__pin_clk_0_; + input left_width_0_height_0_subtile_0__pin_reset_0_; + input pReset; + input prog_clk; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + input top_width_0_height_0_subtile_0__pin_cin_0_; + input top_width_0_height_0_subtile_0__pin_reg_in_0_; + input top_width_0_height_0_subtile_0__pin_sc_in_0_; + output bottom_width_0_height_0_subtile_0__pin_cout_0_; + output bottom_width_0_height_0_subtile_0__pin_inpad_0_; + output bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + output bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + output bottom_width_0_height_0_subtile_1__pin_inpad_0_; + output bottom_width_0_height_0_subtile_2__pin_inpad_0_; + output bottom_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + output ccff_tail_0; + output [29:0]chanx_left_out; + output [29:0]chanx_right_out_0; + output [29:0]chany_bottom_out; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output right_width_0_height_0_subtile_0__pin_O_10_; + output right_width_0_height_0_subtile_0__pin_O_11_; + output right_width_0_height_0_subtile_0__pin_O_12_; + output right_width_0_height_0_subtile_0__pin_O_13_; + output right_width_0_height_0_subtile_0__pin_O_14_; + output right_width_0_height_0_subtile_0__pin_O_15_; + output right_width_0_height_0_subtile_0__pin_O_8_; + output right_width_0_height_0_subtile_0__pin_O_9_; + output top_width_0_height_0_subtile_0__pin_O_0_; + output top_width_0_height_0_subtile_0__pin_O_1_; + output top_width_0_height_0_subtile_0__pin_O_2_; + output top_width_0_height_0_subtile_0__pin_O_3_; + output top_width_0_height_0_subtile_0__pin_O_4_; + output top_width_0_height_0_subtile_0__pin_O_5_; + output top_width_0_height_0_subtile_0__pin_O_6_; + output top_width_0_height_0_subtile_0__pin_O_7_; + + wire IO_ISOL_N; + wire Test_en; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head_1; + wire ccff_head_2; + wire ccff_tail; + wire ccff_tail_0; + wire ccff_tail_1; + wire ccff_tail_2; + wire [29:0]chanx_left_in; + wire [29:0]chanx_left_out; + wire [29:0]chanx_left_out_0; + wire [29:0]chanx_right_in_0; + wire [29:0]chanx_right_out; + wire [29:0]chanx_right_out_0; + wire [29:0]chany_bottom_in; + wire [29:0]chany_bottom_out; + wire [29:0]chany_bottom_out_0; + wire [29:0]chany_top_out; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire left_width_0_height_0_subtile_0__pin_clk_0_; + wire left_width_0_height_0_subtile_0__pin_reset_0_; + wire pReset; + wire prog_clk; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire right_width_0_height_0_subtile_0__pin_O_10_; + wire right_width_0_height_0_subtile_0__pin_O_11_; + wire right_width_0_height_0_subtile_0__pin_O_12_; + wire right_width_0_height_0_subtile_0__pin_O_13_; + wire right_width_0_height_0_subtile_0__pin_O_14_; + wire right_width_0_height_0_subtile_0__pin_O_15_; + wire right_width_0_height_0_subtile_0__pin_O_8_; + wire right_width_0_height_0_subtile_0__pin_O_9_; + wire top_width_0_height_0_subtile_0__pin_O_0_; + wire top_width_0_height_0_subtile_0__pin_O_1_; + wire top_width_0_height_0_subtile_0__pin_O_2_; + wire top_width_0_height_0_subtile_0__pin_O_3_; + wire top_width_0_height_0_subtile_0__pin_O_4_; + wire top_width_0_height_0_subtile_0__pin_O_5_; + wire top_width_0_height_0_subtile_0__pin_O_6_; + wire top_width_0_height_0_subtile_0__pin_O_7_; + wire top_width_0_height_0_subtile_0__pin_cin_0_; + wire top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire top_width_0_height_0_subtile_0__pin_sc_in_0_; + + cbx_1__8_ cbx_1__8_ + ( + .IO_ISOL_N(IO_ISOL_N), + .ccff_head_0(ccff_tail_2), + .chanx_left_in(chanx_left_in), + .chanx_right_in(chanx_left_out_0), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .pReset(pReset), + .prog_clk(prog_clk), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail_0), + .chanx_left_out(chanx_left_out), + .chanx_right_out(chanx_right_out), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT) + ); + cby_1__1_ cby_1__8_ + ( + .ccff_head(ccff_head_1), + .chany_bottom_in(chany_bottom_in), + .chany_top_in(chany_bottom_out_0), + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_tail(ccff_tail_1), + .chany_bottom_out(chany_bottom_out), + .chany_top_out(chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_) + ); + grid_clb grid_clb_1__8_ + ( + .Test_en(Test_en), + .ccff_head(ccff_tail_1), + .left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_), + .left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_cin_0_(top_width_0_height_0_subtile_0__pin_cin_0_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(top_width_0_height_0_subtile_0__pin_sc_in_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(bottom_width_0_height_0_subtile_0__pin_cout_0_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .ccff_tail(ccff_tail), + .right_width_0_height_0_subtile_0__pin_O_10_(right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(right_width_0_height_0_subtile_0__pin_O_15_), + .right_width_0_height_0_subtile_0__pin_O_8_(right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(right_width_0_height_0_subtile_0__pin_O_9_), + .top_width_0_height_0_subtile_0__pin_O_0_(top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(top_width_0_height_0_subtile_0__pin_O_7_) + ); + sb_1__8_ sb_1__8_ + ( + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(right_width_0_height_0_subtile_0__pin_O_9_), + .ccff_head(ccff_head_2), + .chanx_left_in(chanx_right_out), + .chanx_right_in(chanx_right_in_0), + .chany_bottom_in(chany_top_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(top_width_0_height_0_subtile_0__pin_O_7_), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .pReset(pReset), + .prog_clk(prog_clk), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail_2), + .chanx_left_out(chanx_left_out_0), + .chanx_right_out(chanx_right_out_0), + .chany_bottom_out(chany_bottom_out_0) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/CustomModules/custom_module.txt b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/CustomModules/custom_module.txt new file mode 100644 index 0000000..3834131 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/CustomModules/custom_module.txt @@ -0,0 +1 @@ +# Dummy file to list all custom modules used in this project \ No newline at end of file diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/fpga_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/fpga_top.v new file mode 100644 index 0000000..54050e1 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/fpga_top.v @@ -0,0 +1,17437 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module fpga_top +( + clk, + Reset, + IO_ISOL_N, + pReset, + prog_clk, + Test_en, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + ccff_head, + ccff_tail +); + + input clk; + input Reset; + input IO_ISOL_N; + input pReset; + input prog_clk; + input Test_en; + input [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + output [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + input ccff_head; + output ccff_tail; + + wire clk; + wire Reset; + wire IO_ISOL_N; + wire pReset; + wire prog_clk; + wire Test_en; + wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire ccff_head; + wire ccff_tail; + wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__0_ccff_tail; + wire [0:29]cbx_1__0__0_chanx_left_out; + wire [0:29]cbx_1__0__0_chanx_right_out; + wire cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__1_ccff_tail; + wire [0:29]cbx_1__0__1_chanx_left_out; + wire [0:29]cbx_1__0__1_chanx_right_out; + wire cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__2_ccff_tail; + wire [0:29]cbx_1__0__2_chanx_left_out; + wire [0:29]cbx_1__0__2_chanx_right_out; + wire cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__3_ccff_tail; + wire [0:29]cbx_1__0__3_chanx_left_out; + wire [0:29]cbx_1__0__3_chanx_right_out; + wire cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__4_ccff_tail; + wire [0:29]cbx_1__0__4_chanx_left_out; + wire [0:29]cbx_1__0__4_chanx_right_out; + wire cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__5_ccff_tail; + wire [0:29]cbx_1__0__5_chanx_left_out; + wire [0:29]cbx_1__0__5_chanx_right_out; + wire cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__6_ccff_tail; + wire [0:29]cbx_1__0__6_chanx_left_out; + wire [0:29]cbx_1__0__6_chanx_right_out; + wire cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__7_ccff_tail; + wire [0:29]cbx_1__0__7_chanx_left_out; + wire [0:29]cbx_1__0__7_chanx_right_out; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__0_ccff_tail; + wire [0:29]cbx_1__1__0_chanx_left_out; + wire [0:29]cbx_1__1__0_chanx_right_out; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__10_ccff_tail; + wire [0:29]cbx_1__1__10_chanx_left_out; + wire [0:29]cbx_1__1__10_chanx_right_out; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__11_ccff_tail; + wire [0:29]cbx_1__1__11_chanx_left_out; + wire [0:29]cbx_1__1__11_chanx_right_out; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__12_ccff_tail; + wire [0:29]cbx_1__1__12_chanx_left_out; + wire [0:29]cbx_1__1__12_chanx_right_out; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__13_ccff_tail; + wire [0:29]cbx_1__1__13_chanx_left_out; + wire [0:29]cbx_1__1__13_chanx_right_out; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__14_ccff_tail; + wire [0:29]cbx_1__1__14_chanx_left_out; + wire [0:29]cbx_1__1__14_chanx_right_out; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__15_ccff_tail; + wire [0:29]cbx_1__1__15_chanx_left_out; + wire [0:29]cbx_1__1__15_chanx_right_out; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__16_ccff_tail; + wire [0:29]cbx_1__1__16_chanx_left_out; + wire [0:29]cbx_1__1__16_chanx_right_out; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__17_ccff_tail; + wire [0:29]cbx_1__1__17_chanx_left_out; + wire [0:29]cbx_1__1__17_chanx_right_out; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__18_ccff_tail; + wire [0:29]cbx_1__1__18_chanx_left_out; + wire [0:29]cbx_1__1__18_chanx_right_out; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__19_ccff_tail; + wire [0:29]cbx_1__1__19_chanx_left_out; + wire [0:29]cbx_1__1__19_chanx_right_out; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__1_ccff_tail; + wire [0:29]cbx_1__1__1_chanx_left_out; + wire [0:29]cbx_1__1__1_chanx_right_out; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__20_ccff_tail; + wire [0:29]cbx_1__1__20_chanx_left_out; + wire [0:29]cbx_1__1__20_chanx_right_out; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__21_ccff_tail; + wire [0:29]cbx_1__1__21_chanx_left_out; + wire [0:29]cbx_1__1__21_chanx_right_out; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__22_ccff_tail; + wire [0:29]cbx_1__1__22_chanx_left_out; + wire [0:29]cbx_1__1__22_chanx_right_out; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__23_ccff_tail; + wire [0:29]cbx_1__1__23_chanx_left_out; + wire [0:29]cbx_1__1__23_chanx_right_out; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__24_ccff_tail; + wire [0:29]cbx_1__1__24_chanx_left_out; + wire [0:29]cbx_1__1__24_chanx_right_out; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__25_ccff_tail; + wire [0:29]cbx_1__1__25_chanx_left_out; + wire [0:29]cbx_1__1__25_chanx_right_out; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__26_ccff_tail; + wire [0:29]cbx_1__1__26_chanx_left_out; + wire [0:29]cbx_1__1__26_chanx_right_out; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__27_ccff_tail; + wire [0:29]cbx_1__1__27_chanx_left_out; + wire [0:29]cbx_1__1__27_chanx_right_out; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__28_ccff_tail; + wire [0:29]cbx_1__1__28_chanx_left_out; + wire [0:29]cbx_1__1__28_chanx_right_out; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__29_ccff_tail; + wire [0:29]cbx_1__1__29_chanx_left_out; + wire [0:29]cbx_1__1__29_chanx_right_out; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__2_ccff_tail; + wire [0:29]cbx_1__1__2_chanx_left_out; + wire [0:29]cbx_1__1__2_chanx_right_out; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__30_ccff_tail; + wire [0:29]cbx_1__1__30_chanx_left_out; + wire [0:29]cbx_1__1__30_chanx_right_out; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__31_ccff_tail; + wire [0:29]cbx_1__1__31_chanx_left_out; + wire [0:29]cbx_1__1__31_chanx_right_out; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__32_ccff_tail; + wire [0:29]cbx_1__1__32_chanx_left_out; + wire [0:29]cbx_1__1__32_chanx_right_out; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__33_ccff_tail; + wire [0:29]cbx_1__1__33_chanx_left_out; + wire [0:29]cbx_1__1__33_chanx_right_out; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__34_ccff_tail; + wire [0:29]cbx_1__1__34_chanx_left_out; + wire [0:29]cbx_1__1__34_chanx_right_out; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__35_ccff_tail; + wire [0:29]cbx_1__1__35_chanx_left_out; + wire [0:29]cbx_1__1__35_chanx_right_out; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__36_ccff_tail; + wire [0:29]cbx_1__1__36_chanx_left_out; + wire [0:29]cbx_1__1__36_chanx_right_out; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__37_ccff_tail; + wire [0:29]cbx_1__1__37_chanx_left_out; + wire [0:29]cbx_1__1__37_chanx_right_out; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__38_ccff_tail; + wire [0:29]cbx_1__1__38_chanx_left_out; + wire [0:29]cbx_1__1__38_chanx_right_out; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__39_ccff_tail; + wire [0:29]cbx_1__1__39_chanx_left_out; + wire [0:29]cbx_1__1__39_chanx_right_out; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__3_ccff_tail; + wire [0:29]cbx_1__1__3_chanx_left_out; + wire [0:29]cbx_1__1__3_chanx_right_out; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__40_ccff_tail; + wire [0:29]cbx_1__1__40_chanx_left_out; + wire [0:29]cbx_1__1__40_chanx_right_out; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__41_ccff_tail; + wire [0:29]cbx_1__1__41_chanx_left_out; + wire [0:29]cbx_1__1__41_chanx_right_out; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__42_ccff_tail; + wire [0:29]cbx_1__1__42_chanx_left_out; + wire [0:29]cbx_1__1__42_chanx_right_out; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__43_ccff_tail; + wire [0:29]cbx_1__1__43_chanx_left_out; + wire [0:29]cbx_1__1__43_chanx_right_out; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__44_ccff_tail; + wire [0:29]cbx_1__1__44_chanx_left_out; + wire [0:29]cbx_1__1__44_chanx_right_out; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__45_ccff_tail; + wire [0:29]cbx_1__1__45_chanx_left_out; + wire [0:29]cbx_1__1__45_chanx_right_out; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__46_ccff_tail; + wire [0:29]cbx_1__1__46_chanx_left_out; + wire [0:29]cbx_1__1__46_chanx_right_out; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__47_ccff_tail; + wire [0:29]cbx_1__1__47_chanx_left_out; + wire [0:29]cbx_1__1__47_chanx_right_out; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__48_ccff_tail; + wire [0:29]cbx_1__1__48_chanx_left_out; + wire [0:29]cbx_1__1__48_chanx_right_out; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__49_ccff_tail; + wire [0:29]cbx_1__1__49_chanx_left_out; + wire [0:29]cbx_1__1__49_chanx_right_out; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__4_ccff_tail; + wire [0:29]cbx_1__1__4_chanx_left_out; + wire [0:29]cbx_1__1__4_chanx_right_out; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__50_ccff_tail; + wire [0:29]cbx_1__1__50_chanx_left_out; + wire [0:29]cbx_1__1__50_chanx_right_out; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__51_ccff_tail; + wire [0:29]cbx_1__1__51_chanx_left_out; + wire [0:29]cbx_1__1__51_chanx_right_out; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__52_ccff_tail; + wire [0:29]cbx_1__1__52_chanx_left_out; + wire [0:29]cbx_1__1__52_chanx_right_out; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__53_ccff_tail; + wire [0:29]cbx_1__1__53_chanx_left_out; + wire [0:29]cbx_1__1__53_chanx_right_out; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__54_ccff_tail; + wire [0:29]cbx_1__1__54_chanx_left_out; + wire [0:29]cbx_1__1__54_chanx_right_out; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__55_ccff_tail; + wire [0:29]cbx_1__1__55_chanx_left_out; + wire [0:29]cbx_1__1__55_chanx_right_out; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__5_ccff_tail; + wire [0:29]cbx_1__1__5_chanx_left_out; + wire [0:29]cbx_1__1__5_chanx_right_out; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__6_ccff_tail; + wire [0:29]cbx_1__1__6_chanx_left_out; + wire [0:29]cbx_1__1__6_chanx_right_out; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__7_ccff_tail; + wire [0:29]cbx_1__1__7_chanx_left_out; + wire [0:29]cbx_1__1__7_chanx_right_out; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__8_ccff_tail; + wire [0:29]cbx_1__1__8_chanx_left_out; + wire [0:29]cbx_1__1__8_chanx_right_out; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__9_ccff_tail; + wire [0:29]cbx_1__1__9_chanx_left_out; + wire [0:29]cbx_1__1__9_chanx_right_out; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__0_ccff_tail; + wire [0:29]cbx_1__8__0_chanx_left_out; + wire [0:29]cbx_1__8__0_chanx_right_out; + wire cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__1_ccff_tail; + wire [0:29]cbx_1__8__1_chanx_left_out; + wire [0:29]cbx_1__8__1_chanx_right_out; + wire cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__2_ccff_tail; + wire [0:29]cbx_1__8__2_chanx_left_out; + wire [0:29]cbx_1__8__2_chanx_right_out; + wire cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__3_ccff_tail; + wire [0:29]cbx_1__8__3_chanx_left_out; + wire [0:29]cbx_1__8__3_chanx_right_out; + wire cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__4_ccff_tail; + wire [0:29]cbx_1__8__4_chanx_left_out; + wire [0:29]cbx_1__8__4_chanx_right_out; + wire cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__5_ccff_tail; + wire [0:29]cbx_1__8__5_chanx_left_out; + wire [0:29]cbx_1__8__5_chanx_right_out; + wire cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__6_ccff_tail; + wire [0:29]cbx_1__8__6_chanx_left_out; + wire [0:29]cbx_1__8__6_chanx_right_out; + wire cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__7_ccff_tail; + wire [0:29]cbx_1__8__7_chanx_left_out; + wire [0:29]cbx_1__8__7_chanx_right_out; + wire cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__0_ccff_tail; + wire [0:29]cby_0__1__0_chany_bottom_out; + wire [0:29]cby_0__1__0_chany_top_out; + wire cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__1_ccff_tail; + wire [0:29]cby_0__1__1_chany_bottom_out; + wire [0:29]cby_0__1__1_chany_top_out; + wire cby_0__1__1_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__1_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__1_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__1_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__2_ccff_tail; + wire [0:29]cby_0__1__2_chany_bottom_out; + wire [0:29]cby_0__1__2_chany_top_out; + wire cby_0__1__2_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__2_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__2_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__2_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__3_ccff_tail; + wire [0:29]cby_0__1__3_chany_bottom_out; + wire [0:29]cby_0__1__3_chany_top_out; + wire cby_0__1__3_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__3_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__3_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__3_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__4_ccff_tail; + wire [0:29]cby_0__1__4_chany_bottom_out; + wire [0:29]cby_0__1__4_chany_top_out; + wire cby_0__1__4_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__4_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__4_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__4_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__5_ccff_tail; + wire [0:29]cby_0__1__5_chany_bottom_out; + wire [0:29]cby_0__1__5_chany_top_out; + wire cby_0__1__5_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__5_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__5_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__5_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__6_ccff_tail; + wire [0:29]cby_0__1__6_chany_bottom_out; + wire [0:29]cby_0__1__6_chany_top_out; + wire cby_0__1__6_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__6_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__6_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__6_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__7_ccff_tail; + wire [0:29]cby_0__1__7_chany_bottom_out; + wire [0:29]cby_0__1__7_chany_top_out; + wire cby_0__1__7_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__7_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__7_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__7_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_1__1__0_ccff_tail; + wire [0:29]cby_1__1__0_chany_bottom_out; + wire [0:29]cby_1__1__0_chany_top_out; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__10_ccff_tail; + wire [0:29]cby_1__1__10_chany_bottom_out; + wire [0:29]cby_1__1__10_chany_top_out; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__11_ccff_tail; + wire [0:29]cby_1__1__11_chany_bottom_out; + wire [0:29]cby_1__1__11_chany_top_out; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__12_ccff_tail; + wire [0:29]cby_1__1__12_chany_bottom_out; + wire [0:29]cby_1__1__12_chany_top_out; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__13_ccff_tail; + wire [0:29]cby_1__1__13_chany_bottom_out; + wire [0:29]cby_1__1__13_chany_top_out; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__14_ccff_tail; + wire [0:29]cby_1__1__14_chany_bottom_out; + wire [0:29]cby_1__1__14_chany_top_out; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__15_ccff_tail; + wire [0:29]cby_1__1__15_chany_bottom_out; + wire [0:29]cby_1__1__15_chany_top_out; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__16_ccff_tail; + wire [0:29]cby_1__1__16_chany_bottom_out; + wire [0:29]cby_1__1__16_chany_top_out; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__17_ccff_tail; + wire [0:29]cby_1__1__17_chany_bottom_out; + wire [0:29]cby_1__1__17_chany_top_out; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__18_ccff_tail; + wire [0:29]cby_1__1__18_chany_bottom_out; + wire [0:29]cby_1__1__18_chany_top_out; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__19_ccff_tail; + wire [0:29]cby_1__1__19_chany_bottom_out; + wire [0:29]cby_1__1__19_chany_top_out; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__1_ccff_tail; + wire [0:29]cby_1__1__1_chany_bottom_out; + wire [0:29]cby_1__1__1_chany_top_out; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__20_ccff_tail; + wire [0:29]cby_1__1__20_chany_bottom_out; + wire [0:29]cby_1__1__20_chany_top_out; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__21_ccff_tail; + wire [0:29]cby_1__1__21_chany_bottom_out; + wire [0:29]cby_1__1__21_chany_top_out; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__22_ccff_tail; + wire [0:29]cby_1__1__22_chany_bottom_out; + wire [0:29]cby_1__1__22_chany_top_out; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__23_ccff_tail; + wire [0:29]cby_1__1__23_chany_bottom_out; + wire [0:29]cby_1__1__23_chany_top_out; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__24_ccff_tail; + wire [0:29]cby_1__1__24_chany_bottom_out; + wire [0:29]cby_1__1__24_chany_top_out; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__25_ccff_tail; + wire [0:29]cby_1__1__25_chany_bottom_out; + wire [0:29]cby_1__1__25_chany_top_out; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__26_ccff_tail; + wire [0:29]cby_1__1__26_chany_bottom_out; + wire [0:29]cby_1__1__26_chany_top_out; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__27_ccff_tail; + wire [0:29]cby_1__1__27_chany_bottom_out; + wire [0:29]cby_1__1__27_chany_top_out; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__28_ccff_tail; + wire [0:29]cby_1__1__28_chany_bottom_out; + wire [0:29]cby_1__1__28_chany_top_out; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__29_ccff_tail; + wire [0:29]cby_1__1__29_chany_bottom_out; + wire [0:29]cby_1__1__29_chany_top_out; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__2_ccff_tail; + wire [0:29]cby_1__1__2_chany_bottom_out; + wire [0:29]cby_1__1__2_chany_top_out; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__30_ccff_tail; + wire [0:29]cby_1__1__30_chany_bottom_out; + wire [0:29]cby_1__1__30_chany_top_out; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__31_ccff_tail; + wire [0:29]cby_1__1__31_chany_bottom_out; + wire [0:29]cby_1__1__31_chany_top_out; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__32_ccff_tail; + wire [0:29]cby_1__1__32_chany_bottom_out; + wire [0:29]cby_1__1__32_chany_top_out; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__33_ccff_tail; + wire [0:29]cby_1__1__33_chany_bottom_out; + wire [0:29]cby_1__1__33_chany_top_out; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__34_ccff_tail; + wire [0:29]cby_1__1__34_chany_bottom_out; + wire [0:29]cby_1__1__34_chany_top_out; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__35_ccff_tail; + wire [0:29]cby_1__1__35_chany_bottom_out; + wire [0:29]cby_1__1__35_chany_top_out; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__36_ccff_tail; + wire [0:29]cby_1__1__36_chany_bottom_out; + wire [0:29]cby_1__1__36_chany_top_out; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__37_ccff_tail; + wire [0:29]cby_1__1__37_chany_bottom_out; + wire [0:29]cby_1__1__37_chany_top_out; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__38_ccff_tail; + wire [0:29]cby_1__1__38_chany_bottom_out; + wire [0:29]cby_1__1__38_chany_top_out; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__39_ccff_tail; + wire [0:29]cby_1__1__39_chany_bottom_out; + wire [0:29]cby_1__1__39_chany_top_out; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__3_ccff_tail; + wire [0:29]cby_1__1__3_chany_bottom_out; + wire [0:29]cby_1__1__3_chany_top_out; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__40_ccff_tail; + wire [0:29]cby_1__1__40_chany_bottom_out; + wire [0:29]cby_1__1__40_chany_top_out; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__41_ccff_tail; + wire [0:29]cby_1__1__41_chany_bottom_out; + wire [0:29]cby_1__1__41_chany_top_out; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__42_ccff_tail; + wire [0:29]cby_1__1__42_chany_bottom_out; + wire [0:29]cby_1__1__42_chany_top_out; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__43_ccff_tail; + wire [0:29]cby_1__1__43_chany_bottom_out; + wire [0:29]cby_1__1__43_chany_top_out; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__44_ccff_tail; + wire [0:29]cby_1__1__44_chany_bottom_out; + wire [0:29]cby_1__1__44_chany_top_out; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__45_ccff_tail; + wire [0:29]cby_1__1__45_chany_bottom_out; + wire [0:29]cby_1__1__45_chany_top_out; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__46_ccff_tail; + wire [0:29]cby_1__1__46_chany_bottom_out; + wire [0:29]cby_1__1__46_chany_top_out; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__47_ccff_tail; + wire [0:29]cby_1__1__47_chany_bottom_out; + wire [0:29]cby_1__1__47_chany_top_out; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__48_ccff_tail; + wire [0:29]cby_1__1__48_chany_bottom_out; + wire [0:29]cby_1__1__48_chany_top_out; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__49_ccff_tail; + wire [0:29]cby_1__1__49_chany_bottom_out; + wire [0:29]cby_1__1__49_chany_top_out; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__4_ccff_tail; + wire [0:29]cby_1__1__4_chany_bottom_out; + wire [0:29]cby_1__1__4_chany_top_out; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__50_ccff_tail; + wire [0:29]cby_1__1__50_chany_bottom_out; + wire [0:29]cby_1__1__50_chany_top_out; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__51_ccff_tail; + wire [0:29]cby_1__1__51_chany_bottom_out; + wire [0:29]cby_1__1__51_chany_top_out; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__52_ccff_tail; + wire [0:29]cby_1__1__52_chany_bottom_out; + wire [0:29]cby_1__1__52_chany_top_out; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__53_ccff_tail; + wire [0:29]cby_1__1__53_chany_bottom_out; + wire [0:29]cby_1__1__53_chany_top_out; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__54_ccff_tail; + wire [0:29]cby_1__1__54_chany_bottom_out; + wire [0:29]cby_1__1__54_chany_top_out; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__55_ccff_tail; + wire [0:29]cby_1__1__55_chany_bottom_out; + wire [0:29]cby_1__1__55_chany_top_out; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__5_ccff_tail; + wire [0:29]cby_1__1__5_chany_bottom_out; + wire [0:29]cby_1__1__5_chany_top_out; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__6_ccff_tail; + wire [0:29]cby_1__1__6_chany_bottom_out; + wire [0:29]cby_1__1__6_chany_top_out; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__7_ccff_tail; + wire [0:29]cby_1__1__7_chany_bottom_out; + wire [0:29]cby_1__1__7_chany_top_out; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__8_ccff_tail; + wire [0:29]cby_1__1__8_chany_bottom_out; + wire [0:29]cby_1__1__8_chany_top_out; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__9_ccff_tail; + wire [0:29]cby_1__1__9_chany_bottom_out; + wire [0:29]cby_1__1__9_chany_top_out; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__0_ccff_tail; + wire [0:29]cby_8__1__0_chany_bottom_out; + wire [0:29]cby_8__1__0_chany_top_out; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__1_ccff_tail; + wire [0:29]cby_8__1__1_chany_bottom_out; + wire [0:29]cby_8__1__1_chany_top_out; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__1_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__1_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__1_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__2_ccff_tail; + wire [0:29]cby_8__1__2_chany_bottom_out; + wire [0:29]cby_8__1__2_chany_top_out; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__2_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__2_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__2_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__3_ccff_tail; + wire [0:29]cby_8__1__3_chany_bottom_out; + wire [0:29]cby_8__1__3_chany_top_out; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__3_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__3_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__3_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__4_ccff_tail; + wire [0:29]cby_8__1__4_chany_bottom_out; + wire [0:29]cby_8__1__4_chany_top_out; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__4_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__4_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__4_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__4_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__5_ccff_tail; + wire [0:29]cby_8__1__5_chany_bottom_out; + wire [0:29]cby_8__1__5_chany_top_out; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__5_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__5_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__5_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__5_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__6_ccff_tail; + wire [0:29]cby_8__1__6_chany_bottom_out; + wire [0:29]cby_8__1__6_chany_top_out; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__6_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__6_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__6_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__6_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__7_ccff_tail; + wire [0:29]cby_8__1__7_chany_bottom_out; + wire [0:29]cby_8__1__7_chany_top_out; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__7_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__7_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__7_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__7_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire direct_interc_0_out; + wire direct_interc_100_out; + wire direct_interc_101_out; + wire direct_interc_102_out; + wire direct_interc_103_out; + wire direct_interc_104_out; + wire direct_interc_105_out; + wire direct_interc_106_out; + wire direct_interc_107_out; + wire direct_interc_108_out; + wire direct_interc_109_out; + wire direct_interc_10_out; + wire direct_interc_110_out; + wire direct_interc_111_out; + wire direct_interc_112_out; + wire direct_interc_113_out; + wire direct_interc_114_out; + wire direct_interc_115_out; + wire direct_interc_116_out; + wire direct_interc_117_out; + wire direct_interc_118_out; + wire direct_interc_119_out; + wire direct_interc_11_out; + wire direct_interc_120_out; + wire direct_interc_121_out; + wire direct_interc_122_out; + wire direct_interc_123_out; + wire direct_interc_124_out; + wire direct_interc_125_out; + wire direct_interc_126_out; + wire direct_interc_127_out; + wire direct_interc_128_out; + wire direct_interc_129_out; + wire direct_interc_12_out; + wire direct_interc_130_out; + wire direct_interc_131_out; + wire direct_interc_132_out; + wire direct_interc_133_out; + wire direct_interc_134_out; + wire direct_interc_135_out; + wire direct_interc_136_out; + wire direct_interc_137_out; + wire direct_interc_138_out; + wire direct_interc_139_out; + wire direct_interc_13_out; + wire direct_interc_140_out; + wire direct_interc_141_out; + wire direct_interc_142_out; + wire direct_interc_143_out; + wire direct_interc_144_out; + wire direct_interc_145_out; + wire direct_interc_146_out; + wire direct_interc_147_out; + wire direct_interc_148_out; + wire direct_interc_149_out; + wire direct_interc_14_out; + wire direct_interc_150_out; + wire direct_interc_151_out; + wire direct_interc_152_out; + wire direct_interc_153_out; + wire direct_interc_154_out; + wire direct_interc_155_out; + wire direct_interc_156_out; + wire direct_interc_157_out; + wire direct_interc_158_out; + wire direct_interc_159_out; + wire direct_interc_15_out; + wire direct_interc_160_out; + wire direct_interc_161_out; + wire direct_interc_162_out; + wire direct_interc_163_out; + wire direct_interc_164_out; + wire direct_interc_165_out; + wire direct_interc_166_out; + wire direct_interc_167_out; + wire direct_interc_168_out; + wire direct_interc_169_out; + wire direct_interc_16_out; + wire direct_interc_170_out; + wire direct_interc_171_out; + wire direct_interc_172_out; + wire direct_interc_173_out; + wire direct_interc_174_out; + wire direct_interc_17_out; + wire direct_interc_18_out; + wire direct_interc_19_out; + wire direct_interc_1_out; + wire direct_interc_20_out; + wire direct_interc_21_out; + wire direct_interc_22_out; + wire direct_interc_23_out; + wire direct_interc_24_out; + wire direct_interc_25_out; + wire direct_interc_26_out; + wire direct_interc_27_out; + wire direct_interc_28_out; + wire direct_interc_29_out; + wire direct_interc_2_out; + wire direct_interc_30_out; + wire direct_interc_31_out; + wire direct_interc_32_out; + wire direct_interc_33_out; + wire direct_interc_34_out; + wire direct_interc_35_out; + wire direct_interc_36_out; + wire direct_interc_37_out; + wire direct_interc_38_out; + wire direct_interc_39_out; + wire direct_interc_3_out; + wire direct_interc_40_out; + wire direct_interc_41_out; + wire direct_interc_42_out; + wire direct_interc_43_out; + wire direct_interc_44_out; + wire direct_interc_45_out; + wire direct_interc_46_out; + wire direct_interc_47_out; + wire direct_interc_48_out; + wire direct_interc_49_out; + wire direct_interc_4_out; + wire direct_interc_50_out; + wire direct_interc_51_out; + wire direct_interc_52_out; + wire direct_interc_53_out; + wire direct_interc_54_out; + wire direct_interc_55_out; + wire direct_interc_56_out; + wire direct_interc_57_out; + wire direct_interc_58_out; + wire direct_interc_59_out; + wire direct_interc_5_out; + wire direct_interc_60_out; + wire direct_interc_61_out; + wire direct_interc_62_out; + wire direct_interc_63_out; + wire direct_interc_64_out; + wire direct_interc_65_out; + wire direct_interc_66_out; + wire direct_interc_67_out; + wire direct_interc_68_out; + wire direct_interc_69_out; + wire direct_interc_6_out; + wire direct_interc_70_out; + wire direct_interc_71_out; + wire direct_interc_72_out; + wire direct_interc_73_out; + wire direct_interc_74_out; + wire direct_interc_75_out; + wire direct_interc_76_out; + wire direct_interc_77_out; + wire direct_interc_78_out; + wire direct_interc_79_out; + wire direct_interc_7_out; + wire direct_interc_80_out; + wire direct_interc_81_out; + wire direct_interc_82_out; + wire direct_interc_83_out; + wire direct_interc_84_out; + wire direct_interc_85_out; + wire direct_interc_86_out; + wire direct_interc_87_out; + wire direct_interc_88_out; + wire direct_interc_89_out; + wire direct_interc_8_out; + wire direct_interc_90_out; + wire direct_interc_91_out; + wire direct_interc_92_out; + wire direct_interc_93_out; + wire direct_interc_94_out; + wire direct_interc_95_out; + wire direct_interc_96_out; + wire direct_interc_97_out; + wire direct_interc_98_out; + wire direct_interc_99_out; + wire direct_interc_9_out; + wire grid_clb_0_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_0_ccff_tail; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_10_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_10_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_10_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_10_ccff_tail; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_11_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_11_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_11_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_11_ccff_tail; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_12_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_12_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_12_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_12_ccff_tail; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_13_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_13_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_13_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_13_ccff_tail; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_14_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_14_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_14_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_14_ccff_tail; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_15_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_15_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_15_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_15_ccff_tail; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_16_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_16_ccff_tail; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_17_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_17_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_17_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_17_ccff_tail; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_18_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_18_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_18_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_18_ccff_tail; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_19_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_19_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_19_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_19_ccff_tail; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_sc_in_0_; + wire grid_clb_1_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_1_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_1_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_1_ccff_tail; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_20_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_20_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_20_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_20_ccff_tail; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_21_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_21_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_21_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_21_ccff_tail; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_22_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_22_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_22_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_22_ccff_tail; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_23_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_23_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_23_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_23_ccff_tail; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_24_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_24_ccff_tail; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_25_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_25_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_25_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_25_ccff_tail; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_26_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_26_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_26_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_26_ccff_tail; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_27_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_27_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_27_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_27_ccff_tail; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_28_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_28_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_28_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_28_ccff_tail; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_29_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_29_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_29_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_29_ccff_tail; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_2_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_2_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_2_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_2_ccff_tail; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_30_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_30_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_30_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_30_ccff_tail; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_31_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_31_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_31_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_31_ccff_tail; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_32_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_32_ccff_tail; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_33_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_33_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_33_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_33_ccff_tail; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_34_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_34_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_34_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_34_ccff_tail; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_35_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_35_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_35_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_35_ccff_tail; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_36_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_36_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_36_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_36_ccff_tail; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_37_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_37_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_37_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_37_ccff_tail; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_38_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_38_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_38_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_38_ccff_tail; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_39_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_39_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_39_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_39_ccff_tail; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_3_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_3_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_3_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_3_ccff_tail; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_40_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_40_ccff_tail; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_41_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_41_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_41_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_41_ccff_tail; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_42_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_42_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_42_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_42_ccff_tail; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_43_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_43_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_43_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_43_ccff_tail; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_44_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_44_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_44_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_44_ccff_tail; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_45_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_45_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_45_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_45_ccff_tail; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_46_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_46_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_46_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_46_ccff_tail; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_47_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_47_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_47_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_47_ccff_tail; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_48_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_48_ccff_tail; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_49_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_49_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_49_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_49_ccff_tail; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_4_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_4_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_4_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_4_ccff_tail; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_50_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_50_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_50_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_50_ccff_tail; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_51_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_51_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_51_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_51_ccff_tail; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_52_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_52_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_52_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_52_ccff_tail; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_53_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_53_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_53_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_53_ccff_tail; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_54_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_54_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_54_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_54_ccff_tail; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_55_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_55_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_55_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_55_ccff_tail; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_56_ccff_tail; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_57_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_57_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_57_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_57_ccff_tail; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_58_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_58_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_58_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_58_ccff_tail; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_59_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_59_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_59_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_59_ccff_tail; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_5_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_5_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_5_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_5_ccff_tail; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_60_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_60_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_60_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_60_ccff_tail; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_61_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_61_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_61_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_61_ccff_tail; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_62_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_62_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_62_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_62_ccff_tail; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_63_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_63_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_63_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_63_ccff_tail; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_6_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_6_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_6_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_6_ccff_tail; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_7_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_7_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_7_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_8_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_8_ccff_tail; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_9_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_9_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_9_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_9_ccff_tail; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_io_bottom_bottom_0_ccff_tail; + wire grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_1_ccff_tail; + wire grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_1_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_2_ccff_tail; + wire grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_2_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_3_ccff_tail; + wire grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_3_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_4_ccff_tail; + wire grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_4_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_5_ccff_tail; + wire grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_5_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_6_ccff_tail; + wire grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_6_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_7_ccff_tail; + wire grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_7_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_0_ccff_tail; + wire grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_1_ccff_tail; + wire grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_1_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_2_ccff_tail; + wire grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_2_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_3_ccff_tail; + wire grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_3_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_4_ccff_tail; + wire grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_4_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_5_ccff_tail; + wire grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_5_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_6_ccff_tail; + wire grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_6_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_7_ccff_tail; + wire grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_7_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_0_ccff_tail; + wire grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_1_ccff_tail; + wire grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_1_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_2_ccff_tail; + wire grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_2_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_3_ccff_tail; + wire grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_3_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_4_ccff_tail; + wire grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_4_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_5_ccff_tail; + wire grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_5_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_6_ccff_tail; + wire grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_6_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_7_ccff_tail; + wire grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_7_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_0_ccff_tail; + wire grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_1_ccff_tail; + wire grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_2_ccff_tail; + wire grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_3_ccff_tail; + wire grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_4_ccff_tail; + wire grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_5_ccff_tail; + wire grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_6_ccff_tail; + wire grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_7_ccff_tail; + wire sb_0__0__0_ccff_tail; + wire [0:29]sb_0__0__0_chanx_right_out; + wire [0:29]sb_0__0__0_chany_top_out; + wire sb_0__1__0_ccff_tail; + wire [0:29]sb_0__1__0_chanx_right_out; + wire [0:29]sb_0__1__0_chany_bottom_out; + wire [0:29]sb_0__1__0_chany_top_out; + wire sb_0__1__1_ccff_tail; + wire [0:29]sb_0__1__1_chanx_right_out; + wire [0:29]sb_0__1__1_chany_bottom_out; + wire [0:29]sb_0__1__1_chany_top_out; + wire sb_0__1__2_ccff_tail; + wire [0:29]sb_0__1__2_chanx_right_out; + wire [0:29]sb_0__1__2_chany_bottom_out; + wire [0:29]sb_0__1__2_chany_top_out; + wire sb_0__1__3_ccff_tail; + wire [0:29]sb_0__1__3_chanx_right_out; + wire [0:29]sb_0__1__3_chany_bottom_out; + wire [0:29]sb_0__1__3_chany_top_out; + wire sb_0__1__4_ccff_tail; + wire [0:29]sb_0__1__4_chanx_right_out; + wire [0:29]sb_0__1__4_chany_bottom_out; + wire [0:29]sb_0__1__4_chany_top_out; + wire sb_0__1__5_ccff_tail; + wire [0:29]sb_0__1__5_chanx_right_out; + wire [0:29]sb_0__1__5_chany_bottom_out; + wire [0:29]sb_0__1__5_chany_top_out; + wire sb_0__1__6_ccff_tail; + wire [0:29]sb_0__1__6_chanx_right_out; + wire [0:29]sb_0__1__6_chany_bottom_out; + wire [0:29]sb_0__1__6_chany_top_out; + wire sb_0__8__0_ccff_tail; + wire [0:29]sb_0__8__0_chanx_right_out; + wire [0:29]sb_0__8__0_chany_bottom_out; + wire sb_1__0__0_ccff_tail; + wire [0:29]sb_1__0__0_chanx_left_out; + wire [0:29]sb_1__0__0_chanx_right_out; + wire [0:29]sb_1__0__0_chany_top_out; + wire sb_1__0__1_ccff_tail; + wire [0:29]sb_1__0__1_chanx_left_out; + wire [0:29]sb_1__0__1_chanx_right_out; + wire [0:29]sb_1__0__1_chany_top_out; + wire sb_1__0__2_ccff_tail; + wire [0:29]sb_1__0__2_chanx_left_out; + wire [0:29]sb_1__0__2_chanx_right_out; + wire [0:29]sb_1__0__2_chany_top_out; + wire sb_1__0__3_ccff_tail; + wire [0:29]sb_1__0__3_chanx_left_out; + wire [0:29]sb_1__0__3_chanx_right_out; + wire [0:29]sb_1__0__3_chany_top_out; + wire sb_1__0__4_ccff_tail; + wire [0:29]sb_1__0__4_chanx_left_out; + wire [0:29]sb_1__0__4_chanx_right_out; + wire [0:29]sb_1__0__4_chany_top_out; + wire sb_1__0__5_ccff_tail; + wire [0:29]sb_1__0__5_chanx_left_out; + wire [0:29]sb_1__0__5_chanx_right_out; + wire [0:29]sb_1__0__5_chany_top_out; + wire sb_1__0__6_ccff_tail; + wire [0:29]sb_1__0__6_chanx_left_out; + wire [0:29]sb_1__0__6_chanx_right_out; + wire [0:29]sb_1__0__6_chany_top_out; + wire sb_1__1__0_ccff_tail; + wire [0:29]sb_1__1__0_chanx_left_out; + wire [0:29]sb_1__1__0_chanx_right_out; + wire [0:29]sb_1__1__0_chany_bottom_out; + wire [0:29]sb_1__1__0_chany_top_out; + wire sb_1__1__10_ccff_tail; + wire [0:29]sb_1__1__10_chanx_left_out; + wire [0:29]sb_1__1__10_chanx_right_out; + wire [0:29]sb_1__1__10_chany_bottom_out; + wire [0:29]sb_1__1__10_chany_top_out; + wire sb_1__1__11_ccff_tail; + wire [0:29]sb_1__1__11_chanx_left_out; + wire [0:29]sb_1__1__11_chanx_right_out; + wire [0:29]sb_1__1__11_chany_bottom_out; + wire [0:29]sb_1__1__11_chany_top_out; + wire sb_1__1__12_ccff_tail; + wire [0:29]sb_1__1__12_chanx_left_out; + wire [0:29]sb_1__1__12_chanx_right_out; + wire [0:29]sb_1__1__12_chany_bottom_out; + wire [0:29]sb_1__1__12_chany_top_out; + wire sb_1__1__13_ccff_tail; + wire [0:29]sb_1__1__13_chanx_left_out; + wire [0:29]sb_1__1__13_chanx_right_out; + wire [0:29]sb_1__1__13_chany_bottom_out; + wire [0:29]sb_1__1__13_chany_top_out; + wire sb_1__1__14_ccff_tail; + wire [0:29]sb_1__1__14_chanx_left_out; + wire [0:29]sb_1__1__14_chanx_right_out; + wire [0:29]sb_1__1__14_chany_bottom_out; + wire [0:29]sb_1__1__14_chany_top_out; + wire sb_1__1__15_ccff_tail; + wire [0:29]sb_1__1__15_chanx_left_out; + wire [0:29]sb_1__1__15_chanx_right_out; + wire [0:29]sb_1__1__15_chany_bottom_out; + wire [0:29]sb_1__1__15_chany_top_out; + wire sb_1__1__16_ccff_tail; + wire [0:29]sb_1__1__16_chanx_left_out; + wire [0:29]sb_1__1__16_chanx_right_out; + wire [0:29]sb_1__1__16_chany_bottom_out; + wire [0:29]sb_1__1__16_chany_top_out; + wire sb_1__1__17_ccff_tail; + wire [0:29]sb_1__1__17_chanx_left_out; + wire [0:29]sb_1__1__17_chanx_right_out; + wire [0:29]sb_1__1__17_chany_bottom_out; + wire [0:29]sb_1__1__17_chany_top_out; + wire sb_1__1__18_ccff_tail; + wire [0:29]sb_1__1__18_chanx_left_out; + wire [0:29]sb_1__1__18_chanx_right_out; + wire [0:29]sb_1__1__18_chany_bottom_out; + wire [0:29]sb_1__1__18_chany_top_out; + wire sb_1__1__19_ccff_tail; + wire [0:29]sb_1__1__19_chanx_left_out; + wire [0:29]sb_1__1__19_chanx_right_out; + wire [0:29]sb_1__1__19_chany_bottom_out; + wire [0:29]sb_1__1__19_chany_top_out; + wire sb_1__1__1_ccff_tail; + wire [0:29]sb_1__1__1_chanx_left_out; + wire [0:29]sb_1__1__1_chanx_right_out; + wire [0:29]sb_1__1__1_chany_bottom_out; + wire [0:29]sb_1__1__1_chany_top_out; + wire sb_1__1__20_ccff_tail; + wire [0:29]sb_1__1__20_chanx_left_out; + wire [0:29]sb_1__1__20_chanx_right_out; + wire [0:29]sb_1__1__20_chany_bottom_out; + wire [0:29]sb_1__1__20_chany_top_out; + wire sb_1__1__21_ccff_tail; + wire [0:29]sb_1__1__21_chanx_left_out; + wire [0:29]sb_1__1__21_chanx_right_out; + wire [0:29]sb_1__1__21_chany_bottom_out; + wire [0:29]sb_1__1__21_chany_top_out; + wire sb_1__1__22_ccff_tail; + wire [0:29]sb_1__1__22_chanx_left_out; + wire [0:29]sb_1__1__22_chanx_right_out; + wire [0:29]sb_1__1__22_chany_bottom_out; + wire [0:29]sb_1__1__22_chany_top_out; + wire sb_1__1__23_ccff_tail; + wire [0:29]sb_1__1__23_chanx_left_out; + wire [0:29]sb_1__1__23_chanx_right_out; + wire [0:29]sb_1__1__23_chany_bottom_out; + wire [0:29]sb_1__1__23_chany_top_out; + wire sb_1__1__24_ccff_tail; + wire [0:29]sb_1__1__24_chanx_left_out; + wire [0:29]sb_1__1__24_chanx_right_out; + wire [0:29]sb_1__1__24_chany_bottom_out; + wire [0:29]sb_1__1__24_chany_top_out; + wire sb_1__1__25_ccff_tail; + wire [0:29]sb_1__1__25_chanx_left_out; + wire [0:29]sb_1__1__25_chanx_right_out; + wire [0:29]sb_1__1__25_chany_bottom_out; + wire [0:29]sb_1__1__25_chany_top_out; + wire sb_1__1__26_ccff_tail; + wire [0:29]sb_1__1__26_chanx_left_out; + wire [0:29]sb_1__1__26_chanx_right_out; + wire [0:29]sb_1__1__26_chany_bottom_out; + wire [0:29]sb_1__1__26_chany_top_out; + wire sb_1__1__27_ccff_tail; + wire [0:29]sb_1__1__27_chanx_left_out; + wire [0:29]sb_1__1__27_chanx_right_out; + wire [0:29]sb_1__1__27_chany_bottom_out; + wire [0:29]sb_1__1__27_chany_top_out; + wire sb_1__1__28_ccff_tail; + wire [0:29]sb_1__1__28_chanx_left_out; + wire [0:29]sb_1__1__28_chanx_right_out; + wire [0:29]sb_1__1__28_chany_bottom_out; + wire [0:29]sb_1__1__28_chany_top_out; + wire sb_1__1__29_ccff_tail; + wire [0:29]sb_1__1__29_chanx_left_out; + wire [0:29]sb_1__1__29_chanx_right_out; + wire [0:29]sb_1__1__29_chany_bottom_out; + wire [0:29]sb_1__1__29_chany_top_out; + wire sb_1__1__2_ccff_tail; + wire [0:29]sb_1__1__2_chanx_left_out; + wire [0:29]sb_1__1__2_chanx_right_out; + wire [0:29]sb_1__1__2_chany_bottom_out; + wire [0:29]sb_1__1__2_chany_top_out; + wire sb_1__1__30_ccff_tail; + wire [0:29]sb_1__1__30_chanx_left_out; + wire [0:29]sb_1__1__30_chanx_right_out; + wire [0:29]sb_1__1__30_chany_bottom_out; + wire [0:29]sb_1__1__30_chany_top_out; + wire sb_1__1__31_ccff_tail; + wire [0:29]sb_1__1__31_chanx_left_out; + wire [0:29]sb_1__1__31_chanx_right_out; + wire [0:29]sb_1__1__31_chany_bottom_out; + wire [0:29]sb_1__1__31_chany_top_out; + wire sb_1__1__32_ccff_tail; + wire [0:29]sb_1__1__32_chanx_left_out; + wire [0:29]sb_1__1__32_chanx_right_out; + wire [0:29]sb_1__1__32_chany_bottom_out; + wire [0:29]sb_1__1__32_chany_top_out; + wire sb_1__1__33_ccff_tail; + wire [0:29]sb_1__1__33_chanx_left_out; + wire [0:29]sb_1__1__33_chanx_right_out; + wire [0:29]sb_1__1__33_chany_bottom_out; + wire [0:29]sb_1__1__33_chany_top_out; + wire sb_1__1__34_ccff_tail; + wire [0:29]sb_1__1__34_chanx_left_out; + wire [0:29]sb_1__1__34_chanx_right_out; + wire [0:29]sb_1__1__34_chany_bottom_out; + wire [0:29]sb_1__1__34_chany_top_out; + wire sb_1__1__35_ccff_tail; + wire [0:29]sb_1__1__35_chanx_left_out; + wire [0:29]sb_1__1__35_chanx_right_out; + wire [0:29]sb_1__1__35_chany_bottom_out; + wire [0:29]sb_1__1__35_chany_top_out; + wire sb_1__1__36_ccff_tail; + wire [0:29]sb_1__1__36_chanx_left_out; + wire [0:29]sb_1__1__36_chanx_right_out; + wire [0:29]sb_1__1__36_chany_bottom_out; + wire [0:29]sb_1__1__36_chany_top_out; + wire sb_1__1__37_ccff_tail; + wire [0:29]sb_1__1__37_chanx_left_out; + wire [0:29]sb_1__1__37_chanx_right_out; + wire [0:29]sb_1__1__37_chany_bottom_out; + wire [0:29]sb_1__1__37_chany_top_out; + wire sb_1__1__38_ccff_tail; + wire [0:29]sb_1__1__38_chanx_left_out; + wire [0:29]sb_1__1__38_chanx_right_out; + wire [0:29]sb_1__1__38_chany_bottom_out; + wire [0:29]sb_1__1__38_chany_top_out; + wire sb_1__1__39_ccff_tail; + wire [0:29]sb_1__1__39_chanx_left_out; + wire [0:29]sb_1__1__39_chanx_right_out; + wire [0:29]sb_1__1__39_chany_bottom_out; + wire [0:29]sb_1__1__39_chany_top_out; + wire sb_1__1__3_ccff_tail; + wire [0:29]sb_1__1__3_chanx_left_out; + wire [0:29]sb_1__1__3_chanx_right_out; + wire [0:29]sb_1__1__3_chany_bottom_out; + wire [0:29]sb_1__1__3_chany_top_out; + wire sb_1__1__40_ccff_tail; + wire [0:29]sb_1__1__40_chanx_left_out; + wire [0:29]sb_1__1__40_chanx_right_out; + wire [0:29]sb_1__1__40_chany_bottom_out; + wire [0:29]sb_1__1__40_chany_top_out; + wire sb_1__1__41_ccff_tail; + wire [0:29]sb_1__1__41_chanx_left_out; + wire [0:29]sb_1__1__41_chanx_right_out; + wire [0:29]sb_1__1__41_chany_bottom_out; + wire [0:29]sb_1__1__41_chany_top_out; + wire sb_1__1__42_ccff_tail; + wire [0:29]sb_1__1__42_chanx_left_out; + wire [0:29]sb_1__1__42_chanx_right_out; + wire [0:29]sb_1__1__42_chany_bottom_out; + wire [0:29]sb_1__1__42_chany_top_out; + wire sb_1__1__43_ccff_tail; + wire [0:29]sb_1__1__43_chanx_left_out; + wire [0:29]sb_1__1__43_chanx_right_out; + wire [0:29]sb_1__1__43_chany_bottom_out; + wire [0:29]sb_1__1__43_chany_top_out; + wire sb_1__1__44_ccff_tail; + wire [0:29]sb_1__1__44_chanx_left_out; + wire [0:29]sb_1__1__44_chanx_right_out; + wire [0:29]sb_1__1__44_chany_bottom_out; + wire [0:29]sb_1__1__44_chany_top_out; + wire sb_1__1__45_ccff_tail; + wire [0:29]sb_1__1__45_chanx_left_out; + wire [0:29]sb_1__1__45_chanx_right_out; + wire [0:29]sb_1__1__45_chany_bottom_out; + wire [0:29]sb_1__1__45_chany_top_out; + wire sb_1__1__46_ccff_tail; + wire [0:29]sb_1__1__46_chanx_left_out; + wire [0:29]sb_1__1__46_chanx_right_out; + wire [0:29]sb_1__1__46_chany_bottom_out; + wire [0:29]sb_1__1__46_chany_top_out; + wire sb_1__1__47_ccff_tail; + wire [0:29]sb_1__1__47_chanx_left_out; + wire [0:29]sb_1__1__47_chanx_right_out; + wire [0:29]sb_1__1__47_chany_bottom_out; + wire [0:29]sb_1__1__47_chany_top_out; + wire sb_1__1__48_ccff_tail; + wire [0:29]sb_1__1__48_chanx_left_out; + wire [0:29]sb_1__1__48_chanx_right_out; + wire [0:29]sb_1__1__48_chany_bottom_out; + wire [0:29]sb_1__1__48_chany_top_out; + wire sb_1__1__4_ccff_tail; + wire [0:29]sb_1__1__4_chanx_left_out; + wire [0:29]sb_1__1__4_chanx_right_out; + wire [0:29]sb_1__1__4_chany_bottom_out; + wire [0:29]sb_1__1__4_chany_top_out; + wire sb_1__1__5_ccff_tail; + wire [0:29]sb_1__1__5_chanx_left_out; + wire [0:29]sb_1__1__5_chanx_right_out; + wire [0:29]sb_1__1__5_chany_bottom_out; + wire [0:29]sb_1__1__5_chany_top_out; + wire sb_1__1__6_ccff_tail; + wire [0:29]sb_1__1__6_chanx_left_out; + wire [0:29]sb_1__1__6_chanx_right_out; + wire [0:29]sb_1__1__6_chany_bottom_out; + wire [0:29]sb_1__1__6_chany_top_out; + wire sb_1__1__7_ccff_tail; + wire [0:29]sb_1__1__7_chanx_left_out; + wire [0:29]sb_1__1__7_chanx_right_out; + wire [0:29]sb_1__1__7_chany_bottom_out; + wire [0:29]sb_1__1__7_chany_top_out; + wire sb_1__1__8_ccff_tail; + wire [0:29]sb_1__1__8_chanx_left_out; + wire [0:29]sb_1__1__8_chanx_right_out; + wire [0:29]sb_1__1__8_chany_bottom_out; + wire [0:29]sb_1__1__8_chany_top_out; + wire sb_1__1__9_ccff_tail; + wire [0:29]sb_1__1__9_chanx_left_out; + wire [0:29]sb_1__1__9_chanx_right_out; + wire [0:29]sb_1__1__9_chany_bottom_out; + wire [0:29]sb_1__1__9_chany_top_out; + wire sb_1__8__0_ccff_tail; + wire [0:29]sb_1__8__0_chanx_left_out; + wire [0:29]sb_1__8__0_chanx_right_out; + wire [0:29]sb_1__8__0_chany_bottom_out; + wire sb_1__8__1_ccff_tail; + wire [0:29]sb_1__8__1_chanx_left_out; + wire [0:29]sb_1__8__1_chanx_right_out; + wire [0:29]sb_1__8__1_chany_bottom_out; + wire sb_1__8__2_ccff_tail; + wire [0:29]sb_1__8__2_chanx_left_out; + wire [0:29]sb_1__8__2_chanx_right_out; + wire [0:29]sb_1__8__2_chany_bottom_out; + wire sb_1__8__3_ccff_tail; + wire [0:29]sb_1__8__3_chanx_left_out; + wire [0:29]sb_1__8__3_chanx_right_out; + wire [0:29]sb_1__8__3_chany_bottom_out; + wire sb_1__8__4_ccff_tail; + wire [0:29]sb_1__8__4_chanx_left_out; + wire [0:29]sb_1__8__4_chanx_right_out; + wire [0:29]sb_1__8__4_chany_bottom_out; + wire sb_1__8__5_ccff_tail; + wire [0:29]sb_1__8__5_chanx_left_out; + wire [0:29]sb_1__8__5_chanx_right_out; + wire [0:29]sb_1__8__5_chany_bottom_out; + wire sb_1__8__6_ccff_tail; + wire [0:29]sb_1__8__6_chanx_left_out; + wire [0:29]sb_1__8__6_chanx_right_out; + wire [0:29]sb_1__8__6_chany_bottom_out; + wire sb_8__0__0_ccff_tail; + wire [0:29]sb_8__0__0_chanx_left_out; + wire [0:29]sb_8__0__0_chany_top_out; + wire sb_8__1__0_ccff_tail; + wire [0:29]sb_8__1__0_chanx_left_out; + wire [0:29]sb_8__1__0_chany_bottom_out; + wire [0:29]sb_8__1__0_chany_top_out; + wire sb_8__1__1_ccff_tail; + wire [0:29]sb_8__1__1_chanx_left_out; + wire [0:29]sb_8__1__1_chany_bottom_out; + wire [0:29]sb_8__1__1_chany_top_out; + wire sb_8__1__2_ccff_tail; + wire [0:29]sb_8__1__2_chanx_left_out; + wire [0:29]sb_8__1__2_chany_bottom_out; + wire [0:29]sb_8__1__2_chany_top_out; + wire sb_8__1__3_ccff_tail; + wire [0:29]sb_8__1__3_chanx_left_out; + wire [0:29]sb_8__1__3_chany_bottom_out; + wire [0:29]sb_8__1__3_chany_top_out; + wire sb_8__1__4_ccff_tail; + wire [0:29]sb_8__1__4_chanx_left_out; + wire [0:29]sb_8__1__4_chany_bottom_out; + wire [0:29]sb_8__1__4_chany_top_out; + wire sb_8__1__5_ccff_tail; + wire [0:29]sb_8__1__5_chanx_left_out; + wire [0:29]sb_8__1__5_chany_bottom_out; + wire [0:29]sb_8__1__5_chany_top_out; + wire sb_8__1__6_ccff_tail; + wire [0:29]sb_8__1__6_chanx_left_out; + wire [0:29]sb_8__1__6_chany_bottom_out; + wire [0:29]sb_8__1__6_chany_top_out; + wire sb_8__8__0_ccff_tail; + wire [0:29]sb_8__8__0_chanx_left_out; + wire [0:29]sb_8__8__0_chany_bottom_out; + + grid_io_top_top grid_io_top_top_1__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:3]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__0_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_0_ccff_tail) + ); + grid_io_top_top grid_io_top_top_2__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4:7]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4:7]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4:7]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__1_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_1_ccff_tail) + ); + grid_io_top_top grid_io_top_top_3__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8:11]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8:11]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8:11]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__2_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_2_ccff_tail) + ); + grid_io_top_top grid_io_top_top_4__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12:15]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12:15]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12:15]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__3_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_3_ccff_tail) + ); + grid_io_top_top grid_io_top_top_5__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16:19]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16:19]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16:19]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__4_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_4_ccff_tail) + ); + grid_io_top_top grid_io_top_top_6__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20:23]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20:23]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20:23]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__5_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_5_ccff_tail) + ); + grid_io_top_top grid_io_top_top_7__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24:27]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24:27]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24:27]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__6_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_6_ccff_tail) + ); + grid_io_top_top grid_io_top_top_8__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28:31]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28:31]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28:31]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__7_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_7_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__8_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32:35]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32:35]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32:35]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_1_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_0_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__7_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36:39]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36:39]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36:39]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_2_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_1_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__6_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40:43]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40:43]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40:43]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_3_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_2_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__5_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44:47]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44:47]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44:47]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_4_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_3_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__4_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48:51]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48:51]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48:51]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_5_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_4_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__3_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52:55]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52:55]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52:55]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_6_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_5_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__2_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56:59]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56:59]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56:59]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_7_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_6_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__1_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60:63]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60:63]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60:63]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_0_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_7_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_8__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64:67]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64:67]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64:67]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_1_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_0_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_7__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68:71]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68:71]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68:71]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_2_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_1_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_6__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72:75]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72:75]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72:75]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_3_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_2_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_5__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76:79]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76:79]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76:79]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_4_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_3_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_4__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80:83]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80:83]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80:83]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_5_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_4_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_3__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84:87]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84:87]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84:87]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_6_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_5_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_2__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88:91]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88:91]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88:91]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_7_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_6_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_1__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92:95]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92:95]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92:95]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(ccff_head), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_7_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__1_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96:99]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96:99]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96:99]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__0_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_0_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__2_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100:103]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100:103]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100:103]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__1_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_1_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__3_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104:107]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104:107]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104:107]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__2_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_2_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__4_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108:111]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108:111]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108:111]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__3_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_3_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__5_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112:115]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112:115]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112:115]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__4_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_4_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__6_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116:119]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116:119]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116:119]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__5_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_5_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__7_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120:123]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120:123]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120:123]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__6_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_6_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__8_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124:127]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124:127]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124:127]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__7_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_7_ccff_tail) + ); + grid_clb grid_clb_1__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_56_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_112_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_0_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__0_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_0_ccff_tail) + ); + grid_clb grid_clb_1__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_57_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_113_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_1_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__1_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_1_ccff_tail) + ); + grid_clb grid_clb_1__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_58_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_114_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_2_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__2_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_2_ccff_tail) + ); + grid_clb grid_clb_1__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_59_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_115_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_3_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__3_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_3_ccff_tail) + ); + grid_clb grid_clb_1__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_60_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_116_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_4_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__4_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_4_ccff_tail) + ); + grid_clb grid_clb_1__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_61_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_117_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_5_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__5_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_5_ccff_tail) + ); + grid_clb grid_clb_1__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_62_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_118_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_6_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__6_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_6_ccff_tail) + ); + grid_clb grid_clb_1__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_sc_in_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__7_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(ccff_tail) + ); + grid_clb grid_clb_2__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_63_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_119_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_7_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__8_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_8_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_8_ccff_tail) + ); + grid_clb grid_clb_2__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_64_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_120_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_8_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__9_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_9_ccff_tail) + ); + grid_clb grid_clb_2__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_65_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_121_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_9_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__10_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_10_ccff_tail) + ); + grid_clb grid_clb_2__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_66_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_122_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_10_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__11_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_11_ccff_tail) + ); + grid_clb grid_clb_2__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_67_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_123_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_11_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__12_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_12_ccff_tail) + ); + grid_clb grid_clb_2__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_68_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_124_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_12_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__13_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_13_ccff_tail) + ); + grid_clb grid_clb_2__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_69_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_125_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_13_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__14_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_14_ccff_tail) + ); + grid_clb grid_clb_2__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_168_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__15_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_15_ccff_tail) + ); + grid_clb grid_clb_3__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_70_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_126_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_14_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__16_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_16_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_16_ccff_tail) + ); + grid_clb grid_clb_3__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_71_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_127_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_15_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__17_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_17_ccff_tail) + ); + grid_clb grid_clb_3__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_72_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_128_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_16_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__18_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_18_ccff_tail) + ); + grid_clb grid_clb_3__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_73_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_129_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_17_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__19_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_19_ccff_tail) + ); + grid_clb grid_clb_3__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_74_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_130_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_18_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__20_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_20_ccff_tail) + ); + grid_clb grid_clb_3__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_75_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_131_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_19_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__21_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_21_ccff_tail) + ); + grid_clb grid_clb_3__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_76_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_132_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_20_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__22_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_22_ccff_tail) + ); + grid_clb grid_clb_3__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_169_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__23_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_23_ccff_tail) + ); + grid_clb grid_clb_4__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_77_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_133_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_21_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__24_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_24_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_24_ccff_tail) + ); + grid_clb grid_clb_4__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_78_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_134_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_22_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__25_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_25_ccff_tail) + ); + grid_clb grid_clb_4__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_79_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_135_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_23_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__26_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_26_ccff_tail) + ); + grid_clb grid_clb_4__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_80_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_136_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_24_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__27_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_27_ccff_tail) + ); + grid_clb grid_clb_4__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_81_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_137_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_25_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__28_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_28_ccff_tail) + ); + grid_clb grid_clb_4__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_82_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_138_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_26_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__29_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_29_ccff_tail) + ); + grid_clb grid_clb_4__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_83_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_139_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_27_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__30_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_30_ccff_tail) + ); + grid_clb grid_clb_4__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_170_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__31_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_31_ccff_tail) + ); + grid_clb grid_clb_5__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_84_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_140_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_28_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__32_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_32_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_32_ccff_tail) + ); + grid_clb grid_clb_5__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_85_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_141_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_29_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__33_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_33_ccff_tail) + ); + grid_clb grid_clb_5__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_86_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_142_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_30_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__34_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_34_ccff_tail) + ); + grid_clb grid_clb_5__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_87_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_143_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_31_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__35_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_35_ccff_tail) + ); + grid_clb grid_clb_5__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_88_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_144_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_32_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__36_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_36_ccff_tail) + ); + grid_clb grid_clb_5__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_89_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_145_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_33_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__37_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_37_ccff_tail) + ); + grid_clb grid_clb_5__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_90_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_146_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_34_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__38_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_38_ccff_tail) + ); + grid_clb grid_clb_5__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_171_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__39_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_39_ccff_tail) + ); + grid_clb grid_clb_6__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_91_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_147_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_35_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__40_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_40_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_40_ccff_tail) + ); + grid_clb grid_clb_6__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_92_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_148_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_36_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__41_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_41_ccff_tail) + ); + grid_clb grid_clb_6__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_93_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_149_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_37_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__42_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_42_ccff_tail) + ); + grid_clb grid_clb_6__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_94_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_150_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_38_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__43_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_43_ccff_tail) + ); + grid_clb grid_clb_6__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_95_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_151_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_39_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__44_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_44_ccff_tail) + ); + grid_clb grid_clb_6__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_96_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_152_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_40_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__45_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_45_ccff_tail) + ); + grid_clb grid_clb_6__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_97_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_153_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_41_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__46_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_46_ccff_tail) + ); + grid_clb grid_clb_6__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_172_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__47_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_47_ccff_tail) + ); + grid_clb grid_clb_7__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_98_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_154_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_42_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__48_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_48_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_48_ccff_tail) + ); + grid_clb grid_clb_7__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_99_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_155_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_43_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__49_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_49_ccff_tail) + ); + grid_clb grid_clb_7__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_100_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_156_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_44_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__50_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_50_ccff_tail) + ); + grid_clb grid_clb_7__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_101_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_157_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_45_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__51_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_51_ccff_tail) + ); + grid_clb grid_clb_7__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_102_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_158_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_46_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__52_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_52_ccff_tail) + ); + grid_clb grid_clb_7__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_103_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_159_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_47_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__53_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_53_ccff_tail) + ); + grid_clb grid_clb_7__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_104_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_160_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_48_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__54_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_54_ccff_tail) + ); + grid_clb grid_clb_7__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_173_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__55_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_55_ccff_tail) + ); + grid_clb grid_clb_8__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_105_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_161_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_49_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__0_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_56_ccff_tail) + ); + grid_clb grid_clb_8__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_106_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_162_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_50_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__1_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_57_ccff_tail) + ); + grid_clb grid_clb_8__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_107_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_163_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_51_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__2_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_58_ccff_tail) + ); + grid_clb grid_clb_8__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_108_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_164_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_52_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__3_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_59_ccff_tail) + ); + grid_clb grid_clb_8__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_109_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_165_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_53_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__4_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_60_ccff_tail) + ); + grid_clb grid_clb_8__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_110_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_166_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_54_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__5_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_61_ccff_tail) + ); + grid_clb grid_clb_8__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_111_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_167_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_55_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__6_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_62_ccff_tail) + ); + grid_clb grid_clb_8__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_174_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__7_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_63_ccff_tail) + ); + sb_0__0_ sb_0__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__0_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__0__0_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_1_ccff_tail), + .chany_top_out(sb_0__0__0_chany_top_out), + .chanx_right_out(sb_0__0__0_chanx_right_out), + .ccff_tail(sb_0__0__0_ccff_tail) + ); + sb_0__1_ sb_0__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__1_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__0_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__0_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_2_ccff_tail), + .chany_top_out(sb_0__1__0_chany_top_out), + .chanx_right_out(sb_0__1__0_chanx_right_out), + .chany_bottom_out(sb_0__1__0_chany_bottom_out), + .ccff_tail(sb_0__1__0_ccff_tail) + ); + sb_0__1_ sb_0__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__2_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__1_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__1_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_3_ccff_tail), + .chany_top_out(sb_0__1__1_chany_top_out), + .chanx_right_out(sb_0__1__1_chanx_right_out), + .chany_bottom_out(sb_0__1__1_chany_bottom_out), + .ccff_tail(sb_0__1__1_ccff_tail) + ); + sb_0__1_ sb_0__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__3_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__2_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__2_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_4_ccff_tail), + .chany_top_out(sb_0__1__2_chany_top_out), + .chanx_right_out(sb_0__1__2_chanx_right_out), + .chany_bottom_out(sb_0__1__2_chany_bottom_out), + .ccff_tail(sb_0__1__2_ccff_tail) + ); + sb_0__1_ sb_0__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__4_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__3_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__3_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_5_ccff_tail), + .chany_top_out(sb_0__1__3_chany_top_out), + .chanx_right_out(sb_0__1__3_chanx_right_out), + .chany_bottom_out(sb_0__1__3_chany_bottom_out), + .ccff_tail(sb_0__1__3_ccff_tail) + ); + sb_0__1_ sb_0__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__5_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__4_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__4_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_6_ccff_tail), + .chany_top_out(sb_0__1__4_chany_top_out), + .chanx_right_out(sb_0__1__4_chanx_right_out), + .chany_bottom_out(sb_0__1__4_chany_bottom_out), + .ccff_tail(sb_0__1__4_ccff_tail) + ); + sb_0__1_ sb_0__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__6_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__5_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__5_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_7_ccff_tail), + .chany_top_out(sb_0__1__5_chany_top_out), + .chanx_right_out(sb_0__1__5_chanx_right_out), + .chany_bottom_out(sb_0__1__5_chany_bottom_out), + .ccff_tail(sb_0__1__5_ccff_tail) + ); + sb_0__1_ sb_0__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__7_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__6_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__6_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(sb_0__8__0_ccff_tail), + .chany_top_out(sb_0__1__6_chany_top_out), + .chanx_right_out(sb_0__1__6_chanx_right_out), + .chany_bottom_out(sb_0__1__6_chany_bottom_out), + .ccff_tail(sb_0__1__6_ccff_tail) + ); + sb_0__8_ sb_0__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__0_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__7_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_top_top_0_ccff_tail), + .chanx_right_out(sb_0__8__0_chanx_right_out), + .chany_bottom_out(sb_0__8__0_chany_bottom_out), + .ccff_tail(sb_0__8__0_ccff_tail) + ); + sb_1__0_ sb_1__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__0_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__1_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__0_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_0_ccff_tail), + .chany_top_out(sb_1__0__0_chany_top_out), + .chanx_right_out(sb_1__0__0_chanx_right_out), + .chanx_left_out(sb_1__0__0_chanx_left_out), + .ccff_tail(sb_1__0__0_ccff_tail) + ); + sb_1__0_ sb_2__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__8_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__2_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__1_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_0_ccff_tail), + .chany_top_out(sb_1__0__1_chany_top_out), + .chanx_right_out(sb_1__0__1_chanx_right_out), + .chanx_left_out(sb_1__0__1_chanx_left_out), + .ccff_tail(sb_1__0__1_ccff_tail) + ); + sb_1__0_ sb_3__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__16_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__3_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__2_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_8_ccff_tail), + .chany_top_out(sb_1__0__2_chany_top_out), + .chanx_right_out(sb_1__0__2_chanx_right_out), + .chanx_left_out(sb_1__0__2_chanx_left_out), + .ccff_tail(sb_1__0__2_ccff_tail) + ); + sb_1__0_ sb_4__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__24_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__4_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__3_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_16_ccff_tail), + .chany_top_out(sb_1__0__3_chany_top_out), + .chanx_right_out(sb_1__0__3_chanx_right_out), + .chanx_left_out(sb_1__0__3_chanx_left_out), + .ccff_tail(sb_1__0__3_ccff_tail) + ); + sb_1__0_ sb_5__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__32_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__5_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__4_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_24_ccff_tail), + .chany_top_out(sb_1__0__4_chany_top_out), + .chanx_right_out(sb_1__0__4_chanx_right_out), + .chanx_left_out(sb_1__0__4_chanx_left_out), + .ccff_tail(sb_1__0__4_ccff_tail) + ); + sb_1__0_ sb_6__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__40_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__6_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__5_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_32_ccff_tail), + .chany_top_out(sb_1__0__5_chany_top_out), + .chanx_right_out(sb_1__0__5_chanx_right_out), + .chanx_left_out(sb_1__0__5_chanx_left_out), + .ccff_tail(sb_1__0__5_ccff_tail) + ); + sb_1__0_ sb_7__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__48_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__7_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__6_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_40_ccff_tail), + .chany_top_out(sb_1__0__6_chany_top_out), + .chanx_right_out(sb_1__0__6_chanx_right_out), + .chanx_left_out(sb_1__0__6_chanx_left_out), + .ccff_tail(sb_1__0__6_ccff_tail) + ); + sb_1__1_ sb_1__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__1_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__7_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__0_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__0_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_9_ccff_tail), + .chany_top_out(sb_1__1__0_chany_top_out), + .chanx_right_out(sb_1__1__0_chanx_right_out), + .chany_bottom_out(sb_1__1__0_chany_bottom_out), + .chanx_left_out(sb_1__1__0_chanx_left_out), + .ccff_tail(sb_1__1__0_ccff_tail) + ); + sb_1__1_ sb_1__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__2_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__8_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__1_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__1_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_1_ccff_tail), + .chany_top_out(sb_1__1__1_chany_top_out), + .chanx_right_out(sb_1__1__1_chanx_right_out), + .chany_bottom_out(sb_1__1__1_chany_bottom_out), + .chanx_left_out(sb_1__1__1_chanx_left_out), + .ccff_tail(sb_1__1__1_ccff_tail) + ); + sb_1__1_ sb_1__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__3_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__9_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__2_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__2_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_11_ccff_tail), + .chany_top_out(sb_1__1__2_chany_top_out), + .chanx_right_out(sb_1__1__2_chanx_right_out), + .chany_bottom_out(sb_1__1__2_chany_bottom_out), + .chanx_left_out(sb_1__1__2_chanx_left_out), + .ccff_tail(sb_1__1__2_ccff_tail) + ); + sb_1__1_ sb_1__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__4_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__10_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__3_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__3_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_3_ccff_tail), + .chany_top_out(sb_1__1__3_chany_top_out), + .chanx_right_out(sb_1__1__3_chanx_right_out), + .chany_bottom_out(sb_1__1__3_chany_bottom_out), + .chanx_left_out(sb_1__1__3_chanx_left_out), + .ccff_tail(sb_1__1__3_ccff_tail) + ); + sb_1__1_ sb_1__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__5_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__11_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__4_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__4_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_13_ccff_tail), + .chany_top_out(sb_1__1__4_chany_top_out), + .chanx_right_out(sb_1__1__4_chanx_right_out), + .chany_bottom_out(sb_1__1__4_chany_bottom_out), + .chanx_left_out(sb_1__1__4_chanx_left_out), + .ccff_tail(sb_1__1__4_ccff_tail) + ); + sb_1__1_ sb_1__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__6_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__12_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__5_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__5_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_5_ccff_tail), + .chany_top_out(sb_1__1__5_chany_top_out), + .chanx_right_out(sb_1__1__5_chanx_right_out), + .chany_bottom_out(sb_1__1__5_chany_bottom_out), + .chanx_left_out(sb_1__1__5_chanx_left_out), + .ccff_tail(sb_1__1__5_ccff_tail) + ); + sb_1__1_ sb_1__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__7_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__13_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__6_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__6_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_15_ccff_tail), + .chany_top_out(sb_1__1__6_chany_top_out), + .chanx_right_out(sb_1__1__6_chanx_right_out), + .chany_bottom_out(sb_1__1__6_chany_bottom_out), + .chanx_left_out(sb_1__1__6_chanx_left_out), + .ccff_tail(sb_1__1__6_ccff_tail) + ); + sb_1__1_ sb_2__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__9_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__14_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__8_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__7_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_17_ccff_tail), + .chany_top_out(sb_1__1__7_chany_top_out), + .chanx_right_out(sb_1__1__7_chanx_right_out), + .chany_bottom_out(sb_1__1__7_chany_bottom_out), + .chanx_left_out(sb_1__1__7_chanx_left_out), + .ccff_tail(sb_1__1__7_ccff_tail) + ); + sb_1__1_ sb_2__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__10_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__15_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__9_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__8_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_2_ccff_tail), + .chany_top_out(sb_1__1__8_chany_top_out), + .chanx_right_out(sb_1__1__8_chanx_right_out), + .chany_bottom_out(sb_1__1__8_chany_bottom_out), + .chanx_left_out(sb_1__1__8_chanx_left_out), + .ccff_tail(sb_1__1__8_ccff_tail) + ); + sb_1__1_ sb_2__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__11_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__16_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__10_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__9_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_19_ccff_tail), + .chany_top_out(sb_1__1__9_chany_top_out), + .chanx_right_out(sb_1__1__9_chanx_right_out), + .chany_bottom_out(sb_1__1__9_chany_bottom_out), + .chanx_left_out(sb_1__1__9_chanx_left_out), + .ccff_tail(sb_1__1__9_ccff_tail) + ); + sb_1__1_ sb_2__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__12_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__17_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__11_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__10_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_4_ccff_tail), + .chany_top_out(sb_1__1__10_chany_top_out), + .chanx_right_out(sb_1__1__10_chanx_right_out), + .chany_bottom_out(sb_1__1__10_chany_bottom_out), + .chanx_left_out(sb_1__1__10_chanx_left_out), + .ccff_tail(sb_1__1__10_ccff_tail) + ); + sb_1__1_ sb_2__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__13_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__18_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__12_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__11_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_21_ccff_tail), + .chany_top_out(sb_1__1__11_chany_top_out), + .chanx_right_out(sb_1__1__11_chanx_right_out), + .chany_bottom_out(sb_1__1__11_chany_bottom_out), + .chanx_left_out(sb_1__1__11_chanx_left_out), + .ccff_tail(sb_1__1__11_ccff_tail) + ); + sb_1__1_ sb_2__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__14_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__19_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__13_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__12_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_6_ccff_tail), + .chany_top_out(sb_1__1__12_chany_top_out), + .chanx_right_out(sb_1__1__12_chanx_right_out), + .chany_bottom_out(sb_1__1__12_chany_bottom_out), + .chanx_left_out(sb_1__1__12_chanx_left_out), + .ccff_tail(sb_1__1__12_ccff_tail) + ); + sb_1__1_ sb_2__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__15_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__20_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__14_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__13_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_23_ccff_tail), + .chany_top_out(sb_1__1__13_chany_top_out), + .chanx_right_out(sb_1__1__13_chanx_right_out), + .chany_bottom_out(sb_1__1__13_chany_bottom_out), + .chanx_left_out(sb_1__1__13_chanx_left_out), + .ccff_tail(sb_1__1__13_ccff_tail) + ); + sb_1__1_ sb_3__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__17_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__21_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__16_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__14_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_25_ccff_tail), + .chany_top_out(sb_1__1__14_chany_top_out), + .chanx_right_out(sb_1__1__14_chanx_right_out), + .chany_bottom_out(sb_1__1__14_chany_bottom_out), + .chanx_left_out(sb_1__1__14_chanx_left_out), + .ccff_tail(sb_1__1__14_ccff_tail) + ); + sb_1__1_ sb_3__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__18_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__22_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__17_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__15_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_10_ccff_tail), + .chany_top_out(sb_1__1__15_chany_top_out), + .chanx_right_out(sb_1__1__15_chanx_right_out), + .chany_bottom_out(sb_1__1__15_chany_bottom_out), + .chanx_left_out(sb_1__1__15_chanx_left_out), + .ccff_tail(sb_1__1__15_ccff_tail) + ); + sb_1__1_ sb_3__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__19_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__23_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__18_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__16_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_27_ccff_tail), + .chany_top_out(sb_1__1__16_chany_top_out), + .chanx_right_out(sb_1__1__16_chanx_right_out), + .chany_bottom_out(sb_1__1__16_chany_bottom_out), + .chanx_left_out(sb_1__1__16_chanx_left_out), + .ccff_tail(sb_1__1__16_ccff_tail) + ); + sb_1__1_ sb_3__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__20_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__24_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__19_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__17_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_12_ccff_tail), + .chany_top_out(sb_1__1__17_chany_top_out), + .chanx_right_out(sb_1__1__17_chanx_right_out), + .chany_bottom_out(sb_1__1__17_chany_bottom_out), + .chanx_left_out(sb_1__1__17_chanx_left_out), + .ccff_tail(sb_1__1__17_ccff_tail) + ); + sb_1__1_ sb_3__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__21_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__25_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__20_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__18_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_29_ccff_tail), + .chany_top_out(sb_1__1__18_chany_top_out), + .chanx_right_out(sb_1__1__18_chanx_right_out), + .chany_bottom_out(sb_1__1__18_chany_bottom_out), + .chanx_left_out(sb_1__1__18_chanx_left_out), + .ccff_tail(sb_1__1__18_ccff_tail) + ); + sb_1__1_ sb_3__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__22_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__26_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__21_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__19_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_14_ccff_tail), + .chany_top_out(sb_1__1__19_chany_top_out), + .chanx_right_out(sb_1__1__19_chanx_right_out), + .chany_bottom_out(sb_1__1__19_chany_bottom_out), + .chanx_left_out(sb_1__1__19_chanx_left_out), + .ccff_tail(sb_1__1__19_ccff_tail) + ); + sb_1__1_ sb_3__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__23_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__27_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__22_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__20_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_31_ccff_tail), + .chany_top_out(sb_1__1__20_chany_top_out), + .chanx_right_out(sb_1__1__20_chanx_right_out), + .chany_bottom_out(sb_1__1__20_chany_bottom_out), + .chanx_left_out(sb_1__1__20_chanx_left_out), + .ccff_tail(sb_1__1__20_ccff_tail) + ); + sb_1__1_ sb_4__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__25_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__28_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__24_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__21_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_33_ccff_tail), + .chany_top_out(sb_1__1__21_chany_top_out), + .chanx_right_out(sb_1__1__21_chanx_right_out), + .chany_bottom_out(sb_1__1__21_chany_bottom_out), + .chanx_left_out(sb_1__1__21_chanx_left_out), + .ccff_tail(sb_1__1__21_ccff_tail) + ); + sb_1__1_ sb_4__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__26_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__29_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__25_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__22_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_18_ccff_tail), + .chany_top_out(sb_1__1__22_chany_top_out), + .chanx_right_out(sb_1__1__22_chanx_right_out), + .chany_bottom_out(sb_1__1__22_chany_bottom_out), + .chanx_left_out(sb_1__1__22_chanx_left_out), + .ccff_tail(sb_1__1__22_ccff_tail) + ); + sb_1__1_ sb_4__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__27_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__30_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__26_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__23_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_35_ccff_tail), + .chany_top_out(sb_1__1__23_chany_top_out), + .chanx_right_out(sb_1__1__23_chanx_right_out), + .chany_bottom_out(sb_1__1__23_chany_bottom_out), + .chanx_left_out(sb_1__1__23_chanx_left_out), + .ccff_tail(sb_1__1__23_ccff_tail) + ); + sb_1__1_ sb_4__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__28_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__31_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__27_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__24_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_20_ccff_tail), + .chany_top_out(sb_1__1__24_chany_top_out), + .chanx_right_out(sb_1__1__24_chanx_right_out), + .chany_bottom_out(sb_1__1__24_chany_bottom_out), + .chanx_left_out(sb_1__1__24_chanx_left_out), + .ccff_tail(sb_1__1__24_ccff_tail) + ); + sb_1__1_ sb_4__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__29_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__32_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__28_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__25_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_37_ccff_tail), + .chany_top_out(sb_1__1__25_chany_top_out), + .chanx_right_out(sb_1__1__25_chanx_right_out), + .chany_bottom_out(sb_1__1__25_chany_bottom_out), + .chanx_left_out(sb_1__1__25_chanx_left_out), + .ccff_tail(sb_1__1__25_ccff_tail) + ); + sb_1__1_ sb_4__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__30_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__33_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__29_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__26_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_22_ccff_tail), + .chany_top_out(sb_1__1__26_chany_top_out), + .chanx_right_out(sb_1__1__26_chanx_right_out), + .chany_bottom_out(sb_1__1__26_chany_bottom_out), + .chanx_left_out(sb_1__1__26_chanx_left_out), + .ccff_tail(sb_1__1__26_ccff_tail) + ); + sb_1__1_ sb_4__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__31_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__34_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__30_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__27_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_39_ccff_tail), + .chany_top_out(sb_1__1__27_chany_top_out), + .chanx_right_out(sb_1__1__27_chanx_right_out), + .chany_bottom_out(sb_1__1__27_chany_bottom_out), + .chanx_left_out(sb_1__1__27_chanx_left_out), + .ccff_tail(sb_1__1__27_ccff_tail) + ); + sb_1__1_ sb_5__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__33_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__35_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__32_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__28_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_41_ccff_tail), + .chany_top_out(sb_1__1__28_chany_top_out), + .chanx_right_out(sb_1__1__28_chanx_right_out), + .chany_bottom_out(sb_1__1__28_chany_bottom_out), + .chanx_left_out(sb_1__1__28_chanx_left_out), + .ccff_tail(sb_1__1__28_ccff_tail) + ); + sb_1__1_ sb_5__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__34_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__36_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__33_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__29_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_26_ccff_tail), + .chany_top_out(sb_1__1__29_chany_top_out), + .chanx_right_out(sb_1__1__29_chanx_right_out), + .chany_bottom_out(sb_1__1__29_chany_bottom_out), + .chanx_left_out(sb_1__1__29_chanx_left_out), + .ccff_tail(sb_1__1__29_ccff_tail) + ); + sb_1__1_ sb_5__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__35_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__37_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__34_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__30_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_43_ccff_tail), + .chany_top_out(sb_1__1__30_chany_top_out), + .chanx_right_out(sb_1__1__30_chanx_right_out), + .chany_bottom_out(sb_1__1__30_chany_bottom_out), + .chanx_left_out(sb_1__1__30_chanx_left_out), + .ccff_tail(sb_1__1__30_ccff_tail) + ); + sb_1__1_ sb_5__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__36_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__38_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__35_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__31_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_28_ccff_tail), + .chany_top_out(sb_1__1__31_chany_top_out), + .chanx_right_out(sb_1__1__31_chanx_right_out), + .chany_bottom_out(sb_1__1__31_chany_bottom_out), + .chanx_left_out(sb_1__1__31_chanx_left_out), + .ccff_tail(sb_1__1__31_ccff_tail) + ); + sb_1__1_ sb_5__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__37_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__39_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__36_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__32_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_45_ccff_tail), + .chany_top_out(sb_1__1__32_chany_top_out), + .chanx_right_out(sb_1__1__32_chanx_right_out), + .chany_bottom_out(sb_1__1__32_chany_bottom_out), + .chanx_left_out(sb_1__1__32_chanx_left_out), + .ccff_tail(sb_1__1__32_ccff_tail) + ); + sb_1__1_ sb_5__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__38_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__40_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__37_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__33_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_30_ccff_tail), + .chany_top_out(sb_1__1__33_chany_top_out), + .chanx_right_out(sb_1__1__33_chanx_right_out), + .chany_bottom_out(sb_1__1__33_chany_bottom_out), + .chanx_left_out(sb_1__1__33_chanx_left_out), + .ccff_tail(sb_1__1__33_ccff_tail) + ); + sb_1__1_ sb_5__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__39_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__41_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__38_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__34_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_47_ccff_tail), + .chany_top_out(sb_1__1__34_chany_top_out), + .chanx_right_out(sb_1__1__34_chanx_right_out), + .chany_bottom_out(sb_1__1__34_chany_bottom_out), + .chanx_left_out(sb_1__1__34_chanx_left_out), + .ccff_tail(sb_1__1__34_ccff_tail) + ); + sb_1__1_ sb_6__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__41_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__42_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__40_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__35_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_49_ccff_tail), + .chany_top_out(sb_1__1__35_chany_top_out), + .chanx_right_out(sb_1__1__35_chanx_right_out), + .chany_bottom_out(sb_1__1__35_chany_bottom_out), + .chanx_left_out(sb_1__1__35_chanx_left_out), + .ccff_tail(sb_1__1__35_ccff_tail) + ); + sb_1__1_ sb_6__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__42_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__43_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__41_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__36_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_34_ccff_tail), + .chany_top_out(sb_1__1__36_chany_top_out), + .chanx_right_out(sb_1__1__36_chanx_right_out), + .chany_bottom_out(sb_1__1__36_chany_bottom_out), + .chanx_left_out(sb_1__1__36_chanx_left_out), + .ccff_tail(sb_1__1__36_ccff_tail) + ); + sb_1__1_ sb_6__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__43_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__44_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__42_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__37_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_51_ccff_tail), + .chany_top_out(sb_1__1__37_chany_top_out), + .chanx_right_out(sb_1__1__37_chanx_right_out), + .chany_bottom_out(sb_1__1__37_chany_bottom_out), + .chanx_left_out(sb_1__1__37_chanx_left_out), + .ccff_tail(sb_1__1__37_ccff_tail) + ); + sb_1__1_ sb_6__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__44_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__45_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__43_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__38_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_36_ccff_tail), + .chany_top_out(sb_1__1__38_chany_top_out), + .chanx_right_out(sb_1__1__38_chanx_right_out), + .chany_bottom_out(sb_1__1__38_chany_bottom_out), + .chanx_left_out(sb_1__1__38_chanx_left_out), + .ccff_tail(sb_1__1__38_ccff_tail) + ); + sb_1__1_ sb_6__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__45_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__46_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__44_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__39_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_53_ccff_tail), + .chany_top_out(sb_1__1__39_chany_top_out), + .chanx_right_out(sb_1__1__39_chanx_right_out), + .chany_bottom_out(sb_1__1__39_chany_bottom_out), + .chanx_left_out(sb_1__1__39_chanx_left_out), + .ccff_tail(sb_1__1__39_ccff_tail) + ); + sb_1__1_ sb_6__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__46_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__47_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__45_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__40_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_38_ccff_tail), + .chany_top_out(sb_1__1__40_chany_top_out), + .chanx_right_out(sb_1__1__40_chanx_right_out), + .chany_bottom_out(sb_1__1__40_chany_bottom_out), + .chanx_left_out(sb_1__1__40_chanx_left_out), + .ccff_tail(sb_1__1__40_ccff_tail) + ); + sb_1__1_ sb_6__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__47_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__48_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__46_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__41_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_55_ccff_tail), + .chany_top_out(sb_1__1__41_chany_top_out), + .chanx_right_out(sb_1__1__41_chanx_right_out), + .chany_bottom_out(sb_1__1__41_chany_bottom_out), + .chanx_left_out(sb_1__1__41_chanx_left_out), + .ccff_tail(sb_1__1__41_ccff_tail) + ); + sb_1__1_ sb_7__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__49_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__49_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__48_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__42_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_57_ccff_tail), + .chany_top_out(sb_1__1__42_chany_top_out), + .chanx_right_out(sb_1__1__42_chanx_right_out), + .chany_bottom_out(sb_1__1__42_chany_bottom_out), + .chanx_left_out(sb_1__1__42_chanx_left_out), + .ccff_tail(sb_1__1__42_ccff_tail) + ); + sb_1__1_ sb_7__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__50_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__50_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__49_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__43_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_42_ccff_tail), + .chany_top_out(sb_1__1__43_chany_top_out), + .chanx_right_out(sb_1__1__43_chanx_right_out), + .chany_bottom_out(sb_1__1__43_chany_bottom_out), + .chanx_left_out(sb_1__1__43_chanx_left_out), + .ccff_tail(sb_1__1__43_ccff_tail) + ); + sb_1__1_ sb_7__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__51_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__51_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__50_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__44_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_59_ccff_tail), + .chany_top_out(sb_1__1__44_chany_top_out), + .chanx_right_out(sb_1__1__44_chanx_right_out), + .chany_bottom_out(sb_1__1__44_chany_bottom_out), + .chanx_left_out(sb_1__1__44_chanx_left_out), + .ccff_tail(sb_1__1__44_ccff_tail) + ); + sb_1__1_ sb_7__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__52_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__52_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__51_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__45_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_44_ccff_tail), + .chany_top_out(sb_1__1__45_chany_top_out), + .chanx_right_out(sb_1__1__45_chanx_right_out), + .chany_bottom_out(sb_1__1__45_chany_bottom_out), + .chanx_left_out(sb_1__1__45_chanx_left_out), + .ccff_tail(sb_1__1__45_ccff_tail) + ); + sb_1__1_ sb_7__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__53_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__53_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__52_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__46_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_61_ccff_tail), + .chany_top_out(sb_1__1__46_chany_top_out), + .chanx_right_out(sb_1__1__46_chanx_right_out), + .chany_bottom_out(sb_1__1__46_chany_bottom_out), + .chanx_left_out(sb_1__1__46_chanx_left_out), + .ccff_tail(sb_1__1__46_ccff_tail) + ); + sb_1__1_ sb_7__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__54_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__54_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__53_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__47_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_46_ccff_tail), + .chany_top_out(sb_1__1__47_chany_top_out), + .chanx_right_out(sb_1__1__47_chanx_right_out), + .chany_bottom_out(sb_1__1__47_chany_bottom_out), + .chanx_left_out(sb_1__1__47_chanx_left_out), + .ccff_tail(sb_1__1__47_ccff_tail) + ); + sb_1__1_ sb_7__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__55_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__55_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__54_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__48_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_63_ccff_tail), + .chany_top_out(sb_1__1__48_chany_top_out), + .chanx_right_out(sb_1__1__48_chanx_right_out), + .chany_bottom_out(sb_1__1__48_chany_bottom_out), + .chanx_left_out(sb_1__1__48_chanx_left_out), + .ccff_tail(sb_1__1__48_ccff_tail) + ); + sb_1__8_ sb_1__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__1_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__7_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__0_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_1_ccff_tail), + .chanx_right_out(sb_1__8__0_chanx_right_out), + .chany_bottom_out(sb_1__8__0_chany_bottom_out), + .chanx_left_out(sb_1__8__0_chanx_left_out), + .ccff_tail(sb_1__8__0_ccff_tail) + ); + sb_1__8_ sb_2__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__2_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__15_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__1_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_2_ccff_tail), + .chanx_right_out(sb_1__8__1_chanx_right_out), + .chany_bottom_out(sb_1__8__1_chany_bottom_out), + .chanx_left_out(sb_1__8__1_chanx_left_out), + .ccff_tail(sb_1__8__1_ccff_tail) + ); + sb_1__8_ sb_3__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__3_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__23_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__2_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_3_ccff_tail), + .chanx_right_out(sb_1__8__2_chanx_right_out), + .chany_bottom_out(sb_1__8__2_chany_bottom_out), + .chanx_left_out(sb_1__8__2_chanx_left_out), + .ccff_tail(sb_1__8__2_ccff_tail) + ); + sb_1__8_ sb_4__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__4_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__31_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__3_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_4_ccff_tail), + .chanx_right_out(sb_1__8__3_chanx_right_out), + .chany_bottom_out(sb_1__8__3_chany_bottom_out), + .chanx_left_out(sb_1__8__3_chanx_left_out), + .ccff_tail(sb_1__8__3_ccff_tail) + ); + sb_1__8_ sb_5__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__5_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__39_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__4_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_5_ccff_tail), + .chanx_right_out(sb_1__8__4_chanx_right_out), + .chany_bottom_out(sb_1__8__4_chany_bottom_out), + .chanx_left_out(sb_1__8__4_chanx_left_out), + .ccff_tail(sb_1__8__4_ccff_tail) + ); + sb_1__8_ sb_6__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__6_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__47_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__5_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_6_ccff_tail), + .chanx_right_out(sb_1__8__5_chanx_right_out), + .chany_bottom_out(sb_1__8__5_chany_bottom_out), + .chanx_left_out(sb_1__8__5_chanx_left_out), + .ccff_tail(sb_1__8__5_ccff_tail) + ); + sb_1__8_ sb_7__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__7_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__55_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__6_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_7_ccff_tail), + .chanx_right_out(sb_1__8__6_chanx_right_out), + .chany_bottom_out(sb_1__8__6_chany_bottom_out), + .chanx_left_out(sb_1__8__6_chanx_left_out), + .ccff_tail(sb_1__8__6_ccff_tail) + ); + sb_8__0_ sb_8__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__0_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__7_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_48_ccff_tail), + .chany_top_out(sb_8__0__0_chany_top_out), + .chanx_left_out(sb_8__0__0_chanx_left_out), + .ccff_tail(sb_8__0__0_ccff_tail) + ); + sb_8__1_ sb_8__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__1_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__0_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__49_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_56_ccff_tail), + .chany_top_out(sb_8__1__0_chany_top_out), + .chany_bottom_out(sb_8__1__0_chany_bottom_out), + .chanx_left_out(sb_8__1__0_chanx_left_out), + .ccff_tail(sb_8__1__0_ccff_tail) + ); + sb_8__1_ sb_8__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__2_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__1_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__50_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_50_ccff_tail), + .chany_top_out(sb_8__1__1_chany_top_out), + .chany_bottom_out(sb_8__1__1_chany_bottom_out), + .chanx_left_out(sb_8__1__1_chanx_left_out), + .ccff_tail(sb_8__1__1_ccff_tail) + ); + sb_8__1_ sb_8__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__3_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__2_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__51_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_58_ccff_tail), + .chany_top_out(sb_8__1__2_chany_top_out), + .chany_bottom_out(sb_8__1__2_chany_bottom_out), + .chanx_left_out(sb_8__1__2_chanx_left_out), + .ccff_tail(sb_8__1__2_ccff_tail) + ); + sb_8__1_ sb_8__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__4_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__3_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__52_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_52_ccff_tail), + .chany_top_out(sb_8__1__3_chany_top_out), + .chany_bottom_out(sb_8__1__3_chany_bottom_out), + .chanx_left_out(sb_8__1__3_chanx_left_out), + .ccff_tail(sb_8__1__3_ccff_tail) + ); + sb_8__1_ sb_8__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__5_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__4_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__53_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_60_ccff_tail), + .chany_top_out(sb_8__1__4_chany_top_out), + .chany_bottom_out(sb_8__1__4_chany_bottom_out), + .chanx_left_out(sb_8__1__4_chanx_left_out), + .ccff_tail(sb_8__1__4_ccff_tail) + ); + sb_8__1_ sb_8__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__6_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__5_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__54_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_54_ccff_tail), + .chany_top_out(sb_8__1__5_chany_top_out), + .chany_bottom_out(sb_8__1__5_chany_bottom_out), + .chanx_left_out(sb_8__1__5_chanx_left_out), + .ccff_tail(sb_8__1__5_ccff_tail) + ); + sb_8__1_ sb_8__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__7_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__6_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__55_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_62_ccff_tail), + .chany_top_out(sb_8__1__6_chany_top_out), + .chany_bottom_out(sb_8__1__6_chany_bottom_out), + .chanx_left_out(sb_8__1__6_chanx_left_out), + .ccff_tail(sb_8__1__6_ccff_tail) + ); + sb_8__8_ sb_8__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(cby_8__1__7_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__7_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_right_right_0_ccff_tail), + .chany_bottom_out(sb_8__8__0_chany_bottom_out), + .chanx_left_out(sb_8__8__0_chanx_left_out), + .ccff_tail(sb_8__8__0_ccff_tail) + ); + cbx_1__0_ cbx_1__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__0__0_chanx_right_out), + .chanx_right_in(sb_1__0__0_chanx_left_out), + .ccff_head(sb_1__0__0_ccff_tail), + .chanx_left_out(cbx_1__0__0_chanx_left_out), + .chanx_right_out(cbx_1__0__0_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__0_ccff_tail) + ); + cbx_1__0_ cbx_2__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__0_chanx_right_out), + .chanx_right_in(sb_1__0__1_chanx_left_out), + .ccff_head(sb_1__0__1_ccff_tail), + .chanx_left_out(cbx_1__0__1_chanx_left_out), + .chanx_right_out(cbx_1__0__1_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__1_ccff_tail) + ); + cbx_1__0_ cbx_3__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__1_chanx_right_out), + .chanx_right_in(sb_1__0__2_chanx_left_out), + .ccff_head(sb_1__0__2_ccff_tail), + .chanx_left_out(cbx_1__0__2_chanx_left_out), + .chanx_right_out(cbx_1__0__2_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__2_ccff_tail) + ); + cbx_1__0_ cbx_4__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__2_chanx_right_out), + .chanx_right_in(sb_1__0__3_chanx_left_out), + .ccff_head(sb_1__0__3_ccff_tail), + .chanx_left_out(cbx_1__0__3_chanx_left_out), + .chanx_right_out(cbx_1__0__3_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__3_ccff_tail) + ); + cbx_1__0_ cbx_5__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__3_chanx_right_out), + .chanx_right_in(sb_1__0__4_chanx_left_out), + .ccff_head(sb_1__0__4_ccff_tail), + .chanx_left_out(cbx_1__0__4_chanx_left_out), + .chanx_right_out(cbx_1__0__4_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__4_ccff_tail) + ); + cbx_1__0_ cbx_6__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__4_chanx_right_out), + .chanx_right_in(sb_1__0__5_chanx_left_out), + .ccff_head(sb_1__0__5_ccff_tail), + .chanx_left_out(cbx_1__0__5_chanx_left_out), + .chanx_right_out(cbx_1__0__5_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__5_ccff_tail) + ); + cbx_1__0_ cbx_7__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__5_chanx_right_out), + .chanx_right_in(sb_1__0__6_chanx_left_out), + .ccff_head(sb_1__0__6_ccff_tail), + .chanx_left_out(cbx_1__0__6_chanx_left_out), + .chanx_right_out(cbx_1__0__6_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__6_ccff_tail) + ); + cbx_1__0_ cbx_8__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__6_chanx_right_out), + .chanx_right_in(sb_8__0__0_chanx_left_out), + .ccff_head(sb_8__0__0_ccff_tail), + .chanx_left_out(cbx_1__0__7_chanx_left_out), + .chanx_right_out(cbx_1__0__7_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__7_ccff_tail) + ); + cbx_1__1_ cbx_1__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__0_chanx_right_out), + .chanx_right_in(sb_1__1__0_chanx_left_out), + .ccff_head(sb_1__1__0_ccff_tail), + .chanx_left_out(cbx_1__1__0_chanx_left_out), + .chanx_right_out(cbx_1__1__0_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__0_ccff_tail) + ); + cbx_1__1_ cbx_1__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__1_chanx_right_out), + .chanx_right_in(sb_1__1__1_chanx_left_out), + .ccff_head(sb_1__1__1_ccff_tail), + .chanx_left_out(cbx_1__1__1_chanx_left_out), + .chanx_right_out(cbx_1__1__1_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__1_ccff_tail) + ); + cbx_1__1_ cbx_1__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__2_chanx_right_out), + .chanx_right_in(sb_1__1__2_chanx_left_out), + .ccff_head(sb_1__1__2_ccff_tail), + .chanx_left_out(cbx_1__1__2_chanx_left_out), + .chanx_right_out(cbx_1__1__2_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__2_ccff_tail) + ); + cbx_1__1_ cbx_1__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__3_chanx_right_out), + .chanx_right_in(sb_1__1__3_chanx_left_out), + .ccff_head(sb_1__1__3_ccff_tail), + .chanx_left_out(cbx_1__1__3_chanx_left_out), + .chanx_right_out(cbx_1__1__3_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__3_ccff_tail) + ); + cbx_1__1_ cbx_1__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__4_chanx_right_out), + .chanx_right_in(sb_1__1__4_chanx_left_out), + .ccff_head(sb_1__1__4_ccff_tail), + .chanx_left_out(cbx_1__1__4_chanx_left_out), + .chanx_right_out(cbx_1__1__4_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__4_ccff_tail) + ); + cbx_1__1_ cbx_1__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__5_chanx_right_out), + .chanx_right_in(sb_1__1__5_chanx_left_out), + .ccff_head(sb_1__1__5_ccff_tail), + .chanx_left_out(cbx_1__1__5_chanx_left_out), + .chanx_right_out(cbx_1__1__5_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__5_ccff_tail) + ); + cbx_1__1_ cbx_1__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__6_chanx_right_out), + .chanx_right_in(sb_1__1__6_chanx_left_out), + .ccff_head(sb_1__1__6_ccff_tail), + .chanx_left_out(cbx_1__1__6_chanx_left_out), + .chanx_right_out(cbx_1__1__6_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__6_ccff_tail) + ); + cbx_1__1_ cbx_2__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__0_chanx_right_out), + .chanx_right_in(sb_1__1__7_chanx_left_out), + .ccff_head(sb_1__1__7_ccff_tail), + .chanx_left_out(cbx_1__1__7_chanx_left_out), + .chanx_right_out(cbx_1__1__7_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__7_ccff_tail) + ); + cbx_1__1_ cbx_2__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__1_chanx_right_out), + .chanx_right_in(sb_1__1__8_chanx_left_out), + .ccff_head(sb_1__1__8_ccff_tail), + .chanx_left_out(cbx_1__1__8_chanx_left_out), + .chanx_right_out(cbx_1__1__8_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__8_ccff_tail) + ); + cbx_1__1_ cbx_2__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__2_chanx_right_out), + .chanx_right_in(sb_1__1__9_chanx_left_out), + .ccff_head(sb_1__1__9_ccff_tail), + .chanx_left_out(cbx_1__1__9_chanx_left_out), + .chanx_right_out(cbx_1__1__9_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__9_ccff_tail) + ); + cbx_1__1_ cbx_2__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__3_chanx_right_out), + .chanx_right_in(sb_1__1__10_chanx_left_out), + .ccff_head(sb_1__1__10_ccff_tail), + .chanx_left_out(cbx_1__1__10_chanx_left_out), + .chanx_right_out(cbx_1__1__10_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__10_ccff_tail) + ); + cbx_1__1_ cbx_2__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__4_chanx_right_out), + .chanx_right_in(sb_1__1__11_chanx_left_out), + .ccff_head(sb_1__1__11_ccff_tail), + .chanx_left_out(cbx_1__1__11_chanx_left_out), + .chanx_right_out(cbx_1__1__11_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__11_ccff_tail) + ); + cbx_1__1_ cbx_2__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__5_chanx_right_out), + .chanx_right_in(sb_1__1__12_chanx_left_out), + .ccff_head(sb_1__1__12_ccff_tail), + .chanx_left_out(cbx_1__1__12_chanx_left_out), + .chanx_right_out(cbx_1__1__12_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__12_ccff_tail) + ); + cbx_1__1_ cbx_2__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__6_chanx_right_out), + .chanx_right_in(sb_1__1__13_chanx_left_out), + .ccff_head(sb_1__1__13_ccff_tail), + .chanx_left_out(cbx_1__1__13_chanx_left_out), + .chanx_right_out(cbx_1__1__13_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__13_ccff_tail) + ); + cbx_1__1_ cbx_3__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__7_chanx_right_out), + .chanx_right_in(sb_1__1__14_chanx_left_out), + .ccff_head(sb_1__1__14_ccff_tail), + .chanx_left_out(cbx_1__1__14_chanx_left_out), + .chanx_right_out(cbx_1__1__14_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__14_ccff_tail) + ); + cbx_1__1_ cbx_3__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__8_chanx_right_out), + .chanx_right_in(sb_1__1__15_chanx_left_out), + .ccff_head(sb_1__1__15_ccff_tail), + .chanx_left_out(cbx_1__1__15_chanx_left_out), + .chanx_right_out(cbx_1__1__15_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__15_ccff_tail) + ); + cbx_1__1_ cbx_3__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__9_chanx_right_out), + .chanx_right_in(sb_1__1__16_chanx_left_out), + .ccff_head(sb_1__1__16_ccff_tail), + .chanx_left_out(cbx_1__1__16_chanx_left_out), + .chanx_right_out(cbx_1__1__16_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__16_ccff_tail) + ); + cbx_1__1_ cbx_3__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__10_chanx_right_out), + .chanx_right_in(sb_1__1__17_chanx_left_out), + .ccff_head(sb_1__1__17_ccff_tail), + .chanx_left_out(cbx_1__1__17_chanx_left_out), + .chanx_right_out(cbx_1__1__17_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__17_ccff_tail) + ); + cbx_1__1_ cbx_3__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__11_chanx_right_out), + .chanx_right_in(sb_1__1__18_chanx_left_out), + .ccff_head(sb_1__1__18_ccff_tail), + .chanx_left_out(cbx_1__1__18_chanx_left_out), + .chanx_right_out(cbx_1__1__18_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__18_ccff_tail) + ); + cbx_1__1_ cbx_3__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__12_chanx_right_out), + .chanx_right_in(sb_1__1__19_chanx_left_out), + .ccff_head(sb_1__1__19_ccff_tail), + .chanx_left_out(cbx_1__1__19_chanx_left_out), + .chanx_right_out(cbx_1__1__19_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__19_ccff_tail) + ); + cbx_1__1_ cbx_3__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__13_chanx_right_out), + .chanx_right_in(sb_1__1__20_chanx_left_out), + .ccff_head(sb_1__1__20_ccff_tail), + .chanx_left_out(cbx_1__1__20_chanx_left_out), + .chanx_right_out(cbx_1__1__20_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__20_ccff_tail) + ); + cbx_1__1_ cbx_4__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__14_chanx_right_out), + .chanx_right_in(sb_1__1__21_chanx_left_out), + .ccff_head(sb_1__1__21_ccff_tail), + .chanx_left_out(cbx_1__1__21_chanx_left_out), + .chanx_right_out(cbx_1__1__21_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__21_ccff_tail) + ); + cbx_1__1_ cbx_4__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__15_chanx_right_out), + .chanx_right_in(sb_1__1__22_chanx_left_out), + .ccff_head(sb_1__1__22_ccff_tail), + .chanx_left_out(cbx_1__1__22_chanx_left_out), + .chanx_right_out(cbx_1__1__22_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__22_ccff_tail) + ); + cbx_1__1_ cbx_4__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__16_chanx_right_out), + .chanx_right_in(sb_1__1__23_chanx_left_out), + .ccff_head(sb_1__1__23_ccff_tail), + .chanx_left_out(cbx_1__1__23_chanx_left_out), + .chanx_right_out(cbx_1__1__23_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__23_ccff_tail) + ); + cbx_1__1_ cbx_4__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__17_chanx_right_out), + .chanx_right_in(sb_1__1__24_chanx_left_out), + .ccff_head(sb_1__1__24_ccff_tail), + .chanx_left_out(cbx_1__1__24_chanx_left_out), + .chanx_right_out(cbx_1__1__24_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__24_ccff_tail) + ); + cbx_1__1_ cbx_4__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__18_chanx_right_out), + .chanx_right_in(sb_1__1__25_chanx_left_out), + .ccff_head(sb_1__1__25_ccff_tail), + .chanx_left_out(cbx_1__1__25_chanx_left_out), + .chanx_right_out(cbx_1__1__25_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__25_ccff_tail) + ); + cbx_1__1_ cbx_4__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__19_chanx_right_out), + .chanx_right_in(sb_1__1__26_chanx_left_out), + .ccff_head(sb_1__1__26_ccff_tail), + .chanx_left_out(cbx_1__1__26_chanx_left_out), + .chanx_right_out(cbx_1__1__26_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__26_ccff_tail) + ); + cbx_1__1_ cbx_4__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__20_chanx_right_out), + .chanx_right_in(sb_1__1__27_chanx_left_out), + .ccff_head(sb_1__1__27_ccff_tail), + .chanx_left_out(cbx_1__1__27_chanx_left_out), + .chanx_right_out(cbx_1__1__27_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__27_ccff_tail) + ); + cbx_1__1_ cbx_5__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__21_chanx_right_out), + .chanx_right_in(sb_1__1__28_chanx_left_out), + .ccff_head(sb_1__1__28_ccff_tail), + .chanx_left_out(cbx_1__1__28_chanx_left_out), + .chanx_right_out(cbx_1__1__28_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__28_ccff_tail) + ); + cbx_1__1_ cbx_5__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__22_chanx_right_out), + .chanx_right_in(sb_1__1__29_chanx_left_out), + .ccff_head(sb_1__1__29_ccff_tail), + .chanx_left_out(cbx_1__1__29_chanx_left_out), + .chanx_right_out(cbx_1__1__29_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__29_ccff_tail) + ); + cbx_1__1_ cbx_5__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__23_chanx_right_out), + .chanx_right_in(sb_1__1__30_chanx_left_out), + .ccff_head(sb_1__1__30_ccff_tail), + .chanx_left_out(cbx_1__1__30_chanx_left_out), + .chanx_right_out(cbx_1__1__30_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__30_ccff_tail) + ); + cbx_1__1_ cbx_5__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__24_chanx_right_out), + .chanx_right_in(sb_1__1__31_chanx_left_out), + .ccff_head(sb_1__1__31_ccff_tail), + .chanx_left_out(cbx_1__1__31_chanx_left_out), + .chanx_right_out(cbx_1__1__31_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__31_ccff_tail) + ); + cbx_1__1_ cbx_5__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__25_chanx_right_out), + .chanx_right_in(sb_1__1__32_chanx_left_out), + .ccff_head(sb_1__1__32_ccff_tail), + .chanx_left_out(cbx_1__1__32_chanx_left_out), + .chanx_right_out(cbx_1__1__32_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__32_ccff_tail) + ); + cbx_1__1_ cbx_5__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__26_chanx_right_out), + .chanx_right_in(sb_1__1__33_chanx_left_out), + .ccff_head(sb_1__1__33_ccff_tail), + .chanx_left_out(cbx_1__1__33_chanx_left_out), + .chanx_right_out(cbx_1__1__33_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__33_ccff_tail) + ); + cbx_1__1_ cbx_5__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__27_chanx_right_out), + .chanx_right_in(sb_1__1__34_chanx_left_out), + .ccff_head(sb_1__1__34_ccff_tail), + .chanx_left_out(cbx_1__1__34_chanx_left_out), + .chanx_right_out(cbx_1__1__34_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__34_ccff_tail) + ); + cbx_1__1_ cbx_6__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__28_chanx_right_out), + .chanx_right_in(sb_1__1__35_chanx_left_out), + .ccff_head(sb_1__1__35_ccff_tail), + .chanx_left_out(cbx_1__1__35_chanx_left_out), + .chanx_right_out(cbx_1__1__35_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__35_ccff_tail) + ); + cbx_1__1_ cbx_6__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__29_chanx_right_out), + .chanx_right_in(sb_1__1__36_chanx_left_out), + .ccff_head(sb_1__1__36_ccff_tail), + .chanx_left_out(cbx_1__1__36_chanx_left_out), + .chanx_right_out(cbx_1__1__36_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__36_ccff_tail) + ); + cbx_1__1_ cbx_6__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__30_chanx_right_out), + .chanx_right_in(sb_1__1__37_chanx_left_out), + .ccff_head(sb_1__1__37_ccff_tail), + .chanx_left_out(cbx_1__1__37_chanx_left_out), + .chanx_right_out(cbx_1__1__37_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__37_ccff_tail) + ); + cbx_1__1_ cbx_6__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__31_chanx_right_out), + .chanx_right_in(sb_1__1__38_chanx_left_out), + .ccff_head(sb_1__1__38_ccff_tail), + .chanx_left_out(cbx_1__1__38_chanx_left_out), + .chanx_right_out(cbx_1__1__38_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__38_ccff_tail) + ); + cbx_1__1_ cbx_6__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__32_chanx_right_out), + .chanx_right_in(sb_1__1__39_chanx_left_out), + .ccff_head(sb_1__1__39_ccff_tail), + .chanx_left_out(cbx_1__1__39_chanx_left_out), + .chanx_right_out(cbx_1__1__39_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__39_ccff_tail) + ); + cbx_1__1_ cbx_6__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__33_chanx_right_out), + .chanx_right_in(sb_1__1__40_chanx_left_out), + .ccff_head(sb_1__1__40_ccff_tail), + .chanx_left_out(cbx_1__1__40_chanx_left_out), + .chanx_right_out(cbx_1__1__40_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__40_ccff_tail) + ); + cbx_1__1_ cbx_6__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__34_chanx_right_out), + .chanx_right_in(sb_1__1__41_chanx_left_out), + .ccff_head(sb_1__1__41_ccff_tail), + .chanx_left_out(cbx_1__1__41_chanx_left_out), + .chanx_right_out(cbx_1__1__41_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__41_ccff_tail) + ); + cbx_1__1_ cbx_7__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__35_chanx_right_out), + .chanx_right_in(sb_1__1__42_chanx_left_out), + .ccff_head(sb_1__1__42_ccff_tail), + .chanx_left_out(cbx_1__1__42_chanx_left_out), + .chanx_right_out(cbx_1__1__42_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__42_ccff_tail) + ); + cbx_1__1_ cbx_7__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__36_chanx_right_out), + .chanx_right_in(sb_1__1__43_chanx_left_out), + .ccff_head(sb_1__1__43_ccff_tail), + .chanx_left_out(cbx_1__1__43_chanx_left_out), + .chanx_right_out(cbx_1__1__43_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__43_ccff_tail) + ); + cbx_1__1_ cbx_7__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__37_chanx_right_out), + .chanx_right_in(sb_1__1__44_chanx_left_out), + .ccff_head(sb_1__1__44_ccff_tail), + .chanx_left_out(cbx_1__1__44_chanx_left_out), + .chanx_right_out(cbx_1__1__44_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__44_ccff_tail) + ); + cbx_1__1_ cbx_7__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__38_chanx_right_out), + .chanx_right_in(sb_1__1__45_chanx_left_out), + .ccff_head(sb_1__1__45_ccff_tail), + .chanx_left_out(cbx_1__1__45_chanx_left_out), + .chanx_right_out(cbx_1__1__45_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__45_ccff_tail) + ); + cbx_1__1_ cbx_7__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__39_chanx_right_out), + .chanx_right_in(sb_1__1__46_chanx_left_out), + .ccff_head(sb_1__1__46_ccff_tail), + .chanx_left_out(cbx_1__1__46_chanx_left_out), + .chanx_right_out(cbx_1__1__46_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__46_ccff_tail) + ); + cbx_1__1_ cbx_7__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__40_chanx_right_out), + .chanx_right_in(sb_1__1__47_chanx_left_out), + .ccff_head(sb_1__1__47_ccff_tail), + .chanx_left_out(cbx_1__1__47_chanx_left_out), + .chanx_right_out(cbx_1__1__47_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__47_ccff_tail) + ); + cbx_1__1_ cbx_7__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__41_chanx_right_out), + .chanx_right_in(sb_1__1__48_chanx_left_out), + .ccff_head(sb_1__1__48_ccff_tail), + .chanx_left_out(cbx_1__1__48_chanx_left_out), + .chanx_right_out(cbx_1__1__48_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__48_ccff_tail) + ); + cbx_1__1_ cbx_8__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__42_chanx_right_out), + .chanx_right_in(sb_8__1__0_chanx_left_out), + .ccff_head(sb_8__1__0_ccff_tail), + .chanx_left_out(cbx_1__1__49_chanx_left_out), + .chanx_right_out(cbx_1__1__49_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__49_ccff_tail) + ); + cbx_1__1_ cbx_8__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__43_chanx_right_out), + .chanx_right_in(sb_8__1__1_chanx_left_out), + .ccff_head(sb_8__1__1_ccff_tail), + .chanx_left_out(cbx_1__1__50_chanx_left_out), + .chanx_right_out(cbx_1__1__50_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__50_ccff_tail) + ); + cbx_1__1_ cbx_8__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__44_chanx_right_out), + .chanx_right_in(sb_8__1__2_chanx_left_out), + .ccff_head(sb_8__1__2_ccff_tail), + .chanx_left_out(cbx_1__1__51_chanx_left_out), + .chanx_right_out(cbx_1__1__51_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__51_ccff_tail) + ); + cbx_1__1_ cbx_8__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__45_chanx_right_out), + .chanx_right_in(sb_8__1__3_chanx_left_out), + .ccff_head(sb_8__1__3_ccff_tail), + .chanx_left_out(cbx_1__1__52_chanx_left_out), + .chanx_right_out(cbx_1__1__52_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__52_ccff_tail) + ); + cbx_1__1_ cbx_8__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__46_chanx_right_out), + .chanx_right_in(sb_8__1__4_chanx_left_out), + .ccff_head(sb_8__1__4_ccff_tail), + .chanx_left_out(cbx_1__1__53_chanx_left_out), + .chanx_right_out(cbx_1__1__53_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__53_ccff_tail) + ); + cbx_1__1_ cbx_8__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__47_chanx_right_out), + .chanx_right_in(sb_8__1__5_chanx_left_out), + .ccff_head(sb_8__1__5_ccff_tail), + .chanx_left_out(cbx_1__1__54_chanx_left_out), + .chanx_right_out(cbx_1__1__54_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__54_ccff_tail) + ); + cbx_1__1_ cbx_8__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__48_chanx_right_out), + .chanx_right_in(sb_8__1__6_chanx_left_out), + .ccff_head(sb_8__1__6_ccff_tail), + .chanx_left_out(cbx_1__1__55_chanx_left_out), + .chanx_right_out(cbx_1__1__55_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__55_ccff_tail) + ); + cbx_1__8_ cbx_1__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__8__0_chanx_right_out), + .chanx_right_in(sb_1__8__0_chanx_left_out), + .ccff_head(sb_1__8__0_ccff_tail), + .chanx_left_out(cbx_1__8__0_chanx_left_out), + .chanx_right_out(cbx_1__8__0_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__0_ccff_tail) + ); + cbx_1__8_ cbx_2__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__0_chanx_right_out), + .chanx_right_in(sb_1__8__1_chanx_left_out), + .ccff_head(sb_1__8__1_ccff_tail), + .chanx_left_out(cbx_1__8__1_chanx_left_out), + .chanx_right_out(cbx_1__8__1_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__1_ccff_tail) + ); + cbx_1__8_ cbx_3__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__1_chanx_right_out), + .chanx_right_in(sb_1__8__2_chanx_left_out), + .ccff_head(sb_1__8__2_ccff_tail), + .chanx_left_out(cbx_1__8__2_chanx_left_out), + .chanx_right_out(cbx_1__8__2_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__2_ccff_tail) + ); + cbx_1__8_ cbx_4__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__2_chanx_right_out), + .chanx_right_in(sb_1__8__3_chanx_left_out), + .ccff_head(sb_1__8__3_ccff_tail), + .chanx_left_out(cbx_1__8__3_chanx_left_out), + .chanx_right_out(cbx_1__8__3_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__3_ccff_tail) + ); + cbx_1__8_ cbx_5__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__3_chanx_right_out), + .chanx_right_in(sb_1__8__4_chanx_left_out), + .ccff_head(sb_1__8__4_ccff_tail), + .chanx_left_out(cbx_1__8__4_chanx_left_out), + .chanx_right_out(cbx_1__8__4_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__4_ccff_tail) + ); + cbx_1__8_ cbx_6__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__4_chanx_right_out), + .chanx_right_in(sb_1__8__5_chanx_left_out), + .ccff_head(sb_1__8__5_ccff_tail), + .chanx_left_out(cbx_1__8__5_chanx_left_out), + .chanx_right_out(cbx_1__8__5_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__5_ccff_tail) + ); + cbx_1__8_ cbx_7__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__5_chanx_right_out), + .chanx_right_in(sb_1__8__6_chanx_left_out), + .ccff_head(sb_1__8__6_ccff_tail), + .chanx_left_out(cbx_1__8__6_chanx_left_out), + .chanx_right_out(cbx_1__8__6_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__6_ccff_tail) + ); + cbx_1__8_ cbx_8__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__6_chanx_right_out), + .chanx_right_in(sb_8__8__0_chanx_left_out), + .ccff_head(sb_8__8__0_ccff_tail), + .chanx_left_out(cbx_1__8__7_chanx_left_out), + .chanx_right_out(cbx_1__8__7_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__7_ccff_tail) + ); + cby_0__1_ cby_0__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__0__0_chany_top_out), + .chany_top_in(sb_0__1__0_chany_bottom_out), + .ccff_head(sb_0__0__0_ccff_tail), + .chany_bottom_out(cby_0__1__0_chany_bottom_out), + .chany_top_out(cby_0__1__0_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__0_ccff_tail) + ); + cby_0__1_ cby_0__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__0_chany_top_out), + .chany_top_in(sb_0__1__1_chany_bottom_out), + .ccff_head(sb_0__1__0_ccff_tail), + .chany_bottom_out(cby_0__1__1_chany_bottom_out), + .chany_top_out(cby_0__1__1_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__1_ccff_tail) + ); + cby_0__1_ cby_0__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__1_chany_top_out), + .chany_top_in(sb_0__1__2_chany_bottom_out), + .ccff_head(sb_0__1__1_ccff_tail), + .chany_bottom_out(cby_0__1__2_chany_bottom_out), + .chany_top_out(cby_0__1__2_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__2_ccff_tail) + ); + cby_0__1_ cby_0__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__2_chany_top_out), + .chany_top_in(sb_0__1__3_chany_bottom_out), + .ccff_head(sb_0__1__2_ccff_tail), + .chany_bottom_out(cby_0__1__3_chany_bottom_out), + .chany_top_out(cby_0__1__3_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__3_ccff_tail) + ); + cby_0__1_ cby_0__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__3_chany_top_out), + .chany_top_in(sb_0__1__4_chany_bottom_out), + .ccff_head(sb_0__1__3_ccff_tail), + .chany_bottom_out(cby_0__1__4_chany_bottom_out), + .chany_top_out(cby_0__1__4_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__4_ccff_tail) + ); + cby_0__1_ cby_0__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__4_chany_top_out), + .chany_top_in(sb_0__1__5_chany_bottom_out), + .ccff_head(sb_0__1__4_ccff_tail), + .chany_bottom_out(cby_0__1__5_chany_bottom_out), + .chany_top_out(cby_0__1__5_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__5_ccff_tail) + ); + cby_0__1_ cby_0__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__5_chany_top_out), + .chany_top_in(sb_0__1__6_chany_bottom_out), + .ccff_head(sb_0__1__5_ccff_tail), + .chany_bottom_out(cby_0__1__6_chany_bottom_out), + .chany_top_out(cby_0__1__6_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__6_ccff_tail) + ); + cby_0__1_ cby_0__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__6_chany_top_out), + .chany_top_in(sb_0__8__0_chany_bottom_out), + .ccff_head(sb_0__1__6_ccff_tail), + .chany_bottom_out(cby_0__1__7_chany_bottom_out), + .chany_top_out(cby_0__1__7_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__7_ccff_tail) + ); + cby_1__1_ cby_1__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__0_chany_top_out), + .chany_top_in(sb_1__1__0_chany_bottom_out), + .ccff_head(cbx_1__0__0_ccff_tail), + .chany_bottom_out(cby_1__1__0_chany_bottom_out), + .chany_top_out(cby_1__1__0_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__0_ccff_tail) + ); + cby_1__1_ cby_1__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__0_chany_top_out), + .chany_top_in(sb_1__1__1_chany_bottom_out), + .ccff_head(cbx_1__1__0_ccff_tail), + .chany_bottom_out(cby_1__1__1_chany_bottom_out), + .chany_top_out(cby_1__1__1_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__1_ccff_tail) + ); + cby_1__1_ cby_1__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__1_chany_top_out), + .chany_top_in(sb_1__1__2_chany_bottom_out), + .ccff_head(cbx_1__1__1_ccff_tail), + .chany_bottom_out(cby_1__1__2_chany_bottom_out), + .chany_top_out(cby_1__1__2_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__2_ccff_tail) + ); + cby_1__1_ cby_1__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__2_chany_top_out), + .chany_top_in(sb_1__1__3_chany_bottom_out), + .ccff_head(cbx_1__1__2_ccff_tail), + .chany_bottom_out(cby_1__1__3_chany_bottom_out), + .chany_top_out(cby_1__1__3_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__3_ccff_tail) + ); + cby_1__1_ cby_1__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__3_chany_top_out), + .chany_top_in(sb_1__1__4_chany_bottom_out), + .ccff_head(cbx_1__1__3_ccff_tail), + .chany_bottom_out(cby_1__1__4_chany_bottom_out), + .chany_top_out(cby_1__1__4_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__4_ccff_tail) + ); + cby_1__1_ cby_1__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__4_chany_top_out), + .chany_top_in(sb_1__1__5_chany_bottom_out), + .ccff_head(cbx_1__1__4_ccff_tail), + .chany_bottom_out(cby_1__1__5_chany_bottom_out), + .chany_top_out(cby_1__1__5_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__5_ccff_tail) + ); + cby_1__1_ cby_1__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__5_chany_top_out), + .chany_top_in(sb_1__1__6_chany_bottom_out), + .ccff_head(cbx_1__1__5_ccff_tail), + .chany_bottom_out(cby_1__1__6_chany_bottom_out), + .chany_top_out(cby_1__1__6_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__6_ccff_tail) + ); + cby_1__1_ cby_1__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__6_chany_top_out), + .chany_top_in(sb_1__8__0_chany_bottom_out), + .ccff_head(cbx_1__1__6_ccff_tail), + .chany_bottom_out(cby_1__1__7_chany_bottom_out), + .chany_top_out(cby_1__1__7_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__7_ccff_tail) + ); + cby_1__1_ cby_2__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__1_chany_top_out), + .chany_top_in(sb_1__1__7_chany_bottom_out), + .ccff_head(cbx_1__0__1_ccff_tail), + .chany_bottom_out(cby_1__1__8_chany_bottom_out), + .chany_top_out(cby_1__1__8_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__8_ccff_tail) + ); + cby_1__1_ cby_2__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__7_chany_top_out), + .chany_top_in(sb_1__1__8_chany_bottom_out), + .ccff_head(cbx_1__1__7_ccff_tail), + .chany_bottom_out(cby_1__1__9_chany_bottom_out), + .chany_top_out(cby_1__1__9_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__9_ccff_tail) + ); + cby_1__1_ cby_2__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__8_chany_top_out), + .chany_top_in(sb_1__1__9_chany_bottom_out), + .ccff_head(cbx_1__1__8_ccff_tail), + .chany_bottom_out(cby_1__1__10_chany_bottom_out), + .chany_top_out(cby_1__1__10_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__10_ccff_tail) + ); + cby_1__1_ cby_2__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__9_chany_top_out), + .chany_top_in(sb_1__1__10_chany_bottom_out), + .ccff_head(cbx_1__1__9_ccff_tail), + .chany_bottom_out(cby_1__1__11_chany_bottom_out), + .chany_top_out(cby_1__1__11_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__11_ccff_tail) + ); + cby_1__1_ cby_2__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__10_chany_top_out), + .chany_top_in(sb_1__1__11_chany_bottom_out), + .ccff_head(cbx_1__1__10_ccff_tail), + .chany_bottom_out(cby_1__1__12_chany_bottom_out), + .chany_top_out(cby_1__1__12_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__12_ccff_tail) + ); + cby_1__1_ cby_2__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__11_chany_top_out), + .chany_top_in(sb_1__1__12_chany_bottom_out), + .ccff_head(cbx_1__1__11_ccff_tail), + .chany_bottom_out(cby_1__1__13_chany_bottom_out), + .chany_top_out(cby_1__1__13_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__13_ccff_tail) + ); + cby_1__1_ cby_2__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__12_chany_top_out), + .chany_top_in(sb_1__1__13_chany_bottom_out), + .ccff_head(cbx_1__1__12_ccff_tail), + .chany_bottom_out(cby_1__1__14_chany_bottom_out), + .chany_top_out(cby_1__1__14_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__14_ccff_tail) + ); + cby_1__1_ cby_2__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__13_chany_top_out), + .chany_top_in(sb_1__8__1_chany_bottom_out), + .ccff_head(cbx_1__1__13_ccff_tail), + .chany_bottom_out(cby_1__1__15_chany_bottom_out), + .chany_top_out(cby_1__1__15_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__15_ccff_tail) + ); + cby_1__1_ cby_3__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__2_chany_top_out), + .chany_top_in(sb_1__1__14_chany_bottom_out), + .ccff_head(cbx_1__0__2_ccff_tail), + .chany_bottom_out(cby_1__1__16_chany_bottom_out), + .chany_top_out(cby_1__1__16_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__16_ccff_tail) + ); + cby_1__1_ cby_3__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__14_chany_top_out), + .chany_top_in(sb_1__1__15_chany_bottom_out), + .ccff_head(cbx_1__1__14_ccff_tail), + .chany_bottom_out(cby_1__1__17_chany_bottom_out), + .chany_top_out(cby_1__1__17_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__17_ccff_tail) + ); + cby_1__1_ cby_3__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__15_chany_top_out), + .chany_top_in(sb_1__1__16_chany_bottom_out), + .ccff_head(cbx_1__1__15_ccff_tail), + .chany_bottom_out(cby_1__1__18_chany_bottom_out), + .chany_top_out(cby_1__1__18_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__18_ccff_tail) + ); + cby_1__1_ cby_3__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__16_chany_top_out), + .chany_top_in(sb_1__1__17_chany_bottom_out), + .ccff_head(cbx_1__1__16_ccff_tail), + .chany_bottom_out(cby_1__1__19_chany_bottom_out), + .chany_top_out(cby_1__1__19_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__19_ccff_tail) + ); + cby_1__1_ cby_3__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__17_chany_top_out), + .chany_top_in(sb_1__1__18_chany_bottom_out), + .ccff_head(cbx_1__1__17_ccff_tail), + .chany_bottom_out(cby_1__1__20_chany_bottom_out), + .chany_top_out(cby_1__1__20_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__20_ccff_tail) + ); + cby_1__1_ cby_3__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__18_chany_top_out), + .chany_top_in(sb_1__1__19_chany_bottom_out), + .ccff_head(cbx_1__1__18_ccff_tail), + .chany_bottom_out(cby_1__1__21_chany_bottom_out), + .chany_top_out(cby_1__1__21_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__21_ccff_tail) + ); + cby_1__1_ cby_3__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__19_chany_top_out), + .chany_top_in(sb_1__1__20_chany_bottom_out), + .ccff_head(cbx_1__1__19_ccff_tail), + .chany_bottom_out(cby_1__1__22_chany_bottom_out), + .chany_top_out(cby_1__1__22_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__22_ccff_tail) + ); + cby_1__1_ cby_3__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__20_chany_top_out), + .chany_top_in(sb_1__8__2_chany_bottom_out), + .ccff_head(cbx_1__1__20_ccff_tail), + .chany_bottom_out(cby_1__1__23_chany_bottom_out), + .chany_top_out(cby_1__1__23_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__23_ccff_tail) + ); + cby_1__1_ cby_4__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__3_chany_top_out), + .chany_top_in(sb_1__1__21_chany_bottom_out), + .ccff_head(cbx_1__0__3_ccff_tail), + .chany_bottom_out(cby_1__1__24_chany_bottom_out), + .chany_top_out(cby_1__1__24_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__24_ccff_tail) + ); + cby_1__1_ cby_4__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__21_chany_top_out), + .chany_top_in(sb_1__1__22_chany_bottom_out), + .ccff_head(cbx_1__1__21_ccff_tail), + .chany_bottom_out(cby_1__1__25_chany_bottom_out), + .chany_top_out(cby_1__1__25_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__25_ccff_tail) + ); + cby_1__1_ cby_4__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__22_chany_top_out), + .chany_top_in(sb_1__1__23_chany_bottom_out), + .ccff_head(cbx_1__1__22_ccff_tail), + .chany_bottom_out(cby_1__1__26_chany_bottom_out), + .chany_top_out(cby_1__1__26_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__26_ccff_tail) + ); + cby_1__1_ cby_4__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__23_chany_top_out), + .chany_top_in(sb_1__1__24_chany_bottom_out), + .ccff_head(cbx_1__1__23_ccff_tail), + .chany_bottom_out(cby_1__1__27_chany_bottom_out), + .chany_top_out(cby_1__1__27_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__27_ccff_tail) + ); + cby_1__1_ cby_4__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__24_chany_top_out), + .chany_top_in(sb_1__1__25_chany_bottom_out), + .ccff_head(cbx_1__1__24_ccff_tail), + .chany_bottom_out(cby_1__1__28_chany_bottom_out), + .chany_top_out(cby_1__1__28_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__28_ccff_tail) + ); + cby_1__1_ cby_4__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__25_chany_top_out), + .chany_top_in(sb_1__1__26_chany_bottom_out), + .ccff_head(cbx_1__1__25_ccff_tail), + .chany_bottom_out(cby_1__1__29_chany_bottom_out), + .chany_top_out(cby_1__1__29_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__29_ccff_tail) + ); + cby_1__1_ cby_4__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__26_chany_top_out), + .chany_top_in(sb_1__1__27_chany_bottom_out), + .ccff_head(cbx_1__1__26_ccff_tail), + .chany_bottom_out(cby_1__1__30_chany_bottom_out), + .chany_top_out(cby_1__1__30_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__30_ccff_tail) + ); + cby_1__1_ cby_4__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__27_chany_top_out), + .chany_top_in(sb_1__8__3_chany_bottom_out), + .ccff_head(cbx_1__1__27_ccff_tail), + .chany_bottom_out(cby_1__1__31_chany_bottom_out), + .chany_top_out(cby_1__1__31_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__31_ccff_tail) + ); + cby_1__1_ cby_5__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__4_chany_top_out), + .chany_top_in(sb_1__1__28_chany_bottom_out), + .ccff_head(cbx_1__0__4_ccff_tail), + .chany_bottom_out(cby_1__1__32_chany_bottom_out), + .chany_top_out(cby_1__1__32_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__32_ccff_tail) + ); + cby_1__1_ cby_5__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__28_chany_top_out), + .chany_top_in(sb_1__1__29_chany_bottom_out), + .ccff_head(cbx_1__1__28_ccff_tail), + .chany_bottom_out(cby_1__1__33_chany_bottom_out), + .chany_top_out(cby_1__1__33_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__33_ccff_tail) + ); + cby_1__1_ cby_5__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__29_chany_top_out), + .chany_top_in(sb_1__1__30_chany_bottom_out), + .ccff_head(cbx_1__1__29_ccff_tail), + .chany_bottom_out(cby_1__1__34_chany_bottom_out), + .chany_top_out(cby_1__1__34_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__34_ccff_tail) + ); + cby_1__1_ cby_5__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__30_chany_top_out), + .chany_top_in(sb_1__1__31_chany_bottom_out), + .ccff_head(cbx_1__1__30_ccff_tail), + .chany_bottom_out(cby_1__1__35_chany_bottom_out), + .chany_top_out(cby_1__1__35_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__35_ccff_tail) + ); + cby_1__1_ cby_5__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__31_chany_top_out), + .chany_top_in(sb_1__1__32_chany_bottom_out), + .ccff_head(cbx_1__1__31_ccff_tail), + .chany_bottom_out(cby_1__1__36_chany_bottom_out), + .chany_top_out(cby_1__1__36_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__36_ccff_tail) + ); + cby_1__1_ cby_5__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__32_chany_top_out), + .chany_top_in(sb_1__1__33_chany_bottom_out), + .ccff_head(cbx_1__1__32_ccff_tail), + .chany_bottom_out(cby_1__1__37_chany_bottom_out), + .chany_top_out(cby_1__1__37_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__37_ccff_tail) + ); + cby_1__1_ cby_5__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__33_chany_top_out), + .chany_top_in(sb_1__1__34_chany_bottom_out), + .ccff_head(cbx_1__1__33_ccff_tail), + .chany_bottom_out(cby_1__1__38_chany_bottom_out), + .chany_top_out(cby_1__1__38_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__38_ccff_tail) + ); + cby_1__1_ cby_5__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__34_chany_top_out), + .chany_top_in(sb_1__8__4_chany_bottom_out), + .ccff_head(cbx_1__1__34_ccff_tail), + .chany_bottom_out(cby_1__1__39_chany_bottom_out), + .chany_top_out(cby_1__1__39_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__39_ccff_tail) + ); + cby_1__1_ cby_6__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__5_chany_top_out), + .chany_top_in(sb_1__1__35_chany_bottom_out), + .ccff_head(cbx_1__0__5_ccff_tail), + .chany_bottom_out(cby_1__1__40_chany_bottom_out), + .chany_top_out(cby_1__1__40_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__40_ccff_tail) + ); + cby_1__1_ cby_6__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__35_chany_top_out), + .chany_top_in(sb_1__1__36_chany_bottom_out), + .ccff_head(cbx_1__1__35_ccff_tail), + .chany_bottom_out(cby_1__1__41_chany_bottom_out), + .chany_top_out(cby_1__1__41_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__41_ccff_tail) + ); + cby_1__1_ cby_6__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__36_chany_top_out), + .chany_top_in(sb_1__1__37_chany_bottom_out), + .ccff_head(cbx_1__1__36_ccff_tail), + .chany_bottom_out(cby_1__1__42_chany_bottom_out), + .chany_top_out(cby_1__1__42_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__42_ccff_tail) + ); + cby_1__1_ cby_6__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__37_chany_top_out), + .chany_top_in(sb_1__1__38_chany_bottom_out), + .ccff_head(cbx_1__1__37_ccff_tail), + .chany_bottom_out(cby_1__1__43_chany_bottom_out), + .chany_top_out(cby_1__1__43_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__43_ccff_tail) + ); + cby_1__1_ cby_6__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__38_chany_top_out), + .chany_top_in(sb_1__1__39_chany_bottom_out), + .ccff_head(cbx_1__1__38_ccff_tail), + .chany_bottom_out(cby_1__1__44_chany_bottom_out), + .chany_top_out(cby_1__1__44_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__44_ccff_tail) + ); + cby_1__1_ cby_6__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__39_chany_top_out), + .chany_top_in(sb_1__1__40_chany_bottom_out), + .ccff_head(cbx_1__1__39_ccff_tail), + .chany_bottom_out(cby_1__1__45_chany_bottom_out), + .chany_top_out(cby_1__1__45_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__45_ccff_tail) + ); + cby_1__1_ cby_6__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__40_chany_top_out), + .chany_top_in(sb_1__1__41_chany_bottom_out), + .ccff_head(cbx_1__1__40_ccff_tail), + .chany_bottom_out(cby_1__1__46_chany_bottom_out), + .chany_top_out(cby_1__1__46_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__46_ccff_tail) + ); + cby_1__1_ cby_6__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__41_chany_top_out), + .chany_top_in(sb_1__8__5_chany_bottom_out), + .ccff_head(cbx_1__1__41_ccff_tail), + .chany_bottom_out(cby_1__1__47_chany_bottom_out), + .chany_top_out(cby_1__1__47_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__47_ccff_tail) + ); + cby_1__1_ cby_7__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__6_chany_top_out), + .chany_top_in(sb_1__1__42_chany_bottom_out), + .ccff_head(cbx_1__0__6_ccff_tail), + .chany_bottom_out(cby_1__1__48_chany_bottom_out), + .chany_top_out(cby_1__1__48_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__48_ccff_tail) + ); + cby_1__1_ cby_7__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__42_chany_top_out), + .chany_top_in(sb_1__1__43_chany_bottom_out), + .ccff_head(cbx_1__1__42_ccff_tail), + .chany_bottom_out(cby_1__1__49_chany_bottom_out), + .chany_top_out(cby_1__1__49_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__49_ccff_tail) + ); + cby_1__1_ cby_7__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__43_chany_top_out), + .chany_top_in(sb_1__1__44_chany_bottom_out), + .ccff_head(cbx_1__1__43_ccff_tail), + .chany_bottom_out(cby_1__1__50_chany_bottom_out), + .chany_top_out(cby_1__1__50_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__50_ccff_tail) + ); + cby_1__1_ cby_7__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__44_chany_top_out), + .chany_top_in(sb_1__1__45_chany_bottom_out), + .ccff_head(cbx_1__1__44_ccff_tail), + .chany_bottom_out(cby_1__1__51_chany_bottom_out), + .chany_top_out(cby_1__1__51_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__51_ccff_tail) + ); + cby_1__1_ cby_7__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__45_chany_top_out), + .chany_top_in(sb_1__1__46_chany_bottom_out), + .ccff_head(cbx_1__1__45_ccff_tail), + .chany_bottom_out(cby_1__1__52_chany_bottom_out), + .chany_top_out(cby_1__1__52_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__52_ccff_tail) + ); + cby_1__1_ cby_7__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__46_chany_top_out), + .chany_top_in(sb_1__1__47_chany_bottom_out), + .ccff_head(cbx_1__1__46_ccff_tail), + .chany_bottom_out(cby_1__1__53_chany_bottom_out), + .chany_top_out(cby_1__1__53_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__53_ccff_tail) + ); + cby_1__1_ cby_7__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__47_chany_top_out), + .chany_top_in(sb_1__1__48_chany_bottom_out), + .ccff_head(cbx_1__1__47_ccff_tail), + .chany_bottom_out(cby_1__1__54_chany_bottom_out), + .chany_top_out(cby_1__1__54_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__54_ccff_tail) + ); + cby_1__1_ cby_7__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__48_chany_top_out), + .chany_top_in(sb_1__8__6_chany_bottom_out), + .ccff_head(cbx_1__1__48_ccff_tail), + .chany_bottom_out(cby_1__1__55_chany_bottom_out), + .chany_top_out(cby_1__1__55_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__55_ccff_tail) + ); + cby_8__1_ cby_8__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__0__0_chany_top_out), + .chany_top_in(sb_8__1__0_chany_bottom_out), + .ccff_head(cbx_1__0__7_ccff_tail), + .chany_bottom_out(cby_8__1__0_chany_bottom_out), + .chany_top_out(cby_8__1__0_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__0_ccff_tail) + ); + cby_8__1_ cby_8__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__0_chany_top_out), + .chany_top_in(sb_8__1__1_chany_bottom_out), + .ccff_head(cbx_1__1__49_ccff_tail), + .chany_bottom_out(cby_8__1__1_chany_bottom_out), + .chany_top_out(cby_8__1__1_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__1_ccff_tail) + ); + cby_8__1_ cby_8__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__1_chany_top_out), + .chany_top_in(sb_8__1__2_chany_bottom_out), + .ccff_head(cbx_1__1__50_ccff_tail), + .chany_bottom_out(cby_8__1__2_chany_bottom_out), + .chany_top_out(cby_8__1__2_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__2_ccff_tail) + ); + cby_8__1_ cby_8__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__2_chany_top_out), + .chany_top_in(sb_8__1__3_chany_bottom_out), + .ccff_head(cbx_1__1__51_ccff_tail), + .chany_bottom_out(cby_8__1__3_chany_bottom_out), + .chany_top_out(cby_8__1__3_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__3_ccff_tail) + ); + cby_8__1_ cby_8__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__3_chany_top_out), + .chany_top_in(sb_8__1__4_chany_bottom_out), + .ccff_head(cbx_1__1__52_ccff_tail), + .chany_bottom_out(cby_8__1__4_chany_bottom_out), + .chany_top_out(cby_8__1__4_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__4_ccff_tail) + ); + cby_8__1_ cby_8__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__4_chany_top_out), + .chany_top_in(sb_8__1__5_chany_bottom_out), + .ccff_head(cbx_1__1__53_ccff_tail), + .chany_bottom_out(cby_8__1__5_chany_bottom_out), + .chany_top_out(cby_8__1__5_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__5_ccff_tail) + ); + cby_8__1_ cby_8__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__5_chany_top_out), + .chany_top_in(sb_8__1__6_chany_bottom_out), + .ccff_head(cbx_1__1__54_ccff_tail), + .chany_bottom_out(cby_8__1__6_chany_bottom_out), + .chany_top_out(cby_8__1__6_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__6_ccff_tail) + ); + cby_8__1_ cby_8__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__6_chany_top_out), + .chany_top_in(sb_8__8__0_chany_bottom_out), + .ccff_head(cbx_1__1__55_ccff_tail), + .chany_bottom_out(cby_8__1__7_chany_bottom_out), + .chany_top_out(cby_8__1__7_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__7_ccff_tail) + ); + direct_interc direct_interc_0_ + ( + .in(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_0_out) + ); + direct_interc direct_interc_1_ + ( + .in(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_1_out) + ); + direct_interc direct_interc_2_ + ( + .in(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_2_out) + ); + direct_interc direct_interc_3_ + ( + .in(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_3_out) + ); + direct_interc direct_interc_4_ + ( + .in(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_4_out) + ); + direct_interc direct_interc_5_ + ( + .in(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_5_out) + ); + direct_interc direct_interc_6_ + ( + .in(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_6_out) + ); + direct_interc direct_interc_7_ + ( + .in(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_7_out) + ); + direct_interc direct_interc_8_ + ( + .in(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_8_out) + ); + direct_interc direct_interc_9_ + ( + .in(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_9_out) + ); + direct_interc direct_interc_10_ + ( + .in(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_10_out) + ); + direct_interc direct_interc_11_ + ( + .in(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_11_out) + ); + direct_interc direct_interc_12_ + ( + .in(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_12_out) + ); + direct_interc direct_interc_13_ + ( + .in(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_13_out) + ); + direct_interc direct_interc_14_ + ( + .in(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_14_out) + ); + direct_interc direct_interc_15_ + ( + .in(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_15_out) + ); + direct_interc direct_interc_16_ + ( + .in(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_16_out) + ); + direct_interc direct_interc_17_ + ( + .in(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_17_out) + ); + direct_interc direct_interc_18_ + ( + .in(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_18_out) + ); + direct_interc direct_interc_19_ + ( + .in(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_19_out) + ); + direct_interc direct_interc_20_ + ( + .in(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_20_out) + ); + direct_interc direct_interc_21_ + ( + .in(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_21_out) + ); + direct_interc direct_interc_22_ + ( + .in(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_22_out) + ); + direct_interc direct_interc_23_ + ( + .in(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_23_out) + ); + direct_interc direct_interc_24_ + ( + .in(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_24_out) + ); + direct_interc direct_interc_25_ + ( + .in(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_25_out) + ); + direct_interc direct_interc_26_ + ( + .in(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_26_out) + ); + direct_interc direct_interc_27_ + ( + .in(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_27_out) + ); + direct_interc direct_interc_28_ + ( + .in(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_28_out) + ); + direct_interc direct_interc_29_ + ( + .in(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_29_out) + ); + direct_interc direct_interc_30_ + ( + .in(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_30_out) + ); + direct_interc direct_interc_31_ + ( + .in(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_31_out) + ); + direct_interc direct_interc_32_ + ( + .in(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_32_out) + ); + direct_interc direct_interc_33_ + ( + .in(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_33_out) + ); + direct_interc direct_interc_34_ + ( + .in(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_34_out) + ); + direct_interc direct_interc_35_ + ( + .in(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_35_out) + ); + direct_interc direct_interc_36_ + ( + .in(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_36_out) + ); + direct_interc direct_interc_37_ + ( + .in(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_37_out) + ); + direct_interc direct_interc_38_ + ( + .in(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_38_out) + ); + direct_interc direct_interc_39_ + ( + .in(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_39_out) + ); + direct_interc direct_interc_40_ + ( + .in(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_40_out) + ); + direct_interc direct_interc_41_ + ( + .in(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_41_out) + ); + direct_interc direct_interc_42_ + ( + .in(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_42_out) + ); + direct_interc direct_interc_43_ + ( + .in(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_43_out) + ); + direct_interc direct_interc_44_ + ( + .in(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_44_out) + ); + direct_interc direct_interc_45_ + ( + .in(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_45_out) + ); + direct_interc direct_interc_46_ + ( + .in(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_46_out) + ); + direct_interc direct_interc_47_ + ( + .in(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_47_out) + ); + direct_interc direct_interc_48_ + ( + .in(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_48_out) + ); + direct_interc direct_interc_49_ + ( + .in(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_49_out) + ); + direct_interc direct_interc_50_ + ( + .in(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_50_out) + ); + direct_interc direct_interc_51_ + ( + .in(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_51_out) + ); + direct_interc direct_interc_52_ + ( + .in(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_52_out) + ); + direct_interc direct_interc_53_ + ( + .in(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_53_out) + ); + direct_interc direct_interc_54_ + ( + .in(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_54_out) + ); + direct_interc direct_interc_55_ + ( + .in(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_55_out) + ); + direct_interc direct_interc_56_ + ( + .in(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_56_out) + ); + direct_interc direct_interc_57_ + ( + .in(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_57_out) + ); + direct_interc direct_interc_58_ + ( + .in(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_58_out) + ); + direct_interc direct_interc_59_ + ( + .in(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_59_out) + ); + direct_interc direct_interc_60_ + ( + .in(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_60_out) + ); + direct_interc direct_interc_61_ + ( + .in(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_61_out) + ); + direct_interc direct_interc_62_ + ( + .in(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_62_out) + ); + direct_interc direct_interc_63_ + ( + .in(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_63_out) + ); + direct_interc direct_interc_64_ + ( + .in(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_64_out) + ); + direct_interc direct_interc_65_ + ( + .in(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_65_out) + ); + direct_interc direct_interc_66_ + ( + .in(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_66_out) + ); + direct_interc direct_interc_67_ + ( + .in(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_67_out) + ); + direct_interc direct_interc_68_ + ( + .in(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_68_out) + ); + direct_interc direct_interc_69_ + ( + .in(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_69_out) + ); + direct_interc direct_interc_70_ + ( + .in(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_70_out) + ); + direct_interc direct_interc_71_ + ( + .in(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_71_out) + ); + direct_interc direct_interc_72_ + ( + .in(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_72_out) + ); + direct_interc direct_interc_73_ + ( + .in(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_73_out) + ); + direct_interc direct_interc_74_ + ( + .in(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_74_out) + ); + direct_interc direct_interc_75_ + ( + .in(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_75_out) + ); + direct_interc direct_interc_76_ + ( + .in(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_76_out) + ); + direct_interc direct_interc_77_ + ( + .in(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_77_out) + ); + direct_interc direct_interc_78_ + ( + .in(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_78_out) + ); + direct_interc direct_interc_79_ + ( + .in(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_79_out) + ); + direct_interc direct_interc_80_ + ( + .in(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_80_out) + ); + direct_interc direct_interc_81_ + ( + .in(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_81_out) + ); + direct_interc direct_interc_82_ + ( + .in(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_82_out) + ); + direct_interc direct_interc_83_ + ( + .in(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_83_out) + ); + direct_interc direct_interc_84_ + ( + .in(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_84_out) + ); + direct_interc direct_interc_85_ + ( + .in(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_85_out) + ); + direct_interc direct_interc_86_ + ( + .in(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_86_out) + ); + direct_interc direct_interc_87_ + ( + .in(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_87_out) + ); + direct_interc direct_interc_88_ + ( + .in(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_88_out) + ); + direct_interc direct_interc_89_ + ( + .in(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_89_out) + ); + direct_interc direct_interc_90_ + ( + .in(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_90_out) + ); + direct_interc direct_interc_91_ + ( + .in(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_91_out) + ); + direct_interc direct_interc_92_ + ( + .in(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_92_out) + ); + direct_interc direct_interc_93_ + ( + .in(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_93_out) + ); + direct_interc direct_interc_94_ + ( + .in(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_94_out) + ); + direct_interc direct_interc_95_ + ( + .in(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_95_out) + ); + direct_interc direct_interc_96_ + ( + .in(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_96_out) + ); + direct_interc direct_interc_97_ + ( + .in(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_97_out) + ); + direct_interc direct_interc_98_ + ( + .in(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_98_out) + ); + direct_interc direct_interc_99_ + ( + .in(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_99_out) + ); + direct_interc direct_interc_100_ + ( + .in(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_100_out) + ); + direct_interc direct_interc_101_ + ( + .in(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_101_out) + ); + direct_interc direct_interc_102_ + ( + .in(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_102_out) + ); + direct_interc direct_interc_103_ + ( + .in(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_103_out) + ); + direct_interc direct_interc_104_ + ( + .in(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_104_out) + ); + direct_interc direct_interc_105_ + ( + .in(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_105_out) + ); + direct_interc direct_interc_106_ + ( + .in(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_106_out) + ); + direct_interc direct_interc_107_ + ( + .in(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_107_out) + ); + direct_interc direct_interc_108_ + ( + .in(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_108_out) + ); + direct_interc direct_interc_109_ + ( + .in(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_109_out) + ); + direct_interc direct_interc_110_ + ( + .in(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_110_out) + ); + direct_interc direct_interc_111_ + ( + .in(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_111_out) + ); + direct_interc direct_interc_112_ + ( + .in(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_112_out) + ); + direct_interc direct_interc_113_ + ( + .in(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_113_out) + ); + direct_interc direct_interc_114_ + ( + .in(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_114_out) + ); + direct_interc direct_interc_115_ + ( + .in(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_115_out) + ); + direct_interc direct_interc_116_ + ( + .in(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_116_out) + ); + direct_interc direct_interc_117_ + ( + .in(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_117_out) + ); + direct_interc direct_interc_118_ + ( + .in(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_118_out) + ); + direct_interc direct_interc_119_ + ( + .in(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_119_out) + ); + direct_interc direct_interc_120_ + ( + .in(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_120_out) + ); + direct_interc direct_interc_121_ + ( + .in(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_121_out) + ); + direct_interc direct_interc_122_ + ( + .in(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_122_out) + ); + direct_interc direct_interc_123_ + ( + .in(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_123_out) + ); + direct_interc direct_interc_124_ + ( + .in(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_124_out) + ); + direct_interc direct_interc_125_ + ( + .in(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_125_out) + ); + direct_interc direct_interc_126_ + ( + .in(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_126_out) + ); + direct_interc direct_interc_127_ + ( + .in(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_127_out) + ); + direct_interc direct_interc_128_ + ( + .in(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_128_out) + ); + direct_interc direct_interc_129_ + ( + .in(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_129_out) + ); + direct_interc direct_interc_130_ + ( + .in(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_130_out) + ); + direct_interc direct_interc_131_ + ( + .in(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_131_out) + ); + direct_interc direct_interc_132_ + ( + .in(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_132_out) + ); + direct_interc direct_interc_133_ + ( + .in(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_133_out) + ); + direct_interc direct_interc_134_ + ( + .in(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_134_out) + ); + direct_interc direct_interc_135_ + ( + .in(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_135_out) + ); + direct_interc direct_interc_136_ + ( + .in(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_136_out) + ); + direct_interc direct_interc_137_ + ( + .in(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_137_out) + ); + direct_interc direct_interc_138_ + ( + .in(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_138_out) + ); + direct_interc direct_interc_139_ + ( + .in(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_139_out) + ); + direct_interc direct_interc_140_ + ( + .in(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_140_out) + ); + direct_interc direct_interc_141_ + ( + .in(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_141_out) + ); + direct_interc direct_interc_142_ + ( + .in(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_142_out) + ); + direct_interc direct_interc_143_ + ( + .in(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_143_out) + ); + direct_interc direct_interc_144_ + ( + .in(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_144_out) + ); + direct_interc direct_interc_145_ + ( + .in(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_145_out) + ); + direct_interc direct_interc_146_ + ( + .in(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_146_out) + ); + direct_interc direct_interc_147_ + ( + .in(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_147_out) + ); + direct_interc direct_interc_148_ + ( + .in(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_148_out) + ); + direct_interc direct_interc_149_ + ( + .in(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_149_out) + ); + direct_interc direct_interc_150_ + ( + .in(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_150_out) + ); + direct_interc direct_interc_151_ + ( + .in(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_151_out) + ); + direct_interc direct_interc_152_ + ( + .in(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_152_out) + ); + direct_interc direct_interc_153_ + ( + .in(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_153_out) + ); + direct_interc direct_interc_154_ + ( + .in(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_154_out) + ); + direct_interc direct_interc_155_ + ( + .in(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_155_out) + ); + direct_interc direct_interc_156_ + ( + .in(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_156_out) + ); + direct_interc direct_interc_157_ + ( + .in(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_157_out) + ); + direct_interc direct_interc_158_ + ( + .in(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_158_out) + ); + direct_interc direct_interc_159_ + ( + .in(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_159_out) + ); + direct_interc direct_interc_160_ + ( + .in(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_160_out) + ); + direct_interc direct_interc_161_ + ( + .in(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_161_out) + ); + direct_interc direct_interc_162_ + ( + .in(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_162_out) + ); + direct_interc direct_interc_163_ + ( + .in(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_163_out) + ); + direct_interc direct_interc_164_ + ( + .in(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_164_out) + ); + direct_interc direct_interc_165_ + ( + .in(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_165_out) + ); + direct_interc direct_interc_166_ + ( + .in(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_166_out) + ); + direct_interc direct_interc_167_ + ( + .in(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_167_out) + ); + direct_interc direct_interc_168_ + ( + .in(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_168_out) + ); + direct_interc direct_interc_169_ + ( + .in(grid_clb_8_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_169_out) + ); + direct_interc direct_interc_170_ + ( + .in(grid_clb_16_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_170_out) + ); + direct_interc direct_interc_171_ + ( + .in(grid_clb_24_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_171_out) + ); + direct_interc direct_interc_172_ + ( + .in(grid_clb_32_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_172_out) + ); + direct_interc direct_interc_173_ + ( + .in(grid_clb_40_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_173_out) + ); + direct_interc direct_interc_174_ + ( + .in(grid_clb_48_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_174_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_clb.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_clb.v new file mode 100644 index 0000000..cde4367 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_clb.v @@ -0,0 +1,226 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module grid_clb +( + pReset, + prog_clk, + Test_en, + top_width_0_height_0_subtile_0__pin_I0_0_, + top_width_0_height_0_subtile_0__pin_I0_1_, + top_width_0_height_0_subtile_0__pin_I0i_0_, + top_width_0_height_0_subtile_0__pin_I0i_1_, + top_width_0_height_0_subtile_0__pin_I1_0_, + top_width_0_height_0_subtile_0__pin_I1_1_, + top_width_0_height_0_subtile_0__pin_I1i_0_, + top_width_0_height_0_subtile_0__pin_I1i_1_, + top_width_0_height_0_subtile_0__pin_I2_0_, + top_width_0_height_0_subtile_0__pin_I2_1_, + top_width_0_height_0_subtile_0__pin_I2i_0_, + top_width_0_height_0_subtile_0__pin_I2i_1_, + top_width_0_height_0_subtile_0__pin_I3_0_, + top_width_0_height_0_subtile_0__pin_I3_1_, + top_width_0_height_0_subtile_0__pin_I3i_0_, + top_width_0_height_0_subtile_0__pin_I3i_1_, + top_width_0_height_0_subtile_0__pin_reg_in_0_, + top_width_0_height_0_subtile_0__pin_sc_in_0_, + top_width_0_height_0_subtile_0__pin_cin_0_, + right_width_0_height_0_subtile_0__pin_I4_0_, + right_width_0_height_0_subtile_0__pin_I4_1_, + right_width_0_height_0_subtile_0__pin_I4i_0_, + right_width_0_height_0_subtile_0__pin_I4i_1_, + right_width_0_height_0_subtile_0__pin_I5_0_, + right_width_0_height_0_subtile_0__pin_I5_1_, + right_width_0_height_0_subtile_0__pin_I5i_0_, + right_width_0_height_0_subtile_0__pin_I5i_1_, + right_width_0_height_0_subtile_0__pin_I6_0_, + right_width_0_height_0_subtile_0__pin_I6_1_, + right_width_0_height_0_subtile_0__pin_I6i_0_, + right_width_0_height_0_subtile_0__pin_I6i_1_, + right_width_0_height_0_subtile_0__pin_I7_0_, + right_width_0_height_0_subtile_0__pin_I7_1_, + right_width_0_height_0_subtile_0__pin_I7i_0_, + right_width_0_height_0_subtile_0__pin_I7i_1_, + left_width_0_height_0_subtile_0__pin_reset_0_, + left_width_0_height_0_subtile_0__pin_clk_0_, + ccff_head, + top_width_0_height_0_subtile_0__pin_O_0_, + top_width_0_height_0_subtile_0__pin_O_1_, + top_width_0_height_0_subtile_0__pin_O_2_, + top_width_0_height_0_subtile_0__pin_O_3_, + top_width_0_height_0_subtile_0__pin_O_4_, + top_width_0_height_0_subtile_0__pin_O_5_, + top_width_0_height_0_subtile_0__pin_O_6_, + top_width_0_height_0_subtile_0__pin_O_7_, + right_width_0_height_0_subtile_0__pin_O_8_, + right_width_0_height_0_subtile_0__pin_O_9_, + right_width_0_height_0_subtile_0__pin_O_10_, + right_width_0_height_0_subtile_0__pin_O_11_, + right_width_0_height_0_subtile_0__pin_O_12_, + right_width_0_height_0_subtile_0__pin_O_13_, + right_width_0_height_0_subtile_0__pin_O_14_, + right_width_0_height_0_subtile_0__pin_O_15_, + bottom_width_0_height_0_subtile_0__pin_reg_out_0_, + bottom_width_0_height_0_subtile_0__pin_sc_out_0_, + bottom_width_0_height_0_subtile_0__pin_cout_0_, + ccff_tail +); + + input pReset; + input prog_clk; + input Test_en; + input top_width_0_height_0_subtile_0__pin_I0_0_; + input top_width_0_height_0_subtile_0__pin_I0_1_; + input top_width_0_height_0_subtile_0__pin_I0i_0_; + input top_width_0_height_0_subtile_0__pin_I0i_1_; + input top_width_0_height_0_subtile_0__pin_I1_0_; + input top_width_0_height_0_subtile_0__pin_I1_1_; + input top_width_0_height_0_subtile_0__pin_I1i_0_; + input top_width_0_height_0_subtile_0__pin_I1i_1_; + input top_width_0_height_0_subtile_0__pin_I2_0_; + input top_width_0_height_0_subtile_0__pin_I2_1_; + input top_width_0_height_0_subtile_0__pin_I2i_0_; + input top_width_0_height_0_subtile_0__pin_I2i_1_; + input top_width_0_height_0_subtile_0__pin_I3_0_; + input top_width_0_height_0_subtile_0__pin_I3_1_; + input top_width_0_height_0_subtile_0__pin_I3i_0_; + input top_width_0_height_0_subtile_0__pin_I3i_1_; + input top_width_0_height_0_subtile_0__pin_reg_in_0_; + input top_width_0_height_0_subtile_0__pin_sc_in_0_; + input top_width_0_height_0_subtile_0__pin_cin_0_; + input right_width_0_height_0_subtile_0__pin_I4_0_; + input right_width_0_height_0_subtile_0__pin_I4_1_; + input right_width_0_height_0_subtile_0__pin_I4i_0_; + input right_width_0_height_0_subtile_0__pin_I4i_1_; + input right_width_0_height_0_subtile_0__pin_I5_0_; + input right_width_0_height_0_subtile_0__pin_I5_1_; + input right_width_0_height_0_subtile_0__pin_I5i_0_; + input right_width_0_height_0_subtile_0__pin_I5i_1_; + input right_width_0_height_0_subtile_0__pin_I6_0_; + input right_width_0_height_0_subtile_0__pin_I6_1_; + input right_width_0_height_0_subtile_0__pin_I6i_0_; + input right_width_0_height_0_subtile_0__pin_I6i_1_; + input right_width_0_height_0_subtile_0__pin_I7_0_; + input right_width_0_height_0_subtile_0__pin_I7_1_; + input right_width_0_height_0_subtile_0__pin_I7i_0_; + input right_width_0_height_0_subtile_0__pin_I7i_1_; + input left_width_0_height_0_subtile_0__pin_reset_0_; + input left_width_0_height_0_subtile_0__pin_clk_0_; + input ccff_head; + output top_width_0_height_0_subtile_0__pin_O_0_; + output top_width_0_height_0_subtile_0__pin_O_1_; + output top_width_0_height_0_subtile_0__pin_O_2_; + output top_width_0_height_0_subtile_0__pin_O_3_; + output top_width_0_height_0_subtile_0__pin_O_4_; + output top_width_0_height_0_subtile_0__pin_O_5_; + output top_width_0_height_0_subtile_0__pin_O_6_; + output top_width_0_height_0_subtile_0__pin_O_7_; + output right_width_0_height_0_subtile_0__pin_O_8_; + output right_width_0_height_0_subtile_0__pin_O_9_; + output right_width_0_height_0_subtile_0__pin_O_10_; + output right_width_0_height_0_subtile_0__pin_O_11_; + output right_width_0_height_0_subtile_0__pin_O_12_; + output right_width_0_height_0_subtile_0__pin_O_13_; + output right_width_0_height_0_subtile_0__pin_O_14_; + output right_width_0_height_0_subtile_0__pin_O_15_; + output bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + output bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + output bottom_width_0_height_0_subtile_0__pin_cout_0_; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire Test_en; + wire top_width_0_height_0_subtile_0__pin_I0_0_; + wire top_width_0_height_0_subtile_0__pin_I0_1_; + wire top_width_0_height_0_subtile_0__pin_I0i_0_; + wire top_width_0_height_0_subtile_0__pin_I0i_1_; + wire top_width_0_height_0_subtile_0__pin_I1_0_; + wire top_width_0_height_0_subtile_0__pin_I1_1_; + wire top_width_0_height_0_subtile_0__pin_I1i_0_; + wire top_width_0_height_0_subtile_0__pin_I1i_1_; + wire top_width_0_height_0_subtile_0__pin_I2_0_; + wire top_width_0_height_0_subtile_0__pin_I2_1_; + wire top_width_0_height_0_subtile_0__pin_I2i_0_; + wire top_width_0_height_0_subtile_0__pin_I2i_1_; + wire top_width_0_height_0_subtile_0__pin_I3_0_; + wire top_width_0_height_0_subtile_0__pin_I3_1_; + wire top_width_0_height_0_subtile_0__pin_I3i_0_; + wire top_width_0_height_0_subtile_0__pin_I3i_1_; + wire top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire top_width_0_height_0_subtile_0__pin_sc_in_0_; + wire top_width_0_height_0_subtile_0__pin_cin_0_; + wire right_width_0_height_0_subtile_0__pin_I4_0_; + wire right_width_0_height_0_subtile_0__pin_I4_1_; + wire right_width_0_height_0_subtile_0__pin_I4i_0_; + wire right_width_0_height_0_subtile_0__pin_I4i_1_; + wire right_width_0_height_0_subtile_0__pin_I5_0_; + wire right_width_0_height_0_subtile_0__pin_I5_1_; + wire right_width_0_height_0_subtile_0__pin_I5i_0_; + wire right_width_0_height_0_subtile_0__pin_I5i_1_; + wire right_width_0_height_0_subtile_0__pin_I6_0_; + wire right_width_0_height_0_subtile_0__pin_I6_1_; + wire right_width_0_height_0_subtile_0__pin_I6i_0_; + wire right_width_0_height_0_subtile_0__pin_I6i_1_; + wire right_width_0_height_0_subtile_0__pin_I7_0_; + wire right_width_0_height_0_subtile_0__pin_I7_1_; + wire right_width_0_height_0_subtile_0__pin_I7i_0_; + wire right_width_0_height_0_subtile_0__pin_I7i_1_; + wire left_width_0_height_0_subtile_0__pin_reset_0_; + wire left_width_0_height_0_subtile_0__pin_clk_0_; + wire ccff_head; + wire top_width_0_height_0_subtile_0__pin_O_0_; + wire top_width_0_height_0_subtile_0__pin_O_1_; + wire top_width_0_height_0_subtile_0__pin_O_2_; + wire top_width_0_height_0_subtile_0__pin_O_3_; + wire top_width_0_height_0_subtile_0__pin_O_4_; + wire top_width_0_height_0_subtile_0__pin_O_5_; + wire top_width_0_height_0_subtile_0__pin_O_6_; + wire top_width_0_height_0_subtile_0__pin_O_7_; + wire right_width_0_height_0_subtile_0__pin_O_8_; + wire right_width_0_height_0_subtile_0__pin_O_9_; + wire right_width_0_height_0_subtile_0__pin_O_10_; + wire right_width_0_height_0_subtile_0__pin_O_11_; + wire right_width_0_height_0_subtile_0__pin_O_12_; + wire right_width_0_height_0_subtile_0__pin_O_13_; + wire right_width_0_height_0_subtile_0__pin_O_14_; + wire right_width_0_height_0_subtile_0__pin_O_15_; + wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire ccff_tail; + + logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}), + .clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}), + .clb_I1({top_width_0_height_0_subtile_0__pin_I1_0_, top_width_0_height_0_subtile_0__pin_I1_1_}), + .clb_I1i({top_width_0_height_0_subtile_0__pin_I1i_0_, top_width_0_height_0_subtile_0__pin_I1i_1_}), + .clb_I2({top_width_0_height_0_subtile_0__pin_I2_0_, top_width_0_height_0_subtile_0__pin_I2_1_}), + .clb_I2i({top_width_0_height_0_subtile_0__pin_I2i_0_, top_width_0_height_0_subtile_0__pin_I2i_1_}), + .clb_I3({top_width_0_height_0_subtile_0__pin_I3_0_, top_width_0_height_0_subtile_0__pin_I3_1_}), + .clb_I3i({top_width_0_height_0_subtile_0__pin_I3i_0_, top_width_0_height_0_subtile_0__pin_I3i_1_}), + .clb_I4({right_width_0_height_0_subtile_0__pin_I4_0_, right_width_0_height_0_subtile_0__pin_I4_1_}), + .clb_I4i({right_width_0_height_0_subtile_0__pin_I4i_0_, right_width_0_height_0_subtile_0__pin_I4i_1_}), + .clb_I5({right_width_0_height_0_subtile_0__pin_I5_0_, right_width_0_height_0_subtile_0__pin_I5_1_}), + .clb_I5i({right_width_0_height_0_subtile_0__pin_I5i_0_, right_width_0_height_0_subtile_0__pin_I5i_1_}), + .clb_I6({right_width_0_height_0_subtile_0__pin_I6_0_, right_width_0_height_0_subtile_0__pin_I6_1_}), + .clb_I6i({right_width_0_height_0_subtile_0__pin_I6i_0_, right_width_0_height_0_subtile_0__pin_I6i_1_}), + .clb_I7({right_width_0_height_0_subtile_0__pin_I7_0_, right_width_0_height_0_subtile_0__pin_I7_1_}), + .clb_I7i({right_width_0_height_0_subtile_0__pin_I7i_0_, right_width_0_height_0_subtile_0__pin_I7i_1_}), + .clb_reg_in(top_width_0_height_0_subtile_0__pin_reg_in_0_), + .clb_sc_in(top_width_0_height_0_subtile_0__pin_sc_in_0_), + .clb_cin(top_width_0_height_0_subtile_0__pin_cin_0_), + .clb_reset(left_width_0_height_0_subtile_0__pin_reset_0_), + .clb_clk(left_width_0_height_0_subtile_0__pin_clk_0_), + .ccff_head(ccff_head), + .clb_O({top_width_0_height_0_subtile_0__pin_O_0_, top_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, top_width_0_height_0_subtile_0__pin_O_3_, top_width_0_height_0_subtile_0__pin_O_4_, top_width_0_height_0_subtile_0__pin_O_5_, top_width_0_height_0_subtile_0__pin_O_6_, top_width_0_height_0_subtile_0__pin_O_7_, right_width_0_height_0_subtile_0__pin_O_8_, right_width_0_height_0_subtile_0__pin_O_9_, right_width_0_height_0_subtile_0__pin_O_10_, right_width_0_height_0_subtile_0__pin_O_11_, right_width_0_height_0_subtile_0__pin_O_12_, right_width_0_height_0_subtile_0__pin_O_13_, right_width_0_height_0_subtile_0__pin_O_14_, right_width_0_height_0_subtile_0__pin_O_15_}), + .clb_reg_out(bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .clb_sc_out(bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .clb_cout(bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(ccff_tail) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_bottom_bottom.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_bottom_bottom.v new file mode 100644 index 0000000..053e8b5 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_bottom_bottom.v @@ -0,0 +1,113 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module grid_io_bottom_bottom +( + IO_ISOL_N, + pReset, + prog_clk, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + top_width_0_height_0_subtile_0__pin_outpad_0_, + top_width_0_height_0_subtile_1__pin_outpad_0_, + top_width_0_height_0_subtile_2__pin_outpad_0_, + top_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_head, + top_width_0_height_0_subtile_0__pin_inpad_0_, + top_width_0_height_0_subtile_1__pin_inpad_0_, + top_width_0_height_0_subtile_2__pin_inpad_0_, + top_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail +); + + input IO_ISOL_N; + input pReset; + input prog_clk; + input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + input top_width_0_height_0_subtile_0__pin_outpad_0_; + input top_width_0_height_0_subtile_1__pin_outpad_0_; + input top_width_0_height_0_subtile_2__pin_outpad_0_; + input top_width_0_height_0_subtile_3__pin_outpad_0_; + input ccff_head; + output top_width_0_height_0_subtile_0__pin_inpad_0_; + output top_width_0_height_0_subtile_1__pin_inpad_0_; + output top_width_0_height_0_subtile_2__pin_inpad_0_; + output top_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + + wire IO_ISOL_N; + wire pReset; + wire prog_clk; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire top_width_0_height_0_subtile_0__pin_outpad_0_; + wire top_width_0_height_0_subtile_1__pin_outpad_0_; + wire top_width_0_height_0_subtile_2__pin_outpad_0_; + wire top_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_head; + wire top_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_tail; + wire logical_tile_io_mode_io__0_ccff_tail; + wire logical_tile_io_mode_io__1_ccff_tail; + wire logical_tile_io_mode_io__2_ccff_tail; + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]), + .io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]), + .io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]), + .io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]), + .io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_left_left.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_left_left.v new file mode 100644 index 0000000..5d235de --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_left_left.v @@ -0,0 +1,113 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module grid_io_left_left +( + IO_ISOL_N, + pReset, + prog_clk, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + right_width_0_height_0_subtile_0__pin_outpad_0_, + right_width_0_height_0_subtile_1__pin_outpad_0_, + right_width_0_height_0_subtile_2__pin_outpad_0_, + right_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_head, + right_width_0_height_0_subtile_0__pin_inpad_0_, + right_width_0_height_0_subtile_1__pin_inpad_0_, + right_width_0_height_0_subtile_2__pin_inpad_0_, + right_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail +); + + input IO_ISOL_N; + input pReset; + input prog_clk; + input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + input right_width_0_height_0_subtile_0__pin_outpad_0_; + input right_width_0_height_0_subtile_1__pin_outpad_0_; + input right_width_0_height_0_subtile_2__pin_outpad_0_; + input right_width_0_height_0_subtile_3__pin_outpad_0_; + input ccff_head; + output right_width_0_height_0_subtile_0__pin_inpad_0_; + output right_width_0_height_0_subtile_1__pin_inpad_0_; + output right_width_0_height_0_subtile_2__pin_inpad_0_; + output right_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + + wire IO_ISOL_N; + wire pReset; + wire prog_clk; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire right_width_0_height_0_subtile_0__pin_outpad_0_; + wire right_width_0_height_0_subtile_1__pin_outpad_0_; + wire right_width_0_height_0_subtile_2__pin_outpad_0_; + wire right_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_head; + wire right_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_tail; + wire logical_tile_io_mode_io__0_ccff_tail; + wire logical_tile_io_mode_io__1_ccff_tail; + wire logical_tile_io_mode_io__2_ccff_tail; + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]), + .io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]), + .io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]), + .io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]), + .io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_right_right.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_right_right.v new file mode 100644 index 0000000..42d3271 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_right_right.v @@ -0,0 +1,113 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module grid_io_right_right +( + IO_ISOL_N, + pReset, + prog_clk, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + left_width_0_height_0_subtile_0__pin_outpad_0_, + left_width_0_height_0_subtile_1__pin_outpad_0_, + left_width_0_height_0_subtile_2__pin_outpad_0_, + left_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_head, + left_width_0_height_0_subtile_0__pin_inpad_0_, + left_width_0_height_0_subtile_1__pin_inpad_0_, + left_width_0_height_0_subtile_2__pin_inpad_0_, + left_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail +); + + input IO_ISOL_N; + input pReset; + input prog_clk; + input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + input left_width_0_height_0_subtile_0__pin_outpad_0_; + input left_width_0_height_0_subtile_1__pin_outpad_0_; + input left_width_0_height_0_subtile_2__pin_outpad_0_; + input left_width_0_height_0_subtile_3__pin_outpad_0_; + input ccff_head; + output left_width_0_height_0_subtile_0__pin_inpad_0_; + output left_width_0_height_0_subtile_1__pin_inpad_0_; + output left_width_0_height_0_subtile_2__pin_inpad_0_; + output left_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + + wire IO_ISOL_N; + wire pReset; + wire prog_clk; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire left_width_0_height_0_subtile_0__pin_outpad_0_; + wire left_width_0_height_0_subtile_1__pin_outpad_0_; + wire left_width_0_height_0_subtile_2__pin_outpad_0_; + wire left_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_head; + wire left_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_tail; + wire logical_tile_io_mode_io__0_ccff_tail; + wire logical_tile_io_mode_io__1_ccff_tail; + wire logical_tile_io_mode_io__2_ccff_tail; + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]), + .io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]), + .io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]), + .io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]), + .io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_top_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_top_top.v new file mode 100644 index 0000000..b2f5320 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_top_top.v @@ -0,0 +1,113 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module grid_io_top_top +( + IO_ISOL_N, + pReset, + prog_clk, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + bottom_width_0_height_0_subtile_0__pin_outpad_0_, + bottom_width_0_height_0_subtile_1__pin_outpad_0_, + bottom_width_0_height_0_subtile_2__pin_outpad_0_, + bottom_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_head, + bottom_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail +); + + input IO_ISOL_N; + input pReset; + input prog_clk; + input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + input bottom_width_0_height_0_subtile_0__pin_outpad_0_; + input bottom_width_0_height_0_subtile_1__pin_outpad_0_; + input bottom_width_0_height_0_subtile_2__pin_outpad_0_; + input bottom_width_0_height_0_subtile_3__pin_outpad_0_; + input ccff_head; + output bottom_width_0_height_0_subtile_0__pin_inpad_0_; + output bottom_width_0_height_0_subtile_1__pin_inpad_0_; + output bottom_width_0_height_0_subtile_2__pin_inpad_0_; + output bottom_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + + wire IO_ISOL_N; + wire pReset; + wire prog_clk; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_head; + wire bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_tail; + wire logical_tile_io_mode_io__0_ccff_tail; + wire logical_tile_io_mode_io__1_ccff_tail; + wire logical_tile_io_mode_io__2_ccff_tail; + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]), + .io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]), + .io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]), + .io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]), + .io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_clb_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_clb_.v new file mode 100644 index 0000000..8b2da1e --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_clb_.v @@ -0,0 +1,810 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_clb_ +( + pReset, + prog_clk, + Test_en, + clb_I0, + clb_I0i, + clb_I1, + clb_I1i, + clb_I2, + clb_I2i, + clb_I3, + clb_I3i, + clb_I4, + clb_I4i, + clb_I5, + clb_I5i, + clb_I6, + clb_I6i, + clb_I7, + clb_I7i, + clb_reg_in, + clb_sc_in, + clb_cin, + clb_reset, + clb_clk, + ccff_head, + clb_O, + clb_reg_out, + clb_sc_out, + clb_cout, + ccff_tail +); + + input pReset; + input prog_clk; + input Test_en; + input [0:1]clb_I0; + input [0:1]clb_I0i; + input [0:1]clb_I1; + input [0:1]clb_I1i; + input [0:1]clb_I2; + input [0:1]clb_I2i; + input [0:1]clb_I3; + input [0:1]clb_I3i; + input [0:1]clb_I4; + input [0:1]clb_I4i; + input [0:1]clb_I5; + input [0:1]clb_I5i; + input [0:1]clb_I6; + input [0:1]clb_I6i; + input [0:1]clb_I7; + input [0:1]clb_I7i; + input clb_reg_in; + input clb_sc_in; + input clb_cin; + input clb_reset; + input clb_clk; + input ccff_head; + output [0:15]clb_O; + output clb_reg_out; + output clb_sc_out; + output clb_cout; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire Test_en; + wire [0:1]clb_I0; + wire [0:1]clb_I0i; + wire [0:1]clb_I1; + wire [0:1]clb_I1i; + wire [0:1]clb_I2; + wire [0:1]clb_I2i; + wire [0:1]clb_I3; + wire [0:1]clb_I3i; + wire [0:1]clb_I4; + wire [0:1]clb_I4i; + wire [0:1]clb_I5; + wire [0:1]clb_I5i; + wire [0:1]clb_I6; + wire [0:1]clb_I6i; + wire [0:1]clb_I7; + wire [0:1]clb_I7i; + wire clb_reg_in; + wire clb_sc_in; + wire clb_cin; + wire clb_reset; + wire clb_clk; + wire ccff_head; + wire [0:15]clb_O; + wire clb_reg_out; + wire clb_sc_out; + wire clb_cout; + wire ccff_tail; + wire direct_interc_19_out; + wire direct_interc_20_out; + wire direct_interc_21_out; + wire direct_interc_22_out; + wire direct_interc_23_out; + wire direct_interc_24_out; + wire direct_interc_25_out; + wire direct_interc_26_out; + wire direct_interc_27_out; + wire direct_interc_28_out; + wire direct_interc_29_out; + wire direct_interc_30_out; + wire direct_interc_31_out; + wire direct_interc_32_out; + wire direct_interc_33_out; + wire direct_interc_34_out; + wire direct_interc_35_out; + wire direct_interc_36_out; + wire direct_interc_37_out; + wire direct_interc_38_out; + wire direct_interc_39_out; + wire direct_interc_40_out; + wire direct_interc_41_out; + wire direct_interc_42_out; + wire direct_interc_43_out; + wire direct_interc_44_out; + wire direct_interc_45_out; + wire direct_interc_46_out; + wire direct_interc_47_out; + wire direct_interc_48_out; + wire direct_interc_49_out; + wire direct_interc_50_out; + wire direct_interc_51_out; + wire direct_interc_52_out; + wire direct_interc_53_out; + wire direct_interc_54_out; + wire direct_interc_55_out; + wire direct_interc_56_out; + wire direct_interc_57_out; + wire direct_interc_58_out; + wire direct_interc_59_out; + wire direct_interc_60_out; + wire direct_interc_61_out; + wire direct_interc_62_out; + wire direct_interc_63_out; + wire direct_interc_64_out; + wire direct_interc_65_out; + wire direct_interc_66_out; + wire direct_interc_67_out; + wire direct_interc_68_out; + wire direct_interc_69_out; + wire direct_interc_70_out; + wire direct_interc_71_out; + wire direct_interc_72_out; + wire direct_interc_73_out; + wire direct_interc_74_out; + wire direct_interc_75_out; + wire direct_interc_76_out; + wire direct_interc_77_out; + wire direct_interc_78_out; + wire direct_interc_79_out; + wire direct_interc_80_out; + wire direct_interc_81_out; + wire direct_interc_82_out; + wire direct_interc_83_out; + wire direct_interc_84_out; + wire direct_interc_85_out; + wire direct_interc_86_out; + wire direct_interc_87_out; + wire direct_interc_88_out; + wire direct_interc_89_out; + wire direct_interc_90_out; + wire logical_tile_clb_mode_default__fle_0_ccff_tail; + wire logical_tile_clb_mode_default__fle_0_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_0_fle_out; + wire logical_tile_clb_mode_default__fle_0_fle_reg_out; + wire logical_tile_clb_mode_default__fle_0_fle_sc_out; + wire logical_tile_clb_mode_default__fle_1_ccff_tail; + wire logical_tile_clb_mode_default__fle_1_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_1_fle_out; + wire logical_tile_clb_mode_default__fle_1_fle_reg_out; + wire logical_tile_clb_mode_default__fle_1_fle_sc_out; + wire logical_tile_clb_mode_default__fle_2_ccff_tail; + wire logical_tile_clb_mode_default__fle_2_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_2_fle_out; + wire logical_tile_clb_mode_default__fle_2_fle_reg_out; + wire logical_tile_clb_mode_default__fle_2_fle_sc_out; + wire logical_tile_clb_mode_default__fle_3_ccff_tail; + wire logical_tile_clb_mode_default__fle_3_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_3_fle_out; + wire logical_tile_clb_mode_default__fle_3_fle_reg_out; + wire logical_tile_clb_mode_default__fle_3_fle_sc_out; + wire logical_tile_clb_mode_default__fle_4_ccff_tail; + wire logical_tile_clb_mode_default__fle_4_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_4_fle_out; + wire logical_tile_clb_mode_default__fle_4_fle_reg_out; + wire logical_tile_clb_mode_default__fle_4_fle_sc_out; + wire logical_tile_clb_mode_default__fle_5_ccff_tail; + wire logical_tile_clb_mode_default__fle_5_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_5_fle_out; + wire logical_tile_clb_mode_default__fle_5_fle_reg_out; + wire logical_tile_clb_mode_default__fle_5_fle_sc_out; + wire logical_tile_clb_mode_default__fle_6_ccff_tail; + wire logical_tile_clb_mode_default__fle_6_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_6_fle_out; + wire logical_tile_clb_mode_default__fle_6_fle_reg_out; + wire logical_tile_clb_mode_default__fle_6_fle_sc_out; + wire logical_tile_clb_mode_default__fle_7_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_7_fle_out; + wire logical_tile_clb_mode_default__fle_7_fle_reg_out; + wire logical_tile_clb_mode_default__fle_7_fle_sc_out; + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_19_out, direct_interc_20_out, direct_interc_21_out, direct_interc_22_out}), + .fle_reg_in(direct_interc_23_out), + .fle_sc_in(direct_interc_24_out), + .fle_cin(direct_interc_25_out), + .fle_reset(direct_interc_26_out), + .fle_clk(direct_interc_27_out), + .ccff_head(ccff_head), + .fle_out(logical_tile_clb_mode_default__fle_0_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_0_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_0_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_0_fle_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_28_out, direct_interc_29_out, direct_interc_30_out, direct_interc_31_out}), + .fle_reg_in(direct_interc_32_out), + .fle_sc_in(direct_interc_33_out), + .fle_cin(direct_interc_34_out), + .fle_reset(direct_interc_35_out), + .fle_clk(direct_interc_36_out), + .ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_1_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_1_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_1_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_1_fle_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_37_out, direct_interc_38_out, direct_interc_39_out, direct_interc_40_out}), + .fle_reg_in(direct_interc_41_out), + .fle_sc_in(direct_interc_42_out), + .fle_cin(direct_interc_43_out), + .fle_reset(direct_interc_44_out), + .fle_clk(direct_interc_45_out), + .ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_2_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_2_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_2_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_2_fle_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_46_out, direct_interc_47_out, direct_interc_48_out, direct_interc_49_out}), + .fle_reg_in(direct_interc_50_out), + .fle_sc_in(direct_interc_51_out), + .fle_cin(direct_interc_52_out), + .fle_reset(direct_interc_53_out), + .fle_clk(direct_interc_54_out), + .ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_3_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_3_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_3_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_3_fle_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_55_out, direct_interc_56_out, direct_interc_57_out, direct_interc_58_out}), + .fle_reg_in(direct_interc_59_out), + .fle_sc_in(direct_interc_60_out), + .fle_cin(direct_interc_61_out), + .fle_reset(direct_interc_62_out), + .fle_clk(direct_interc_63_out), + .ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_4_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_4_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_4_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_4_fle_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_64_out, direct_interc_65_out, direct_interc_66_out, direct_interc_67_out}), + .fle_reg_in(direct_interc_68_out), + .fle_sc_in(direct_interc_69_out), + .fle_cin(direct_interc_70_out), + .fle_reset(direct_interc_71_out), + .fle_clk(direct_interc_72_out), + .ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_5_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_5_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_5_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_5_fle_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_73_out, direct_interc_74_out, direct_interc_75_out, direct_interc_76_out}), + .fle_reg_in(direct_interc_77_out), + .fle_sc_in(direct_interc_78_out), + .fle_cin(direct_interc_79_out), + .fle_reset(direct_interc_80_out), + .fle_clk(direct_interc_81_out), + .ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_6_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_6_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_6_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_6_fle_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_82_out, direct_interc_83_out, direct_interc_84_out, direct_interc_85_out}), + .fle_reg_in(direct_interc_86_out), + .fle_sc_in(direct_interc_87_out), + .fle_cin(direct_interc_88_out), + .fle_reset(direct_interc_89_out), + .fle_clk(direct_interc_90_out), + .ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_7_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_7_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_7_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_7_fle_cout), + .ccff_tail(ccff_tail) + ); + direct_interc direct_interc_0_ + ( + .in(logical_tile_clb_mode_default__fle_0_fle_out[1]), + .out(clb_O[0]) + ); + direct_interc direct_interc_1_ + ( + .in(logical_tile_clb_mode_default__fle_0_fle_out[0]), + .out(clb_O[1]) + ); + direct_interc direct_interc_2_ + ( + .in(logical_tile_clb_mode_default__fle_1_fle_out[1]), + .out(clb_O[2]) + ); + direct_interc direct_interc_3_ + ( + .in(logical_tile_clb_mode_default__fle_1_fle_out[0]), + .out(clb_O[3]) + ); + direct_interc direct_interc_4_ + ( + .in(logical_tile_clb_mode_default__fle_2_fle_out[1]), + .out(clb_O[4]) + ); + direct_interc direct_interc_5_ + ( + .in(logical_tile_clb_mode_default__fle_2_fle_out[0]), + .out(clb_O[5]) + ); + direct_interc direct_interc_6_ + ( + .in(logical_tile_clb_mode_default__fle_3_fle_out[1]), + .out(clb_O[6]) + ); + direct_interc direct_interc_7_ + ( + .in(logical_tile_clb_mode_default__fle_3_fle_out[0]), + .out(clb_O[7]) + ); + direct_interc direct_interc_8_ + ( + .in(logical_tile_clb_mode_default__fle_4_fle_out[1]), + .out(clb_O[8]) + ); + direct_interc direct_interc_9_ + ( + .in(logical_tile_clb_mode_default__fle_4_fle_out[0]), + .out(clb_O[9]) + ); + direct_interc direct_interc_10_ + ( + .in(logical_tile_clb_mode_default__fle_5_fle_out[1]), + .out(clb_O[10]) + ); + direct_interc direct_interc_11_ + ( + .in(logical_tile_clb_mode_default__fle_5_fle_out[0]), + .out(clb_O[11]) + ); + direct_interc direct_interc_12_ + ( + .in(logical_tile_clb_mode_default__fle_6_fle_out[1]), + .out(clb_O[12]) + ); + direct_interc direct_interc_13_ + ( + .in(logical_tile_clb_mode_default__fle_6_fle_out[0]), + .out(clb_O[13]) + ); + direct_interc direct_interc_14_ + ( + .in(logical_tile_clb_mode_default__fle_7_fle_out[1]), + .out(clb_O[14]) + ); + direct_interc direct_interc_15_ + ( + .in(logical_tile_clb_mode_default__fle_7_fle_out[0]), + .out(clb_O[15]) + ); + direct_interc direct_interc_16_ + ( + .in(logical_tile_clb_mode_default__fle_7_fle_reg_out), + .out(clb_reg_out) + ); + direct_interc direct_interc_17_ + ( + .in(logical_tile_clb_mode_default__fle_7_fle_sc_out), + .out(clb_sc_out) + ); + direct_interc direct_interc_18_ + ( + .in(logical_tile_clb_mode_default__fle_7_fle_cout), + .out(clb_cout) + ); + direct_interc direct_interc_19_ + ( + .in(clb_I0[0]), + .out(direct_interc_19_out) + ); + direct_interc direct_interc_20_ + ( + .in(clb_I0[1]), + .out(direct_interc_20_out) + ); + direct_interc direct_interc_21_ + ( + .in(clb_I0i[0]), + .out(direct_interc_21_out) + ); + direct_interc direct_interc_22_ + ( + .in(clb_I0i[1]), + .out(direct_interc_22_out) + ); + direct_interc direct_interc_23_ + ( + .in(clb_reg_in), + .out(direct_interc_23_out) + ); + direct_interc direct_interc_24_ + ( + .in(clb_sc_in), + .out(direct_interc_24_out) + ); + direct_interc direct_interc_25_ + ( + .in(clb_cin), + .out(direct_interc_25_out) + ); + direct_interc direct_interc_26_ + ( + .in(clb_reset), + .out(direct_interc_26_out) + ); + direct_interc direct_interc_27_ + ( + .in(clb_clk), + .out(direct_interc_27_out) + ); + direct_interc direct_interc_28_ + ( + .in(clb_I1[0]), + .out(direct_interc_28_out) + ); + direct_interc direct_interc_29_ + ( + .in(clb_I1[1]), + .out(direct_interc_29_out) + ); + direct_interc direct_interc_30_ + ( + .in(clb_I1i[0]), + .out(direct_interc_30_out) + ); + direct_interc direct_interc_31_ + ( + .in(clb_I1i[1]), + .out(direct_interc_31_out) + ); + direct_interc direct_interc_32_ + ( + .in(logical_tile_clb_mode_default__fle_0_fle_reg_out), + .out(direct_interc_32_out) + ); + direct_interc direct_interc_33_ + ( + .in(logical_tile_clb_mode_default__fle_0_fle_sc_out), + .out(direct_interc_33_out) + ); + direct_interc direct_interc_34_ + ( + .in(logical_tile_clb_mode_default__fle_0_fle_cout), + .out(direct_interc_34_out) + ); + direct_interc direct_interc_35_ + ( + .in(clb_reset), + .out(direct_interc_35_out) + ); + direct_interc direct_interc_36_ + ( + .in(clb_clk), + .out(direct_interc_36_out) + ); + direct_interc direct_interc_37_ + ( + .in(clb_I2[0]), + .out(direct_interc_37_out) + ); + direct_interc direct_interc_38_ + ( + .in(clb_I2[1]), + .out(direct_interc_38_out) + ); + direct_interc direct_interc_39_ + ( + .in(clb_I2i[0]), + .out(direct_interc_39_out) + ); + direct_interc direct_interc_40_ + ( + .in(clb_I2i[1]), + .out(direct_interc_40_out) + ); + direct_interc direct_interc_41_ + ( + .in(logical_tile_clb_mode_default__fle_1_fle_reg_out), + .out(direct_interc_41_out) + ); + direct_interc direct_interc_42_ + ( + .in(logical_tile_clb_mode_default__fle_1_fle_sc_out), + .out(direct_interc_42_out) + ); + direct_interc direct_interc_43_ + ( + .in(logical_tile_clb_mode_default__fle_1_fle_cout), + .out(direct_interc_43_out) + ); + direct_interc direct_interc_44_ + ( + .in(clb_reset), + .out(direct_interc_44_out) + ); + direct_interc direct_interc_45_ + ( + .in(clb_clk), + .out(direct_interc_45_out) + ); + direct_interc direct_interc_46_ + ( + .in(clb_I3[0]), + .out(direct_interc_46_out) + ); + direct_interc direct_interc_47_ + ( + .in(clb_I3[1]), + .out(direct_interc_47_out) + ); + direct_interc direct_interc_48_ + ( + .in(clb_I3i[0]), + .out(direct_interc_48_out) + ); + direct_interc direct_interc_49_ + ( + .in(clb_I3i[1]), + .out(direct_interc_49_out) + ); + direct_interc direct_interc_50_ + ( + .in(logical_tile_clb_mode_default__fle_2_fle_reg_out), + .out(direct_interc_50_out) + ); + direct_interc direct_interc_51_ + ( + .in(logical_tile_clb_mode_default__fle_2_fle_sc_out), + .out(direct_interc_51_out) + ); + direct_interc direct_interc_52_ + ( + .in(logical_tile_clb_mode_default__fle_2_fle_cout), + .out(direct_interc_52_out) + ); + direct_interc direct_interc_53_ + ( + .in(clb_reset), + .out(direct_interc_53_out) + ); + direct_interc direct_interc_54_ + ( + .in(clb_clk), + .out(direct_interc_54_out) + ); + direct_interc direct_interc_55_ + ( + .in(clb_I4[0]), + .out(direct_interc_55_out) + ); + direct_interc direct_interc_56_ + ( + .in(clb_I4[1]), + .out(direct_interc_56_out) + ); + direct_interc direct_interc_57_ + ( + .in(clb_I4i[0]), + .out(direct_interc_57_out) + ); + direct_interc direct_interc_58_ + ( + .in(clb_I4i[1]), + .out(direct_interc_58_out) + ); + direct_interc direct_interc_59_ + ( + .in(logical_tile_clb_mode_default__fle_3_fle_reg_out), + .out(direct_interc_59_out) + ); + direct_interc direct_interc_60_ + ( + .in(logical_tile_clb_mode_default__fle_3_fle_sc_out), + .out(direct_interc_60_out) + ); + direct_interc direct_interc_61_ + ( + .in(logical_tile_clb_mode_default__fle_3_fle_cout), + .out(direct_interc_61_out) + ); + direct_interc direct_interc_62_ + ( + .in(clb_reset), + .out(direct_interc_62_out) + ); + direct_interc direct_interc_63_ + ( + .in(clb_clk), + .out(direct_interc_63_out) + ); + direct_interc direct_interc_64_ + ( + .in(clb_I5[0]), + .out(direct_interc_64_out) + ); + direct_interc direct_interc_65_ + ( + .in(clb_I5[1]), + .out(direct_interc_65_out) + ); + direct_interc direct_interc_66_ + ( + .in(clb_I5i[0]), + .out(direct_interc_66_out) + ); + direct_interc direct_interc_67_ + ( + .in(clb_I5i[1]), + .out(direct_interc_67_out) + ); + direct_interc direct_interc_68_ + ( + .in(logical_tile_clb_mode_default__fle_4_fle_reg_out), + .out(direct_interc_68_out) + ); + direct_interc direct_interc_69_ + ( + .in(logical_tile_clb_mode_default__fle_4_fle_sc_out), + .out(direct_interc_69_out) + ); + direct_interc direct_interc_70_ + ( + .in(logical_tile_clb_mode_default__fle_4_fle_cout), + .out(direct_interc_70_out) + ); + direct_interc direct_interc_71_ + ( + .in(clb_reset), + .out(direct_interc_71_out) + ); + direct_interc direct_interc_72_ + ( + .in(clb_clk), + .out(direct_interc_72_out) + ); + direct_interc direct_interc_73_ + ( + .in(clb_I6[0]), + .out(direct_interc_73_out) + ); + direct_interc direct_interc_74_ + ( + .in(clb_I6[1]), + .out(direct_interc_74_out) + ); + direct_interc direct_interc_75_ + ( + .in(clb_I6i[0]), + .out(direct_interc_75_out) + ); + direct_interc direct_interc_76_ + ( + .in(clb_I6i[1]), + .out(direct_interc_76_out) + ); + direct_interc direct_interc_77_ + ( + .in(logical_tile_clb_mode_default__fle_5_fle_reg_out), + .out(direct_interc_77_out) + ); + direct_interc direct_interc_78_ + ( + .in(logical_tile_clb_mode_default__fle_5_fle_sc_out), + .out(direct_interc_78_out) + ); + direct_interc direct_interc_79_ + ( + .in(logical_tile_clb_mode_default__fle_5_fle_cout), + .out(direct_interc_79_out) + ); + direct_interc direct_interc_80_ + ( + .in(clb_reset), + .out(direct_interc_80_out) + ); + direct_interc direct_interc_81_ + ( + .in(clb_clk), + .out(direct_interc_81_out) + ); + direct_interc direct_interc_82_ + ( + .in(clb_I7[0]), + .out(direct_interc_82_out) + ); + direct_interc direct_interc_83_ + ( + .in(clb_I7[1]), + .out(direct_interc_83_out) + ); + direct_interc direct_interc_84_ + ( + .in(clb_I7i[0]), + .out(direct_interc_84_out) + ); + direct_interc direct_interc_85_ + ( + .in(clb_I7i[1]), + .out(direct_interc_85_out) + ); + direct_interc direct_interc_86_ + ( + .in(logical_tile_clb_mode_default__fle_6_fle_reg_out), + .out(direct_interc_86_out) + ); + direct_interc direct_interc_87_ + ( + .in(logical_tile_clb_mode_default__fle_6_fle_sc_out), + .out(direct_interc_87_out) + ); + direct_interc direct_interc_88_ + ( + .in(logical_tile_clb_mode_default__fle_6_fle_cout), + .out(direct_interc_88_out) + ); + direct_interc direct_interc_89_ + ( + .in(clb_reset), + .out(direct_interc_89_out) + ); + direct_interc direct_interc_90_ + ( + .in(clb_clk), + .out(direct_interc_90_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle.v new file mode 100644 index 0000000..b19563a --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle.v @@ -0,0 +1,156 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle +( + pReset, + prog_clk, + Test_en, + fle_in, + fle_reg_in, + fle_sc_in, + fle_cin, + fle_reset, + fle_clk, + ccff_head, + fle_out, + fle_reg_out, + fle_sc_out, + fle_cout, + ccff_tail +); + + input pReset; + input prog_clk; + input Test_en; + input [0:3]fle_in; + input fle_reg_in; + input fle_sc_in; + input fle_cin; + input fle_reset; + input fle_clk; + input ccff_head; + output [0:1]fle_out; + output fle_reg_out; + output fle_sc_out; + output fle_cout; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire Test_en; + wire [0:3]fle_in; + wire fle_reg_in; + wire fle_sc_in; + wire fle_cin; + wire fle_reset; + wire fle_clk; + wire ccff_head; + wire [0:1]fle_out; + wire fle_reg_out; + wire fle_sc_out; + wire fle_cout; + wire ccff_tail; + wire direct_interc_10_out; + wire direct_interc_11_out; + wire direct_interc_12_out; + wire direct_interc_13_out; + wire direct_interc_5_out; + wire direct_interc_6_out; + wire direct_interc_7_out; + wire direct_interc_8_out; + wire direct_interc_9_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout; + wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out; + + logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fabric_in({direct_interc_5_out, direct_interc_6_out, direct_interc_7_out, direct_interc_8_out}), + .fabric_reg_in(direct_interc_9_out), + .fabric_sc_in(direct_interc_10_out), + .fabric_cin(direct_interc_11_out), + .fabric_reset(direct_interc_12_out), + .fabric_clk(direct_interc_13_out), + .ccff_head(ccff_head), + .fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out), + .fabric_reg_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out), + .fabric_sc_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out), + .fabric_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout), + .ccff_tail(ccff_tail) + ); + direct_interc direct_interc_0_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0]), + .out(fle_out[0]) + ); + direct_interc direct_interc_1_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[1]), + .out(fle_out[1]) + ); + direct_interc direct_interc_2_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out), + .out(fle_reg_out) + ); + direct_interc direct_interc_3_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out), + .out(fle_sc_out) + ); + direct_interc direct_interc_4_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout), + .out(fle_cout) + ); + direct_interc direct_interc_5_ + ( + .in(fle_in[0]), + .out(direct_interc_5_out) + ); + direct_interc direct_interc_6_ + ( + .in(fle_in[1]), + .out(direct_interc_6_out) + ); + direct_interc direct_interc_7_ + ( + .in(fle_in[2]), + .out(direct_interc_7_out) + ); + direct_interc direct_interc_8_ + ( + .in(fle_in[3]), + .out(direct_interc_8_out) + ); + direct_interc direct_interc_9_ + ( + .in(fle_reg_in), + .out(direct_interc_9_out) + ); + direct_interc direct_interc_10_ + ( + .in(fle_sc_in), + .out(direct_interc_10_out) + ); + direct_interc direct_interc_11_ + ( + .in(fle_cin), + .out(direct_interc_11_out) + ); + direct_interc direct_interc_12_ + ( + .in(fle_reset), + .out(direct_interc_12_out) + ); + direct_interc direct_interc_13_ + ( + .in(fle_clk), + .out(direct_interc_13_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v new file mode 100644 index 0000000..817e939 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v @@ -0,0 +1,243 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle_mode_physical__fabric +( + pReset, + prog_clk, + Test_en, + fabric_in, + fabric_reg_in, + fabric_sc_in, + fabric_cin, + fabric_reset, + fabric_clk, + ccff_head, + fabric_out, + fabric_reg_out, + fabric_sc_out, + fabric_cout, + ccff_tail +); + + input pReset; + input prog_clk; + input Test_en; + input [0:3]fabric_in; + input fabric_reg_in; + input fabric_sc_in; + input fabric_cin; + input fabric_reset; + input fabric_clk; + input ccff_head; + output [0:1]fabric_out; + output fabric_reg_out; + output fabric_sc_out; + output fabric_cout; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire Test_en; + wire [0:3]fabric_in; + wire fabric_reg_in; + wire fabric_sc_in; + wire fabric_cin; + wire fabric_reset; + wire fabric_clk; + wire ccff_head; + wire [0:1]fabric_out; + wire fabric_reg_out; + wire fabric_sc_out; + wire fabric_cout; + wire ccff_tail; + wire direct_interc_10_out; + wire direct_interc_11_out; + wire direct_interc_12_out; + wire direct_interc_13_out; + wire direct_interc_3_out; + wire direct_interc_4_out; + wire direct_interc_5_out; + wire direct_interc_6_out; + wire direct_interc_7_out; + wire direct_interc_8_out; + wire direct_interc_9_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout; + wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out; + wire [0:1]mux_fabric_out_0_undriven_sram_inv; + wire [0:1]mux_fabric_out_1_undriven_sram_inv; + wire [0:1]mux_ff_0_D_0_undriven_sram_inv; + wire [0:1]mux_ff_1_D_0_undriven_sram_inv; + wire [0:1]mux_tree_size2_0_sram; + wire [0:1]mux_tree_size2_1_sram; + wire mux_tree_size2_2_out; + wire [0:1]mux_tree_size2_2_sram; + wire mux_tree_size2_3_out; + wire [0:1]mux_tree_size2_3_sram; + wire mux_tree_size2_mem_0_ccff_tail; + wire mux_tree_size2_mem_1_ccff_tail; + wire mux_tree_size2_mem_2_ccff_tail; + + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .frac_logic_in({direct_interc_3_out, direct_interc_4_out, direct_interc_5_out, direct_interc_6_out}), + .frac_logic_cin(direct_interc_7_out), + .ccff_head(ccff_head), + .frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out), + .frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail) + ); + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 + ( + .Test_en(Test_en), + .ff_D(mux_tree_size2_2_out), + .ff_DI(direct_interc_8_out), + .ff_reset(direct_interc_9_out), + .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q), + .ff_clk(direct_interc_10_out) + ); + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 + ( + .Test_en(Test_en), + .ff_D(mux_tree_size2_3_out), + .ff_DI(direct_interc_11_out), + .ff_reset(direct_interc_12_out), + .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q), + .ff_clk(direct_interc_13_out) + ); + mux_tree_size2 mux_fabric_out_0 + ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}), + .sram(mux_tree_size2_0_sram), + .sram_inv(mux_fabric_out_0_undriven_sram_inv), + .out(fabric_out[0]) + ); + mux_tree_size2 mux_fabric_out_1 + ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}), + .sram(mux_tree_size2_1_sram), + .sram_inv(mux_fabric_out_1_undriven_sram_inv), + .out(fabric_out[1]) + ); + mux_tree_size2 mux_ff_0_D_0 + ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_reg_in}), + .sram(mux_tree_size2_2_sram), + .sram_inv(mux_ff_0_D_0_undriven_sram_inv), + .out(mux_tree_size2_2_out) + ); + mux_tree_size2 mux_ff_1_D_0 + ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q}), + .sram(mux_tree_size2_3_sram), + .sram_inv(mux_ff_1_D_0_undriven_sram_inv), + .out(mux_tree_size2_3_out) + ); + mux_tree_size2_mem mem_fabric_out_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail), + .ccff_tail(mux_tree_size2_mem_0_ccff_tail), + .mem_out(mux_tree_size2_0_sram) + ); + mux_tree_size2_mem mem_fabric_out_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_size2_mem_1_ccff_tail), + .mem_out(mux_tree_size2_1_sram) + ); + mux_tree_size2_mem mem_ff_0_D_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_size2_mem_2_ccff_tail), + .mem_out(mux_tree_size2_2_sram) + ); + mux_tree_size2_mem mem_ff_1_D_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_size2_mem_2_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_size2_3_sram) + ); + direct_interc direct_interc_0_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q), + .out(fabric_reg_out) + ); + direct_interc direct_interc_1_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q), + .out(fabric_sc_out) + ); + direct_interc direct_interc_2_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout), + .out(fabric_cout) + ); + direct_interc direct_interc_3_ + ( + .in(fabric_in[0]), + .out(direct_interc_3_out) + ); + direct_interc direct_interc_4_ + ( + .in(fabric_in[1]), + .out(direct_interc_4_out) + ); + direct_interc direct_interc_5_ + ( + .in(fabric_in[2]), + .out(direct_interc_5_out) + ); + direct_interc direct_interc_6_ + ( + .in(fabric_in[3]), + .out(direct_interc_6_out) + ); + direct_interc direct_interc_7_ + ( + .in(fabric_cin), + .out(direct_interc_7_out) + ); + direct_interc direct_interc_8_ + ( + .in(fabric_sc_in), + .out(direct_interc_8_out) + ); + direct_interc direct_interc_9_ + ( + .in(fabric_reset), + .out(direct_interc_9_out) + ); + direct_interc direct_interc_10_ + ( + .in(fabric_clk), + .out(direct_interc_10_out) + ); + direct_interc direct_interc_11_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q), + .out(direct_interc_11_out) + ); + direct_interc direct_interc_12_ + ( + .in(fabric_reset), + .out(direct_interc_12_out) + ); + direct_interc direct_interc_13_ + ( + .in(fabric_clk), + .out(direct_interc_13_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v new file mode 100644 index 0000000..72a652c --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v @@ -0,0 +1,37 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff +( + Test_en, + ff_D, + ff_DI, + ff_reset, + ff_Q, + ff_clk +); + + input Test_en; + input ff_D; + input ff_DI; + input ff_reset; + output ff_Q; + input ff_clk; + + wire Test_en; + wire ff_D; + wire ff_DI; + wire ff_reset; + wire ff_Q; + wire ff_clk; + + sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ + ( + .SCE(Test_en), + .D(ff_D), + .SCD(ff_DI), + .RESET_B(ff_reset), + .CLK(ff_clk), + .Q(ff_Q) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v new file mode 100644 index 0000000..87e59c3 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v @@ -0,0 +1,139 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic +( + pReset, + prog_clk, + frac_logic_in, + frac_logic_cin, + ccff_head, + frac_logic_out, + frac_logic_cout, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:3]frac_logic_in; + input frac_logic_cin; + input ccff_head; + output [0:1]frac_logic_out; + output frac_logic_cout; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:3]frac_logic_in; + wire frac_logic_cin; + wire ccff_head; + wire [0:1]frac_logic_out; + wire frac_logic_cout; + wire ccff_tail; + wire direct_interc_2_out; + wire direct_interc_3_out; + wire direct_interc_4_out; + wire direct_interc_5_out; + wire direct_interc_6_out; + wire direct_interc_7_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail; + wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out; + wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out; + wire [0:1]mux_frac_logic_out_0_undriven_sram_inv; + wire [0:1]mux_frac_lut4_0_in_2_undriven_sram_inv; + wire [0:1]mux_tree_size2_0_sram; + wire mux_tree_size2_1_out; + wire [0:1]mux_tree_size2_1_sram; + wire mux_tree_size2_mem_0_ccff_tail; + + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .frac_lut4_in({direct_interc_2_out, direct_interc_3_out, mux_tree_size2_1_out, direct_interc_4_out}), + .ccff_head(ccff_head), + .frac_lut4_lut2_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out), + .frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out), + .frac_lut4_lut4_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out), + .ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail) + ); + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 + ( + .carry_follower_a(direct_interc_5_out), + .carry_follower_b(direct_interc_6_out), + .carry_follower_cin(direct_interc_7_out), + .carry_follower_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout) + ); + mux_tree_size2 mux_frac_logic_out_0 + ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}), + .sram(mux_tree_size2_0_sram), + .sram_inv(mux_frac_logic_out_0_undriven_sram_inv), + .out(frac_logic_out[0]) + ); + mux_tree_size2 mux_frac_lut4_0_in_2 + ( + .in({frac_logic_cin, frac_logic_in[2]}), + .sram(mux_tree_size2_1_sram), + .sram_inv(mux_frac_lut4_0_in_2_undriven_sram_inv), + .out(mux_tree_size2_1_out) + ); + mux_tree_size2_mem mem_frac_logic_out_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail), + .ccff_tail(mux_tree_size2_mem_0_ccff_tail), + .mem_out(mux_tree_size2_0_sram) + ); + mux_tree_size2_mem mem_frac_lut4_0_in_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_size2_mem_0_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_size2_1_sram) + ); + direct_interc direct_interc_0_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]), + .out(frac_logic_out[1]) + ); + direct_interc direct_interc_1_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout), + .out(frac_logic_cout) + ); + direct_interc direct_interc_2_ + ( + .in(frac_logic_in[0]), + .out(direct_interc_2_out) + ); + direct_interc direct_interc_3_ + ( + .in(frac_logic_in[1]), + .out(direct_interc_3_out) + ); + direct_interc direct_interc_4_ + ( + .in(frac_logic_in[3]), + .out(direct_interc_4_out) + ); + direct_interc direct_interc_5_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[1]), + .out(direct_interc_5_out) + ); + direct_interc direct_interc_6_ + ( + .in(frac_logic_cin), + .out(direct_interc_6_out) + ); + direct_interc direct_interc_7_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[0]), + .out(direct_interc_7_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v new file mode 100644 index 0000000..5264e03 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v @@ -0,0 +1,29 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower +( + carry_follower_a, + carry_follower_b, + carry_follower_cin, + carry_follower_cout +); + + input carry_follower_a; + input carry_follower_b; + input carry_follower_cin; + output carry_follower_cout; + + wire carry_follower_a; + wire carry_follower_b; + wire carry_follower_cin; + wire carry_follower_cout; + + sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_ + ( + .A0(carry_follower_a), + .A1(carry_follower_b), + .S(carry_follower_cin), + .X(carry_follower_cout) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v new file mode 100644 index 0000000..03b1192 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v @@ -0,0 +1,57 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 +( + pReset, + prog_clk, + frac_lut4_in, + ccff_head, + frac_lut4_lut2_out, + frac_lut4_lut3_out, + frac_lut4_lut4_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:3]frac_lut4_in; + input ccff_head; + output [0:1]frac_lut4_lut2_out; + output [0:1]frac_lut4_lut3_out; + output frac_lut4_lut4_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:3]frac_lut4_in; + wire ccff_head; + wire [0:1]frac_lut4_lut2_out; + wire [0:1]frac_lut4_lut3_out; + wire frac_lut4_lut4_out; + wire ccff_tail; + wire frac_lut4_0__undriven_mode_inv; + wire [0:15]frac_lut4_0__undriven_sram_inv; + wire frac_lut4_0_mode; + wire [0:15]frac_lut4_0_sram; + + frac_lut4 frac_lut4_0_ + ( + .in(frac_lut4_in), + .sram(frac_lut4_0_sram), + .sram_inv(frac_lut4_0__undriven_sram_inv), + .mode(frac_lut4_0_mode), + .mode_inv(frac_lut4_0__undriven_mode_inv), + .lut2_out(frac_lut4_lut2_out), + .lut3_out(frac_lut4_lut3_out), + .lut4_out(frac_lut4_lut4_out) + ); + frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(ccff_tail), + .mem_out({frac_lut4_0_sram[0], frac_lut4_0_sram[1], frac_lut4_0_sram[2], frac_lut4_0_sram[3], frac_lut4_0_sram[4], frac_lut4_0_sram[5], frac_lut4_0_sram[6], frac_lut4_0_sram[7], frac_lut4_0_sram[8], frac_lut4_0_sram[9], frac_lut4_0_sram[10], frac_lut4_0_sram[11], frac_lut4_0_sram[12], frac_lut4_0_sram[13], frac_lut4_0_sram[14], frac_lut4_0_sram[15], frac_lut4_0_mode}) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_io_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_io_.v new file mode 100644 index 0000000..73136e0 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_io_.v @@ -0,0 +1,65 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_io_mode_io_ +( + IO_ISOL_N, + pReset, + prog_clk, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + io_outpad, + ccff_head, + io_inpad, + ccff_tail +); + + input IO_ISOL_N; + input pReset; + input prog_clk; + input gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + input io_outpad; + input ccff_head; + output io_inpad; + output ccff_tail; + + wire IO_ISOL_N; + wire pReset; + wire prog_clk; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire io_outpad; + wire ccff_head; + wire io_inpad; + wire ccff_tail; + wire direct_interc_1_out; + wire logical_tile_io_mode_physical__iopad_0_iopad_inpad; + + logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .iopad_outpad(direct_interc_1_out), + .ccff_head(ccff_head), + .iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad), + .ccff_tail(ccff_tail) + ); + direct_interc direct_interc_0_ + ( + .in(logical_tile_io_mode_physical__iopad_0_iopad_inpad), + .out(io_inpad) + ); + direct_interc direct_interc_1_ + ( + .in(io_outpad), + .out(direct_interc_1_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_physical__iopad.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_physical__iopad.v new file mode 100644 index 0000000..3b88cdc --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_physical__iopad.v @@ -0,0 +1,59 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_io_mode_physical__iopad +( + IO_ISOL_N, + pReset, + prog_clk, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + iopad_outpad, + ccff_head, + iopad_inpad, + ccff_tail +); + + input IO_ISOL_N; + input pReset; + input prog_clk; + input gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + input iopad_outpad; + input ccff_head; + output iopad_inpad; + output ccff_tail; + + wire IO_ISOL_N; + wire pReset; + wire prog_clk; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire iopad_outpad; + wire ccff_head; + wire iopad_inpad; + wire ccff_tail; + wire EMBEDDED_IO_HD_0_en; + + EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), + .SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .FPGA_OUT(iopad_outpad), + .FPGA_DIR(EMBEDDED_IO_HD_0_en), + .FPGA_IN(iopad_inpad) + ); + EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(ccff_tail), + .mem_out(EMBEDDED_IO_HD_0_en) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__0_.v new file mode 100644 index 0000000..44990ca --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__0_.v @@ -0,0 +1,177 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cbx_1__0_ +( + pReset, + prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chanx_left_in; + input [0:29]chanx_right_in; + input ccff_head; + output [0:29]chanx_left_out; + output [0:29]chanx_right_out; + output bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + output bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + output bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + output bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chanx_left_in; + wire [0:29]chanx_right_in; + wire ccff_head; + wire [0:29]chanx_left_out; + wire [0:29]chanx_right_out; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_tail; + wire [0:3]mux_top_ipin_0_undriven_sram_inv; + wire [0:3]mux_top_ipin_1_undriven_sram_inv; + wire [0:3]mux_top_ipin_2_undriven_sram_inv; + wire [0:3]mux_top_ipin_3_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + +assign chanx_right_out[0] = chanx_left_in[0]; +assign chanx_right_out[1] = chanx_left_in[1]; +assign chanx_right_out[2] = chanx_left_in[2]; +assign chanx_right_out[3] = chanx_left_in[3]; +assign chanx_right_out[4] = chanx_left_in[4]; +assign chanx_right_out[5] = chanx_left_in[5]; +assign chanx_right_out[6] = chanx_left_in[6]; +assign chanx_right_out[7] = chanx_left_in[7]; +assign chanx_right_out[8] = chanx_left_in[8]; +assign chanx_right_out[9] = chanx_left_in[9]; +assign chanx_right_out[10] = chanx_left_in[10]; +assign chanx_right_out[11] = chanx_left_in[11]; +assign chanx_right_out[12] = chanx_left_in[12]; +assign chanx_right_out[13] = chanx_left_in[13]; +assign chanx_right_out[14] = chanx_left_in[14]; +assign chanx_right_out[15] = chanx_left_in[15]; +assign chanx_right_out[16] = chanx_left_in[16]; +assign chanx_right_out[17] = chanx_left_in[17]; +assign chanx_right_out[18] = chanx_left_in[18]; +assign chanx_right_out[19] = chanx_left_in[19]; +assign chanx_right_out[20] = chanx_left_in[20]; +assign chanx_right_out[21] = chanx_left_in[21]; +assign chanx_right_out[22] = chanx_left_in[22]; +assign chanx_right_out[23] = chanx_left_in[23]; +assign chanx_right_out[24] = chanx_left_in[24]; +assign chanx_right_out[25] = chanx_left_in[25]; +assign chanx_right_out[26] = chanx_left_in[26]; +assign chanx_right_out[27] = chanx_left_in[27]; +assign chanx_right_out[28] = chanx_left_in[28]; +assign chanx_right_out[29] = chanx_left_in[29]; +assign chanx_left_out[0] = chanx_right_in[0]; +assign chanx_left_out[1] = chanx_right_in[1]; +assign chanx_left_out[2] = chanx_right_in[2]; +assign chanx_left_out[3] = chanx_right_in[3]; +assign chanx_left_out[4] = chanx_right_in[4]; +assign chanx_left_out[5] = chanx_right_in[5]; +assign chanx_left_out[6] = chanx_right_in[6]; +assign chanx_left_out[7] = chanx_right_in[7]; +assign chanx_left_out[8] = chanx_right_in[8]; +assign chanx_left_out[9] = chanx_right_in[9]; +assign chanx_left_out[10] = chanx_right_in[10]; +assign chanx_left_out[11] = chanx_right_in[11]; +assign chanx_left_out[12] = chanx_right_in[12]; +assign chanx_left_out[13] = chanx_right_in[13]; +assign chanx_left_out[14] = chanx_right_in[14]; +assign chanx_left_out[15] = chanx_right_in[15]; +assign chanx_left_out[16] = chanx_right_in[16]; +assign chanx_left_out[17] = chanx_right_in[17]; +assign chanx_left_out[18] = chanx_right_in[18]; +assign chanx_left_out[19] = chanx_right_in[19]; +assign chanx_left_out[20] = chanx_right_in[20]; +assign chanx_left_out[21] = chanx_right_in[21]; +assign chanx_left_out[22] = chanx_right_in[22]; +assign chanx_left_out[23] = chanx_right_in[23]; +assign chanx_left_out[24] = chanx_right_in[24]; +assign chanx_left_out[25] = chanx_right_in[25]; +assign chanx_left_out[26] = chanx_right_in[26]; +assign chanx_left_out[27] = chanx_right_in[27]; +assign chanx_left_out[28] = chanx_right_in[28]; +assign chanx_left_out[29] = chanx_right_in[29]; + mux_tree_tapbuf_size12 mux_top_ipin_0 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_top_ipin_0_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_1 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_top_ipin_1_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_2 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_top_ipin_2_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_3 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21], chanx_left_in[27], chanx_right_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_top_ipin_3_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__1_.v new file mode 100644 index 0000000..b218cae --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__1_.v @@ -0,0 +1,429 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cbx_1__1_ +( + pReset, + prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chanx_left_in; + input [0:29]chanx_right_in; + input ccff_head; + output [0:29]chanx_left_out; + output [0:29]chanx_right_out; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chanx_left_in; + wire [0:29]chanx_right_in; + wire ccff_head; + wire [0:29]chanx_left_out; + wire [0:29]chanx_right_out; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire ccff_tail; + wire [0:3]mux_top_ipin_0_undriven_sram_inv; + wire [0:3]mux_top_ipin_10_undriven_sram_inv; + wire [0:3]mux_top_ipin_11_undriven_sram_inv; + wire [0:3]mux_top_ipin_12_undriven_sram_inv; + wire [0:3]mux_top_ipin_13_undriven_sram_inv; + wire [0:3]mux_top_ipin_14_undriven_sram_inv; + wire [0:3]mux_top_ipin_15_undriven_sram_inv; + wire [0:3]mux_top_ipin_1_undriven_sram_inv; + wire [0:3]mux_top_ipin_2_undriven_sram_inv; + wire [0:3]mux_top_ipin_3_undriven_sram_inv; + wire [0:3]mux_top_ipin_4_undriven_sram_inv; + wire [0:3]mux_top_ipin_5_undriven_sram_inv; + wire [0:3]mux_top_ipin_6_undriven_sram_inv; + wire [0:3]mux_top_ipin_7_undriven_sram_inv; + wire [0:3]mux_top_ipin_8_undriven_sram_inv; + wire [0:3]mux_top_ipin_9_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire [0:3]mux_tree_tapbuf_size10_1_sram; + wire [0:3]mux_tree_tapbuf_size10_2_sram; + wire [0:3]mux_tree_tapbuf_size10_3_sram; + wire [0:3]mux_tree_tapbuf_size10_4_sram; + wire [0:3]mux_tree_tapbuf_size10_5_sram; + wire [0:3]mux_tree_tapbuf_size10_6_sram; + wire [0:3]mux_tree_tapbuf_size10_7_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire [0:3]mux_tree_tapbuf_size12_4_sram; + wire [0:3]mux_tree_tapbuf_size12_5_sram; + wire [0:3]mux_tree_tapbuf_size12_6_sram; + wire [0:3]mux_tree_tapbuf_size12_7_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire mux_tree_tapbuf_size12_mem_7_ccff_tail; + +assign chanx_right_out[0] = chanx_left_in[0]; +assign chanx_right_out[1] = chanx_left_in[1]; +assign chanx_right_out[2] = chanx_left_in[2]; +assign chanx_right_out[3] = chanx_left_in[3]; +assign chanx_right_out[4] = chanx_left_in[4]; +assign chanx_right_out[5] = chanx_left_in[5]; +assign chanx_right_out[6] = chanx_left_in[6]; +assign chanx_right_out[7] = chanx_left_in[7]; +assign chanx_right_out[8] = chanx_left_in[8]; +assign chanx_right_out[9] = chanx_left_in[9]; +assign chanx_right_out[10] = chanx_left_in[10]; +assign chanx_right_out[11] = chanx_left_in[11]; +assign chanx_right_out[12] = chanx_left_in[12]; +assign chanx_right_out[13] = chanx_left_in[13]; +assign chanx_right_out[14] = chanx_left_in[14]; +assign chanx_right_out[15] = chanx_left_in[15]; +assign chanx_right_out[16] = chanx_left_in[16]; +assign chanx_right_out[17] = chanx_left_in[17]; +assign chanx_right_out[18] = chanx_left_in[18]; +assign chanx_right_out[19] = chanx_left_in[19]; +assign chanx_right_out[20] = chanx_left_in[20]; +assign chanx_right_out[21] = chanx_left_in[21]; +assign chanx_right_out[22] = chanx_left_in[22]; +assign chanx_right_out[23] = chanx_left_in[23]; +assign chanx_right_out[24] = chanx_left_in[24]; +assign chanx_right_out[25] = chanx_left_in[25]; +assign chanx_right_out[26] = chanx_left_in[26]; +assign chanx_right_out[27] = chanx_left_in[27]; +assign chanx_right_out[28] = chanx_left_in[28]; +assign chanx_right_out[29] = chanx_left_in[29]; +assign chanx_left_out[0] = chanx_right_in[0]; +assign chanx_left_out[1] = chanx_right_in[1]; +assign chanx_left_out[2] = chanx_right_in[2]; +assign chanx_left_out[3] = chanx_right_in[3]; +assign chanx_left_out[4] = chanx_right_in[4]; +assign chanx_left_out[5] = chanx_right_in[5]; +assign chanx_left_out[6] = chanx_right_in[6]; +assign chanx_left_out[7] = chanx_right_in[7]; +assign chanx_left_out[8] = chanx_right_in[8]; +assign chanx_left_out[9] = chanx_right_in[9]; +assign chanx_left_out[10] = chanx_right_in[10]; +assign chanx_left_out[11] = chanx_right_in[11]; +assign chanx_left_out[12] = chanx_right_in[12]; +assign chanx_left_out[13] = chanx_right_in[13]; +assign chanx_left_out[14] = chanx_right_in[14]; +assign chanx_left_out[15] = chanx_right_in[15]; +assign chanx_left_out[16] = chanx_right_in[16]; +assign chanx_left_out[17] = chanx_right_in[17]; +assign chanx_left_out[18] = chanx_right_in[18]; +assign chanx_left_out[19] = chanx_right_in[19]; +assign chanx_left_out[20] = chanx_right_in[20]; +assign chanx_left_out[21] = chanx_right_in[21]; +assign chanx_left_out[22] = chanx_right_in[22]; +assign chanx_left_out[23] = chanx_right_in[23]; +assign chanx_left_out[24] = chanx_right_in[24]; +assign chanx_left_out[25] = chanx_right_in[25]; +assign chanx_left_out[26] = chanx_right_in[26]; +assign chanx_left_out[27] = chanx_right_in[27]; +assign chanx_left_out[28] = chanx_right_in[28]; +assign chanx_left_out[29] = chanx_right_in[29]; + mux_tree_tapbuf_size12 mux_top_ipin_0 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_top_ipin_0_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_2 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_top_ipin_2_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_4 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_top_ipin_4_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_6 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_top_ipin_6_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_8 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_4_sram), + .sram_inv(mux_top_ipin_8_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_10 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_5_sram), + .sram_inv(mux_top_ipin_10_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_12 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_6_sram), + .sram_inv(mux_top_ipin_12_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_14 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_7_sram), + .sram_inv(mux_top_ipin_14_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram) + ); + mux_tree_tapbuf_size10 mux_top_ipin_1 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[16], chanx_right_in[16], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_top_ipin_1_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_3 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[18], chanx_right_in[18], chanx_left_in[27], chanx_right_in[27]}), + .sram(mux_tree_tapbuf_size10_1_sram), + .sram_inv(mux_top_ipin_3_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_5 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[20], chanx_right_in[20], chanx_left_in[29], chanx_right_in[29]}), + .sram(mux_tree_tapbuf_size10_2_sram), + .sram_inv(mux_top_ipin_5_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_7 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[22], chanx_right_in[22]}), + .sram(mux_tree_tapbuf_size10_3_sram), + .sram_inv(mux_top_ipin_7_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_9 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size10_4_sram), + .sram_inv(mux_top_ipin_9_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_11 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size10_5_sram), + .sram_inv(mux_top_ipin_11_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_13 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size10_6_sram), + .sram_inv(mux_top_ipin_13_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_15 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21]}), + .sram(mux_tree_tapbuf_size10_7_sram), + .sram_inv(mux_top_ipin_15_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__8_.v new file mode 100644 index 0000000..11749f0 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__8_.v @@ -0,0 +1,513 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cbx_1__8_ +( + pReset, + prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chanx_left_in; + input [0:29]chanx_right_in; + input ccff_head; + output [0:29]chanx_left_out; + output [0:29]chanx_right_out; + output top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + output top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + output top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + output top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chanx_left_in; + wire [0:29]chanx_right_in; + wire ccff_head; + wire [0:29]chanx_left_out; + wire [0:29]chanx_right_out; + wire top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire ccff_tail; + wire [0:3]mux_bottom_ipin_0_undriven_sram_inv; + wire [0:3]mux_bottom_ipin_1_undriven_sram_inv; + wire [0:3]mux_bottom_ipin_2_undriven_sram_inv; + wire [0:3]mux_bottom_ipin_3_undriven_sram_inv; + wire [0:3]mux_top_ipin_0_undriven_sram_inv; + wire [0:3]mux_top_ipin_10_undriven_sram_inv; + wire [0:3]mux_top_ipin_11_undriven_sram_inv; + wire [0:3]mux_top_ipin_12_undriven_sram_inv; + wire [0:3]mux_top_ipin_13_undriven_sram_inv; + wire [0:3]mux_top_ipin_14_undriven_sram_inv; + wire [0:3]mux_top_ipin_15_undriven_sram_inv; + wire [0:3]mux_top_ipin_1_undriven_sram_inv; + wire [0:3]mux_top_ipin_2_undriven_sram_inv; + wire [0:3]mux_top_ipin_3_undriven_sram_inv; + wire [0:3]mux_top_ipin_4_undriven_sram_inv; + wire [0:3]mux_top_ipin_5_undriven_sram_inv; + wire [0:3]mux_top_ipin_6_undriven_sram_inv; + wire [0:3]mux_top_ipin_7_undriven_sram_inv; + wire [0:3]mux_top_ipin_8_undriven_sram_inv; + wire [0:3]mux_top_ipin_9_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire [0:3]mux_tree_tapbuf_size10_1_sram; + wire [0:3]mux_tree_tapbuf_size10_2_sram; + wire [0:3]mux_tree_tapbuf_size10_3_sram; + wire [0:3]mux_tree_tapbuf_size10_4_sram; + wire [0:3]mux_tree_tapbuf_size10_5_sram; + wire [0:3]mux_tree_tapbuf_size10_6_sram; + wire [0:3]mux_tree_tapbuf_size10_7_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_10_sram; + wire [0:3]mux_tree_tapbuf_size12_11_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire [0:3]mux_tree_tapbuf_size12_4_sram; + wire [0:3]mux_tree_tapbuf_size12_5_sram; + wire [0:3]mux_tree_tapbuf_size12_6_sram; + wire [0:3]mux_tree_tapbuf_size12_7_sram; + wire [0:3]mux_tree_tapbuf_size12_8_sram; + wire [0:3]mux_tree_tapbuf_size12_9_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_10_ccff_tail; + wire mux_tree_tapbuf_size12_mem_11_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire mux_tree_tapbuf_size12_mem_7_ccff_tail; + wire mux_tree_tapbuf_size12_mem_8_ccff_tail; + wire mux_tree_tapbuf_size12_mem_9_ccff_tail; + +assign chanx_right_out[0] = chanx_left_in[0]; +assign chanx_right_out[1] = chanx_left_in[1]; +assign chanx_right_out[2] = chanx_left_in[2]; +assign chanx_right_out[3] = chanx_left_in[3]; +assign chanx_right_out[4] = chanx_left_in[4]; +assign chanx_right_out[5] = chanx_left_in[5]; +assign chanx_right_out[6] = chanx_left_in[6]; +assign chanx_right_out[7] = chanx_left_in[7]; +assign chanx_right_out[8] = chanx_left_in[8]; +assign chanx_right_out[9] = chanx_left_in[9]; +assign chanx_right_out[10] = chanx_left_in[10]; +assign chanx_right_out[11] = chanx_left_in[11]; +assign chanx_right_out[12] = chanx_left_in[12]; +assign chanx_right_out[13] = chanx_left_in[13]; +assign chanx_right_out[14] = chanx_left_in[14]; +assign chanx_right_out[15] = chanx_left_in[15]; +assign chanx_right_out[16] = chanx_left_in[16]; +assign chanx_right_out[17] = chanx_left_in[17]; +assign chanx_right_out[18] = chanx_left_in[18]; +assign chanx_right_out[19] = chanx_left_in[19]; +assign chanx_right_out[20] = chanx_left_in[20]; +assign chanx_right_out[21] = chanx_left_in[21]; +assign chanx_right_out[22] = chanx_left_in[22]; +assign chanx_right_out[23] = chanx_left_in[23]; +assign chanx_right_out[24] = chanx_left_in[24]; +assign chanx_right_out[25] = chanx_left_in[25]; +assign chanx_right_out[26] = chanx_left_in[26]; +assign chanx_right_out[27] = chanx_left_in[27]; +assign chanx_right_out[28] = chanx_left_in[28]; +assign chanx_right_out[29] = chanx_left_in[29]; +assign chanx_left_out[0] = chanx_right_in[0]; +assign chanx_left_out[1] = chanx_right_in[1]; +assign chanx_left_out[2] = chanx_right_in[2]; +assign chanx_left_out[3] = chanx_right_in[3]; +assign chanx_left_out[4] = chanx_right_in[4]; +assign chanx_left_out[5] = chanx_right_in[5]; +assign chanx_left_out[6] = chanx_right_in[6]; +assign chanx_left_out[7] = chanx_right_in[7]; +assign chanx_left_out[8] = chanx_right_in[8]; +assign chanx_left_out[9] = chanx_right_in[9]; +assign chanx_left_out[10] = chanx_right_in[10]; +assign chanx_left_out[11] = chanx_right_in[11]; +assign chanx_left_out[12] = chanx_right_in[12]; +assign chanx_left_out[13] = chanx_right_in[13]; +assign chanx_left_out[14] = chanx_right_in[14]; +assign chanx_left_out[15] = chanx_right_in[15]; +assign chanx_left_out[16] = chanx_right_in[16]; +assign chanx_left_out[17] = chanx_right_in[17]; +assign chanx_left_out[18] = chanx_right_in[18]; +assign chanx_left_out[19] = chanx_right_in[19]; +assign chanx_left_out[20] = chanx_right_in[20]; +assign chanx_left_out[21] = chanx_right_in[21]; +assign chanx_left_out[22] = chanx_right_in[22]; +assign chanx_left_out[23] = chanx_right_in[23]; +assign chanx_left_out[24] = chanx_right_in[24]; +assign chanx_left_out[25] = chanx_right_in[25]; +assign chanx_left_out[26] = chanx_right_in[26]; +assign chanx_left_out[27] = chanx_right_in[27]; +assign chanx_left_out[28] = chanx_right_in[28]; +assign chanx_left_out[29] = chanx_right_in[29]; + mux_tree_tapbuf_size12 mux_bottom_ipin_0 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_bottom_ipin_0_undriven_sram_inv), + .out(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_bottom_ipin_1 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_bottom_ipin_1_undriven_sram_inv), + .out(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_bottom_ipin_2 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_bottom_ipin_2_undriven_sram_inv), + .out(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_bottom_ipin_3 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21], chanx_left_in[27], chanx_right_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_bottom_ipin_3_undriven_sram_inv), + .out(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_0 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_4_sram), + .sram_inv(mux_top_ipin_0_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_2 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_5_sram), + .sram_inv(mux_top_ipin_2_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_4 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_6_sram), + .sram_inv(mux_top_ipin_4_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_6 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_7_sram), + .sram_inv(mux_top_ipin_6_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_8 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_8_sram), + .sram_inv(mux_top_ipin_8_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_10 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_9_sram), + .sram_inv(mux_top_ipin_10_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_12 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_10_sram), + .sram_inv(mux_top_ipin_12_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_14 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_11_sram), + .sram_inv(mux_top_ipin_14_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_) + ); + mux_tree_tapbuf_size12_mem mem_bottom_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_bottom_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_bottom_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_bottom_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_8_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_9_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_10_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_11_sram) + ); + mux_tree_tapbuf_size10 mux_top_ipin_1 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[20], chanx_right_in[20], chanx_left_in[29], chanx_right_in[29]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_top_ipin_1_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_3 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[22], chanx_right_in[22]}), + .sram(mux_tree_tapbuf_size10_1_sram), + .sram_inv(mux_top_ipin_3_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_5 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size10_2_sram), + .sram_inv(mux_top_ipin_5_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_7 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size10_3_sram), + .sram_inv(mux_top_ipin_7_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_9 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size10_4_sram), + .sram_inv(mux_top_ipin_9_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_11 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21]}), + .sram(mux_tree_tapbuf_size10_5_sram), + .sram_inv(mux_top_ipin_11_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_13 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[17], chanx_right_in[17], chanx_left_in[23], chanx_right_in[23]}), + .sram(mux_tree_tapbuf_size10_6_sram), + .sram_inv(mux_top_ipin_13_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_15 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size10_7_sram), + .sram_inv(mux_top_ipin_15_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_0__1_.v new file mode 100644 index 0000000..b25d4b1 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_0__1_.v @@ -0,0 +1,177 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cby_0__1_ +( + pReset, + prog_clk, + chany_bottom_in, + chany_top_in, + ccff_head, + chany_bottom_out, + chany_top_out, + left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_bottom_in; + input [0:29]chany_top_in; + input ccff_head; + output [0:29]chany_bottom_out; + output [0:29]chany_top_out; + output left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + output left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + output left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + output left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_bottom_in; + wire [0:29]chany_top_in; + wire ccff_head; + wire [0:29]chany_bottom_out; + wire [0:29]chany_top_out; + wire left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_tail; + wire [0:3]mux_right_ipin_0_undriven_sram_inv; + wire [0:3]mux_right_ipin_1_undriven_sram_inv; + wire [0:3]mux_right_ipin_2_undriven_sram_inv; + wire [0:3]mux_right_ipin_3_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + +assign chany_top_out[0] = chany_bottom_in[0]; +assign chany_top_out[1] = chany_bottom_in[1]; +assign chany_top_out[2] = chany_bottom_in[2]; +assign chany_top_out[3] = chany_bottom_in[3]; +assign chany_top_out[4] = chany_bottom_in[4]; +assign chany_top_out[5] = chany_bottom_in[5]; +assign chany_top_out[6] = chany_bottom_in[6]; +assign chany_top_out[7] = chany_bottom_in[7]; +assign chany_top_out[8] = chany_bottom_in[8]; +assign chany_top_out[9] = chany_bottom_in[9]; +assign chany_top_out[10] = chany_bottom_in[10]; +assign chany_top_out[11] = chany_bottom_in[11]; +assign chany_top_out[12] = chany_bottom_in[12]; +assign chany_top_out[13] = chany_bottom_in[13]; +assign chany_top_out[14] = chany_bottom_in[14]; +assign chany_top_out[15] = chany_bottom_in[15]; +assign chany_top_out[16] = chany_bottom_in[16]; +assign chany_top_out[17] = chany_bottom_in[17]; +assign chany_top_out[18] = chany_bottom_in[18]; +assign chany_top_out[19] = chany_bottom_in[19]; +assign chany_top_out[20] = chany_bottom_in[20]; +assign chany_top_out[21] = chany_bottom_in[21]; +assign chany_top_out[22] = chany_bottom_in[22]; +assign chany_top_out[23] = chany_bottom_in[23]; +assign chany_top_out[24] = chany_bottom_in[24]; +assign chany_top_out[25] = chany_bottom_in[25]; +assign chany_top_out[26] = chany_bottom_in[26]; +assign chany_top_out[27] = chany_bottom_in[27]; +assign chany_top_out[28] = chany_bottom_in[28]; +assign chany_top_out[29] = chany_bottom_in[29]; +assign chany_bottom_out[0] = chany_top_in[0]; +assign chany_bottom_out[1] = chany_top_in[1]; +assign chany_bottom_out[2] = chany_top_in[2]; +assign chany_bottom_out[3] = chany_top_in[3]; +assign chany_bottom_out[4] = chany_top_in[4]; +assign chany_bottom_out[5] = chany_top_in[5]; +assign chany_bottom_out[6] = chany_top_in[6]; +assign chany_bottom_out[7] = chany_top_in[7]; +assign chany_bottom_out[8] = chany_top_in[8]; +assign chany_bottom_out[9] = chany_top_in[9]; +assign chany_bottom_out[10] = chany_top_in[10]; +assign chany_bottom_out[11] = chany_top_in[11]; +assign chany_bottom_out[12] = chany_top_in[12]; +assign chany_bottom_out[13] = chany_top_in[13]; +assign chany_bottom_out[14] = chany_top_in[14]; +assign chany_bottom_out[15] = chany_top_in[15]; +assign chany_bottom_out[16] = chany_top_in[16]; +assign chany_bottom_out[17] = chany_top_in[17]; +assign chany_bottom_out[18] = chany_top_in[18]; +assign chany_bottom_out[19] = chany_top_in[19]; +assign chany_bottom_out[20] = chany_top_in[20]; +assign chany_bottom_out[21] = chany_top_in[21]; +assign chany_bottom_out[22] = chany_top_in[22]; +assign chany_bottom_out[23] = chany_top_in[23]; +assign chany_bottom_out[24] = chany_top_in[24]; +assign chany_bottom_out[25] = chany_top_in[25]; +assign chany_bottom_out[26] = chany_top_in[26]; +assign chany_bottom_out[27] = chany_top_in[27]; +assign chany_bottom_out[28] = chany_top_in[28]; +assign chany_bottom_out[29] = chany_top_in[29]; + mux_tree_tapbuf_size12 mux_right_ipin_0 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_right_ipin_0_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_1 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_right_ipin_1_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_2 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_right_ipin_2_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_3 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21], chany_bottom_in[27], chany_top_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_right_ipin_3_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_1__1_.v new file mode 100644 index 0000000..e07ffde --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_1__1_.v @@ -0,0 +1,429 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cby_1__1_ +( + pReset, + prog_clk, + chany_bottom_in, + chany_top_in, + ccff_head, + chany_bottom_out, + chany_top_out, + left_grid_right_width_0_height_0_subtile_0__pin_I4_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_bottom_in; + input [0:29]chany_top_in; + input ccff_head; + output [0:29]chany_bottom_out; + output [0:29]chany_top_out; + output left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_bottom_in; + wire [0:29]chany_top_in; + wire ccff_head; + wire [0:29]chany_bottom_out; + wire [0:29]chany_top_out; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire ccff_tail; + wire [0:3]mux_right_ipin_0_undriven_sram_inv; + wire [0:3]mux_right_ipin_10_undriven_sram_inv; + wire [0:3]mux_right_ipin_11_undriven_sram_inv; + wire [0:3]mux_right_ipin_12_undriven_sram_inv; + wire [0:3]mux_right_ipin_13_undriven_sram_inv; + wire [0:3]mux_right_ipin_14_undriven_sram_inv; + wire [0:3]mux_right_ipin_15_undriven_sram_inv; + wire [0:3]mux_right_ipin_1_undriven_sram_inv; + wire [0:3]mux_right_ipin_2_undriven_sram_inv; + wire [0:3]mux_right_ipin_3_undriven_sram_inv; + wire [0:3]mux_right_ipin_4_undriven_sram_inv; + wire [0:3]mux_right_ipin_5_undriven_sram_inv; + wire [0:3]mux_right_ipin_6_undriven_sram_inv; + wire [0:3]mux_right_ipin_7_undriven_sram_inv; + wire [0:3]mux_right_ipin_8_undriven_sram_inv; + wire [0:3]mux_right_ipin_9_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire [0:3]mux_tree_tapbuf_size10_1_sram; + wire [0:3]mux_tree_tapbuf_size10_2_sram; + wire [0:3]mux_tree_tapbuf_size10_3_sram; + wire [0:3]mux_tree_tapbuf_size10_4_sram; + wire [0:3]mux_tree_tapbuf_size10_5_sram; + wire [0:3]mux_tree_tapbuf_size10_6_sram; + wire [0:3]mux_tree_tapbuf_size10_7_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire [0:3]mux_tree_tapbuf_size12_4_sram; + wire [0:3]mux_tree_tapbuf_size12_5_sram; + wire [0:3]mux_tree_tapbuf_size12_6_sram; + wire [0:3]mux_tree_tapbuf_size12_7_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire mux_tree_tapbuf_size12_mem_7_ccff_tail; + +assign chany_top_out[0] = chany_bottom_in[0]; +assign chany_top_out[1] = chany_bottom_in[1]; +assign chany_top_out[2] = chany_bottom_in[2]; +assign chany_top_out[3] = chany_bottom_in[3]; +assign chany_top_out[4] = chany_bottom_in[4]; +assign chany_top_out[5] = chany_bottom_in[5]; +assign chany_top_out[6] = chany_bottom_in[6]; +assign chany_top_out[7] = chany_bottom_in[7]; +assign chany_top_out[8] = chany_bottom_in[8]; +assign chany_top_out[9] = chany_bottom_in[9]; +assign chany_top_out[10] = chany_bottom_in[10]; +assign chany_top_out[11] = chany_bottom_in[11]; +assign chany_top_out[12] = chany_bottom_in[12]; +assign chany_top_out[13] = chany_bottom_in[13]; +assign chany_top_out[14] = chany_bottom_in[14]; +assign chany_top_out[15] = chany_bottom_in[15]; +assign chany_top_out[16] = chany_bottom_in[16]; +assign chany_top_out[17] = chany_bottom_in[17]; +assign chany_top_out[18] = chany_bottom_in[18]; +assign chany_top_out[19] = chany_bottom_in[19]; +assign chany_top_out[20] = chany_bottom_in[20]; +assign chany_top_out[21] = chany_bottom_in[21]; +assign chany_top_out[22] = chany_bottom_in[22]; +assign chany_top_out[23] = chany_bottom_in[23]; +assign chany_top_out[24] = chany_bottom_in[24]; +assign chany_top_out[25] = chany_bottom_in[25]; +assign chany_top_out[26] = chany_bottom_in[26]; +assign chany_top_out[27] = chany_bottom_in[27]; +assign chany_top_out[28] = chany_bottom_in[28]; +assign chany_top_out[29] = chany_bottom_in[29]; +assign chany_bottom_out[0] = chany_top_in[0]; +assign chany_bottom_out[1] = chany_top_in[1]; +assign chany_bottom_out[2] = chany_top_in[2]; +assign chany_bottom_out[3] = chany_top_in[3]; +assign chany_bottom_out[4] = chany_top_in[4]; +assign chany_bottom_out[5] = chany_top_in[5]; +assign chany_bottom_out[6] = chany_top_in[6]; +assign chany_bottom_out[7] = chany_top_in[7]; +assign chany_bottom_out[8] = chany_top_in[8]; +assign chany_bottom_out[9] = chany_top_in[9]; +assign chany_bottom_out[10] = chany_top_in[10]; +assign chany_bottom_out[11] = chany_top_in[11]; +assign chany_bottom_out[12] = chany_top_in[12]; +assign chany_bottom_out[13] = chany_top_in[13]; +assign chany_bottom_out[14] = chany_top_in[14]; +assign chany_bottom_out[15] = chany_top_in[15]; +assign chany_bottom_out[16] = chany_top_in[16]; +assign chany_bottom_out[17] = chany_top_in[17]; +assign chany_bottom_out[18] = chany_top_in[18]; +assign chany_bottom_out[19] = chany_top_in[19]; +assign chany_bottom_out[20] = chany_top_in[20]; +assign chany_bottom_out[21] = chany_top_in[21]; +assign chany_bottom_out[22] = chany_top_in[22]; +assign chany_bottom_out[23] = chany_top_in[23]; +assign chany_bottom_out[24] = chany_top_in[24]; +assign chany_bottom_out[25] = chany_top_in[25]; +assign chany_bottom_out[26] = chany_top_in[26]; +assign chany_bottom_out[27] = chany_top_in[27]; +assign chany_bottom_out[28] = chany_top_in[28]; +assign chany_bottom_out[29] = chany_top_in[29]; + mux_tree_tapbuf_size12 mux_right_ipin_0 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_right_ipin_0_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_2 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_right_ipin_2_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_4 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_right_ipin_4_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_6 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_right_ipin_6_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_8 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_4_sram), + .sram_inv(mux_right_ipin_8_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_10 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_5_sram), + .sram_inv(mux_right_ipin_10_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_12 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_6_sram), + .sram_inv(mux_right_ipin_12_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_14 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_7_sram), + .sram_inv(mux_right_ipin_14_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram) + ); + mux_tree_tapbuf_size10 mux_right_ipin_1 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_right_ipin_1_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_3 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[27], chany_top_in[27]}), + .sram(mux_tree_tapbuf_size10_1_sram), + .sram_inv(mux_right_ipin_3_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_5 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[29], chany_top_in[29]}), + .sram(mux_tree_tapbuf_size10_2_sram), + .sram_inv(mux_right_ipin_5_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_7 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[22], chany_top_in[22]}), + .sram(mux_tree_tapbuf_size10_3_sram), + .sram_inv(mux_right_ipin_7_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_9 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size10_4_sram), + .sram_inv(mux_right_ipin_9_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_11 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size10_5_sram), + .sram_inv(mux_right_ipin_11_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_13 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size10_6_sram), + .sram_inv(mux_right_ipin_13_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_15 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21]}), + .sram(mux_tree_tapbuf_size10_7_sram), + .sram_inv(mux_right_ipin_15_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_8__1_.v new file mode 100644 index 0000000..3400642 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_8__1_.v @@ -0,0 +1,513 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cby_8__1_ +( + pReset, + prog_clk, + chany_bottom_in, + chany_top_in, + ccff_head, + chany_bottom_out, + chany_top_out, + right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_bottom_in; + input [0:29]chany_top_in; + input ccff_head; + output [0:29]chany_bottom_out; + output [0:29]chany_top_out; + output right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + output right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + output right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + output right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_bottom_in; + wire [0:29]chany_top_in; + wire ccff_head; + wire [0:29]chany_bottom_out; + wire [0:29]chany_top_out; + wire right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire ccff_tail; + wire [0:3]mux_left_ipin_0_undriven_sram_inv; + wire [0:3]mux_left_ipin_1_undriven_sram_inv; + wire [0:3]mux_left_ipin_2_undriven_sram_inv; + wire [0:3]mux_left_ipin_3_undriven_sram_inv; + wire [0:3]mux_right_ipin_0_undriven_sram_inv; + wire [0:3]mux_right_ipin_10_undriven_sram_inv; + wire [0:3]mux_right_ipin_11_undriven_sram_inv; + wire [0:3]mux_right_ipin_12_undriven_sram_inv; + wire [0:3]mux_right_ipin_13_undriven_sram_inv; + wire [0:3]mux_right_ipin_14_undriven_sram_inv; + wire [0:3]mux_right_ipin_15_undriven_sram_inv; + wire [0:3]mux_right_ipin_1_undriven_sram_inv; + wire [0:3]mux_right_ipin_2_undriven_sram_inv; + wire [0:3]mux_right_ipin_3_undriven_sram_inv; + wire [0:3]mux_right_ipin_4_undriven_sram_inv; + wire [0:3]mux_right_ipin_5_undriven_sram_inv; + wire [0:3]mux_right_ipin_6_undriven_sram_inv; + wire [0:3]mux_right_ipin_7_undriven_sram_inv; + wire [0:3]mux_right_ipin_8_undriven_sram_inv; + wire [0:3]mux_right_ipin_9_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire [0:3]mux_tree_tapbuf_size10_1_sram; + wire [0:3]mux_tree_tapbuf_size10_2_sram; + wire [0:3]mux_tree_tapbuf_size10_3_sram; + wire [0:3]mux_tree_tapbuf_size10_4_sram; + wire [0:3]mux_tree_tapbuf_size10_5_sram; + wire [0:3]mux_tree_tapbuf_size10_6_sram; + wire [0:3]mux_tree_tapbuf_size10_7_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_10_sram; + wire [0:3]mux_tree_tapbuf_size12_11_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire [0:3]mux_tree_tapbuf_size12_4_sram; + wire [0:3]mux_tree_tapbuf_size12_5_sram; + wire [0:3]mux_tree_tapbuf_size12_6_sram; + wire [0:3]mux_tree_tapbuf_size12_7_sram; + wire [0:3]mux_tree_tapbuf_size12_8_sram; + wire [0:3]mux_tree_tapbuf_size12_9_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_10_ccff_tail; + wire mux_tree_tapbuf_size12_mem_11_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire mux_tree_tapbuf_size12_mem_7_ccff_tail; + wire mux_tree_tapbuf_size12_mem_8_ccff_tail; + wire mux_tree_tapbuf_size12_mem_9_ccff_tail; + +assign chany_top_out[0] = chany_bottom_in[0]; +assign chany_top_out[1] = chany_bottom_in[1]; +assign chany_top_out[2] = chany_bottom_in[2]; +assign chany_top_out[3] = chany_bottom_in[3]; +assign chany_top_out[4] = chany_bottom_in[4]; +assign chany_top_out[5] = chany_bottom_in[5]; +assign chany_top_out[6] = chany_bottom_in[6]; +assign chany_top_out[7] = chany_bottom_in[7]; +assign chany_top_out[8] = chany_bottom_in[8]; +assign chany_top_out[9] = chany_bottom_in[9]; +assign chany_top_out[10] = chany_bottom_in[10]; +assign chany_top_out[11] = chany_bottom_in[11]; +assign chany_top_out[12] = chany_bottom_in[12]; +assign chany_top_out[13] = chany_bottom_in[13]; +assign chany_top_out[14] = chany_bottom_in[14]; +assign chany_top_out[15] = chany_bottom_in[15]; +assign chany_top_out[16] = chany_bottom_in[16]; +assign chany_top_out[17] = chany_bottom_in[17]; +assign chany_top_out[18] = chany_bottom_in[18]; +assign chany_top_out[19] = chany_bottom_in[19]; +assign chany_top_out[20] = chany_bottom_in[20]; +assign chany_top_out[21] = chany_bottom_in[21]; +assign chany_top_out[22] = chany_bottom_in[22]; +assign chany_top_out[23] = chany_bottom_in[23]; +assign chany_top_out[24] = chany_bottom_in[24]; +assign chany_top_out[25] = chany_bottom_in[25]; +assign chany_top_out[26] = chany_bottom_in[26]; +assign chany_top_out[27] = chany_bottom_in[27]; +assign chany_top_out[28] = chany_bottom_in[28]; +assign chany_top_out[29] = chany_bottom_in[29]; +assign chany_bottom_out[0] = chany_top_in[0]; +assign chany_bottom_out[1] = chany_top_in[1]; +assign chany_bottom_out[2] = chany_top_in[2]; +assign chany_bottom_out[3] = chany_top_in[3]; +assign chany_bottom_out[4] = chany_top_in[4]; +assign chany_bottom_out[5] = chany_top_in[5]; +assign chany_bottom_out[6] = chany_top_in[6]; +assign chany_bottom_out[7] = chany_top_in[7]; +assign chany_bottom_out[8] = chany_top_in[8]; +assign chany_bottom_out[9] = chany_top_in[9]; +assign chany_bottom_out[10] = chany_top_in[10]; +assign chany_bottom_out[11] = chany_top_in[11]; +assign chany_bottom_out[12] = chany_top_in[12]; +assign chany_bottom_out[13] = chany_top_in[13]; +assign chany_bottom_out[14] = chany_top_in[14]; +assign chany_bottom_out[15] = chany_top_in[15]; +assign chany_bottom_out[16] = chany_top_in[16]; +assign chany_bottom_out[17] = chany_top_in[17]; +assign chany_bottom_out[18] = chany_top_in[18]; +assign chany_bottom_out[19] = chany_top_in[19]; +assign chany_bottom_out[20] = chany_top_in[20]; +assign chany_bottom_out[21] = chany_top_in[21]; +assign chany_bottom_out[22] = chany_top_in[22]; +assign chany_bottom_out[23] = chany_top_in[23]; +assign chany_bottom_out[24] = chany_top_in[24]; +assign chany_bottom_out[25] = chany_top_in[25]; +assign chany_bottom_out[26] = chany_top_in[26]; +assign chany_bottom_out[27] = chany_top_in[27]; +assign chany_bottom_out[28] = chany_top_in[28]; +assign chany_bottom_out[29] = chany_top_in[29]; + mux_tree_tapbuf_size12 mux_left_ipin_0 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_left_ipin_0_undriven_sram_inv), + .out(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_left_ipin_1 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_left_ipin_1_undriven_sram_inv), + .out(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_left_ipin_2 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_left_ipin_2_undriven_sram_inv), + .out(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_left_ipin_3 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21], chany_bottom_in[27], chany_top_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_left_ipin_3_undriven_sram_inv), + .out(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_0 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_4_sram), + .sram_inv(mux_right_ipin_0_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_2 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_5_sram), + .sram_inv(mux_right_ipin_2_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_4 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_6_sram), + .sram_inv(mux_right_ipin_4_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_6 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_7_sram), + .sram_inv(mux_right_ipin_6_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_8 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_8_sram), + .sram_inv(mux_right_ipin_8_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_10 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_9_sram), + .sram_inv(mux_right_ipin_10_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_12 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_10_sram), + .sram_inv(mux_right_ipin_12_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_14 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_11_sram), + .sram_inv(mux_right_ipin_14_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_) + ); + mux_tree_tapbuf_size12_mem mem_left_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_left_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_left_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_left_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_8_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_9_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_10_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_11_sram) + ); + mux_tree_tapbuf_size10 mux_right_ipin_1 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[29], chany_top_in[29]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_right_ipin_1_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_3 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[22], chany_top_in[22]}), + .sram(mux_tree_tapbuf_size10_1_sram), + .sram_inv(mux_right_ipin_3_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_5 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size10_2_sram), + .sram_inv(mux_right_ipin_5_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_7 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size10_3_sram), + .sram_inv(mux_right_ipin_7_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_9 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size10_4_sram), + .sram_inv(mux_right_ipin_9_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_11 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21]}), + .sram(mux_tree_tapbuf_size10_5_sram), + .sram_inv(mux_right_ipin_11_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_13 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[23], chany_top_in[23]}), + .sram(mux_tree_tapbuf_size10_6_sram), + .sram_inv(mux_right_ipin_13_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_15 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size10_7_sram), + .sram_inv(mux_right_ipin_15_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__0_.v new file mode 100644 index 0000000..cbaa50a --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__0_.v @@ -0,0 +1,729 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_0__0_ +( + pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + chanx_right_in, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_right_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_top_in; + input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + input [0:29]chanx_right_in; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + input ccff_head; + output [0:29]chany_top_out; + output [0:29]chanx_right_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_top_in; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire [0:29]chanx_right_in; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head; + wire [0:29]chany_top_out; + wire [0:29]chanx_right_out; + wire ccff_tail; + wire [0:1]mux_right_track_0_undriven_sram_inv; + wire [0:1]mux_right_track_10_undriven_sram_inv; + wire [0:1]mux_right_track_12_undriven_sram_inv; + wire [0:1]mux_right_track_14_undriven_sram_inv; + wire [0:1]mux_right_track_16_undriven_sram_inv; + wire [0:1]mux_right_track_18_undriven_sram_inv; + wire [0:1]mux_right_track_28_undriven_sram_inv; + wire [0:1]mux_right_track_2_undriven_sram_inv; + wire [0:1]mux_right_track_30_undriven_sram_inv; + wire [0:1]mux_right_track_32_undriven_sram_inv; + wire [0:1]mux_right_track_34_undriven_sram_inv; + wire [0:1]mux_right_track_44_undriven_sram_inv; + wire [0:1]mux_right_track_46_undriven_sram_inv; + wire [0:1]mux_right_track_48_undriven_sram_inv; + wire [0:1]mux_right_track_4_undriven_sram_inv; + wire [0:1]mux_right_track_50_undriven_sram_inv; + wire [0:1]mux_right_track_6_undriven_sram_inv; + wire [0:1]mux_right_track_8_undriven_sram_inv; + wire [0:1]mux_top_track_0_undriven_sram_inv; + wire [0:1]mux_top_track_10_undriven_sram_inv; + wire [0:1]mux_top_track_12_undriven_sram_inv; + wire [0:1]mux_top_track_14_undriven_sram_inv; + wire [0:1]mux_top_track_16_undriven_sram_inv; + wire [0:1]mux_top_track_18_undriven_sram_inv; + wire [0:1]mux_top_track_28_undriven_sram_inv; + wire [0:1]mux_top_track_2_undriven_sram_inv; + wire [0:1]mux_top_track_30_undriven_sram_inv; + wire [0:1]mux_top_track_32_undriven_sram_inv; + wire [0:1]mux_top_track_34_undriven_sram_inv; + wire [0:1]mux_top_track_44_undriven_sram_inv; + wire [0:1]mux_top_track_46_undriven_sram_inv; + wire [0:1]mux_top_track_48_undriven_sram_inv; + wire [0:1]mux_top_track_4_undriven_sram_inv; + wire [0:1]mux_top_track_50_undriven_sram_inv; + wire [0:1]mux_top_track_6_undriven_sram_inv; + wire [0:1]mux_top_track_8_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_11_sram; + wire [0:1]mux_tree_tapbuf_size2_12_sram; + wire [0:1]mux_tree_tapbuf_size2_13_sram; + wire [0:1]mux_tree_tapbuf_size2_14_sram; + wire [0:1]mux_tree_tapbuf_size2_15_sram; + wire [0:1]mux_tree_tapbuf_size2_16_sram; + wire [0:1]mux_tree_tapbuf_size2_17_sram; + wire [0:1]mux_tree_tapbuf_size2_18_sram; + wire [0:1]mux_tree_tapbuf_size2_19_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_20_sram; + wire [0:1]mux_tree_tapbuf_size2_21_sram; + wire [0:1]mux_tree_tapbuf_size2_22_sram; + wire [0:1]mux_tree_tapbuf_size2_23_sram; + wire [0:1]mux_tree_tapbuf_size2_24_sram; + wire [0:1]mux_tree_tapbuf_size2_25_sram; + wire [0:1]mux_tree_tapbuf_size2_26_sram; + wire [0:1]mux_tree_tapbuf_size2_27_sram; + wire [0:1]mux_tree_tapbuf_size2_28_sram; + wire [0:1]mux_tree_tapbuf_size2_29_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_30_sram; + wire [0:1]mux_tree_tapbuf_size2_31_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire mux_tree_tapbuf_size2_mem_19_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_20_ccff_tail; + wire mux_tree_tapbuf_size2_mem_21_ccff_tail; + wire mux_tree_tapbuf_size2_mem_22_ccff_tail; + wire mux_tree_tapbuf_size2_mem_23_ccff_tail; + wire mux_tree_tapbuf_size2_mem_24_ccff_tail; + wire mux_tree_tapbuf_size2_mem_25_ccff_tail; + wire mux_tree_tapbuf_size2_mem_26_ccff_tail; + wire mux_tree_tapbuf_size2_mem_27_ccff_tail; + wire mux_tree_tapbuf_size2_mem_28_ccff_tail; + wire mux_tree_tapbuf_size2_mem_29_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_30_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + +assign chanx_right_out[10] = chany_top_in[9]; +assign chanx_right_out[11] = chany_top_in[10]; +assign chanx_right_out[12] = chany_top_in[11]; +assign chanx_right_out[13] = chany_top_in[12]; +assign chanx_right_out[18] = chany_top_in[17]; +assign chanx_right_out[19] = chany_top_in[18]; +assign chanx_right_out[20] = chany_top_in[19]; +assign chanx_right_out[21] = chany_top_in[20]; +assign chanx_right_out[26] = chany_top_in[25]; +assign chanx_right_out[27] = chany_top_in[26]; +assign chanx_right_out[28] = chany_top_in[27]; +assign chanx_right_out[29] = chany_top_in[28]; +assign chany_top_out[29] = chanx_right_in[0]; +assign chany_top_out[10] = chanx_right_in[11]; +assign chany_top_out[11] = chanx_right_in[12]; +assign chany_top_out[12] = chanx_right_in[13]; +assign chany_top_out[13] = chanx_right_in[14]; +assign chany_top_out[18] = chanx_right_in[19]; +assign chany_top_out[19] = chanx_right_in[20]; +assign chany_top_out[20] = chanx_right_in[21]; +assign chany_top_out[21] = chanx_right_in[22]; +assign chany_top_out[26] = chanx_right_in[27]; +assign chany_top_out[27] = chanx_right_in[28]; +assign chany_top_out[28] = chanx_right_in[29]; + mux_tree_tapbuf_size3 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[1]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size3 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[4]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); + mux_tree_tapbuf_size3 mux_right_track_0 + ( + .in({chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size3 mux_right_track_6 + ( + .in({chany_top_in[2], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size3_mem mem_top_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size2 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[2]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size2 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[3]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size2 mux_top_track_8 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[5]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_top_track_8_undriven_sram_inv), + .out(chany_top_out[4]) + ); + mux_tree_tapbuf_size2 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[6]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size2 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[7]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size2 mux_top_track_14 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[8]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_top_track_14_undriven_sram_inv), + .out(chany_top_out[7]) + ); + mux_tree_tapbuf_size2 mux_top_track_16 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[9]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_top_track_16_undriven_sram_inv), + .out(chany_top_out[8]) + ); + mux_tree_tapbuf_size2 mux_top_track_18 + ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[10]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_top_track_18_undriven_sram_inv), + .out(chany_top_out[9]) + ); + mux_tree_tapbuf_size2 mux_top_track_28 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[15]}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size2 mux_top_track_30 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[16]}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_top_track_30_undriven_sram_inv), + .out(chany_top_out[15]) + ); + mux_tree_tapbuf_size2 mux_top_track_32 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[17]}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_top_track_32_undriven_sram_inv), + .out(chany_top_out[16]) + ); + mux_tree_tapbuf_size2 mux_top_track_34 + ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[18]}), + .sram(mux_tree_tapbuf_size2_11_sram), + .sram_inv(mux_top_track_34_undriven_sram_inv), + .out(chany_top_out[17]) + ); + mux_tree_tapbuf_size2 mux_top_track_44 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[23]}), + .sram(mux_tree_tapbuf_size2_12_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size2 mux_top_track_46 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size2_13_sram), + .sram_inv(mux_top_track_46_undriven_sram_inv), + .out(chany_top_out[23]) + ); + mux_tree_tapbuf_size2 mux_top_track_48 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size2_14_sram), + .sram_inv(mux_top_track_48_undriven_sram_inv), + .out(chany_top_out[24]) + ); + mux_tree_tapbuf_size2 mux_top_track_50 + ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size2_15_sram), + .sram_inv(mux_top_track_50_undriven_sram_inv), + .out(chany_top_out[25]) + ); + mux_tree_tapbuf_size2 mux_right_track_2 + ( + .in({chany_top_in[0], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_16_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size2 mux_right_track_4 + ( + .in({chany_top_in[1], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_17_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size2 mux_right_track_8 + ( + .in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_18_sram), + .sram_inv(mux_right_track_8_undriven_sram_inv), + .out(chanx_right_out[4]) + ); + mux_tree_tapbuf_size2 mux_right_track_10 + ( + .in({chany_top_in[4], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_19_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size2 mux_right_track_12 + ( + .in({chany_top_in[5], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_20_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size2 mux_right_track_14 + ( + .in({chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram), + .sram_inv(mux_right_track_14_undriven_sram_inv), + .out(chanx_right_out[7]) + ); + mux_tree_tapbuf_size2 mux_right_track_16 + ( + .in({chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_22_sram), + .sram_inv(mux_right_track_16_undriven_sram_inv), + .out(chanx_right_out[8]) + ); + mux_tree_tapbuf_size2 mux_right_track_18 + ( + .in({chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_23_sram), + .sram_inv(mux_right_track_18_undriven_sram_inv), + .out(chanx_right_out[9]) + ); + mux_tree_tapbuf_size2 mux_right_track_28 + ( + .in({chany_top_in[13], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_24_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size2 mux_right_track_30 + ( + .in({chany_top_in[14], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_25_sram), + .sram_inv(mux_right_track_30_undriven_sram_inv), + .out(chanx_right_out[15]) + ); + mux_tree_tapbuf_size2 mux_right_track_32 + ( + .in({chany_top_in[15], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_26_sram), + .sram_inv(mux_right_track_32_undriven_sram_inv), + .out(chanx_right_out[16]) + ); + mux_tree_tapbuf_size2 mux_right_track_34 + ( + .in({chany_top_in[16], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_27_sram), + .sram_inv(mux_right_track_34_undriven_sram_inv), + .out(chanx_right_out[17]) + ); + mux_tree_tapbuf_size2 mux_right_track_44 + ( + .in({chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_28_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size2 mux_right_track_46 + ( + .in({chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_29_sram), + .sram_inv(mux_right_track_46_undriven_sram_inv), + .out(chanx_right_out[23]) + ); + mux_tree_tapbuf_size2 mux_right_track_48 + ( + .in({chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_30_sram), + .sram_inv(mux_right_track_48_undriven_sram_inv), + .out(chanx_right_out[24]) + ); + mux_tree_tapbuf_size2 mux_right_track_50 + ( + .in({chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_31_sram), + .sram_inv(mux_right_track_50_undriven_sram_inv), + .out(chanx_right_out[25]) + ); + mux_tree_tapbuf_size2_mem mem_top_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_16 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_18 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_30 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_32 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_34 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_46 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_48 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_50 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_16 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_18 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_30 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_25_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_32 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_26_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_34 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_27_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_28_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_28_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_46 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_28_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_29_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_29_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_48 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_29_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_30_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_30_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_50 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_30_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_31_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__1_.v new file mode 100644 index 0000000..d28f361 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__1_.v @@ -0,0 +1,1026 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_0__1_ +( + pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + chanx_right_in, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + chany_bottom_in, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_right_out, + chany_bottom_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_top_in; + input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + input [0:29]chanx_right_in; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input [0:29]chany_bottom_in; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + input ccff_head; + output [0:29]chany_top_out; + output [0:29]chanx_right_out; + output [0:29]chany_bottom_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_top_in; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire [0:29]chanx_right_in; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire [0:29]chany_bottom_in; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head; + wire [0:29]chany_top_out; + wire [0:29]chanx_right_out; + wire [0:29]chany_bottom_out; + wire ccff_tail; + wire [0:2]mux_bottom_track_11_undriven_sram_inv; + wire [0:2]mux_bottom_track_13_undriven_sram_inv; + wire [0:2]mux_bottom_track_1_undriven_sram_inv; + wire [0:2]mux_bottom_track_21_undriven_sram_inv; + wire [0:2]mux_bottom_track_29_undriven_sram_inv; + wire [0:2]mux_bottom_track_37_undriven_sram_inv; + wire [0:2]mux_bottom_track_3_undriven_sram_inv; + wire [0:2]mux_bottom_track_45_undriven_sram_inv; + wire [0:1]mux_bottom_track_53_undriven_sram_inv; + wire [0:2]mux_bottom_track_5_undriven_sram_inv; + wire [0:2]mux_bottom_track_7_undriven_sram_inv; + wire [0:2]mux_right_track_0_undriven_sram_inv; + wire [0:2]mux_right_track_10_undriven_sram_inv; + wire [0:2]mux_right_track_12_undriven_sram_inv; + wire [0:2]mux_right_track_14_undriven_sram_inv; + wire [0:2]mux_right_track_16_undriven_sram_inv; + wire [0:2]mux_right_track_18_undriven_sram_inv; + wire [0:2]mux_right_track_20_undriven_sram_inv; + wire [0:2]mux_right_track_22_undriven_sram_inv; + wire [0:1]mux_right_track_24_undriven_sram_inv; + wire [0:1]mux_right_track_26_undriven_sram_inv; + wire [0:1]mux_right_track_28_undriven_sram_inv; + wire [0:2]mux_right_track_2_undriven_sram_inv; + wire [0:1]mux_right_track_30_undriven_sram_inv; + wire [0:1]mux_right_track_32_undriven_sram_inv; + wire [0:1]mux_right_track_34_undriven_sram_inv; + wire [0:2]mux_right_track_36_undriven_sram_inv; + wire [0:1]mux_right_track_38_undriven_sram_inv; + wire [0:1]mux_right_track_40_undriven_sram_inv; + wire [0:1]mux_right_track_44_undriven_sram_inv; + wire [0:1]mux_right_track_46_undriven_sram_inv; + wire [0:1]mux_right_track_48_undriven_sram_inv; + wire [0:2]mux_right_track_4_undriven_sram_inv; + wire [0:1]mux_right_track_50_undriven_sram_inv; + wire [0:1]mux_right_track_52_undriven_sram_inv; + wire [0:1]mux_right_track_54_undriven_sram_inv; + wire [0:1]mux_right_track_56_undriven_sram_inv; + wire [0:2]mux_right_track_6_undriven_sram_inv; + wire [0:2]mux_right_track_8_undriven_sram_inv; + wire [0:2]mux_top_track_0_undriven_sram_inv; + wire [0:2]mux_top_track_10_undriven_sram_inv; + wire [0:2]mux_top_track_12_undriven_sram_inv; + wire [0:2]mux_top_track_20_undriven_sram_inv; + wire [0:2]mux_top_track_28_undriven_sram_inv; + wire [0:2]mux_top_track_2_undriven_sram_inv; + wire [0:2]mux_top_track_36_undriven_sram_inv; + wire [0:1]mux_top_track_44_undriven_sram_inv; + wire [0:2]mux_top_track_4_undriven_sram_inv; + wire [0:2]mux_top_track_52_undriven_sram_inv; + wire [0:2]mux_top_track_6_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire [0:1]mux_tree_tapbuf_size3_7_sram; + wire [0:1]mux_tree_tapbuf_size3_8_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire mux_tree_tapbuf_size3_mem_7_ccff_tail; + wire [0:2]mux_tree_tapbuf_size4_0_sram; + wire [0:2]mux_tree_tapbuf_size4_1_sram; + wire [0:2]mux_tree_tapbuf_size4_2_sram; + wire [0:2]mux_tree_tapbuf_size4_3_sram; + wire [0:2]mux_tree_tapbuf_size4_4_sram; + wire [0:2]mux_tree_tapbuf_size4_5_sram; + wire [0:2]mux_tree_tapbuf_size4_6_sram; + wire [0:2]mux_tree_tapbuf_size4_7_sram; + wire [0:2]mux_tree_tapbuf_size4_8_sram; + wire [0:2]mux_tree_tapbuf_size4_9_sram; + wire mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire mux_tree_tapbuf_size4_mem_4_ccff_tail; + wire mux_tree_tapbuf_size4_mem_5_ccff_tail; + wire mux_tree_tapbuf_size4_mem_6_ccff_tail; + wire mux_tree_tapbuf_size4_mem_7_ccff_tail; + wire mux_tree_tapbuf_size4_mem_8_ccff_tail; + wire mux_tree_tapbuf_size4_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire [0:2]mux_tree_tapbuf_size5_5_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire mux_tree_tapbuf_size5_mem_5_ccff_tail; + wire [0:2]mux_tree_tapbuf_size6_0_sram; + wire [0:2]mux_tree_tapbuf_size6_10_sram; + wire [0:2]mux_tree_tapbuf_size6_11_sram; + wire [0:2]mux_tree_tapbuf_size6_1_sram; + wire [0:2]mux_tree_tapbuf_size6_2_sram; + wire [0:2]mux_tree_tapbuf_size6_3_sram; + wire [0:2]mux_tree_tapbuf_size6_4_sram; + wire [0:2]mux_tree_tapbuf_size6_5_sram; + wire [0:2]mux_tree_tapbuf_size6_6_sram; + wire [0:2]mux_tree_tapbuf_size6_7_sram; + wire [0:2]mux_tree_tapbuf_size6_8_sram; + wire [0:2]mux_tree_tapbuf_size6_9_sram; + wire mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire mux_tree_tapbuf_size6_mem_10_ccff_tail; + wire mux_tree_tapbuf_size6_mem_11_ccff_tail; + wire mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire mux_tree_tapbuf_size6_mem_7_ccff_tail; + wire mux_tree_tapbuf_size6_mem_8_ccff_tail; + wire mux_tree_tapbuf_size6_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size7_0_sram; + wire [0:2]mux_tree_tapbuf_size7_1_sram; + wire [0:2]mux_tree_tapbuf_size7_2_sram; + wire [0:2]mux_tree_tapbuf_size7_3_sram; + wire [0:2]mux_tree_tapbuf_size7_4_sram; + wire mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire mux_tree_tapbuf_size7_mem_4_ccff_tail; + +assign chany_bottom_out[4] = chany_top_in[3]; +assign chany_bottom_out[7] = chany_top_in[6]; +assign chany_bottom_out[8] = chany_top_in[7]; +assign chany_bottom_out[9] = chany_top_in[8]; +assign chany_bottom_out[11] = chany_top_in[10]; +assign chany_bottom_out[12] = chany_top_in[11]; +assign chany_bottom_out[13] = chany_top_in[12]; +assign chany_bottom_out[15] = chany_top_in[14]; +assign chany_bottom_out[16] = chany_top_in[15]; +assign chany_bottom_out[17] = chany_top_in[16]; +assign chany_bottom_out[19] = chany_top_in[18]; +assign chany_bottom_out[20] = chany_top_in[19]; +assign chany_bottom_out[21] = chany_top_in[20]; +assign chany_bottom_out[23] = chany_top_in[22]; +assign chany_bottom_out[24] = chany_top_in[23]; +assign chany_bottom_out[25] = chany_top_in[24]; +assign chany_bottom_out[27] = chany_top_in[26]; +assign chany_bottom_out[28] = chany_top_in[27]; +assign chany_bottom_out[29] = chany_top_in[28]; +assign chany_top_out[4] = chany_bottom_in[3]; +assign chany_top_out[7] = chany_bottom_in[6]; +assign chany_top_out[8] = chany_bottom_in[7]; +assign chany_top_out[9] = chany_bottom_in[8]; +assign chany_top_out[11] = chany_bottom_in[10]; +assign chany_top_out[12] = chany_bottom_in[11]; +assign chany_top_out[13] = chany_bottom_in[12]; +assign chany_top_out[15] = chany_bottom_in[14]; +assign chany_top_out[16] = chany_bottom_in[15]; +assign chany_top_out[17] = chany_bottom_in[16]; +assign chanx_right_out[21] = chany_bottom_in[17]; +assign chany_top_out[19] = chany_bottom_in[18]; +assign chany_top_out[20] = chany_bottom_in[19]; +assign chany_top_out[21] = chany_bottom_in[20]; +assign chany_top_out[23] = chany_bottom_in[22]; +assign chany_top_out[24] = chany_bottom_in[23]; +assign chany_top_out[25] = chany_bottom_in[24]; +assign chany_top_out[27] = chany_bottom_in[26]; +assign chany_top_out[28] = chany_bottom_in[27]; +assign chany_top_out[29] = chany_bottom_in[28]; + mux_tree_tapbuf_size7 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[1], chanx_right_in[12], chanx_right_in[23], chany_bottom_in[3], chany_bottom_in[19]}), + .sram(mux_tree_tapbuf_size7_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size7 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[4], chanx_right_in[15], chanx_right_in[26], chany_bottom_in[8], chany_bottom_in[23]}), + .sram(mux_tree_tapbuf_size7_1_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); + mux_tree_tapbuf_size7 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[5], chanx_right_in[16], chanx_right_in[27], chany_bottom_in[10], chany_bottom_in[24]}), + .sram(mux_tree_tapbuf_size7_2_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size7 mux_bottom_track_7 + ( + .in({chany_top_in[8], chany_top_in[23], chanx_right_in[6], chanx_right_in[17], chanx_right_in[28], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_3_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size7 mux_bottom_track_11 + ( + .in({chany_top_in[10], chany_top_in[24], chanx_right_in[5], chanx_right_in[16], chanx_right_in[27], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_4_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size7_mem mem_top_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram) + ); + mux_tree_tapbuf_size7_mem mem_top_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram) + ); + mux_tree_tapbuf_size7_mem mem_top_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram) + ); + mux_tree_tapbuf_size7_mem mem_bottom_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram) + ); + mux_tree_tapbuf_size7_mem mem_bottom_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram) + ); + mux_tree_tapbuf_size6 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[2], chanx_right_in[13], chanx_right_in[24], chany_bottom_in[6], chany_bottom_in[20]}), + .sram(mux_tree_tapbuf_size6_0_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size6 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[3], chanx_right_in[14], chanx_right_in[25], chany_bottom_in[7], chany_bottom_in[22]}), + .sram(mux_tree_tapbuf_size6_1_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size6 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[6], chanx_right_in[17], chanx_right_in[28], chany_bottom_in[11], chany_bottom_in[26]}), + .sram(mux_tree_tapbuf_size6_2_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size6 mux_top_track_20 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[7], chanx_right_in[18], chanx_right_in[29], chany_bottom_in[12], chany_bottom_in[27]}), + .sram(mux_tree_tapbuf_size6_3_sram), + .sram_inv(mux_top_track_20_undriven_sram_inv), + .out(chany_top_out[10]) + ); + mux_tree_tapbuf_size6 mux_right_track_2 + ( + .in({chany_top_in[0], chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[6]}), + .sram(mux_tree_tapbuf_size6_4_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size6 mux_right_track_6 + ( + .in({chany_top_in[2], chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[8]}), + .sram(mux_tree_tapbuf_size6_5_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size6 mux_right_track_8 + ( + .in({chany_top_in[4], chany_top_in[10], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[10]}), + .sram(mux_tree_tapbuf_size6_6_sram), + .sram_inv(mux_right_track_8_undriven_sram_inv), + .out(chanx_right_out[4]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_1 + ( + .in({chany_top_in[3], chany_top_in[19], chanx_right_in[9], chanx_right_in[20], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_7_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_5 + ( + .in({chany_top_in[7], chany_top_in[22], chanx_right_in[7], chanx_right_in[18], chanx_right_in[29], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_8_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_13 + ( + .in({chany_top_in[11], chany_top_in[26], chanx_right_in[4], chanx_right_in[15], chanx_right_in[26], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_9_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_21 + ( + .in({chany_top_in[12], chany_top_in[27], chanx_right_in[3], chanx_right_in[14], chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_10_sram), + .sram_inv(mux_bottom_track_21_undriven_sram_inv), + .out(chany_bottom_out[10]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_29 + ( + .in({chany_top_in[14], chany_top_in[28], chanx_right_in[2], chanx_right_in[13], chanx_right_in[24], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_11_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size6_mem mem_top_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_11_sram) + ); + mux_tree_tapbuf_size5 mux_top_track_28 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[8], chanx_right_in[19], chany_bottom_in[14], chany_bottom_in[28]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size5 mux_right_track_0 + ( + .in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[3]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size5 mux_right_track_4 + ( + .in({chany_top_in[1], chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[7]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size5 mux_right_track_10 + ( + .in({chany_top_in[5], chany_top_in[11], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[11]}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_3 + ( + .in({chany_top_in[6], chany_top_in[20], chanx_right_in[8], chanx_right_in[19], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_37 + ( + .in({chany_top_in[15], chanx_right_in[1], chanx_right_in[12], chanx_right_in[23], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_5_sram), + .sram_inv(mux_bottom_track_37_undriven_sram_inv), + .out(chany_bottom_out[18]) + ); + mux_tree_tapbuf_size5_mem mem_top_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram) + ); + mux_tree_tapbuf_size4 mux_top_track_36 + ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[9], chanx_right_in[20], chany_bottom_in[15]}), + .sram(mux_tree_tapbuf_size4_0_sram), + .sram_inv(mux_top_track_36_undriven_sram_inv), + .out(chany_top_out[18]) + ); + mux_tree_tapbuf_size4 mux_top_track_52 + ( + .in({chanx_right_in[0], chanx_right_in[11], chanx_right_in[22], chany_bottom_in[18]}), + .sram(mux_tree_tapbuf_size4_1_sram), + .sram_inv(mux_top_track_52_undriven_sram_inv), + .out(chany_top_out[26]) + ); + mux_tree_tapbuf_size4 mux_right_track_12 + ( + .in({chany_top_in[9], chany_top_in[12], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[12]}), + .sram(mux_tree_tapbuf_size4_2_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size4 mux_right_track_14 + ( + .in({chany_top_in[13], chany_top_in[14], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[14]}), + .sram(mux_tree_tapbuf_size4_3_sram), + .sram_inv(mux_right_track_14_undriven_sram_inv), + .out(chanx_right_out[7]) + ); + mux_tree_tapbuf_size4 mux_right_track_16 + ( + .in({chany_top_in[15], chany_top_in[17], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[15]}), + .sram(mux_tree_tapbuf_size4_4_sram), + .sram_inv(mux_right_track_16_undriven_sram_inv), + .out(chanx_right_out[8]) + ); + mux_tree_tapbuf_size4 mux_right_track_18 + ( + .in({chany_top_in[16], chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[16]}), + .sram(mux_tree_tapbuf_size4_5_sram), + .sram_inv(mux_right_track_18_undriven_sram_inv), + .out(chanx_right_out[9]) + ); + mux_tree_tapbuf_size4 mux_right_track_20 + ( + .in({chany_top_in[18], chany_top_in[25], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[18]}), + .sram(mux_tree_tapbuf_size4_6_sram), + .sram_inv(mux_right_track_20_undriven_sram_inv), + .out(chanx_right_out[10]) + ); + mux_tree_tapbuf_size4 mux_right_track_22 + ( + .in({chany_top_in[19], chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[19]}), + .sram(mux_tree_tapbuf_size4_7_sram), + .sram_inv(mux_right_track_22_undriven_sram_inv), + .out(chanx_right_out[11]) + ); + mux_tree_tapbuf_size4 mux_right_track_36 + ( + .in({chany_top_in[28], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[28], chany_bottom_in[29]}), + .sram(mux_tree_tapbuf_size4_8_sram), + .sram_inv(mux_right_track_36_undriven_sram_inv), + .out(chanx_right_out[18]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_45 + ( + .in({chany_top_in[16], chanx_right_in[0], chanx_right_in[11], chanx_right_in[22]}), + .sram(mux_tree_tapbuf_size4_9_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size4_mem mem_top_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram) + ); + mux_tree_tapbuf_size4_mem mem_top_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_16 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_18 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_6_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_22 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_7_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_8_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_9_sram) + ); + mux_tree_tapbuf_size3 mux_top_track_44 + ( + .in({chanx_right_in[10], chanx_right_in[21], chany_bottom_in[16]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size3 mux_right_track_24 + ( + .in({chany_top_in[20], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[20]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_right_track_24_undriven_sram_inv), + .out(chanx_right_out[12]) + ); + mux_tree_tapbuf_size3 mux_right_track_26 + ( + .in({chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[22]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_right_track_26_undriven_sram_inv), + .out(chanx_right_out[13]) + ); + mux_tree_tapbuf_size3 mux_right_track_28 + ( + .in({chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[23]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size3 mux_right_track_30 + ( + .in({chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[24]}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_right_track_30_undriven_sram_inv), + .out(chanx_right_out[15]) + ); + mux_tree_tapbuf_size3 mux_right_track_32 + ( + .in({chany_top_in[26], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[26]}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_right_track_32_undriven_sram_inv), + .out(chanx_right_out[16]) + ); + mux_tree_tapbuf_size3 mux_right_track_34 + ( + .in({chany_top_in[27], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[27]}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_right_track_34_undriven_sram_inv), + .out(chanx_right_out[17]) + ); + mux_tree_tapbuf_size3 mux_right_track_50 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[4]}), + .sram(mux_tree_tapbuf_size3_7_sram), + .sram_inv(mux_right_track_50_undriven_sram_inv), + .out(chanx_right_out[25]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_53 + ( + .in({chany_top_in[18], chanx_right_in[10], chanx_right_in[21]}), + .sram(mux_tree_tapbuf_size3_8_sram), + .sram_inv(mux_bottom_track_53_undriven_sram_inv), + .out(chany_bottom_out[26]) + ); + mux_tree_tapbuf_size3_mem mem_top_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_24 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_26 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_30 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_32 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_34 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_50 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_9_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram) + ); + mux_tree_tapbuf_size2 mux_right_track_38 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[25]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_right_track_38_undriven_sram_inv), + .out(chanx_right_out[19]) + ); + mux_tree_tapbuf_size2 mux_right_track_40 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[21]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_right_track_40_undriven_sram_inv), + .out(chanx_right_out[20]) + ); + mux_tree_tapbuf_size2 mux_right_track_44 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[13]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size2 mux_right_track_46 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[9]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_right_track_46_undriven_sram_inv), + .out(chanx_right_out[23]) + ); + mux_tree_tapbuf_size2 mux_right_track_48 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[5]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_right_track_48_undriven_sram_inv), + .out(chanx_right_out[24]) + ); + mux_tree_tapbuf_size2 mux_right_track_52 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[2]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_right_track_52_undriven_sram_inv), + .out(chanx_right_out[26]) + ); + mux_tree_tapbuf_size2 mux_right_track_54 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[1]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_right_track_54_undriven_sram_inv), + .out(chanx_right_out[27]) + ); + mux_tree_tapbuf_size2 mux_right_track_56 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[0]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_right_track_56_undriven_sram_inv), + .out(chanx_right_out[28]) + ); + mux_tree_tapbuf_size2_mem mem_right_track_38 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_40 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_46 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_48 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_54 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_56 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__8_.v new file mode 100644 index 0000000..a9fc3df --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__8_.v @@ -0,0 +1,957 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_0__8_ +( + pReset, + prog_clk, + chanx_right_in, + right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + chany_bottom_in, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chanx_right_out, + chany_bottom_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chanx_right_in; + input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input [0:29]chany_bottom_in; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + input ccff_head; + output [0:29]chanx_right_out; + output [0:29]chany_bottom_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chanx_right_in; + wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire [0:29]chany_bottom_in; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head; + wire [0:29]chanx_right_out; + wire [0:29]chany_bottom_out; + wire ccff_tail; + wire [0:1]mux_bottom_track_11_undriven_sram_inv; + wire [0:1]mux_bottom_track_13_undriven_sram_inv; + wire [0:1]mux_bottom_track_15_undriven_sram_inv; + wire [0:1]mux_bottom_track_17_undriven_sram_inv; + wire [0:1]mux_bottom_track_19_undriven_sram_inv; + wire [0:1]mux_bottom_track_1_undriven_sram_inv; + wire [0:1]mux_bottom_track_29_undriven_sram_inv; + wire [0:1]mux_bottom_track_31_undriven_sram_inv; + wire [0:1]mux_bottom_track_33_undriven_sram_inv; + wire [0:1]mux_bottom_track_35_undriven_sram_inv; + wire [0:1]mux_bottom_track_3_undriven_sram_inv; + wire [0:1]mux_bottom_track_45_undriven_sram_inv; + wire [0:1]mux_bottom_track_47_undriven_sram_inv; + wire [0:1]mux_bottom_track_49_undriven_sram_inv; + wire [0:1]mux_bottom_track_51_undriven_sram_inv; + wire [0:1]mux_bottom_track_5_undriven_sram_inv; + wire [0:1]mux_bottom_track_7_undriven_sram_inv; + wire [0:1]mux_bottom_track_9_undriven_sram_inv; + wire [0:2]mux_right_track_0_undriven_sram_inv; + wire [0:2]mux_right_track_10_undriven_sram_inv; + wire [0:1]mux_right_track_12_undriven_sram_inv; + wire [0:1]mux_right_track_14_undriven_sram_inv; + wire [0:1]mux_right_track_16_undriven_sram_inv; + wire [0:1]mux_right_track_18_undriven_sram_inv; + wire [0:1]mux_right_track_20_undriven_sram_inv; + wire [0:1]mux_right_track_22_undriven_sram_inv; + wire [0:1]mux_right_track_24_undriven_sram_inv; + wire [0:1]mux_right_track_26_undriven_sram_inv; + wire [0:1]mux_right_track_28_undriven_sram_inv; + wire [0:2]mux_right_track_2_undriven_sram_inv; + wire [0:1]mux_right_track_30_undriven_sram_inv; + wire [0:1]mux_right_track_32_undriven_sram_inv; + wire [0:1]mux_right_track_34_undriven_sram_inv; + wire [0:1]mux_right_track_36_undriven_sram_inv; + wire [0:1]mux_right_track_38_undriven_sram_inv; + wire [0:1]mux_right_track_40_undriven_sram_inv; + wire [0:1]mux_right_track_42_undriven_sram_inv; + wire [0:1]mux_right_track_44_undriven_sram_inv; + wire [0:1]mux_right_track_46_undriven_sram_inv; + wire [0:1]mux_right_track_48_undriven_sram_inv; + wire [0:2]mux_right_track_4_undriven_sram_inv; + wire [0:1]mux_right_track_50_undriven_sram_inv; + wire [0:1]mux_right_track_52_undriven_sram_inv; + wire [0:1]mux_right_track_54_undriven_sram_inv; + wire [0:1]mux_right_track_56_undriven_sram_inv; + wire [0:1]mux_right_track_58_undriven_sram_inv; + wire [0:2]mux_right_track_6_undriven_sram_inv; + wire [0:2]mux_right_track_8_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_11_sram; + wire [0:1]mux_tree_tapbuf_size2_12_sram; + wire [0:1]mux_tree_tapbuf_size2_13_sram; + wire [0:1]mux_tree_tapbuf_size2_14_sram; + wire [0:1]mux_tree_tapbuf_size2_15_sram; + wire [0:1]mux_tree_tapbuf_size2_16_sram; + wire [0:1]mux_tree_tapbuf_size2_17_sram; + wire [0:1]mux_tree_tapbuf_size2_18_sram; + wire [0:1]mux_tree_tapbuf_size2_19_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_20_sram; + wire [0:1]mux_tree_tapbuf_size2_21_sram; + wire [0:1]mux_tree_tapbuf_size2_22_sram; + wire [0:1]mux_tree_tapbuf_size2_23_sram; + wire [0:1]mux_tree_tapbuf_size2_24_sram; + wire [0:1]mux_tree_tapbuf_size2_25_sram; + wire [0:1]mux_tree_tapbuf_size2_26_sram; + wire [0:1]mux_tree_tapbuf_size2_27_sram; + wire [0:1]mux_tree_tapbuf_size2_28_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire mux_tree_tapbuf_size2_mem_19_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_20_ccff_tail; + wire mux_tree_tapbuf_size2_mem_21_ccff_tail; + wire mux_tree_tapbuf_size2_mem_22_ccff_tail; + wire mux_tree_tapbuf_size2_mem_23_ccff_tail; + wire mux_tree_tapbuf_size2_mem_24_ccff_tail; + wire mux_tree_tapbuf_size2_mem_25_ccff_tail; + wire mux_tree_tapbuf_size2_mem_26_ccff_tail; + wire mux_tree_tapbuf_size2_mem_27_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_10_sram; + wire [0:1]mux_tree_tapbuf_size3_11_sram; + wire [0:1]mux_tree_tapbuf_size3_12_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire [0:1]mux_tree_tapbuf_size3_7_sram; + wire [0:1]mux_tree_tapbuf_size3_8_sram; + wire [0:1]mux_tree_tapbuf_size3_9_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_10_ccff_tail; + wire mux_tree_tapbuf_size3_mem_11_ccff_tail; + wire mux_tree_tapbuf_size3_mem_12_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire mux_tree_tapbuf_size3_mem_7_ccff_tail; + wire mux_tree_tapbuf_size3_mem_8_ccff_tail; + wire mux_tree_tapbuf_size3_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire [0:2]mux_tree_tapbuf_size5_5_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire mux_tree_tapbuf_size5_mem_5_ccff_tail; + +assign chany_bottom_out[28] = chanx_right_in[0]; +assign chany_bottom_out[27] = chanx_right_in[1]; +assign chany_bottom_out[26] = chanx_right_in[2]; +assign chany_bottom_out[21] = chanx_right_in[7]; +assign chany_bottom_out[20] = chanx_right_in[8]; +assign chany_bottom_out[19] = chanx_right_in[9]; +assign chany_bottom_out[18] = chanx_right_in[10]; +assign chany_bottom_out[13] = chanx_right_in[15]; +assign chany_bottom_out[12] = chanx_right_in[16]; +assign chany_bottom_out[11] = chanx_right_in[17]; +assign chany_bottom_out[10] = chanx_right_in[18]; +assign chany_bottom_out[29] = chanx_right_in[29]; + mux_tree_tapbuf_size5 mux_right_track_0 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[28]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size5 mux_right_track_2 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[27]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size5 mux_right_track_4 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[26]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size5 mux_right_track_6 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[25]}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size5 mux_right_track_8 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[24]}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_right_track_8_undriven_sram_inv), + .out(chanx_right_out[4]) + ); + mux_tree_tapbuf_size5 mux_right_track_10 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[23]}), + .sram(mux_tree_tapbuf_size5_5_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size5_mem mem_right_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram) + ); + mux_tree_tapbuf_size3 mux_right_track_12 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[22]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size3 mux_right_track_14 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[21]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_right_track_14_undriven_sram_inv), + .out(chanx_right_out[7]) + ); + mux_tree_tapbuf_size3 mux_right_track_16 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[20]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_right_track_16_undriven_sram_inv), + .out(chanx_right_out[8]) + ); + mux_tree_tapbuf_size3 mux_right_track_28 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[14]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size3 mux_right_track_30 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[13]}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_right_track_30_undriven_sram_inv), + .out(chanx_right_out[15]) + ); + mux_tree_tapbuf_size3 mux_right_track_32 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[12]}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_right_track_32_undriven_sram_inv), + .out(chanx_right_out[16]) + ); + mux_tree_tapbuf_size3 mux_right_track_34 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[11]}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_right_track_34_undriven_sram_inv), + .out(chanx_right_out[17]) + ); + mux_tree_tapbuf_size3 mux_right_track_44 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[6]}), + .sram(mux_tree_tapbuf_size3_7_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size3 mux_right_track_46 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[5]}), + .sram(mux_tree_tapbuf_size3_8_sram), + .sram_inv(mux_right_track_46_undriven_sram_inv), + .out(chanx_right_out[23]) + ); + mux_tree_tapbuf_size3 mux_right_track_48 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[4]}), + .sram(mux_tree_tapbuf_size3_9_sram), + .sram_inv(mux_right_track_48_undriven_sram_inv), + .out(chanx_right_out[24]) + ); + mux_tree_tapbuf_size3 mux_right_track_58 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[29]}), + .sram(mux_tree_tapbuf_size3_10_sram), + .sram_inv(mux_right_track_58_undriven_sram_inv), + .out(chanx_right_out[29]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_1 + ( + .in({chanx_right_in[28], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_11_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_7 + ( + .in({chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_12_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size3_mem mem_right_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_16 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_30 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_32 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_34 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_46 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_48 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_58 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_12_sram) + ); + mux_tree_tapbuf_size2 mux_right_track_18 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[19]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_right_track_18_undriven_sram_inv), + .out(chanx_right_out[9]) + ); + mux_tree_tapbuf_size2 mux_right_track_20 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[18]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_right_track_20_undriven_sram_inv), + .out(chanx_right_out[10]) + ); + mux_tree_tapbuf_size2 mux_right_track_22 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[17]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_right_track_22_undriven_sram_inv), + .out(chanx_right_out[11]) + ); + mux_tree_tapbuf_size2 mux_right_track_24 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[16]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_right_track_24_undriven_sram_inv), + .out(chanx_right_out[12]) + ); + mux_tree_tapbuf_size2 mux_right_track_26 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[15]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_right_track_26_undriven_sram_inv), + .out(chanx_right_out[13]) + ); + mux_tree_tapbuf_size2 mux_right_track_36 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[10]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_right_track_36_undriven_sram_inv), + .out(chanx_right_out[18]) + ); + mux_tree_tapbuf_size2 mux_right_track_38 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[9]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_right_track_38_undriven_sram_inv), + .out(chanx_right_out[19]) + ); + mux_tree_tapbuf_size2 mux_right_track_40 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[8]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_right_track_40_undriven_sram_inv), + .out(chanx_right_out[20]) + ); + mux_tree_tapbuf_size2 mux_right_track_42 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[7]}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_right_track_42_undriven_sram_inv), + .out(chanx_right_out[21]) + ); + mux_tree_tapbuf_size2 mux_right_track_50 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[3]}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_right_track_50_undriven_sram_inv), + .out(chanx_right_out[25]) + ); + mux_tree_tapbuf_size2 mux_right_track_52 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[2]}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_right_track_52_undriven_sram_inv), + .out(chanx_right_out[26]) + ); + mux_tree_tapbuf_size2 mux_right_track_54 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[1]}), + .sram(mux_tree_tapbuf_size2_11_sram), + .sram_inv(mux_right_track_54_undriven_sram_inv), + .out(chanx_right_out[27]) + ); + mux_tree_tapbuf_size2 mux_right_track_56 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[0]}), + .sram(mux_tree_tapbuf_size2_12_sram), + .sram_inv(mux_right_track_56_undriven_sram_inv), + .out(chanx_right_out[28]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_3 + ( + .in({chanx_right_in[27], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_13_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_5 + ( + .in({chanx_right_in[26], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_14_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_9 + ( + .in({chanx_right_in[24], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_15_sram), + .sram_inv(mux_bottom_track_9_undriven_sram_inv), + .out(chany_bottom_out[4]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_11 + ( + .in({chanx_right_in[23], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_16_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_13 + ( + .in({chanx_right_in[22], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_17_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_15 + ( + .in({chanx_right_in[21], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_18_sram), + .sram_inv(mux_bottom_track_15_undriven_sram_inv), + .out(chany_bottom_out[7]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_17 + ( + .in({chanx_right_in[20], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_19_sram), + .sram_inv(mux_bottom_track_17_undriven_sram_inv), + .out(chany_bottom_out[8]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_19 + ( + .in({chanx_right_in[19], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_20_sram), + .sram_inv(mux_bottom_track_19_undriven_sram_inv), + .out(chany_bottom_out[9]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_29 + ( + .in({chanx_right_in[14], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_31 + ( + .in({chanx_right_in[13], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_22_sram), + .sram_inv(mux_bottom_track_31_undriven_sram_inv), + .out(chany_bottom_out[15]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_33 + ( + .in({chanx_right_in[12], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_23_sram), + .sram_inv(mux_bottom_track_33_undriven_sram_inv), + .out(chany_bottom_out[16]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_35 + ( + .in({chanx_right_in[11], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_24_sram), + .sram_inv(mux_bottom_track_35_undriven_sram_inv), + .out(chany_bottom_out[17]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_45 + ( + .in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_25_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_47 + ( + .in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_26_sram), + .sram_inv(mux_bottom_track_47_undriven_sram_inv), + .out(chany_bottom_out[23]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_49 + ( + .in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_27_sram), + .sram_inv(mux_bottom_track_49_undriven_sram_inv), + .out(chany_bottom_out[24]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_51 + ( + .in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_28_sram), + .sram_inv(mux_bottom_track_51_undriven_sram_inv), + .out(chany_bottom_out[25]) + ); + mux_tree_tapbuf_size2_mem mem_right_track_18 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_22 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_24 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_26 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_38 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_40 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_42 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_50 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_54 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_56 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_17 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_19 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_31 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_33 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_35 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_25_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_47 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_26_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_49 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_27_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_51 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_28_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__0_.v new file mode 100644 index 0000000..8e5fb2d --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__0_.v @@ -0,0 +1,993 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_1__0_ +( + pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_right_in, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + chanx_left_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_right_out, + chanx_left_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_top_in; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input [0:29]chanx_right_in; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + input [0:29]chanx_left_in; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + input ccff_head; + output [0:29]chany_top_out; + output [0:29]chanx_right_out; + output [0:29]chanx_left_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_top_in; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire [0:29]chanx_right_in; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire [0:29]chanx_left_in; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head; + wire [0:29]chany_top_out; + wire [0:29]chanx_right_out; + wire [0:29]chanx_left_out; + wire ccff_tail; + wire [0:2]mux_left_track_11_undriven_sram_inv; + wire [0:2]mux_left_track_13_undriven_sram_inv; + wire [0:2]mux_left_track_1_undriven_sram_inv; + wire [0:2]mux_left_track_21_undriven_sram_inv; + wire [0:2]mux_left_track_29_undriven_sram_inv; + wire [0:2]mux_left_track_37_undriven_sram_inv; + wire [0:2]mux_left_track_3_undriven_sram_inv; + wire [0:2]mux_left_track_45_undriven_sram_inv; + wire [0:2]mux_left_track_53_undriven_sram_inv; + wire [0:2]mux_left_track_5_undriven_sram_inv; + wire [0:2]mux_left_track_7_undriven_sram_inv; + wire [0:2]mux_right_track_0_undriven_sram_inv; + wire [0:2]mux_right_track_10_undriven_sram_inv; + wire [0:2]mux_right_track_12_undriven_sram_inv; + wire [0:2]mux_right_track_20_undriven_sram_inv; + wire [0:2]mux_right_track_28_undriven_sram_inv; + wire [0:2]mux_right_track_2_undriven_sram_inv; + wire [0:2]mux_right_track_36_undriven_sram_inv; + wire [0:1]mux_right_track_44_undriven_sram_inv; + wire [0:2]mux_right_track_4_undriven_sram_inv; + wire [0:1]mux_right_track_52_undriven_sram_inv; + wire [0:2]mux_right_track_6_undriven_sram_inv; + wire [0:2]mux_top_track_0_undriven_sram_inv; + wire [0:2]mux_top_track_10_undriven_sram_inv; + wire [0:2]mux_top_track_12_undriven_sram_inv; + wire [0:2]mux_top_track_14_undriven_sram_inv; + wire [0:2]mux_top_track_16_undriven_sram_inv; + wire [0:2]mux_top_track_18_undriven_sram_inv; + wire [0:1]mux_top_track_20_undriven_sram_inv; + wire [0:1]mux_top_track_22_undriven_sram_inv; + wire [0:1]mux_top_track_24_undriven_sram_inv; + wire [0:1]mux_top_track_26_undriven_sram_inv; + wire [0:1]mux_top_track_28_undriven_sram_inv; + wire [0:2]mux_top_track_2_undriven_sram_inv; + wire [0:1]mux_top_track_30_undriven_sram_inv; + wire [0:1]mux_top_track_32_undriven_sram_inv; + wire [0:1]mux_top_track_34_undriven_sram_inv; + wire [0:1]mux_top_track_36_undriven_sram_inv; + wire [0:1]mux_top_track_40_undriven_sram_inv; + wire [0:1]mux_top_track_42_undriven_sram_inv; + wire [0:1]mux_top_track_44_undriven_sram_inv; + wire [0:1]mux_top_track_46_undriven_sram_inv; + wire [0:1]mux_top_track_48_undriven_sram_inv; + wire [0:2]mux_top_track_4_undriven_sram_inv; + wire [0:1]mux_top_track_50_undriven_sram_inv; + wire [0:1]mux_top_track_58_undriven_sram_inv; + wire [0:2]mux_top_track_6_undriven_sram_inv; + wire [0:2]mux_top_track_8_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire [0:2]mux_tree_tapbuf_size4_0_sram; + wire [0:2]mux_tree_tapbuf_size4_1_sram; + wire [0:2]mux_tree_tapbuf_size4_2_sram; + wire [0:2]mux_tree_tapbuf_size4_3_sram; + wire [0:2]mux_tree_tapbuf_size4_4_sram; + wire [0:2]mux_tree_tapbuf_size4_5_sram; + wire mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire mux_tree_tapbuf_size4_mem_4_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire [0:2]mux_tree_tapbuf_size5_5_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire mux_tree_tapbuf_size5_mem_5_ccff_tail; + wire [0:2]mux_tree_tapbuf_size6_0_sram; + wire [0:2]mux_tree_tapbuf_size6_10_sram; + wire [0:2]mux_tree_tapbuf_size6_11_sram; + wire [0:2]mux_tree_tapbuf_size6_12_sram; + wire [0:2]mux_tree_tapbuf_size6_1_sram; + wire [0:2]mux_tree_tapbuf_size6_2_sram; + wire [0:2]mux_tree_tapbuf_size6_3_sram; + wire [0:2]mux_tree_tapbuf_size6_4_sram; + wire [0:2]mux_tree_tapbuf_size6_5_sram; + wire [0:2]mux_tree_tapbuf_size6_6_sram; + wire [0:2]mux_tree_tapbuf_size6_7_sram; + wire [0:2]mux_tree_tapbuf_size6_8_sram; + wire [0:2]mux_tree_tapbuf_size6_9_sram; + wire mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire mux_tree_tapbuf_size6_mem_10_ccff_tail; + wire mux_tree_tapbuf_size6_mem_11_ccff_tail; + wire mux_tree_tapbuf_size6_mem_12_ccff_tail; + wire mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire mux_tree_tapbuf_size6_mem_7_ccff_tail; + wire mux_tree_tapbuf_size6_mem_8_ccff_tail; + wire mux_tree_tapbuf_size6_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size7_0_sram; + wire [0:2]mux_tree_tapbuf_size7_1_sram; + wire [0:2]mux_tree_tapbuf_size7_2_sram; + wire [0:2]mux_tree_tapbuf_size7_3_sram; + wire [0:2]mux_tree_tapbuf_size7_4_sram; + wire mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire mux_tree_tapbuf_size7_mem_4_ccff_tail; + +assign chany_top_out[19] = top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; +assign chanx_left_out[4] = chanx_right_in[3]; +assign chanx_left_out[7] = chanx_right_in[6]; +assign chanx_left_out[8] = chanx_right_in[7]; +assign chanx_left_out[9] = chanx_right_in[8]; +assign chanx_left_out[11] = chanx_right_in[10]; +assign chanx_left_out[12] = chanx_right_in[11]; +assign chanx_left_out[13] = chanx_right_in[12]; +assign chanx_left_out[15] = chanx_right_in[14]; +assign chanx_left_out[16] = chanx_right_in[15]; +assign chanx_left_out[17] = chanx_right_in[16]; +assign chanx_left_out[19] = chanx_right_in[18]; +assign chanx_left_out[20] = chanx_right_in[19]; +assign chanx_left_out[21] = chanx_right_in[20]; +assign chanx_left_out[23] = chanx_right_in[22]; +assign chanx_left_out[24] = chanx_right_in[23]; +assign chanx_left_out[25] = chanx_right_in[24]; +assign chanx_left_out[27] = chanx_right_in[26]; +assign chanx_left_out[28] = chanx_right_in[27]; +assign chanx_left_out[29] = chanx_right_in[28]; +assign chany_top_out[28] = chanx_left_in[2]; +assign chanx_right_out[4] = chanx_left_in[3]; +assign chany_top_out[27] = chanx_left_in[4]; +assign chany_top_out[26] = chanx_left_in[5]; +assign chanx_right_out[7] = chanx_left_in[6]; +assign chanx_right_out[8] = chanx_left_in[7]; +assign chanx_right_out[9] = chanx_left_in[8]; +assign chanx_right_out[11] = chanx_left_in[10]; +assign chanx_right_out[12] = chanx_left_in[11]; +assign chanx_right_out[13] = chanx_left_in[12]; +assign chanx_right_out[15] = chanx_left_in[14]; +assign chanx_right_out[16] = chanx_left_in[15]; +assign chanx_right_out[17] = chanx_left_in[16]; +assign chanx_right_out[19] = chanx_left_in[18]; +assign chanx_right_out[20] = chanx_left_in[19]; +assign chanx_right_out[21] = chanx_left_in[20]; +assign chanx_right_out[23] = chanx_left_in[22]; +assign chanx_right_out[24] = chanx_left_in[23]; +assign chanx_right_out[25] = chanx_left_in[24]; +assign chanx_right_out[27] = chanx_left_in[26]; +assign chanx_right_out[28] = chanx_left_in[27]; +assign chanx_right_out[29] = chanx_left_in[28]; + mux_tree_tapbuf_size7 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[1], chanx_right_in[3], chanx_left_in[0], chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size7_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size7 mux_right_track_6 + ( + .in({chany_top_in[2], chany_top_in[13], chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size7_1_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size7 mux_right_track_10 + ( + .in({chany_top_in[3], chany_top_in[14], chany_top_in[25], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size7_2_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size7 mux_left_track_1 + ( + .in({chany_top_in[0], chany_top_in[11], chany_top_in[22], chanx_right_in[3], chanx_right_in[19], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_3_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size7 mux_left_track_11 + ( + .in({chany_top_in[7], chany_top_in[18], chany_top_in[29], chanx_right_in[10], chanx_right_in[24], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_4_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size7_mem mem_top_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram) + ); + mux_tree_tapbuf_size7_mem mem_right_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram) + ); + mux_tree_tapbuf_size7_mem mem_right_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram) + ); + mux_tree_tapbuf_size7_mem mem_left_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram) + ); + mux_tree_tapbuf_size7_mem mem_left_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram) + ); + mux_tree_tapbuf_size6 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[2], chanx_right_in[6], chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size6_0_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size6 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[5], chanx_right_in[8], chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size6_1_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); + mux_tree_tapbuf_size6 mux_top_track_8 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[9], chanx_right_in[10], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size6_2_sram), + .sram_inv(mux_top_track_8_undriven_sram_inv), + .out(chany_top_out[4]) + ); + mux_tree_tapbuf_size6 mux_right_track_0 + ( + .in({chany_top_in[10], chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size6_3_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size6 mux_right_track_2 + ( + .in({chany_top_in[0], chany_top_in[11], chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size6_4_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size6 mux_right_track_4 + ( + .in({chany_top_in[1], chany_top_in[12], chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size6_5_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size6 mux_right_track_12 + ( + .in({chany_top_in[4], chany_top_in[15], chany_top_in[26], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[11], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size6_6_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size6 mux_right_track_20 + ( + .in({chany_top_in[5], chany_top_in[16], chany_top_in[27], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size6_7_sram), + .sram_inv(mux_right_track_20_undriven_sram_inv), + .out(chanx_right_out[10]) + ); + mux_tree_tapbuf_size6 mux_right_track_28 + ( + .in({chany_top_in[6], chany_top_in[17], chany_top_in[28], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size6_8_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size6 mux_left_track_7 + ( + .in({chany_top_in[8], chany_top_in[19], chanx_right_in[8], chanx_right_in[23], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_9_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size6 mux_left_track_13 + ( + .in({chany_top_in[6], chany_top_in[17], chany_top_in[28], chanx_right_in[11], chanx_right_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_10_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size6 mux_left_track_21 + ( + .in({chany_top_in[5], chany_top_in[16], chany_top_in[27], chanx_right_in[12], chanx_right_in[27], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_11_sram), + .sram_inv(mux_left_track_21_undriven_sram_inv), + .out(chanx_left_out[10]) + ); + mux_tree_tapbuf_size6 mux_left_track_29 + ( + .in({chany_top_in[4], chany_top_in[15], chany_top_in[26], chanx_right_in[14], chanx_right_in[28], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_12_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size6_mem mem_top_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_11_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_12_sram) + ); + mux_tree_tapbuf_size5 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[4], chanx_right_in[7], chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size5 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[11], chanx_right_in[13], chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size5 mux_right_track_36 + ( + .in({chany_top_in[7], chany_top_in[18], chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_right_track_36_undriven_sram_inv), + .out(chanx_right_out[18]) + ); + mux_tree_tapbuf_size5 mux_left_track_3 + ( + .in({chany_top_in[10], chany_top_in[21], chanx_right_in[6], chanx_right_in[20], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size5 mux_left_track_5 + ( + .in({chany_top_in[9], chany_top_in[20], chanx_right_in[7], chanx_right_in[22], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size5 mux_left_track_37 + ( + .in({chany_top_in[3], chany_top_in[14], chany_top_in[25], chanx_right_in[15], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_5_sram), + .sram_inv(mux_left_track_37_undriven_sram_inv), + .out(chanx_left_out[18]) + ); + mux_tree_tapbuf_size5_mem mem_top_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram) + ); + mux_tree_tapbuf_size4 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_right_in[12], chanx_right_in[17], chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size4_0_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size4 mux_top_track_14 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_right_in[14], chanx_right_in[21], chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size4_1_sram), + .sram_inv(mux_top_track_14_undriven_sram_inv), + .out(chany_top_out[7]) + ); + mux_tree_tapbuf_size4 mux_top_track_16 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_right_in[15], chanx_right_in[25], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size4_2_sram), + .sram_inv(mux_top_track_16_undriven_sram_inv), + .out(chany_top_out[8]) + ); + mux_tree_tapbuf_size4 mux_top_track_18 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_right_in[16], chanx_right_in[29], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size4_3_sram), + .sram_inv(mux_top_track_18_undriven_sram_inv), + .out(chany_top_out[9]) + ); + mux_tree_tapbuf_size4 mux_left_track_45 + ( + .in({chany_top_in[2], chany_top_in[13], chany_top_in[24], chanx_right_in[16]}), + .sram(mux_tree_tapbuf_size4_4_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size4 mux_left_track_53 + ( + .in({chany_top_in[1], chany_top_in[12], chany_top_in[23], chanx_right_in[18]}), + .sram(mux_tree_tapbuf_size4_5_sram), + .sram_inv(mux_left_track_53_undriven_sram_inv), + .out(chanx_left_out[26]) + ); + mux_tree_tapbuf_size4_mem mem_top_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram) + ); + mux_tree_tapbuf_size4_mem mem_top_track_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram) + ); + mux_tree_tapbuf_size4_mem mem_top_track_16 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram) + ); + mux_tree_tapbuf_size4_mem mem_top_track_18 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram) + ); + mux_tree_tapbuf_size3 mux_top_track_20 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_right_in[18], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_top_track_20_undriven_sram_inv), + .out(chany_top_out[10]) + ); + mux_tree_tapbuf_size3 mux_top_track_22 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[19], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_top_track_22_undriven_sram_inv), + .out(chany_top_out[11]) + ); + mux_tree_tapbuf_size3 mux_top_track_24 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[20], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_top_track_24_undriven_sram_inv), + .out(chany_top_out[12]) + ); + mux_tree_tapbuf_size3 mux_top_track_26 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[22], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_top_track_26_undriven_sram_inv), + .out(chany_top_out[13]) + ); + mux_tree_tapbuf_size3 mux_top_track_36 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_right_in[28], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_top_track_36_undriven_sram_inv), + .out(chany_top_out[18]) + ); + mux_tree_tapbuf_size3 mux_right_track_44 + ( + .in({chany_top_in[8], chany_top_in[19], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size3 mux_right_track_52 + ( + .in({chany_top_in[9], chany_top_in[20], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_right_track_52_undriven_sram_inv), + .out(chanx_right_out[26]) + ); + mux_tree_tapbuf_size3_mem mem_top_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_22 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_24 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_26 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size2 mux_top_track_28 + ( + .in({chanx_right_in[23], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size2 mux_top_track_30 + ( + .in({chanx_right_in[24], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_top_track_30_undriven_sram_inv), + .out(chany_top_out[15]) + ); + mux_tree_tapbuf_size2 mux_top_track_32 + ( + .in({chanx_right_in[26], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_top_track_32_undriven_sram_inv), + .out(chany_top_out[16]) + ); + mux_tree_tapbuf_size2 mux_top_track_34 + ( + .in({chanx_right_in[27], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_top_track_34_undriven_sram_inv), + .out(chany_top_out[17]) + ); + mux_tree_tapbuf_size2 mux_top_track_40 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_top_track_40_undriven_sram_inv), + .out(chany_top_out[20]) + ); + mux_tree_tapbuf_size2 mux_top_track_42 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_top_track_42_undriven_sram_inv), + .out(chany_top_out[21]) + ); + mux_tree_tapbuf_size2 mux_top_track_44 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size2 mux_top_track_46 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_top_track_46_undriven_sram_inv), + .out(chany_top_out[23]) + ); + mux_tree_tapbuf_size2 mux_top_track_48 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_top_track_48_undriven_sram_inv), + .out(chany_top_out[24]) + ); + mux_tree_tapbuf_size2 mux_top_track_50 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_top_track_50_undriven_sram_inv), + .out(chany_top_out[25]) + ); + mux_tree_tapbuf_size2 mux_top_track_58 + ( + .in({chanx_right_in[0], chanx_left_in[1]}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_top_track_58_undriven_sram_inv), + .out(chany_top_out[29]) + ); + mux_tree_tapbuf_size2_mem mem_top_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_30 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_32 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_34 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_40 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_42 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_46 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_48 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_50 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_58 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__1_.v new file mode 100644 index 0000000..834c68d --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__1_.v @@ -0,0 +1,1009 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_1__1_ +( + pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_right_in, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + chany_bottom_in, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_left_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + ccff_head, + chany_top_out, + chanx_right_out, + chany_bottom_out, + chanx_left_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_top_in; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input [0:29]chanx_right_in; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input [0:29]chany_bottom_in; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input [0:29]chanx_left_in; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input ccff_head; + output [0:29]chany_top_out; + output [0:29]chanx_right_out; + output [0:29]chany_bottom_out; + output [0:29]chanx_left_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_top_in; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire [0:29]chanx_right_in; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire [0:29]chany_bottom_in; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire [0:29]chanx_left_in; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire ccff_head; + wire [0:29]chany_top_out; + wire [0:29]chanx_right_out; + wire [0:29]chany_bottom_out; + wire [0:29]chanx_left_out; + wire ccff_tail; + wire [0:3]mux_bottom_track_11_undriven_sram_inv; + wire [0:3]mux_bottom_track_13_undriven_sram_inv; + wire [0:3]mux_bottom_track_1_undriven_sram_inv; + wire [0:3]mux_bottom_track_21_undriven_sram_inv; + wire [0:3]mux_bottom_track_29_undriven_sram_inv; + wire [0:2]mux_bottom_track_37_undriven_sram_inv; + wire [0:3]mux_bottom_track_3_undriven_sram_inv; + wire [0:2]mux_bottom_track_45_undriven_sram_inv; + wire [0:2]mux_bottom_track_53_undriven_sram_inv; + wire [0:3]mux_bottom_track_5_undriven_sram_inv; + wire [0:3]mux_bottom_track_7_undriven_sram_inv; + wire [0:3]mux_left_track_11_undriven_sram_inv; + wire [0:3]mux_left_track_13_undriven_sram_inv; + wire [0:3]mux_left_track_1_undriven_sram_inv; + wire [0:3]mux_left_track_21_undriven_sram_inv; + wire [0:3]mux_left_track_29_undriven_sram_inv; + wire [0:2]mux_left_track_37_undriven_sram_inv; + wire [0:3]mux_left_track_3_undriven_sram_inv; + wire [0:2]mux_left_track_45_undriven_sram_inv; + wire [0:2]mux_left_track_53_undriven_sram_inv; + wire [0:3]mux_left_track_5_undriven_sram_inv; + wire [0:3]mux_left_track_7_undriven_sram_inv; + wire [0:3]mux_right_track_0_undriven_sram_inv; + wire [0:3]mux_right_track_10_undriven_sram_inv; + wire [0:3]mux_right_track_12_undriven_sram_inv; + wire [0:3]mux_right_track_20_undriven_sram_inv; + wire [0:3]mux_right_track_28_undriven_sram_inv; + wire [0:3]mux_right_track_2_undriven_sram_inv; + wire [0:2]mux_right_track_36_undriven_sram_inv; + wire [0:2]mux_right_track_44_undriven_sram_inv; + wire [0:3]mux_right_track_4_undriven_sram_inv; + wire [0:2]mux_right_track_52_undriven_sram_inv; + wire [0:3]mux_right_track_6_undriven_sram_inv; + wire [0:3]mux_top_track_0_undriven_sram_inv; + wire [0:3]mux_top_track_10_undriven_sram_inv; + wire [0:3]mux_top_track_12_undriven_sram_inv; + wire [0:3]mux_top_track_20_undriven_sram_inv; + wire [0:3]mux_top_track_28_undriven_sram_inv; + wire [0:3]mux_top_track_2_undriven_sram_inv; + wire [0:2]mux_top_track_36_undriven_sram_inv; + wire [0:2]mux_top_track_44_undriven_sram_inv; + wire [0:3]mux_top_track_4_undriven_sram_inv; + wire [0:2]mux_top_track_52_undriven_sram_inv; + wire [0:3]mux_top_track_6_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire [0:3]mux_tree_tapbuf_size10_10_sram; + wire [0:3]mux_tree_tapbuf_size10_11_sram; + wire [0:3]mux_tree_tapbuf_size10_1_sram; + wire [0:3]mux_tree_tapbuf_size10_2_sram; + wire [0:3]mux_tree_tapbuf_size10_3_sram; + wire [0:3]mux_tree_tapbuf_size10_4_sram; + wire [0:3]mux_tree_tapbuf_size10_5_sram; + wire [0:3]mux_tree_tapbuf_size10_6_sram; + wire [0:3]mux_tree_tapbuf_size10_7_sram; + wire [0:3]mux_tree_tapbuf_size10_8_sram; + wire [0:3]mux_tree_tapbuf_size10_9_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire mux_tree_tapbuf_size10_mem_10_ccff_tail; + wire mux_tree_tapbuf_size10_mem_11_ccff_tail; + wire mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire mux_tree_tapbuf_size10_mem_7_ccff_tail; + wire mux_tree_tapbuf_size10_mem_8_ccff_tail; + wire mux_tree_tapbuf_size10_mem_9_ccff_tail; + wire [0:3]mux_tree_tapbuf_size11_0_sram; + wire [0:3]mux_tree_tapbuf_size11_1_sram; + wire [0:3]mux_tree_tapbuf_size11_2_sram; + wire [0:3]mux_tree_tapbuf_size11_3_sram; + wire [0:3]mux_tree_tapbuf_size11_4_sram; + wire [0:3]mux_tree_tapbuf_size11_5_sram; + wire [0:3]mux_tree_tapbuf_size11_6_sram; + wire [0:3]mux_tree_tapbuf_size11_7_sram; + wire mux_tree_tapbuf_size11_mem_0_ccff_tail; + wire mux_tree_tapbuf_size11_mem_1_ccff_tail; + wire mux_tree_tapbuf_size11_mem_2_ccff_tail; + wire mux_tree_tapbuf_size11_mem_3_ccff_tail; + wire mux_tree_tapbuf_size11_mem_4_ccff_tail; + wire mux_tree_tapbuf_size11_mem_5_ccff_tail; + wire mux_tree_tapbuf_size11_mem_6_ccff_tail; + wire mux_tree_tapbuf_size11_mem_7_ccff_tail; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire [0:3]mux_tree_tapbuf_size12_4_sram; + wire [0:3]mux_tree_tapbuf_size12_5_sram; + wire [0:3]mux_tree_tapbuf_size12_6_sram; + wire [0:3]mux_tree_tapbuf_size12_7_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire mux_tree_tapbuf_size12_mem_7_ccff_tail; + wire [0:2]mux_tree_tapbuf_size6_0_sram; + wire [0:2]mux_tree_tapbuf_size6_10_sram; + wire [0:2]mux_tree_tapbuf_size6_11_sram; + wire [0:2]mux_tree_tapbuf_size6_1_sram; + wire [0:2]mux_tree_tapbuf_size6_2_sram; + wire [0:2]mux_tree_tapbuf_size6_3_sram; + wire [0:2]mux_tree_tapbuf_size6_4_sram; + wire [0:2]mux_tree_tapbuf_size6_5_sram; + wire [0:2]mux_tree_tapbuf_size6_6_sram; + wire [0:2]mux_tree_tapbuf_size6_7_sram; + wire [0:2]mux_tree_tapbuf_size6_8_sram; + wire [0:2]mux_tree_tapbuf_size6_9_sram; + wire mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire mux_tree_tapbuf_size6_mem_10_ccff_tail; + wire mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire mux_tree_tapbuf_size6_mem_7_ccff_tail; + wire mux_tree_tapbuf_size6_mem_8_ccff_tail; + wire mux_tree_tapbuf_size6_mem_9_ccff_tail; + wire [0:3]mux_tree_tapbuf_size9_0_sram; + wire [0:3]mux_tree_tapbuf_size9_1_sram; + wire [0:3]mux_tree_tapbuf_size9_2_sram; + wire [0:3]mux_tree_tapbuf_size9_3_sram; + wire mux_tree_tapbuf_size9_mem_0_ccff_tail; + wire mux_tree_tapbuf_size9_mem_1_ccff_tail; + wire mux_tree_tapbuf_size9_mem_2_ccff_tail; + wire mux_tree_tapbuf_size9_mem_3_ccff_tail; + +assign chany_bottom_out[4] = chany_top_in[3]; +assign chany_bottom_out[7] = chany_top_in[6]; +assign chany_bottom_out[8] = chany_top_in[7]; +assign chany_bottom_out[9] = chany_top_in[8]; +assign chany_bottom_out[11] = chany_top_in[10]; +assign chany_bottom_out[12] = chany_top_in[11]; +assign chany_bottom_out[13] = chany_top_in[12]; +assign chany_bottom_out[15] = chany_top_in[14]; +assign chany_bottom_out[16] = chany_top_in[15]; +assign chany_bottom_out[17] = chany_top_in[16]; +assign chany_bottom_out[19] = chany_top_in[18]; +assign chany_bottom_out[20] = chany_top_in[19]; +assign chany_bottom_out[21] = chany_top_in[20]; +assign chany_bottom_out[23] = chany_top_in[22]; +assign chany_bottom_out[24] = chany_top_in[23]; +assign chany_bottom_out[25] = chany_top_in[24]; +assign chany_bottom_out[27] = chany_top_in[26]; +assign chany_bottom_out[28] = chany_top_in[27]; +assign chany_bottom_out[29] = chany_top_in[28]; +assign chanx_left_out[4] = chanx_right_in[3]; +assign chanx_left_out[7] = chanx_right_in[6]; +assign chanx_left_out[8] = chanx_right_in[7]; +assign chanx_left_out[9] = chanx_right_in[8]; +assign chanx_left_out[11] = chanx_right_in[10]; +assign chanx_left_out[12] = chanx_right_in[11]; +assign chanx_left_out[13] = chanx_right_in[12]; +assign chanx_left_out[15] = chanx_right_in[14]; +assign chanx_left_out[16] = chanx_right_in[15]; +assign chanx_left_out[17] = chanx_right_in[16]; +assign chanx_left_out[19] = chanx_right_in[18]; +assign chanx_left_out[20] = chanx_right_in[19]; +assign chanx_left_out[21] = chanx_right_in[20]; +assign chanx_left_out[23] = chanx_right_in[22]; +assign chanx_left_out[24] = chanx_right_in[23]; +assign chanx_left_out[25] = chanx_right_in[24]; +assign chanx_left_out[27] = chanx_right_in[26]; +assign chanx_left_out[28] = chanx_right_in[27]; +assign chanx_left_out[29] = chanx_right_in[28]; +assign chany_top_out[4] = chany_bottom_in[3]; +assign chany_top_out[7] = chany_bottom_in[6]; +assign chany_top_out[8] = chany_bottom_in[7]; +assign chany_top_out[9] = chany_bottom_in[8]; +assign chany_top_out[11] = chany_bottom_in[10]; +assign chany_top_out[12] = chany_bottom_in[11]; +assign chany_top_out[13] = chany_bottom_in[12]; +assign chany_top_out[15] = chany_bottom_in[14]; +assign chany_top_out[16] = chany_bottom_in[15]; +assign chany_top_out[17] = chany_bottom_in[16]; +assign chany_top_out[19] = chany_bottom_in[18]; +assign chany_top_out[20] = chany_bottom_in[19]; +assign chany_top_out[21] = chany_bottom_in[20]; +assign chany_top_out[23] = chany_bottom_in[22]; +assign chany_top_out[24] = chany_bottom_in[23]; +assign chany_top_out[25] = chany_bottom_in[24]; +assign chany_top_out[27] = chany_bottom_in[26]; +assign chany_top_out[28] = chany_bottom_in[27]; +assign chany_top_out[29] = chany_bottom_in[28]; +assign chanx_right_out[4] = chanx_left_in[3]; +assign chanx_right_out[7] = chanx_left_in[6]; +assign chanx_right_out[8] = chanx_left_in[7]; +assign chanx_right_out[9] = chanx_left_in[8]; +assign chanx_right_out[11] = chanx_left_in[10]; +assign chanx_right_out[12] = chanx_left_in[11]; +assign chanx_right_out[13] = chanx_left_in[12]; +assign chanx_right_out[15] = chanx_left_in[14]; +assign chanx_right_out[16] = chanx_left_in[15]; +assign chanx_right_out[17] = chanx_left_in[16]; +assign chanx_right_out[19] = chanx_left_in[18]; +assign chanx_right_out[20] = chanx_left_in[19]; +assign chanx_right_out[21] = chanx_left_in[20]; +assign chanx_right_out[23] = chanx_left_in[22]; +assign chanx_right_out[24] = chanx_left_in[23]; +assign chanx_right_out[25] = chanx_left_in[24]; +assign chanx_right_out[27] = chanx_left_in[26]; +assign chanx_right_out[28] = chanx_left_in[27]; +assign chanx_right_out[29] = chanx_left_in[28]; + mux_tree_tapbuf_size11 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[1], chanx_right_in[3], chanx_right_in[19], chany_bottom_in[3], chany_bottom_in[19], chanx_left_in[0], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size11_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size11 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[2], chanx_right_in[6], chanx_right_in[20], chany_bottom_in[6], chany_bottom_in[20], chanx_left_in[6], chanx_left_in[20], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size11_1_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size11 mux_right_track_0 + ( + .in({chany_top_in[3], chany_top_in[19], chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[3], chany_bottom_in[19], chany_bottom_in[25], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size11_2_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size11 mux_right_track_2 + ( + .in({chany_top_in[0], chany_top_in[6], chany_top_in[20], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[6], chany_bottom_in[20], chany_bottom_in[21], chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size11_3_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size11 mux_bottom_track_1 + ( + .in({chany_top_in[3], chany_top_in[19], chanx_right_in[3], chanx_right_in[19], chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[1], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size11_4_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size11 mux_bottom_track_3 + ( + .in({chany_top_in[6], chany_top_in[20], chanx_right_in[6], chanx_right_in[20], chanx_right_in[21], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[2], chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size11_5_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size11 mux_left_track_1 + ( + .in({chany_top_in[0], chany_top_in[3], chany_top_in[19], chanx_right_in[3], chanx_right_in[19], chany_bottom_in[3], chany_bottom_in[19], chany_bottom_in[29], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size11_6_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size11 mux_left_track_3 + ( + .in({chany_top_in[6], chany_top_in[20], chany_top_in[29], chanx_right_in[6], chanx_right_in[20], chany_bottom_in[0], chany_bottom_in[6], chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size11_7_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size11_mem mem_top_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_0_sram) + ); + mux_tree_tapbuf_size11_mem mem_top_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_1_sram) + ); + mux_tree_tapbuf_size11_mem mem_right_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_2_sram) + ); + mux_tree_tapbuf_size11_mem mem_right_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_3_sram) + ); + mux_tree_tapbuf_size11_mem mem_bottom_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_4_sram) + ); + mux_tree_tapbuf_size11_mem mem_bottom_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_5_sram) + ); + mux_tree_tapbuf_size11_mem mem_left_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_6_sram) + ); + mux_tree_tapbuf_size11_mem mem_left_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_7_sram) + ); + mux_tree_tapbuf_size10 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[4], chanx_right_in[7], chanx_right_in[22], chany_bottom_in[7], chany_bottom_in[22], chanx_left_in[7], chanx_left_in[22], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size10 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[11], chanx_right_in[13], chanx_right_in[26], chany_bottom_in[11], chany_bottom_in[26], chanx_left_in[11], chanx_left_in[13], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size10_1_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size10 mux_top_track_20 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[12], chanx_right_in[17], chanx_right_in[27], chany_bottom_in[12], chany_bottom_in[27], chanx_left_in[9], chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size10_2_sram), + .sram_inv(mux_top_track_20_undriven_sram_inv), + .out(chany_top_out[10]) + ); + mux_tree_tapbuf_size10 mux_right_track_4 + ( + .in({chany_top_in[1], chany_top_in[7], chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[7], chany_bottom_in[17], chany_bottom_in[22], chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size10_3_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size10 mux_right_track_12 + ( + .in({chany_top_in[5], chany_top_in[11], chany_top_in[26], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[5], chany_bottom_in[11], chany_bottom_in[26], chanx_left_in[11], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size10_4_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size10 mux_right_track_20 + ( + .in({chany_top_in[9], chany_top_in[12], chany_top_in[27], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[4], chany_bottom_in[12], chany_bottom_in[27], chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size10_5_sram), + .sram_inv(mux_right_track_20_undriven_sram_inv), + .out(chanx_right_out[10]) + ); + mux_tree_tapbuf_size10 mux_bottom_track_5 + ( + .in({chany_top_in[7], chany_top_in[22], chanx_right_in[7], chanx_right_in[17], chanx_right_in[22], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[4], chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size10_6_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size10 mux_bottom_track_13 + ( + .in({chany_top_in[11], chany_top_in[26], chanx_right_in[5], chanx_right_in[11], chanx_right_in[26], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[11], chanx_left_in[13], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size10_7_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size10 mux_bottom_track_21 + ( + .in({chany_top_in[12], chany_top_in[27], chanx_right_in[4], chanx_right_in[12], chanx_right_in[27], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[12], chanx_left_in[17], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size10_8_sram), + .sram_inv(mux_bottom_track_21_undriven_sram_inv), + .out(chany_bottom_out[10]) + ); + mux_tree_tapbuf_size10 mux_left_track_5 + ( + .in({chany_top_in[7], chany_top_in[22], chany_top_in[25], chanx_right_in[7], chanx_right_in[22], chany_bottom_in[1], chany_bottom_in[7], chany_bottom_in[22], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size10_9_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size10 mux_left_track_13 + ( + .in({chany_top_in[11], chany_top_in[13], chany_top_in[26], chanx_right_in[11], chanx_right_in[26], chany_bottom_in[5], chany_bottom_in[11], chany_bottom_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size10_10_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size10 mux_left_track_21 + ( + .in({chany_top_in[9], chany_top_in[12], chany_top_in[27], chanx_right_in[12], chanx_right_in[27], chany_bottom_in[9], chany_bottom_in[12], chany_bottom_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size10_11_sram), + .sram_inv(mux_left_track_21_undriven_sram_inv), + .out(chanx_left_out[10]) + ); + mux_tree_tapbuf_size10_mem mem_top_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram) + ); + mux_tree_tapbuf_size10_mem mem_bottom_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram) + ); + mux_tree_tapbuf_size10_mem mem_bottom_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram) + ); + mux_tree_tapbuf_size10_mem mem_bottom_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_8_sram) + ); + mux_tree_tapbuf_size10_mem mem_left_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_9_sram) + ); + mux_tree_tapbuf_size10_mem mem_left_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_10_sram) + ); + mux_tree_tapbuf_size10_mem mem_left_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_11_sram) + ); + mux_tree_tapbuf_size12 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[5], chanx_right_in[8], chanx_right_in[23], chany_bottom_in[8], chany_bottom_in[23], chanx_left_in[8], chanx_left_in[21], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); + mux_tree_tapbuf_size12 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[9], chanx_right_in[10], chanx_right_in[24], chany_bottom_in[10], chany_bottom_in[24], chanx_left_in[10], chanx_left_in[17], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size12 mux_right_track_6 + ( + .in({chany_top_in[2], chany_top_in[8], chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[8], chany_bottom_in[13], chany_bottom_in[23], chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size12 mux_right_track_10 + ( + .in({chany_top_in[4], chany_top_in[10], chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[9], chany_bottom_in[10], chany_bottom_in[24], chanx_left_in[10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size12 mux_bottom_track_7 + ( + .in({chany_top_in[8], chany_top_in[23], chanx_right_in[8], chanx_right_in[13], chanx_right_in[23], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[5], chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size12_4_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size12 mux_bottom_track_11 + ( + .in({chany_top_in[10], chany_top_in[24], chanx_right_in[9], chanx_right_in[10], chanx_right_in[24], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[9], chanx_left_in[10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size12_5_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size12 mux_left_track_7 + ( + .in({chany_top_in[8], chany_top_in[21], chany_top_in[23], chanx_right_in[8], chanx_right_in[23], chany_bottom_in[2], chany_bottom_in[8], chany_bottom_in[23], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size12_6_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size12 mux_left_track_11 + ( + .in({chany_top_in[10], chany_top_in[17], chany_top_in[24], chanx_right_in[10], chanx_right_in[24], chany_bottom_in[4], chany_bottom_in[10], chany_bottom_in[24], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size12_7_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size12_mem mem_top_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_bottom_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram) + ); + mux_tree_tapbuf_size12_mem mem_bottom_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram) + ); + mux_tree_tapbuf_size12_mem mem_left_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram) + ); + mux_tree_tapbuf_size12_mem mem_left_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram) + ); + mux_tree_tapbuf_size9 mux_top_track_28 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_right_in[14], chanx_right_in[21], chanx_right_in[28], chany_bottom_in[14], chany_bottom_in[28], chanx_left_in[5], chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size9_0_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size9 mux_right_track_28 + ( + .in({chany_top_in[13], chany_top_in[14], chany_top_in[28], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[2], chany_bottom_in[14], chany_bottom_in[28], chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size9_1_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size9 mux_bottom_track_29 + ( + .in({chany_top_in[14], chany_top_in[28], chanx_right_in[2], chanx_right_in[14], chanx_right_in[28], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[14], chanx_left_in[21], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size9_2_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size9 mux_left_track_29 + ( + .in({chany_top_in[5], chany_top_in[14], chany_top_in[28], chanx_right_in[14], chanx_right_in[28], chany_bottom_in[13], chany_bottom_in[14], chany_bottom_in[28], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size9_3_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size9_mem mem_top_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_0_sram) + ); + mux_tree_tapbuf_size9_mem mem_right_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_1_sram) + ); + mux_tree_tapbuf_size9_mem mem_bottom_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_2_sram) + ); + mux_tree_tapbuf_size9_mem mem_left_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_3_sram) + ); + mux_tree_tapbuf_size6 mux_top_track_36 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_right_in[15], chanx_right_in[25], chany_bottom_in[15], chanx_left_in[4], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size6_0_sram), + .sram_inv(mux_top_track_36_undriven_sram_inv), + .out(chany_top_out[18]) + ); + mux_tree_tapbuf_size6 mux_top_track_44 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_right_in[16], chanx_right_in[29], chany_bottom_in[16], chanx_left_in[2], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size6_1_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size6 mux_top_track_52 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[0], chanx_right_in[18], chany_bottom_in[18], chanx_left_in[1], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size6_2_sram), + .sram_inv(mux_top_track_52_undriven_sram_inv), + .out(chany_top_out[26]) + ); + mux_tree_tapbuf_size6 mux_right_track_36 + ( + .in({chany_top_in[15], chany_top_in[17], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[1], chany_bottom_in[15], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size6_3_sram), + .sram_inv(mux_right_track_36_undriven_sram_inv), + .out(chanx_right_out[18]) + ); + mux_tree_tapbuf_size6 mux_right_track_44 + ( + .in({chany_top_in[16], chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[0], chany_bottom_in[16], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size6_4_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size6 mux_right_track_52 + ( + .in({chany_top_in[18], chany_top_in[25], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[18], chany_bottom_in[29], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size6_5_sram), + .sram_inv(mux_right_track_52_undriven_sram_inv), + .out(chanx_right_out[26]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_37 + ( + .in({chany_top_in[15], chanx_right_in[1], chanx_right_in[15], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[15], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size6_6_sram), + .sram_inv(mux_bottom_track_37_undriven_sram_inv), + .out(chany_bottom_out[18]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_45 + ( + .in({chany_top_in[16], chanx_right_in[0], chanx_right_in[16], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[16], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size6_7_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_53 + ( + .in({chany_top_in[18], chanx_right_in[18], chanx_right_in[29], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[0], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size6_8_sram), + .sram_inv(mux_bottom_track_53_undriven_sram_inv), + .out(chany_bottom_out[26]) + ); + mux_tree_tapbuf_size6 mux_left_track_37 + ( + .in({chany_top_in[4], chany_top_in[15], chanx_right_in[15], chany_bottom_in[15], chany_bottom_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size6_9_sram), + .sram_inv(mux_left_track_37_undriven_sram_inv), + .out(chanx_left_out[18]) + ); + mux_tree_tapbuf_size6 mux_left_track_45 + ( + .in({chany_top_in[2], chany_top_in[16], chanx_right_in[16], chany_bottom_in[16], chany_bottom_in[21], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size6_10_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size6 mux_left_track_53 + ( + .in({chany_top_in[1], chany_top_in[18], chanx_right_in[18], chany_bottom_in[18], chany_bottom_in[25], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size6_11_sram), + .sram_inv(mux_left_track_53_undriven_sram_inv), + .out(chanx_left_out[26]) + ); + mux_tree_tapbuf_size6_mem mem_top_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size6_11_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__8_.v new file mode 100644 index 0000000..0d620a7 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__8_.v @@ -0,0 +1,1041 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_1__8_ +( + pReset, + prog_clk, + chanx_right_in, + right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + chany_bottom_in, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_left_in, + left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + ccff_head, + chanx_right_out, + chany_bottom_out, + chanx_left_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chanx_right_in; + input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input [0:29]chany_bottom_in; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input [0:29]chanx_left_in; + input left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input ccff_head; + output [0:29]chanx_right_out; + output [0:29]chany_bottom_out; + output [0:29]chanx_left_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chanx_right_in; + wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire [0:29]chany_bottom_in; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire [0:29]chanx_left_in; + wire left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire ccff_head; + wire [0:29]chanx_right_out; + wire [0:29]chany_bottom_out; + wire [0:29]chanx_left_out; + wire ccff_tail; + wire [0:2]mux_bottom_track_11_undriven_sram_inv; + wire [0:2]mux_bottom_track_13_undriven_sram_inv; + wire [0:2]mux_bottom_track_15_undriven_sram_inv; + wire [0:2]mux_bottom_track_17_undriven_sram_inv; + wire [0:2]mux_bottom_track_19_undriven_sram_inv; + wire [0:2]mux_bottom_track_1_undriven_sram_inv; + wire [0:1]mux_bottom_track_21_undriven_sram_inv; + wire [0:1]mux_bottom_track_23_undriven_sram_inv; + wire [0:1]mux_bottom_track_25_undriven_sram_inv; + wire [0:1]mux_bottom_track_27_undriven_sram_inv; + wire [0:1]mux_bottom_track_29_undriven_sram_inv; + wire [0:1]mux_bottom_track_31_undriven_sram_inv; + wire [0:1]mux_bottom_track_33_undriven_sram_inv; + wire [0:1]mux_bottom_track_35_undriven_sram_inv; + wire [0:2]mux_bottom_track_37_undriven_sram_inv; + wire [0:1]mux_bottom_track_39_undriven_sram_inv; + wire [0:2]mux_bottom_track_3_undriven_sram_inv; + wire [0:1]mux_bottom_track_41_undriven_sram_inv; + wire [0:1]mux_bottom_track_43_undriven_sram_inv; + wire [0:1]mux_bottom_track_45_undriven_sram_inv; + wire [0:1]mux_bottom_track_47_undriven_sram_inv; + wire [0:1]mux_bottom_track_49_undriven_sram_inv; + wire [0:1]mux_bottom_track_51_undriven_sram_inv; + wire [0:2]mux_bottom_track_5_undriven_sram_inv; + wire [0:2]mux_bottom_track_7_undriven_sram_inv; + wire [0:2]mux_bottom_track_9_undriven_sram_inv; + wire [0:3]mux_left_track_11_undriven_sram_inv; + wire [0:2]mux_left_track_13_undriven_sram_inv; + wire [0:3]mux_left_track_1_undriven_sram_inv; + wire [0:2]mux_left_track_21_undriven_sram_inv; + wire [0:2]mux_left_track_29_undriven_sram_inv; + wire [0:2]mux_left_track_37_undriven_sram_inv; + wire [0:3]mux_left_track_3_undriven_sram_inv; + wire [0:2]mux_left_track_45_undriven_sram_inv; + wire [0:2]mux_left_track_53_undriven_sram_inv; + wire [0:3]mux_left_track_5_undriven_sram_inv; + wire [0:3]mux_left_track_7_undriven_sram_inv; + wire [0:3]mux_right_track_0_undriven_sram_inv; + wire [0:3]mux_right_track_10_undriven_sram_inv; + wire [0:2]mux_right_track_12_undriven_sram_inv; + wire [0:2]mux_right_track_20_undriven_sram_inv; + wire [0:2]mux_right_track_28_undriven_sram_inv; + wire [0:3]mux_right_track_2_undriven_sram_inv; + wire [0:2]mux_right_track_36_undriven_sram_inv; + wire [0:2]mux_right_track_44_undriven_sram_inv; + wire [0:3]mux_right_track_4_undriven_sram_inv; + wire [0:2]mux_right_track_52_undriven_sram_inv; + wire [0:3]mux_right_track_6_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size11_0_sram; + wire [0:3]mux_tree_tapbuf_size11_1_sram; + wire [0:3]mux_tree_tapbuf_size11_2_sram; + wire [0:3]mux_tree_tapbuf_size11_3_sram; + wire mux_tree_tapbuf_size11_mem_0_ccff_tail; + wire mux_tree_tapbuf_size11_mem_1_ccff_tail; + wire mux_tree_tapbuf_size11_mem_2_ccff_tail; + wire mux_tree_tapbuf_size11_mem_3_ccff_tail; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire [0:2]mux_tree_tapbuf_size4_0_sram; + wire [0:2]mux_tree_tapbuf_size4_1_sram; + wire [0:2]mux_tree_tapbuf_size4_2_sram; + wire [0:2]mux_tree_tapbuf_size4_3_sram; + wire [0:2]mux_tree_tapbuf_size4_4_sram; + wire mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire mux_tree_tapbuf_size4_mem_4_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire [0:2]mux_tree_tapbuf_size6_0_sram; + wire [0:2]mux_tree_tapbuf_size6_1_sram; + wire [0:2]mux_tree_tapbuf_size6_2_sram; + wire [0:2]mux_tree_tapbuf_size6_3_sram; + wire [0:2]mux_tree_tapbuf_size6_4_sram; + wire [0:2]mux_tree_tapbuf_size6_5_sram; + wire [0:2]mux_tree_tapbuf_size6_6_sram; + wire mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire [0:2]mux_tree_tapbuf_size7_0_sram; + wire [0:2]mux_tree_tapbuf_size7_1_sram; + wire [0:2]mux_tree_tapbuf_size7_2_sram; + wire [0:2]mux_tree_tapbuf_size7_3_sram; + wire [0:2]mux_tree_tapbuf_size7_4_sram; + wire [0:2]mux_tree_tapbuf_size7_5_sram; + wire mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire mux_tree_tapbuf_size7_mem_4_ccff_tail; + wire mux_tree_tapbuf_size7_mem_5_ccff_tail; + wire [0:3]mux_tree_tapbuf_size8_0_sram; + wire [0:3]mux_tree_tapbuf_size8_1_sram; + wire [0:3]mux_tree_tapbuf_size8_2_sram; + wire mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire mux_tree_tapbuf_size8_mem_2_ccff_tail; + wire [0:3]mux_tree_tapbuf_size9_0_sram; + wire [0:3]mux_tree_tapbuf_size9_1_sram; + wire [0:3]mux_tree_tapbuf_size9_2_sram; + wire mux_tree_tapbuf_size9_mem_0_ccff_tail; + wire mux_tree_tapbuf_size9_mem_1_ccff_tail; + wire mux_tree_tapbuf_size9_mem_2_ccff_tail; + +assign chany_bottom_out[28] = chanx_right_in[0]; +assign chany_bottom_out[27] = chanx_right_in[1]; +assign chany_bottom_out[26] = chanx_right_in[2]; +assign chanx_left_out[4] = chanx_right_in[3]; +assign chanx_left_out[7] = chanx_right_in[6]; +assign chanx_left_out[8] = chanx_right_in[7]; +assign chanx_left_out[9] = chanx_right_in[8]; +assign chanx_left_out[11] = chanx_right_in[10]; +assign chanx_left_out[12] = chanx_right_in[11]; +assign chanx_left_out[13] = chanx_right_in[12]; +assign chanx_left_out[15] = chanx_right_in[14]; +assign chanx_left_out[16] = chanx_right_in[15]; +assign chanx_left_out[17] = chanx_right_in[16]; +assign chanx_left_out[19] = chanx_right_in[18]; +assign chanx_left_out[20] = chanx_right_in[19]; +assign chanx_left_out[21] = chanx_right_in[20]; +assign chanx_left_out[23] = chanx_right_in[22]; +assign chanx_left_out[24] = chanx_right_in[23]; +assign chanx_left_out[25] = chanx_right_in[24]; +assign chanx_left_out[27] = chanx_right_in[26]; +assign chanx_left_out[28] = chanx_right_in[27]; +assign chanx_left_out[29] = chanx_right_in[28]; +assign chany_bottom_out[29] = chanx_left_in[0]; +assign chanx_right_out[4] = chanx_left_in[3]; +assign chanx_right_out[7] = chanx_left_in[6]; +assign chanx_right_out[8] = chanx_left_in[7]; +assign chanx_right_out[9] = chanx_left_in[8]; +assign chanx_right_out[11] = chanx_left_in[10]; +assign chanx_right_out[12] = chanx_left_in[11]; +assign chanx_right_out[13] = chanx_left_in[12]; +assign chanx_right_out[15] = chanx_left_in[14]; +assign chanx_right_out[16] = chanx_left_in[15]; +assign chanx_right_out[17] = chanx_left_in[16]; +assign chanx_right_out[19] = chanx_left_in[18]; +assign chanx_right_out[20] = chanx_left_in[19]; +assign chanx_right_out[21] = chanx_left_in[20]; +assign chanx_right_out[23] = chanx_left_in[22]; +assign chanx_right_out[24] = chanx_left_in[23]; +assign chanx_right_out[25] = chanx_left_in[24]; +assign chanx_right_out[27] = chanx_left_in[26]; +assign chanx_right_out[28] = chanx_left_in[27]; +assign chanx_right_out[29] = chanx_left_in[28]; + mux_tree_tapbuf_size8 mux_right_track_0 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[9], chany_bottom_in[20], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size8_0_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size8 mux_right_track_2 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[8], chany_bottom_in[19], chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size8_1_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size8 mux_left_track_1 + ( + .in({chanx_right_in[3], chanx_right_in[19], chany_bottom_in[10], chany_bottom_in[21], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size8_2_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size8_mem mem_right_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_0_sram) + ); + mux_tree_tapbuf_size8_mem mem_right_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_1_sram) + ); + mux_tree_tapbuf_size8_mem mem_left_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_2_sram) + ); + mux_tree_tapbuf_size9 mux_right_track_4 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[7], chany_bottom_in[18], chany_bottom_in[29], chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size9_0_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size9 mux_left_track_3 + ( + .in({chanx_right_in[6], chanx_right_in[20], chany_bottom_in[0], chany_bottom_in[11], chany_bottom_in[22], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size9_1_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size9 mux_left_track_5 + ( + .in({chanx_right_in[7], chanx_right_in[22], chany_bottom_in[1], chany_bottom_in[12], chany_bottom_in[23], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size9_2_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size9_mem mem_right_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_0_sram) + ); + mux_tree_tapbuf_size9_mem mem_left_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_1_sram) + ); + mux_tree_tapbuf_size9_mem mem_left_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_2_sram) + ); + mux_tree_tapbuf_size11 mux_right_track_6 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[6], chany_bottom_in[17], chany_bottom_in[28], chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size11_0_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size11 mux_right_track_10 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[5], chany_bottom_in[16], chany_bottom_in[27], chanx_left_in[10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size11_1_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size11 mux_left_track_7 + ( + .in({chanx_right_in[8], chanx_right_in[23], chany_bottom_in[2], chany_bottom_in[13], chany_bottom_in[24], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size11_2_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size11 mux_left_track_11 + ( + .in({chanx_right_in[10], chanx_right_in[24], chany_bottom_in[3], chany_bottom_in[14], chany_bottom_in[25], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size11_3_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size11_mem mem_right_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_0_sram) + ); + mux_tree_tapbuf_size11_mem mem_right_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_1_sram) + ); + mux_tree_tapbuf_size11_mem mem_left_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_2_sram) + ); + mux_tree_tapbuf_size11_mem mem_left_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_3_sram) + ); + mux_tree_tapbuf_size7 mux_right_track_12 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[4], chany_bottom_in[15], chany_bottom_in[26], chanx_left_in[11], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size7_0_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size7 mux_right_track_20 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[3], chany_bottom_in[14], chany_bottom_in[25], chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size7_1_sram), + .sram_inv(mux_right_track_20_undriven_sram_inv), + .out(chanx_right_out[10]) + ); + mux_tree_tapbuf_size7 mux_right_track_28 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[2], chany_bottom_in[13], chany_bottom_in[24], chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size7_2_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size7 mux_left_track_13 + ( + .in({chanx_right_in[11], chanx_right_in[26], chany_bottom_in[4], chany_bottom_in[15], chany_bottom_in[26], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size7_3_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size7 mux_left_track_21 + ( + .in({chanx_right_in[12], chanx_right_in[27], chany_bottom_in[5], chany_bottom_in[16], chany_bottom_in[27], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size7_4_sram), + .sram_inv(mux_left_track_21_undriven_sram_inv), + .out(chanx_left_out[10]) + ); + mux_tree_tapbuf_size7 mux_left_track_29 + ( + .in({chanx_right_in[14], chanx_right_in[28], chany_bottom_in[6], chany_bottom_in[17], chany_bottom_in[28], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size7_5_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size7_mem mem_right_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram) + ); + mux_tree_tapbuf_size7_mem mem_right_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram) + ); + mux_tree_tapbuf_size7_mem mem_right_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram) + ); + mux_tree_tapbuf_size7_mem mem_left_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram) + ); + mux_tree_tapbuf_size7_mem mem_left_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram) + ); + mux_tree_tapbuf_size7_mem mem_left_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_5_sram) + ); + mux_tree_tapbuf_size6 mux_right_track_36 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[1], chany_bottom_in[12], chany_bottom_in[23], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size6_0_sram), + .sram_inv(mux_right_track_36_undriven_sram_inv), + .out(chanx_right_out[18]) + ); + mux_tree_tapbuf_size6 mux_right_track_44 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[0], chany_bottom_in[11], chany_bottom_in[22], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size6_1_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_1 + ( + .in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[1], chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size6_2_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_3 + ( + .in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[2], chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size6_3_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_7 + ( + .in({chanx_right_in[8], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[5], chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size6_4_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_9 + ( + .in({chanx_right_in[10], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[9], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size6_5_sram), + .sram_inv(mux_bottom_track_9_undriven_sram_inv), + .out(chany_bottom_out[4]) + ); + mux_tree_tapbuf_size6 mux_left_track_37 + ( + .in({chanx_right_in[15], chany_bottom_in[7], chany_bottom_in[18], chany_bottom_in[29], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size6_6_sram), + .sram_inv(mux_left_track_37_undriven_sram_inv), + .out(chanx_left_out[18]) + ); + mux_tree_tapbuf_size6_mem mem_right_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram) + ); + mux_tree_tapbuf_size5 mux_right_track_52 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[10], chany_bottom_in[21], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_right_track_52_undriven_sram_inv), + .out(chanx_right_out[26]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_5 + ( + .in({chanx_right_in[7], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[4], chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_11 + ( + .in({chanx_right_in[11], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[11], chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size5 mux_left_track_45 + ( + .in({chanx_right_in[16], chany_bottom_in[8], chany_bottom_in[19], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size5 mux_left_track_53 + ( + .in({chanx_right_in[18], chany_bottom_in[9], chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_left_track_53_undriven_sram_inv), + .out(chanx_left_out[26]) + ); + mux_tree_tapbuf_size5_mem mem_right_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size4 mux_bottom_track_13 + ( + .in({chanx_right_in[12], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[12], chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size4_0_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_15 + ( + .in({chanx_right_in[14], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[14], chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size4_1_sram), + .sram_inv(mux_bottom_track_15_undriven_sram_inv), + .out(chany_bottom_out[7]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_17 + ( + .in({chanx_right_in[15], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[15], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size4_2_sram), + .sram_inv(mux_bottom_track_17_undriven_sram_inv), + .out(chany_bottom_out[8]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_19 + ( + .in({chanx_right_in[16], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[16], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size4_3_sram), + .sram_inv(mux_bottom_track_19_undriven_sram_inv), + .out(chany_bottom_out[9]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_37 + ( + .in({chanx_right_in[28], chanx_right_in[29], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size4_4_sram), + .sram_inv(mux_bottom_track_37_undriven_sram_inv), + .out(chany_bottom_out[18]) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_17 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_19 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram) + ); + mux_tree_tapbuf_size3 mux_bottom_track_21 + ( + .in({chanx_right_in[18], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_bottom_track_21_undriven_sram_inv), + .out(chany_bottom_out[10]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_23 + ( + .in({chanx_right_in[19], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_bottom_track_23_undriven_sram_inv), + .out(chany_bottom_out[11]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_25 + ( + .in({chanx_right_in[20], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_bottom_track_25_undriven_sram_inv), + .out(chany_bottom_out[12]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_27 + ( + .in({chanx_right_in[22], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_bottom_track_27_undriven_sram_inv), + .out(chany_bottom_out[13]) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_23 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_25 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_27 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size2 mux_bottom_track_29 + ( + .in({chanx_right_in[23], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_31 + ( + .in({chanx_right_in[24], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_bottom_track_31_undriven_sram_inv), + .out(chany_bottom_out[15]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_33 + ( + .in({chanx_right_in[26], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_bottom_track_33_undriven_sram_inv), + .out(chany_bottom_out[16]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_35 + ( + .in({chanx_right_in[27], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_bottom_track_35_undriven_sram_inv), + .out(chany_bottom_out[17]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_39 + ( + .in({chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_bottom_track_39_undriven_sram_inv), + .out(chany_bottom_out[19]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_41 + ( + .in({chanx_right_in[21], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_bottom_track_41_undriven_sram_inv), + .out(chany_bottom_out[20]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_43 + ( + .in({chanx_right_in[17], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_bottom_track_43_undriven_sram_inv), + .out(chany_bottom_out[21]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_45 + ( + .in({chanx_right_in[13], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_47 + ( + .in({chanx_right_in[9], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_bottom_track_47_undriven_sram_inv), + .out(chany_bottom_out[23]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_49 + ( + .in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_bottom_track_49_undriven_sram_inv), + .out(chany_bottom_out[24]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_51 + ( + .in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_bottom_track_51_undriven_sram_inv), + .out(chany_bottom_out[25]) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_31 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_33 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_35 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_39 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_41 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_43 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_47 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_49 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_51 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__0_.v new file mode 100644 index 0000000..51920ee --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__0_.v @@ -0,0 +1,889 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_8__0_ +( + pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + chanx_left_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_left_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_top_in; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + input [0:29]chanx_left_in; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + input ccff_head; + output [0:29]chany_top_out; + output [0:29]chanx_left_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_top_in; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire [0:29]chanx_left_in; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head; + wire [0:29]chany_top_out; + wire [0:29]chanx_left_out; + wire ccff_tail; + wire [0:1]mux_left_track_11_undriven_sram_inv; + wire [0:1]mux_left_track_13_undriven_sram_inv; + wire [0:1]mux_left_track_15_undriven_sram_inv; + wire [0:1]mux_left_track_17_undriven_sram_inv; + wire [0:1]mux_left_track_19_undriven_sram_inv; + wire [0:1]mux_left_track_1_undriven_sram_inv; + wire [0:1]mux_left_track_29_undriven_sram_inv; + wire [0:1]mux_left_track_31_undriven_sram_inv; + wire [0:1]mux_left_track_33_undriven_sram_inv; + wire [0:1]mux_left_track_35_undriven_sram_inv; + wire [0:1]mux_left_track_3_undriven_sram_inv; + wire [0:1]mux_left_track_45_undriven_sram_inv; + wire [0:1]mux_left_track_47_undriven_sram_inv; + wire [0:1]mux_left_track_49_undriven_sram_inv; + wire [0:1]mux_left_track_51_undriven_sram_inv; + wire [0:1]mux_left_track_5_undriven_sram_inv; + wire [0:1]mux_left_track_7_undriven_sram_inv; + wire [0:1]mux_left_track_9_undriven_sram_inv; + wire [0:2]mux_top_track_0_undriven_sram_inv; + wire [0:2]mux_top_track_10_undriven_sram_inv; + wire [0:1]mux_top_track_12_undriven_sram_inv; + wire [0:1]mux_top_track_14_undriven_sram_inv; + wire [0:1]mux_top_track_16_undriven_sram_inv; + wire [0:1]mux_top_track_18_undriven_sram_inv; + wire [0:1]mux_top_track_20_undriven_sram_inv; + wire [0:1]mux_top_track_22_undriven_sram_inv; + wire [0:1]mux_top_track_24_undriven_sram_inv; + wire [0:1]mux_top_track_26_undriven_sram_inv; + wire [0:1]mux_top_track_28_undriven_sram_inv; + wire [0:2]mux_top_track_2_undriven_sram_inv; + wire [0:1]mux_top_track_30_undriven_sram_inv; + wire [0:1]mux_top_track_32_undriven_sram_inv; + wire [0:1]mux_top_track_34_undriven_sram_inv; + wire [0:1]mux_top_track_36_undriven_sram_inv; + wire [0:1]mux_top_track_38_undriven_sram_inv; + wire [0:1]mux_top_track_40_undriven_sram_inv; + wire [0:1]mux_top_track_42_undriven_sram_inv; + wire [0:1]mux_top_track_44_undriven_sram_inv; + wire [0:1]mux_top_track_46_undriven_sram_inv; + wire [0:1]mux_top_track_48_undriven_sram_inv; + wire [0:2]mux_top_track_4_undriven_sram_inv; + wire [0:1]mux_top_track_50_undriven_sram_inv; + wire [0:2]mux_top_track_6_undriven_sram_inv; + wire [0:2]mux_top_track_8_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_11_sram; + wire [0:1]mux_tree_tapbuf_size2_12_sram; + wire [0:1]mux_tree_tapbuf_size2_13_sram; + wire [0:1]mux_tree_tapbuf_size2_14_sram; + wire [0:1]mux_tree_tapbuf_size2_15_sram; + wire [0:1]mux_tree_tapbuf_size2_16_sram; + wire [0:1]mux_tree_tapbuf_size2_17_sram; + wire [0:1]mux_tree_tapbuf_size2_18_sram; + wire [0:1]mux_tree_tapbuf_size2_19_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_20_sram; + wire [0:1]mux_tree_tapbuf_size2_21_sram; + wire [0:1]mux_tree_tapbuf_size2_22_sram; + wire [0:1]mux_tree_tapbuf_size2_23_sram; + wire [0:1]mux_tree_tapbuf_size2_24_sram; + wire [0:1]mux_tree_tapbuf_size2_25_sram; + wire [0:1]mux_tree_tapbuf_size2_26_sram; + wire [0:1]mux_tree_tapbuf_size2_27_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire mux_tree_tapbuf_size2_mem_19_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_20_ccff_tail; + wire mux_tree_tapbuf_size2_mem_21_ccff_tail; + wire mux_tree_tapbuf_size2_mem_22_ccff_tail; + wire mux_tree_tapbuf_size2_mem_23_ccff_tail; + wire mux_tree_tapbuf_size2_mem_24_ccff_tail; + wire mux_tree_tapbuf_size2_mem_25_ccff_tail; + wire mux_tree_tapbuf_size2_mem_26_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire [0:1]mux_tree_tapbuf_size3_7_sram; + wire [0:1]mux_tree_tapbuf_size3_8_sram; + wire [0:1]mux_tree_tapbuf_size3_9_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire mux_tree_tapbuf_size3_mem_7_ccff_tail; + wire mux_tree_tapbuf_size3_mem_8_ccff_tail; + wire mux_tree_tapbuf_size3_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire [0:2]mux_tree_tapbuf_size5_5_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire mux_tree_tapbuf_size5_mem_5_ccff_tail; + +assign chanx_left_out[29] = chany_top_in[1]; +assign chanx_left_out[28] = chany_top_in[2]; +assign chanx_left_out[27] = chany_top_in[3]; +assign chanx_left_out[26] = chany_top_in[4]; +assign chanx_left_out[21] = chany_top_in[9]; +assign chanx_left_out[20] = chany_top_in[10]; +assign chanx_left_out[19] = chany_top_in[11]; +assign chanx_left_out[18] = chany_top_in[12]; +assign chanx_left_out[13] = chany_top_in[17]; +assign chanx_left_out[12] = chany_top_in[18]; +assign chanx_left_out[11] = chany_top_in[19]; +assign chanx_left_out[10] = chany_top_in[20]; +assign chany_top_out[29] = chanx_left_in[1]; +assign chany_top_out[28] = chanx_left_in[2]; +assign chany_top_out[27] = chanx_left_in[3]; +assign chany_top_out[26] = chanx_left_in[4]; + mux_tree_tapbuf_size5 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[0]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size5 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size5 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size5 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); + mux_tree_tapbuf_size5 mux_top_track_8 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_top_track_8_undriven_sram_inv), + .out(chany_top_out[4]) + ); + mux_tree_tapbuf_size5 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size5_5_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size5_mem mem_top_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram) + ); + mux_tree_tapbuf_size3 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size3 mux_top_track_14 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_top_track_14_undriven_sram_inv), + .out(chany_top_out[7]) + ); + mux_tree_tapbuf_size3 mux_top_track_16 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_top_track_16_undriven_sram_inv), + .out(chany_top_out[8]) + ); + mux_tree_tapbuf_size3 mux_top_track_18 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_top_track_18_undriven_sram_inv), + .out(chany_top_out[9]) + ); + mux_tree_tapbuf_size3 mux_top_track_44 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size3 mux_top_track_46 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_top_track_46_undriven_sram_inv), + .out(chany_top_out[23]) + ); + mux_tree_tapbuf_size3 mux_top_track_48 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_top_track_48_undriven_sram_inv), + .out(chany_top_out[24]) + ); + mux_tree_tapbuf_size3 mux_top_track_50 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[5]}), + .sram(mux_tree_tapbuf_size3_7_sram), + .sram_inv(mux_top_track_50_undriven_sram_inv), + .out(chany_top_out[25]) + ); + mux_tree_tapbuf_size3 mux_left_track_1 + ( + .in({chany_top_in[0], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_8_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size3 mux_left_track_7 + ( + .in({chany_top_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_9_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size3_mem mem_top_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_16 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_18 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_46 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_48 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_50 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram) + ); + mux_tree_tapbuf_size2 mux_top_track_20 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_top_track_20_undriven_sram_inv), + .out(chany_top_out[10]) + ); + mux_tree_tapbuf_size2 mux_top_track_22 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_top_track_22_undriven_sram_inv), + .out(chany_top_out[11]) + ); + mux_tree_tapbuf_size2 mux_top_track_24 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_top_track_24_undriven_sram_inv), + .out(chany_top_out[12]) + ); + mux_tree_tapbuf_size2 mux_top_track_26 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_top_track_26_undriven_sram_inv), + .out(chany_top_out[13]) + ); + mux_tree_tapbuf_size2 mux_top_track_28 + ( + .in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size2 mux_top_track_30 + ( + .in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_top_track_30_undriven_sram_inv), + .out(chany_top_out[15]) + ); + mux_tree_tapbuf_size2 mux_top_track_32 + ( + .in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_top_track_32_undriven_sram_inv), + .out(chany_top_out[16]) + ); + mux_tree_tapbuf_size2 mux_top_track_34 + ( + .in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_top_track_34_undriven_sram_inv), + .out(chany_top_out[17]) + ); + mux_tree_tapbuf_size2 mux_top_track_36 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_top_track_36_undriven_sram_inv), + .out(chany_top_out[18]) + ); + mux_tree_tapbuf_size2 mux_top_track_38 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_top_track_38_undriven_sram_inv), + .out(chany_top_out[19]) + ); + mux_tree_tapbuf_size2 mux_top_track_40 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_top_track_40_undriven_sram_inv), + .out(chany_top_out[20]) + ); + mux_tree_tapbuf_size2 mux_top_track_42 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size2_11_sram), + .sram_inv(mux_top_track_42_undriven_sram_inv), + .out(chany_top_out[21]) + ); + mux_tree_tapbuf_size2 mux_left_track_3 + ( + .in({chany_top_in[29], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_12_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size2 mux_left_track_5 + ( + .in({chany_top_in[28], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_13_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size2 mux_left_track_9 + ( + .in({chany_top_in[26], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_14_sram), + .sram_inv(mux_left_track_9_undriven_sram_inv), + .out(chanx_left_out[4]) + ); + mux_tree_tapbuf_size2 mux_left_track_11 + ( + .in({chany_top_in[25], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_15_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size2 mux_left_track_13 + ( + .in({chany_top_in[24], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_16_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size2 mux_left_track_15 + ( + .in({chany_top_in[23], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_17_sram), + .sram_inv(mux_left_track_15_undriven_sram_inv), + .out(chanx_left_out[7]) + ); + mux_tree_tapbuf_size2 mux_left_track_17 + ( + .in({chany_top_in[22], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_18_sram), + .sram_inv(mux_left_track_17_undriven_sram_inv), + .out(chanx_left_out[8]) + ); + mux_tree_tapbuf_size2 mux_left_track_19 + ( + .in({chany_top_in[21], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_19_sram), + .sram_inv(mux_left_track_19_undriven_sram_inv), + .out(chanx_left_out[9]) + ); + mux_tree_tapbuf_size2 mux_left_track_29 + ( + .in({chany_top_in[16], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_20_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size2 mux_left_track_31 + ( + .in({chany_top_in[15], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram), + .sram_inv(mux_left_track_31_undriven_sram_inv), + .out(chanx_left_out[15]) + ); + mux_tree_tapbuf_size2 mux_left_track_33 + ( + .in({chany_top_in[14], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_22_sram), + .sram_inv(mux_left_track_33_undriven_sram_inv), + .out(chanx_left_out[16]) + ); + mux_tree_tapbuf_size2 mux_left_track_35 + ( + .in({chany_top_in[13], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_23_sram), + .sram_inv(mux_left_track_35_undriven_sram_inv), + .out(chanx_left_out[17]) + ); + mux_tree_tapbuf_size2 mux_left_track_45 + ( + .in({chany_top_in[8], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_24_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size2 mux_left_track_47 + ( + .in({chany_top_in[7], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_25_sram), + .sram_inv(mux_left_track_47_undriven_sram_inv), + .out(chanx_left_out[23]) + ); + mux_tree_tapbuf_size2 mux_left_track_49 + ( + .in({chany_top_in[6], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_26_sram), + .sram_inv(mux_left_track_49_undriven_sram_inv), + .out(chanx_left_out[24]) + ); + mux_tree_tapbuf_size2 mux_left_track_51 + ( + .in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_27_sram), + .sram_inv(mux_left_track_51_undriven_sram_inv), + .out(chanx_left_out[25]) + ); + mux_tree_tapbuf_size2_mem mem_top_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_22 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_24 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_26 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_30 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_32 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_34 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_38 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_40 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_42 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_17 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_19 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_31 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_33 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_35 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_47 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_25_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_49 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_26_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_51 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_27_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__1_.v new file mode 100644 index 0000000..bdabe6b --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__1_.v @@ -0,0 +1,1058 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_8__1_ +( + pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + chany_bottom_in, + bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_left_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + ccff_head, + chany_top_out, + chany_bottom_out, + chanx_left_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_top_in; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + input [0:29]chany_bottom_in; + input bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input [0:29]chanx_left_in; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input ccff_head; + output [0:29]chany_top_out; + output [0:29]chany_bottom_out; + output [0:29]chanx_left_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_top_in; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire [0:29]chany_bottom_in; + wire bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire [0:29]chanx_left_in; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire ccff_head; + wire [0:29]chany_top_out; + wire [0:29]chany_bottom_out; + wire [0:29]chanx_left_out; + wire ccff_tail; + wire [0:3]mux_bottom_track_11_undriven_sram_inv; + wire [0:2]mux_bottom_track_13_undriven_sram_inv; + wire [0:3]mux_bottom_track_1_undriven_sram_inv; + wire [0:2]mux_bottom_track_21_undriven_sram_inv; + wire [0:2]mux_bottom_track_29_undriven_sram_inv; + wire [0:2]mux_bottom_track_37_undriven_sram_inv; + wire [0:3]mux_bottom_track_3_undriven_sram_inv; + wire [0:2]mux_bottom_track_45_undriven_sram_inv; + wire [0:2]mux_bottom_track_53_undriven_sram_inv; + wire [0:3]mux_bottom_track_5_undriven_sram_inv; + wire [0:3]mux_bottom_track_7_undriven_sram_inv; + wire [0:2]mux_left_track_11_undriven_sram_inv; + wire [0:2]mux_left_track_13_undriven_sram_inv; + wire [0:2]mux_left_track_15_undriven_sram_inv; + wire [0:2]mux_left_track_17_undriven_sram_inv; + wire [0:2]mux_left_track_19_undriven_sram_inv; + wire [0:2]mux_left_track_1_undriven_sram_inv; + wire [0:2]mux_left_track_21_undriven_sram_inv; + wire [0:2]mux_left_track_23_undriven_sram_inv; + wire [0:1]mux_left_track_25_undriven_sram_inv; + wire [0:1]mux_left_track_27_undriven_sram_inv; + wire [0:1]mux_left_track_29_undriven_sram_inv; + wire [0:1]mux_left_track_31_undriven_sram_inv; + wire [0:1]mux_left_track_33_undriven_sram_inv; + wire [0:1]mux_left_track_35_undriven_sram_inv; + wire [0:1]mux_left_track_37_undriven_sram_inv; + wire [0:2]mux_left_track_3_undriven_sram_inv; + wire [0:1]mux_left_track_41_undriven_sram_inv; + wire [0:1]mux_left_track_45_undriven_sram_inv; + wire [0:1]mux_left_track_47_undriven_sram_inv; + wire [0:1]mux_left_track_49_undriven_sram_inv; + wire [0:1]mux_left_track_51_undriven_sram_inv; + wire [0:1]mux_left_track_53_undriven_sram_inv; + wire [0:1]mux_left_track_55_undriven_sram_inv; + wire [0:1]mux_left_track_57_undriven_sram_inv; + wire [0:2]mux_left_track_5_undriven_sram_inv; + wire [0:2]mux_left_track_7_undriven_sram_inv; + wire [0:2]mux_left_track_9_undriven_sram_inv; + wire [0:3]mux_top_track_0_undriven_sram_inv; + wire [0:3]mux_top_track_10_undriven_sram_inv; + wire [0:2]mux_top_track_12_undriven_sram_inv; + wire [0:2]mux_top_track_20_undriven_sram_inv; + wire [0:2]mux_top_track_28_undriven_sram_inv; + wire [0:3]mux_top_track_2_undriven_sram_inv; + wire [0:2]mux_top_track_36_undriven_sram_inv; + wire [0:2]mux_top_track_44_undriven_sram_inv; + wire [0:3]mux_top_track_4_undriven_sram_inv; + wire [0:2]mux_top_track_52_undriven_sram_inv; + wire [0:3]mux_top_track_6_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:3]mux_tree_tapbuf_size11_0_sram; + wire [0:3]mux_tree_tapbuf_size11_1_sram; + wire [0:3]mux_tree_tapbuf_size11_2_sram; + wire mux_tree_tapbuf_size11_mem_0_ccff_tail; + wire mux_tree_tapbuf_size11_mem_1_ccff_tail; + wire mux_tree_tapbuf_size11_mem_2_ccff_tail; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire [0:1]mux_tree_tapbuf_size3_7_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire mux_tree_tapbuf_size3_mem_7_ccff_tail; + wire [0:2]mux_tree_tapbuf_size4_0_sram; + wire [0:2]mux_tree_tapbuf_size4_1_sram; + wire [0:2]mux_tree_tapbuf_size4_2_sram; + wire [0:2]mux_tree_tapbuf_size4_3_sram; + wire [0:2]mux_tree_tapbuf_size4_4_sram; + wire [0:2]mux_tree_tapbuf_size4_5_sram; + wire mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire mux_tree_tapbuf_size4_mem_4_ccff_tail; + wire mux_tree_tapbuf_size4_mem_5_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire [0:2]mux_tree_tapbuf_size6_0_sram; + wire [0:2]mux_tree_tapbuf_size6_1_sram; + wire [0:2]mux_tree_tapbuf_size6_2_sram; + wire [0:2]mux_tree_tapbuf_size6_3_sram; + wire [0:2]mux_tree_tapbuf_size6_4_sram; + wire [0:2]mux_tree_tapbuf_size6_5_sram; + wire [0:2]mux_tree_tapbuf_size6_6_sram; + wire [0:2]mux_tree_tapbuf_size6_7_sram; + wire [0:2]mux_tree_tapbuf_size6_8_sram; + wire mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire mux_tree_tapbuf_size6_mem_7_ccff_tail; + wire mux_tree_tapbuf_size6_mem_8_ccff_tail; + wire [0:2]mux_tree_tapbuf_size7_0_sram; + wire [0:2]mux_tree_tapbuf_size7_1_sram; + wire [0:2]mux_tree_tapbuf_size7_2_sram; + wire [0:2]mux_tree_tapbuf_size7_3_sram; + wire [0:2]mux_tree_tapbuf_size7_4_sram; + wire mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire mux_tree_tapbuf_size7_mem_4_ccff_tail; + wire [0:3]mux_tree_tapbuf_size8_0_sram; + wire [0:3]mux_tree_tapbuf_size8_1_sram; + wire mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:3]mux_tree_tapbuf_size9_0_sram; + wire [0:3]mux_tree_tapbuf_size9_1_sram; + wire [0:3]mux_tree_tapbuf_size9_2_sram; + wire [0:3]mux_tree_tapbuf_size9_3_sram; + wire mux_tree_tapbuf_size9_mem_0_ccff_tail; + wire mux_tree_tapbuf_size9_mem_1_ccff_tail; + wire mux_tree_tapbuf_size9_mem_2_ccff_tail; + wire mux_tree_tapbuf_size9_mem_3_ccff_tail; + +assign chanx_left_out[29] = chany_top_in[1]; +assign chany_bottom_out[4] = chany_top_in[3]; +assign chany_bottom_out[7] = chany_top_in[6]; +assign chany_bottom_out[8] = chany_top_in[7]; +assign chany_bottom_out[9] = chany_top_in[8]; +assign chany_bottom_out[11] = chany_top_in[10]; +assign chany_bottom_out[12] = chany_top_in[11]; +assign chany_bottom_out[13] = chany_top_in[12]; +assign chany_bottom_out[15] = chany_top_in[14]; +assign chany_bottom_out[16] = chany_top_in[15]; +assign chany_bottom_out[17] = chany_top_in[16]; +assign chany_bottom_out[19] = chany_top_in[18]; +assign chany_bottom_out[20] = chany_top_in[19]; +assign chany_bottom_out[21] = chany_top_in[20]; +assign chany_bottom_out[23] = chany_top_in[22]; +assign chany_bottom_out[24] = chany_top_in[23]; +assign chany_bottom_out[25] = chany_top_in[24]; +assign chanx_left_out[21] = chany_top_in[25]; +assign chany_bottom_out[27] = chany_top_in[26]; +assign chany_bottom_out[28] = chany_top_in[27]; +assign chany_bottom_out[29] = chany_top_in[28]; +assign chany_top_out[4] = chany_bottom_in[3]; +assign chany_top_out[7] = chany_bottom_in[6]; +assign chany_top_out[8] = chany_bottom_in[7]; +assign chany_top_out[9] = chany_bottom_in[8]; +assign chany_top_out[11] = chany_bottom_in[10]; +assign chany_top_out[12] = chany_bottom_in[11]; +assign chany_top_out[13] = chany_bottom_in[12]; +assign chany_top_out[15] = chany_bottom_in[14]; +assign chany_top_out[16] = chany_bottom_in[15]; +assign chany_top_out[17] = chany_bottom_in[16]; +assign chany_top_out[19] = chany_bottom_in[18]; +assign chany_top_out[20] = chany_bottom_in[19]; +assign chany_top_out[21] = chany_bottom_in[20]; +assign chany_top_out[23] = chany_bottom_in[22]; +assign chany_top_out[24] = chany_bottom_in[23]; +assign chany_top_out[25] = chany_bottom_in[24]; +assign chany_top_out[27] = chany_bottom_in[26]; +assign chany_top_out[28] = chany_bottom_in[27]; +assign chany_top_out[29] = chany_bottom_in[28]; +assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + mux_tree_tapbuf_size9 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chany_bottom_in[3], chany_bottom_in[19], chanx_left_in[0], chanx_left_in[11], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size9_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size9 mux_bottom_track_1 + ( + .in({chany_top_in[3], chany_top_in[19], bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[1], chanx_left_in[12], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size9_1_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size9 mux_bottom_track_3 + ( + .in({chany_top_in[6], chany_top_in[20], bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[2], chanx_left_in[13], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size9_2_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size9 mux_bottom_track_5 + ( + .in({chany_top_in[7], chany_top_in[22], bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[3], chanx_left_in[14], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size9_3_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size9_mem mem_top_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_0_sram) + ); + mux_tree_tapbuf_size9_mem mem_bottom_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_1_sram) + ); + mux_tree_tapbuf_size9_mem mem_bottom_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_2_sram) + ); + mux_tree_tapbuf_size9_mem mem_bottom_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_3_sram) + ); + mux_tree_tapbuf_size8 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[6], chany_bottom_in[20], chanx_left_in[10], chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size8_0_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size8 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[7], chany_bottom_in[22], chanx_left_in[9], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size8_1_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size8_mem mem_top_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_0_sram) + ); + mux_tree_tapbuf_size8_mem mem_top_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_1_sram) + ); + mux_tree_tapbuf_size10 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[8], chany_bottom_in[23], chanx_left_in[8], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); + mux_tree_tapbuf_size10_mem mem_top_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size11 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[10], chany_bottom_in[24], chanx_left_in[7], chanx_left_in[18], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size11_0_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size11 mux_bottom_track_7 + ( + .in({chany_top_in[8], chany_top_in[23], bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[4], chanx_left_in[15], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size11_1_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size11 mux_bottom_track_11 + ( + .in({chany_top_in[10], chany_top_in[24], bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[5], chanx_left_in[16], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size11_2_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size11_mem mem_top_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_0_sram) + ); + mux_tree_tapbuf_size11_mem mem_bottom_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_1_sram) + ); + mux_tree_tapbuf_size11_mem mem_bottom_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_2_sram) + ); + mux_tree_tapbuf_size7 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chany_bottom_in[11], chany_bottom_in[26], chanx_left_in[6], chanx_left_in[17], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size7_0_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size7 mux_top_track_20 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chany_bottom_in[12], chany_bottom_in[27], chanx_left_in[5], chanx_left_in[16], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size7_1_sram), + .sram_inv(mux_top_track_20_undriven_sram_inv), + .out(chany_top_out[10]) + ); + mux_tree_tapbuf_size7 mux_top_track_28 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chany_bottom_in[14], chany_bottom_in[28], chanx_left_in[4], chanx_left_in[15], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size7_2_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size7 mux_bottom_track_13 + ( + .in({chany_top_in[11], chany_top_in[26], bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[6], chanx_left_in[17], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size7_3_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size7 mux_bottom_track_21 + ( + .in({chany_top_in[12], chany_top_in[27], bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[7], chanx_left_in[18], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size7_4_sram), + .sram_inv(mux_bottom_track_21_undriven_sram_inv), + .out(chany_bottom_out[10]) + ); + mux_tree_tapbuf_size7_mem mem_top_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram) + ); + mux_tree_tapbuf_size7_mem mem_top_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram) + ); + mux_tree_tapbuf_size7_mem mem_top_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram) + ); + mux_tree_tapbuf_size7_mem mem_bottom_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram) + ); + mux_tree_tapbuf_size7_mem mem_bottom_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram) + ); + mux_tree_tapbuf_size6 mux_top_track_36 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chany_bottom_in[15], chanx_left_in[3], chanx_left_in[14], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size6_0_sram), + .sram_inv(mux_top_track_36_undriven_sram_inv), + .out(chany_top_out[18]) + ); + mux_tree_tapbuf_size6 mux_top_track_44 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[16], chanx_left_in[2], chanx_left_in[13], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size6_1_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size6 mux_top_track_52 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[18], chanx_left_in[1], chanx_left_in[12], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size6_2_sram), + .sram_inv(mux_top_track_52_undriven_sram_inv), + .out(chany_top_out[26]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_29 + ( + .in({chany_top_in[14], chany_top_in[28], bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[8], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size6_3_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_53 + ( + .in({chany_top_in[18], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[0], chanx_left_in[11], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size6_4_sram), + .sram_inv(mux_bottom_track_53_undriven_sram_inv), + .out(chany_bottom_out[26]) + ); + mux_tree_tapbuf_size6 mux_left_track_1 + ( + .in({chany_top_in[0], chany_top_in[3], chany_bottom_in[3], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size6_5_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size6 mux_left_track_3 + ( + .in({chany_top_in[6], chany_bottom_in[0], chany_bottom_in[6], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size6_6_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size6 mux_left_track_7 + ( + .in({chany_top_in[8], chany_bottom_in[2], chany_bottom_in[8], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size6_7_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size6 mux_left_track_9 + ( + .in({chany_top_in[10], chany_bottom_in[4], chany_bottom_in[10], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size6_8_sram), + .sram_inv(mux_left_track_9_undriven_sram_inv), + .out(chanx_left_out[4]) + ); + mux_tree_tapbuf_size6_mem mem_top_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram) + ); + mux_tree_tapbuf_size5 mux_bottom_track_37 + ( + .in({chany_top_in[15], bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[9], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_bottom_track_37_undriven_sram_inv), + .out(chany_bottom_out[18]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_45 + ( + .in({chany_top_in[16], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[10], chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size5 mux_left_track_5 + ( + .in({chany_top_in[7], chany_bottom_in[1], chany_bottom_in[7], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size5 mux_left_track_11 + ( + .in({chany_top_in[11], chany_bottom_in[5], chany_bottom_in[11], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size4 mux_left_track_13 + ( + .in({chany_top_in[12], chany_bottom_in[9], chany_bottom_in[12], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size4_0_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size4 mux_left_track_15 + ( + .in({chany_top_in[14], chany_bottom_in[13], chany_bottom_in[14], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size4_1_sram), + .sram_inv(mux_left_track_15_undriven_sram_inv), + .out(chanx_left_out[7]) + ); + mux_tree_tapbuf_size4 mux_left_track_17 + ( + .in({chany_top_in[15], chany_bottom_in[15], chany_bottom_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size4_2_sram), + .sram_inv(mux_left_track_17_undriven_sram_inv), + .out(chanx_left_out[8]) + ); + mux_tree_tapbuf_size4 mux_left_track_19 + ( + .in({chany_top_in[16], chany_bottom_in[16], chany_bottom_in[21], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size4_3_sram), + .sram_inv(mux_left_track_19_undriven_sram_inv), + .out(chanx_left_out[9]) + ); + mux_tree_tapbuf_size4 mux_left_track_21 + ( + .in({chany_top_in[18], chany_bottom_in[18], chany_bottom_in[25], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size4_4_sram), + .sram_inv(mux_left_track_21_undriven_sram_inv), + .out(chanx_left_out[10]) + ); + mux_tree_tapbuf_size4 mux_left_track_23 + ( + .in({chany_top_in[19], chany_bottom_in[19], chany_bottom_in[29], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size4_5_sram), + .sram_inv(mux_left_track_23_undriven_sram_inv), + .out(chanx_left_out[11]) + ); + mux_tree_tapbuf_size4_mem mem_left_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_17 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_19 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_23 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram) + ); + mux_tree_tapbuf_size3 mux_left_track_25 + ( + .in({chany_top_in[20], chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_left_track_25_undriven_sram_inv), + .out(chanx_left_out[12]) + ); + mux_tree_tapbuf_size3 mux_left_track_27 + ( + .in({chany_top_in[22], chany_bottom_in[22], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_left_track_27_undriven_sram_inv), + .out(chanx_left_out[13]) + ); + mux_tree_tapbuf_size3 mux_left_track_29 + ( + .in({chany_top_in[23], chany_bottom_in[23], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size3 mux_left_track_31 + ( + .in({chany_top_in[24], chany_bottom_in[24], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_left_track_31_undriven_sram_inv), + .out(chanx_left_out[15]) + ); + mux_tree_tapbuf_size3 mux_left_track_33 + ( + .in({chany_top_in[26], chany_bottom_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_left_track_33_undriven_sram_inv), + .out(chanx_left_out[16]) + ); + mux_tree_tapbuf_size3 mux_left_track_35 + ( + .in({chany_top_in[27], chany_bottom_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_left_track_35_undriven_sram_inv), + .out(chanx_left_out[17]) + ); + mux_tree_tapbuf_size3 mux_left_track_37 + ( + .in({chany_top_in[28], chany_bottom_in[28], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_left_track_37_undriven_sram_inv), + .out(chanx_left_out[18]) + ); + mux_tree_tapbuf_size3 mux_left_track_51 + ( + .in({chany_top_in[9], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_7_sram), + .sram_inv(mux_left_track_51_undriven_sram_inv), + .out(chanx_left_out[25]) + ); + mux_tree_tapbuf_size3_mem mem_left_track_25 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_27 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_31 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_33 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_35 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_51 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram) + ); + mux_tree_tapbuf_size2 mux_left_track_41 + ( + .in({chany_top_in[29], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_left_track_41_undriven_sram_inv), + .out(chanx_left_out[20]) + ); + mux_tree_tapbuf_size2 mux_left_track_45 + ( + .in({chany_top_in[21], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size2 mux_left_track_47 + ( + .in({chany_top_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_left_track_47_undriven_sram_inv), + .out(chanx_left_out[23]) + ); + mux_tree_tapbuf_size2 mux_left_track_49 + ( + .in({chany_top_in[13], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_left_track_49_undriven_sram_inv), + .out(chanx_left_out[24]) + ); + mux_tree_tapbuf_size2 mux_left_track_53 + ( + .in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_left_track_53_undriven_sram_inv), + .out(chanx_left_out[26]) + ); + mux_tree_tapbuf_size2 mux_left_track_55 + ( + .in({chany_top_in[4], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_left_track_55_undriven_sram_inv), + .out(chanx_left_out[27]) + ); + mux_tree_tapbuf_size2 mux_left_track_57 + ( + .in({chany_top_in[2], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_left_track_57_undriven_sram_inv), + .out(chanx_left_out[28]) + ); + mux_tree_tapbuf_size2_mem mem_left_track_41 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_47 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_49 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_55 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_57 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__8_.v new file mode 100644 index 0000000..79a9f96 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__8_.v @@ -0,0 +1,1117 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_8__8_ +( + pReset, + prog_clk, + chany_bottom_in, + bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_left_in, + left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + ccff_head, + chany_bottom_out, + chanx_left_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_bottom_in; + input bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input [0:29]chanx_left_in; + input left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input ccff_head; + output [0:29]chany_bottom_out; + output [0:29]chanx_left_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_bottom_in; + wire bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire [0:29]chanx_left_in; + wire left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire ccff_head; + wire [0:29]chany_bottom_out; + wire [0:29]chanx_left_out; + wire ccff_tail; + wire [0:2]mux_bottom_track_11_undriven_sram_inv; + wire [0:1]mux_bottom_track_13_undriven_sram_inv; + wire [0:1]mux_bottom_track_15_undriven_sram_inv; + wire [0:1]mux_bottom_track_17_undriven_sram_inv; + wire [0:1]mux_bottom_track_19_undriven_sram_inv; + wire [0:2]mux_bottom_track_1_undriven_sram_inv; + wire [0:1]mux_bottom_track_21_undriven_sram_inv; + wire [0:1]mux_bottom_track_23_undriven_sram_inv; + wire [0:1]mux_bottom_track_25_undriven_sram_inv; + wire [0:1]mux_bottom_track_27_undriven_sram_inv; + wire [0:1]mux_bottom_track_29_undriven_sram_inv; + wire [0:1]mux_bottom_track_31_undriven_sram_inv; + wire [0:1]mux_bottom_track_33_undriven_sram_inv; + wire [0:1]mux_bottom_track_35_undriven_sram_inv; + wire [0:2]mux_bottom_track_3_undriven_sram_inv; + wire [0:1]mux_bottom_track_45_undriven_sram_inv; + wire [0:1]mux_bottom_track_47_undriven_sram_inv; + wire [0:1]mux_bottom_track_49_undriven_sram_inv; + wire [0:1]mux_bottom_track_51_undriven_sram_inv; + wire [0:1]mux_bottom_track_53_undriven_sram_inv; + wire [0:1]mux_bottom_track_55_undriven_sram_inv; + wire [0:1]mux_bottom_track_57_undriven_sram_inv; + wire [0:1]mux_bottom_track_59_undriven_sram_inv; + wire [0:2]mux_bottom_track_5_undriven_sram_inv; + wire [0:2]mux_bottom_track_7_undriven_sram_inv; + wire [0:2]mux_bottom_track_9_undriven_sram_inv; + wire [0:2]mux_left_track_11_undriven_sram_inv; + wire [0:1]mux_left_track_13_undriven_sram_inv; + wire [0:1]mux_left_track_15_undriven_sram_inv; + wire [0:1]mux_left_track_17_undriven_sram_inv; + wire [0:1]mux_left_track_19_undriven_sram_inv; + wire [0:2]mux_left_track_1_undriven_sram_inv; + wire [0:1]mux_left_track_21_undriven_sram_inv; + wire [0:1]mux_left_track_23_undriven_sram_inv; + wire [0:1]mux_left_track_25_undriven_sram_inv; + wire [0:1]mux_left_track_27_undriven_sram_inv; + wire [0:1]mux_left_track_29_undriven_sram_inv; + wire [0:1]mux_left_track_31_undriven_sram_inv; + wire [0:1]mux_left_track_33_undriven_sram_inv; + wire [0:1]mux_left_track_35_undriven_sram_inv; + wire [0:1]mux_left_track_37_undriven_sram_inv; + wire [0:1]mux_left_track_39_undriven_sram_inv; + wire [0:2]mux_left_track_3_undriven_sram_inv; + wire [0:1]mux_left_track_41_undriven_sram_inv; + wire [0:1]mux_left_track_43_undriven_sram_inv; + wire [0:1]mux_left_track_45_undriven_sram_inv; + wire [0:1]mux_left_track_47_undriven_sram_inv; + wire [0:1]mux_left_track_49_undriven_sram_inv; + wire [0:1]mux_left_track_51_undriven_sram_inv; + wire [0:1]mux_left_track_53_undriven_sram_inv; + wire [0:1]mux_left_track_55_undriven_sram_inv; + wire [0:1]mux_left_track_57_undriven_sram_inv; + wire [0:1]mux_left_track_59_undriven_sram_inv; + wire [0:2]mux_left_track_5_undriven_sram_inv; + wire [0:2]mux_left_track_7_undriven_sram_inv; + wire [0:2]mux_left_track_9_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_11_sram; + wire [0:1]mux_tree_tapbuf_size2_12_sram; + wire [0:1]mux_tree_tapbuf_size2_13_sram; + wire [0:1]mux_tree_tapbuf_size2_14_sram; + wire [0:1]mux_tree_tapbuf_size2_15_sram; + wire [0:1]mux_tree_tapbuf_size2_16_sram; + wire [0:1]mux_tree_tapbuf_size2_17_sram; + wire [0:1]mux_tree_tapbuf_size2_18_sram; + wire [0:1]mux_tree_tapbuf_size2_19_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_20_sram; + wire [0:1]mux_tree_tapbuf_size2_21_sram; + wire [0:1]mux_tree_tapbuf_size2_22_sram; + wire [0:1]mux_tree_tapbuf_size2_23_sram; + wire [0:1]mux_tree_tapbuf_size2_24_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire mux_tree_tapbuf_size2_mem_19_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_20_ccff_tail; + wire mux_tree_tapbuf_size2_mem_21_ccff_tail; + wire mux_tree_tapbuf_size2_mem_22_ccff_tail; + wire mux_tree_tapbuf_size2_mem_23_ccff_tail; + wire mux_tree_tapbuf_size2_mem_24_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_10_sram; + wire [0:1]mux_tree_tapbuf_size3_11_sram; + wire [0:1]mux_tree_tapbuf_size3_12_sram; + wire [0:1]mux_tree_tapbuf_size3_13_sram; + wire [0:1]mux_tree_tapbuf_size3_14_sram; + wire [0:1]mux_tree_tapbuf_size3_15_sram; + wire [0:1]mux_tree_tapbuf_size3_16_sram; + wire [0:1]mux_tree_tapbuf_size3_17_sram; + wire [0:1]mux_tree_tapbuf_size3_18_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire [0:1]mux_tree_tapbuf_size3_7_sram; + wire [0:1]mux_tree_tapbuf_size3_8_sram; + wire [0:1]mux_tree_tapbuf_size3_9_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_10_ccff_tail; + wire mux_tree_tapbuf_size3_mem_11_ccff_tail; + wire mux_tree_tapbuf_size3_mem_12_ccff_tail; + wire mux_tree_tapbuf_size3_mem_13_ccff_tail; + wire mux_tree_tapbuf_size3_mem_14_ccff_tail; + wire mux_tree_tapbuf_size3_mem_15_ccff_tail; + wire mux_tree_tapbuf_size3_mem_16_ccff_tail; + wire mux_tree_tapbuf_size3_mem_17_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire mux_tree_tapbuf_size3_mem_7_ccff_tail; + wire mux_tree_tapbuf_size3_mem_8_ccff_tail; + wire mux_tree_tapbuf_size3_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_10_sram; + wire [0:2]mux_tree_tapbuf_size5_11_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire [0:2]mux_tree_tapbuf_size5_5_sram; + wire [0:2]mux_tree_tapbuf_size5_6_sram; + wire [0:2]mux_tree_tapbuf_size5_7_sram; + wire [0:2]mux_tree_tapbuf_size5_8_sram; + wire [0:2]mux_tree_tapbuf_size5_9_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_10_ccff_tail; + wire mux_tree_tapbuf_size5_mem_11_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire mux_tree_tapbuf_size5_mem_5_ccff_tail; + wire mux_tree_tapbuf_size5_mem_6_ccff_tail; + wire mux_tree_tapbuf_size5_mem_7_ccff_tail; + wire mux_tree_tapbuf_size5_mem_8_ccff_tail; + wire mux_tree_tapbuf_size5_mem_9_ccff_tail; + +assign chany_bottom_out[18] = chanx_left_in[19]; +assign chany_bottom_out[19] = chanx_left_in[20]; +assign chany_bottom_out[20] = chanx_left_in[21]; +assign chany_bottom_out[21] = chanx_left_in[22]; + mux_tree_tapbuf_size5 mux_bottom_track_1 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[1]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_3 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[2]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_5 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_7 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[4]}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_9 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[5]}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_bottom_track_9_undriven_sram_inv), + .out(chany_bottom_out[4]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_11 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size5_5_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size5 mux_left_track_1 + ( + .in({chany_bottom_in[29], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_6_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size5 mux_left_track_3 + ( + .in({chany_bottom_in[0], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size5_7_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size5 mux_left_track_5 + ( + .in({chany_bottom_in[1], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size5_8_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size5 mux_left_track_7 + ( + .in({chany_bottom_in[2], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_9_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size5 mux_left_track_9 + ( + .in({chany_bottom_in[3], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size5_10_sram), + .sram_inv(mux_left_track_9_undriven_sram_inv), + .out(chanx_left_out[4]) + ); + mux_tree_tapbuf_size5 mux_left_track_11 + ( + .in({chany_bottom_in[4], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size5_11_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_6_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_7_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_8_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_9_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_10_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_11_sram) + ); + mux_tree_tapbuf_size2 mux_bottom_track_13 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_15 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_bottom_track_15_undriven_sram_inv), + .out(chany_bottom_out[7]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_17 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_bottom_track_17_undriven_sram_inv), + .out(chany_bottom_out[8]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_19 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_bottom_track_19_undriven_sram_inv), + .out(chany_bottom_out[9]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_21 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_bottom_track_21_undriven_sram_inv), + .out(chany_bottom_out[10]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_23 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_bottom_track_23_undriven_sram_inv), + .out(chany_bottom_out[11]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_25 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_bottom_track_25_undriven_sram_inv), + .out(chany_bottom_out[12]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_27 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_bottom_track_27_undriven_sram_inv), + .out(chany_bottom_out[13]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_53 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_bottom_track_53_undriven_sram_inv), + .out(chany_bottom_out[26]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_55 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_bottom_track_55_undriven_sram_inv), + .out(chany_bottom_out[27]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_57 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_bottom_track_57_undriven_sram_inv), + .out(chany_bottom_out[28]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_59 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[0]}), + .sram(mux_tree_tapbuf_size2_11_sram), + .sram_inv(mux_bottom_track_59_undriven_sram_inv), + .out(chany_bottom_out[29]) + ); + mux_tree_tapbuf_size2 mux_left_track_19 + ( + .in({chany_bottom_in[8], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_12_sram), + .sram_inv(mux_left_track_19_undriven_sram_inv), + .out(chanx_left_out[9]) + ); + mux_tree_tapbuf_size2 mux_left_track_21 + ( + .in({chany_bottom_in[9], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_13_sram), + .sram_inv(mux_left_track_21_undriven_sram_inv), + .out(chanx_left_out[10]) + ); + mux_tree_tapbuf_size2 mux_left_track_23 + ( + .in({chany_bottom_in[10], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_14_sram), + .sram_inv(mux_left_track_23_undriven_sram_inv), + .out(chanx_left_out[11]) + ); + mux_tree_tapbuf_size2 mux_left_track_25 + ( + .in({chany_bottom_in[11], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_15_sram), + .sram_inv(mux_left_track_25_undriven_sram_inv), + .out(chanx_left_out[12]) + ); + mux_tree_tapbuf_size2 mux_left_track_27 + ( + .in({chany_bottom_in[12], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size2_16_sram), + .sram_inv(mux_left_track_27_undriven_sram_inv), + .out(chanx_left_out[13]) + ); + mux_tree_tapbuf_size2 mux_left_track_37 + ( + .in({chany_bottom_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_17_sram), + .sram_inv(mux_left_track_37_undriven_sram_inv), + .out(chanx_left_out[18]) + ); + mux_tree_tapbuf_size2 mux_left_track_39 + ( + .in({chany_bottom_in[18], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_18_sram), + .sram_inv(mux_left_track_39_undriven_sram_inv), + .out(chanx_left_out[19]) + ); + mux_tree_tapbuf_size2 mux_left_track_41 + ( + .in({chany_bottom_in[19], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_19_sram), + .sram_inv(mux_left_track_41_undriven_sram_inv), + .out(chanx_left_out[20]) + ); + mux_tree_tapbuf_size2 mux_left_track_43 + ( + .in({chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size2_20_sram), + .sram_inv(mux_left_track_43_undriven_sram_inv), + .out(chanx_left_out[21]) + ); + mux_tree_tapbuf_size2 mux_left_track_51 + ( + .in({chany_bottom_in[24], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram), + .sram_inv(mux_left_track_51_undriven_sram_inv), + .out(chanx_left_out[25]) + ); + mux_tree_tapbuf_size2 mux_left_track_53 + ( + .in({chany_bottom_in[25], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_22_sram), + .sram_inv(mux_left_track_53_undriven_sram_inv), + .out(chanx_left_out[26]) + ); + mux_tree_tapbuf_size2 mux_left_track_55 + ( + .in({chany_bottom_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_23_sram), + .sram_inv(mux_left_track_55_undriven_sram_inv), + .out(chanx_left_out[27]) + ); + mux_tree_tapbuf_size2 mux_left_track_57 + ( + .in({chany_bottom_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_24_sram), + .sram_inv(mux_left_track_57_undriven_sram_inv), + .out(chanx_left_out[28]) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_17 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_19 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_23 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_25 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_27 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_55 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_57 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_59 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_19 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_23 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_25 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_27 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_39 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_41 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_43 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_51 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_17_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_55 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_57 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram) + ); + mux_tree_tapbuf_size3 mux_bottom_track_29 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_31 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_bottom_track_31_undriven_sram_inv), + .out(chany_bottom_out[15]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_33 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_bottom_track_33_undriven_sram_inv), + .out(chany_bottom_out[16]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_35 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_bottom_track_35_undriven_sram_inv), + .out(chany_bottom_out[17]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_45 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_47 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_bottom_track_47_undriven_sram_inv), + .out(chany_bottom_out[23]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_49 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_bottom_track_49_undriven_sram_inv), + .out(chany_bottom_out[24]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_51 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size3_7_sram), + .sram_inv(mux_bottom_track_51_undriven_sram_inv), + .out(chany_bottom_out[25]) + ); + mux_tree_tapbuf_size3 mux_left_track_13 + ( + .in({chany_bottom_in[5], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_8_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size3 mux_left_track_15 + ( + .in({chany_bottom_in[6], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size3_9_sram), + .sram_inv(mux_left_track_15_undriven_sram_inv), + .out(chanx_left_out[7]) + ); + mux_tree_tapbuf_size3 mux_left_track_17 + ( + .in({chany_bottom_in[7], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_10_sram), + .sram_inv(mux_left_track_17_undriven_sram_inv), + .out(chanx_left_out[8]) + ); + mux_tree_tapbuf_size3 mux_left_track_29 + ( + .in({chany_bottom_in[13], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_11_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size3 mux_left_track_31 + ( + .in({chany_bottom_in[14], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size3_12_sram), + .sram_inv(mux_left_track_31_undriven_sram_inv), + .out(chanx_left_out[15]) + ); + mux_tree_tapbuf_size3 mux_left_track_33 + ( + .in({chany_bottom_in[15], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_13_sram), + .sram_inv(mux_left_track_33_undriven_sram_inv), + .out(chanx_left_out[16]) + ); + mux_tree_tapbuf_size3 mux_left_track_35 + ( + .in({chany_bottom_in[16], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_14_sram), + .sram_inv(mux_left_track_35_undriven_sram_inv), + .out(chanx_left_out[17]) + ); + mux_tree_tapbuf_size3 mux_left_track_45 + ( + .in({chany_bottom_in[21], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_15_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size3 mux_left_track_47 + ( + .in({chany_bottom_in[22], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size3_16_sram), + .sram_inv(mux_left_track_47_undriven_sram_inv), + .out(chanx_left_out[23]) + ); + mux_tree_tapbuf_size3 mux_left_track_49 + ( + .in({chany_bottom_in[23], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_17_sram), + .sram_inv(mux_left_track_49_undriven_sram_inv), + .out(chanx_left_out[24]) + ); + mux_tree_tapbuf_size3 mux_left_track_59 + ( + .in({chany_bottom_in[28], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_18_sram), + .sram_inv(mux_left_track_59_undriven_sram_inv), + .out(chanx_left_out[29]) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_31 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_33 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_35 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_47 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_49 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_51 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_17 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_31 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_12_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_33 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_13_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_35 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_14_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_15_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_47 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_15_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_16_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_49 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_16_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_17_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_59 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size3_18_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/inv_buf_passgate.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/inv_buf_passgate.v new file mode 100644 index 0000000..5fbf891 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/inv_buf_passgate.v @@ -0,0 +1,28 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module const0 +( + const0 +); + + output const0; + + wire const0; + wire \ ; + +assign const0 = \ ; +endmodule + +module const1 +( + const1 +); + + output const1; + + wire const1; + wire \ ; + +assign const1 = \ ; +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/luts.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/luts.v new file mode 100644 index 0000000..ed44c51 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/luts.v @@ -0,0 +1,98 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module frac_lut4 +( + in, + sram, + sram_inv, + mode, + mode_inv, + lut2_out, + lut3_out, + lut4_out +); + + input [0:3]in; + input [0:15]sram; + input [0:15]sram_inv; + input mode; + input mode_inv; + output [0:1]lut2_out; + output [0:1]lut3_out; + output lut4_out; + + wire [0:3]in; + wire [0:15]sram; + wire [0:15]sram_inv; + wire mode; + wire mode_inv; + wire [0:1]lut2_out; + wire [0:1]lut3_out; + wire lut4_out; + wire sky130_fd_sc_hd__buf_2_0_X; + wire sky130_fd_sc_hd__buf_2_1_X; + wire sky130_fd_sc_hd__buf_2_2_X; + wire sky130_fd_sc_hd__buf_2_3_X; + wire sky130_fd_sc_hd__inv_1_0_Y; + wire sky130_fd_sc_hd__inv_1_1_Y; + wire sky130_fd_sc_hd__inv_1_2_Y; + wire sky130_fd_sc_hd__inv_1_3_Y; + wire sky130_fd_sc_hd__or2_1_0_X; + + sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_ + ( + .A(mode), + .B(in[3]), + .X(sky130_fd_sc_hd__or2_1_0_X) + ); + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ + ( + .A(in[0]), + .Y(sky130_fd_sc_hd__inv_1_0_Y) + ); + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ + ( + .A(in[1]), + .Y(sky130_fd_sc_hd__inv_1_1_Y) + ); + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ + ( + .A(in[2]), + .Y(sky130_fd_sc_hd__inv_1_2_Y) + ); + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ + ( + .A(sky130_fd_sc_hd__or2_1_0_X), + .Y(sky130_fd_sc_hd__inv_1_3_Y) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ + ( + .A(in[0]), + .X(sky130_fd_sc_hd__buf_2_0_X) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ + ( + .A(in[1]), + .X(sky130_fd_sc_hd__buf_2_1_X) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ + ( + .A(in[2]), + .X(sky130_fd_sc_hd__buf_2_2_X) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ + ( + .A(sky130_fd_sc_hd__or2_1_0_X), + .X(sky130_fd_sc_hd__buf_2_3_X) + ); + frac_lut4_mux frac_lut4_mux_0_ + ( + .in(sram), + .sram({sky130_fd_sc_hd__buf_2_0_X, sky130_fd_sc_hd__buf_2_1_X, sky130_fd_sc_hd__buf_2_2_X, sky130_fd_sc_hd__buf_2_3_X}), + .sram_inv({sky130_fd_sc_hd__inv_1_0_Y, sky130_fd_sc_hd__inv_1_1_Y, sky130_fd_sc_hd__inv_1_2_Y, sky130_fd_sc_hd__inv_1_3_Y}), + .lut2_out(lut2_out), + .lut3_out(lut3_out), + .lut4_out(lut4_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/memories.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/memories.v new file mode 100644 index 0000000..7c86232 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/memories.v @@ -0,0 +1,730 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size12_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:3]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:3]mem_out; + +assign ccff_tail = mem_out[3]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]) + ); +endmodule + +module mux_tree_tapbuf_size10_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:3]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:3]mem_out; + +assign ccff_tail = mem_out[3]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]) + ); +endmodule + +module mux_tree_tapbuf_size3_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:1]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:1]mem_out; + +assign ccff_tail = mem_out[1]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); +endmodule + +module mux_tree_tapbuf_size7_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:2]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:2]mem_out; + +assign ccff_tail = mem_out[2]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); +endmodule + +module mux_tree_tapbuf_size2_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:1]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:1]mem_out; + +assign ccff_tail = mem_out[1]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); +endmodule + +module mux_tree_tapbuf_size5_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:2]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:2]mem_out; + +assign ccff_tail = mem_out[2]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); +endmodule + +module mux_tree_tapbuf_size6_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:2]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:2]mem_out; + +assign ccff_tail = mem_out[2]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); +endmodule + +module mux_tree_tapbuf_size4_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:2]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:2]mem_out; + +assign ccff_tail = mem_out[2]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); +endmodule + +module mux_tree_tapbuf_size11_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:3]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:3]mem_out; + +assign ccff_tail = mem_out[3]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]) + ); +endmodule + +module mux_tree_tapbuf_size9_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:3]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:3]mem_out; + +assign ccff_tail = mem_out[3]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]) + ); +endmodule + +module mux_tree_tapbuf_size8_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:3]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:3]mem_out; + +assign ccff_tail = mem_out[3]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]) + ); +endmodule + +module mux_tree_size2_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:1]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:1]mem_out; + +assign ccff_tail = mem_out[1]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); +endmodule + +module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:16]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:16]mem_out; + +assign ccff_tail = mem_out[16]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[3]), + .Q(mem_out[4]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[4]), + .Q(mem_out[5]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[5]), + .Q(mem_out[6]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[6]), + .Q(mem_out[7]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[7]), + .Q(mem_out[8]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[8]), + .Q(mem_out[9]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[9]), + .Q(mem_out[10]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[10]), + .Q(mem_out[11]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[11]), + .Q(mem_out[12]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[12]), + .Q(mem_out[13]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[13]), + .Q(mem_out[14]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[14]), + .Q(mem_out[15]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[15]), + .Q(mem_out[16]) + ); +endmodule + +module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire mem_out; + +assign ccff_tail = mem_out; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/muxes.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/muxes.v new file mode 100644 index 0000000..6a57e06 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/muxes.v @@ -0,0 +1,1171 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size12 +( + in, + sram, + sram_inv, + out +); + + input [0:11]in; + input [0:3]sram; + input [0:3]sram_inv; + output out; + + wire [0:11]in; + wire [0:3]sram; + wire [0:3]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_10_X; + wire sky130_fd_sc_hd__mux2_1_11_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire sky130_fd_sc_hd__mux2_1_8_X; + wire sky130_fd_sc_hd__mux2_1_9_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_11_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ + ( + .A1(in[6]), + .A0(in[7]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ + ( + .A1(in[8]), + .A0(in[9]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .A0(in[10]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A1(in[11]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_8_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_5_X), + .A0(sky130_fd_sc_hd__mux2_1_6_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_9_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_7_X), + .A0(sky130_fd_sc_hd__mux2_1_8_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_10_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_9_X), + .A0(sky130_fd_sc_hd__mux2_1_10_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_11_X) + ); +endmodule + +module mux_tree_tapbuf_size10 +( + in, + sram, + sram_inv, + out +); + + input [0:9]in; + input [0:3]sram; + input [0:3]sram_inv; + output out; + + wire [0:9]in; + wire [0:3]sram; + wire [0:3]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire sky130_fd_sc_hd__mux2_1_8_X; + wire sky130_fd_sc_hd__mux2_1_9_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_9_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(in[6]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A1(in[7]), + .A0(in[8]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A1(in[9]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_3_X), + .A0(sky130_fd_sc_hd__mux2_1_4_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_5_X), + .A0(sky130_fd_sc_hd__mux2_1_6_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_8_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_7_X), + .A0(sky130_fd_sc_hd__mux2_1_8_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_9_X) + ); +endmodule + +module mux_tree_tapbuf_size3 +( + in, + sram, + sram_inv, + out +); + + input [0:2]in; + input [0:1]sram; + input [0:1]sram_inv; + output out; + + wire [0:2]in; + wire [0:1]sram; + wire [0:1]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_2_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(const1_0_const1), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); +endmodule + +module mux_tree_tapbuf_size7 +( + in, + sram, + sram_inv, + out +); + + input [0:6]in; + input [0:2]sram; + input [0:2]sram_inv; + output out; + + wire [0:6]in; + wire [0:2]sram; + wire [0:2]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_6_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ + ( + .A1(in[6]), + .A0(const1_0_const1), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .A0(sky130_fd_sc_hd__mux2_1_5_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); +endmodule + +module mux_tree_tapbuf_size2 +( + in, + sram, + sram_inv, + out +); + + input [0:1]in; + input [0:1]sram; + input [0:1]sram_inv; + output out; + + wire [0:1]in; + wire [0:1]sram; + wire [0:1]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_1_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); +endmodule + +module mux_tree_tapbuf_size5 +( + in, + sram, + sram_inv, + out +); + + input [0:4]in; + input [0:2]sram; + input [0:2]sram_inv; + output out; + + wire [0:4]in; + wire [0:2]sram; + wire [0:2]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_4_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(in[4]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); +endmodule + +module mux_tree_tapbuf_size6 +( + in, + sram, + sram_inv, + out +); + + input [0:5]in; + input [0:2]sram; + input [0:2]sram_inv; + output out; + + wire [0:5]in; + wire [0:2]sram; + wire [0:2]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_5_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_3_X), + .A0(sky130_fd_sc_hd__mux2_1_4_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); +endmodule + +module mux_tree_tapbuf_size4 +( + in, + sram, + sram_inv, + out +); + + input [0:3]in; + input [0:2]sram; + input [0:2]sram_inv; + output out; + + wire [0:3]in; + wire [0:2]sram; + wire [0:2]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_3_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(in[2]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(in[3]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_1_X), + .A0(sky130_fd_sc_hd__mux2_1_2_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); +endmodule + +module mux_tree_tapbuf_size11 +( + in, + sram, + sram_inv, + out +); + + input [0:10]in; + input [0:3]sram; + input [0:3]sram_inv; + output out; + + wire [0:10]in; + wire [0:3]sram; + wire [0:3]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_10_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire sky130_fd_sc_hd__mux2_1_8_X; + wire sky130_fd_sc_hd__mux2_1_9_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_10_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ + ( + .A1(in[6]), + .A0(in[7]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A1(in[8]), + .A0(in[9]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A1(in[10]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .A0(sky130_fd_sc_hd__mux2_1_5_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_8_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_6_X), + .A0(sky130_fd_sc_hd__mux2_1_7_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_9_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_8_X), + .A0(sky130_fd_sc_hd__mux2_1_9_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_10_X) + ); +endmodule + +module mux_tree_tapbuf_size9 +( + in, + sram, + sram_inv, + out +); + + input [0:8]in; + input [0:3]sram; + input [0:3]sram_inv; + output out; + + wire [0:8]in; + wire [0:3]sram; + wire [0:3]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire sky130_fd_sc_hd__mux2_1_8_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_8_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(in[4]), + .A0(in[5]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A1(in[6]), + .A0(in[7]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A1(in[8]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .A0(sky130_fd_sc_hd__mux2_1_5_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_6_X), + .A0(sky130_fd_sc_hd__mux2_1_7_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_8_X) + ); +endmodule + +module mux_tree_tapbuf_size8 +( + in, + sram, + sram_inv, + out +); + + input [0:7]in; + input [0:3]sram; + input [0:3]sram_inv; + output out; + + wire [0:7]in; + wire [0:3]sram; + wire [0:3]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_7_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(in[2]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(in[3]), + .A0(in[4]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A1(in[5]), + .A0(in[6]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A1(in[7]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_1_X), + .A0(sky130_fd_sc_hd__mux2_1_2_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_3_X), + .A0(sky130_fd_sc_hd__mux2_1_4_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_5_X), + .A0(sky130_fd_sc_hd__mux2_1_6_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); +endmodule + +module mux_tree_size2 +( + in, + sram, + sram_inv, + out +); + + input [0:1]in; + input [0:1]sram; + input [0:1]sram_inv; + output out; + + wire [0:1]in; + wire [0:1]sram; + wire [0:1]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(const1_0_const1), + .S(sram[1]), + .X(out) + ); +endmodule + +module frac_lut4_mux +( + in, + sram, + sram_inv, + lut2_out, + lut3_out, + lut4_out +); + + input [0:15]in; + input [0:3]sram; + input [0:3]sram_inv; + output [0:1]lut2_out; + output [0:1]lut3_out; + output lut4_out; + + wire [0:15]in; + wire [0:3]sram; + wire [0:3]sram_inv; + wire [0:1]lut2_out; + wire [0:1]lut3_out; + wire lut4_out; + wire sky130_fd_sc_hd__buf_2_5_X; + wire sky130_fd_sc_hd__buf_2_6_X; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_10_X; + wire sky130_fd_sc_hd__mux2_1_11_X; + wire sky130_fd_sc_hd__mux2_1_12_X; + wire sky130_fd_sc_hd__mux2_1_13_X; + wire sky130_fd_sc_hd__mux2_1_14_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire sky130_fd_sc_hd__mux2_1_8_X; + wire sky130_fd_sc_hd__mux2_1_9_X; + + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_10_X), + .X(lut2_out[0]) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ + ( + .A(sky130_fd_sc_hd__mux2_1_11_X), + .X(lut2_out[1]) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ + ( + .A(sky130_fd_sc_hd__mux2_1_12_X), + .X(lut3_out[0]) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ + ( + .A(sky130_fd_sc_hd__mux2_1_13_X), + .X(lut3_out[1]) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ + ( + .A(sky130_fd_sc_hd__mux2_1_14_X), + .X(lut4_out) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ + ( + .A(sky130_fd_sc_hd__mux2_1_8_X), + .X(sky130_fd_sc_hd__buf_2_5_X) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ + ( + .A(sky130_fd_sc_hd__mux2_1_9_X), + .X(sky130_fd_sc_hd__buf_2_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ + ( + .A1(in[6]), + .A0(in[7]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ + ( + .A1(in[8]), + .A0(in[9]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ + ( + .A1(in[10]), + .A0(in[11]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ + ( + .A1(in[12]), + .A0(in[13]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ + ( + .A1(in[14]), + .A0(in[15]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_8_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_9_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .A0(sky130_fd_sc_hd__mux2_1_5_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_10_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A1(sky130_fd_sc_hd__mux2_1_6_X), + .A0(sky130_fd_sc_hd__mux2_1_7_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_11_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__buf_2_5_X), + .A0(sky130_fd_sc_hd__buf_2_6_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_12_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_10_X), + .A0(sky130_fd_sc_hd__mux2_1_11_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_13_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_12_X), + .A0(sky130_fd_sc_hd__mux2_1_13_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_14_X) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/user_defined_templates.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/user_defined_templates.v new file mode 100644 index 0000000..6647581 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/user_defined_templates.v @@ -0,0 +1,190 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sky130_fd_sc_hd__inv_1 +( + A, + Y +); + + input A; + output Y; + + wire A; + wire Y; + +endmodule + +module sky130_fd_sc_hd__buf_2 +( + A, + X +); + + input A; + output X; + + wire A; + wire X; + +endmodule + +module sky130_fd_sc_hd__buf_4 +( + A, + X +); + + input A; + output X; + + wire A; + wire X; + +endmodule + +module sky130_fd_sc_hd__inv_2 +( + A, + Y +); + + input A; + output Y; + + wire A; + wire Y; + +endmodule + +module sky130_fd_sc_hd__or2_1 +( + A, + B, + X +); + + input A; + input B; + output X; + + wire A; + wire B; + wire X; + +endmodule + +module sky130_fd_sc_hd__mux2_1 +( + A1, + A0, + S, + X +); + + input A1; + input A0; + input S; + output X; + + wire A1; + wire A0; + wire S; + wire X; + +endmodule + +module sky130_fd_sc_hd__sdfrtp_1 +( + SCE, + D, + SCD, + RESET_B, + CLK, + Q +); + + input SCE; + input D; + input SCD; + input RESET_B; + input CLK; + output Q; + + wire SCE; + wire D; + wire SCD; + wire RESET_B; + wire CLK; + wire Q; + +endmodule + +module sky130_fd_sc_hd__dfrtp_1 +( + RESET_B, + CLK, + D, + Q +); + + input RESET_B; + input CLK; + input D; + output Q; + + wire RESET_B; + wire CLK; + wire D; + wire Q; + +endmodule + +module EMBEDDED_IO_HD +( + IO_ISOL_N, + SOC_IN, + SOC_OUT, + SOC_DIR, + FPGA_OUT, + FPGA_DIR, + FPGA_IN +); + + input IO_ISOL_N; + input SOC_IN; + output SOC_OUT; + output SOC_DIR; + input FPGA_OUT; + input FPGA_DIR; + output FPGA_IN; + + wire IO_ISOL_N; + wire SOC_IN; + wire SOC_OUT; + wire SOC_DIR; + wire FPGA_OUT; + wire FPGA_DIR; + wire FPGA_IN; + +endmodule + +module sky130_fd_sc_hd__mux2_1_wrapper +( + A0, + A1, + S, + X +); + + input A0; + input A1; + input S; + output X; + + wire A0; + wire A1; + wire S; + wire X; + +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/wires.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/wires.v new file mode 100644 index 0000000..304b7eb --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/wires.v @@ -0,0 +1,17 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module direct_interc +( + in, + out +); + + input in; + output out; + + wire in; + wire out; + +assign out = in; +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/top_hierarchy.yml b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/top_hierarchy.yml new file mode 100644 index 0000000..6b64b64 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/top_hierarchy.yml @@ -0,0 +1,517 @@ +cbx_1__0_: +- cbx_1__0_ +- cbx_2__0_ +- cbx_3__0_ +- cbx_4__0_ +- cbx_5__0_ +- cbx_6__0_ +- cbx_7__0_ +- cbx_8__0_ +cbx_1__1_: +- cbx_1__1_ +- cbx_1__2_ +- cbx_1__3_ +- cbx_1__4_ +- cbx_1__5_ +- cbx_1__6_ +- cbx_1__7_ +- cbx_2__1_ +- cbx_2__2_ +- cbx_2__3_ +- cbx_2__4_ +- cbx_2__5_ +- cbx_2__6_ +- cbx_2__7_ +- cbx_3__1_ +- cbx_3__2_ +- cbx_3__3_ +- cbx_3__4_ +- cbx_3__5_ +- cbx_3__6_ +- cbx_3__7_ +- cbx_4__1_ +- cbx_4__2_ +- cbx_4__3_ +- cbx_4__4_ +- cbx_4__5_ +- cbx_4__6_ +- cbx_4__7_ +- cbx_5__1_ +- cbx_5__2_ +- cbx_5__3_ +- cbx_5__4_ +- cbx_5__5_ +- cbx_5__6_ +- cbx_5__7_ +- cbx_6__1_ +- cbx_6__2_ +- cbx_6__3_ +- cbx_6__4_ +- cbx_6__5_ +- cbx_6__6_ +- cbx_6__7_ +- cbx_7__1_ +- cbx_7__2_ +- cbx_7__3_ +- cbx_7__4_ +- cbx_7__5_ +- cbx_7__6_ +- cbx_7__7_ +- cbx_8__1_ +- cbx_8__2_ +- cbx_8__3_ +- cbx_8__4_ +- cbx_8__5_ +- cbx_8__6_ +- cbx_8__7_ +cbx_1__8_: +- cbx_1__8_ +- cbx_2__8_ +- cbx_3__8_ +- cbx_4__8_ +- cbx_5__8_ +- cbx_6__8_ +- cbx_7__8_ +- cbx_8__8_ +cby_0__1_: +- cby_0__1_ +- cby_0__2_ +- cby_0__3_ +- cby_0__4_ +- cby_0__5_ +- cby_0__6_ +- cby_0__7_ +- cby_0__8_ +cby_1__1_: +- cby_1__1_ +- cby_1__2_ +- cby_1__3_ +- cby_1__4_ +- cby_1__5_ +- cby_1__6_ +- cby_1__7_ +- cby_1__8_ +- cby_2__1_ +- cby_2__2_ +- cby_2__3_ +- cby_2__4_ +- cby_2__5_ +- cby_2__6_ +- cby_2__7_ +- cby_2__8_ +- cby_3__1_ +- cby_3__2_ +- cby_3__3_ +- cby_3__4_ +- cby_3__5_ +- cby_3__6_ +- cby_3__7_ +- cby_3__8_ +- cby_4__1_ +- cby_4__2_ +- cby_4__3_ +- cby_4__4_ +- cby_4__5_ +- cby_4__6_ +- cby_4__7_ +- cby_4__8_ +- cby_5__1_ +- cby_5__2_ +- cby_5__3_ +- cby_5__4_ +- cby_5__5_ +- cby_5__6_ +- cby_5__7_ +- cby_5__8_ +- cby_6__1_ +- cby_6__2_ +- cby_6__3_ +- cby_6__4_ +- cby_6__5_ +- cby_6__6_ +- cby_6__7_ +- cby_6__8_ +- cby_7__1_ +- cby_7__2_ +- cby_7__3_ +- cby_7__4_ +- cby_7__5_ +- cby_7__6_ +- cby_7__7_ +- cby_7__8_ +cby_8__1_: +- cby_8__1_ +- cby_8__2_ +- cby_8__3_ +- cby_8__4_ +- cby_8__5_ +- cby_8__6_ +- cby_8__7_ +- cby_8__8_ +direct_interc: +- direct_interc_0_ +- direct_interc_100_ +- direct_interc_101_ +- direct_interc_102_ +- direct_interc_103_ +- direct_interc_104_ +- direct_interc_105_ +- direct_interc_106_ +- direct_interc_107_ +- direct_interc_108_ +- direct_interc_109_ +- direct_interc_10_ +- direct_interc_110_ +- direct_interc_111_ +- direct_interc_112_ +- direct_interc_113_ +- direct_interc_114_ +- direct_interc_115_ +- direct_interc_116_ +- direct_interc_117_ +- direct_interc_118_ +- direct_interc_119_ +- direct_interc_11_ +- direct_interc_120_ +- direct_interc_121_ +- direct_interc_122_ +- direct_interc_123_ +- direct_interc_124_ +- direct_interc_125_ +- direct_interc_126_ +- direct_interc_127_ +- direct_interc_128_ +- direct_interc_129_ +- direct_interc_12_ +- direct_interc_130_ +- direct_interc_131_ +- direct_interc_132_ +- direct_interc_133_ +- direct_interc_134_ +- direct_interc_135_ +- direct_interc_136_ +- direct_interc_137_ +- direct_interc_138_ +- direct_interc_139_ +- direct_interc_13_ +- direct_interc_140_ +- direct_interc_141_ +- direct_interc_142_ +- direct_interc_143_ +- direct_interc_144_ +- direct_interc_145_ +- direct_interc_146_ +- direct_interc_147_ +- direct_interc_148_ +- direct_interc_149_ +- direct_interc_14_ +- direct_interc_150_ +- direct_interc_151_ +- direct_interc_152_ +- direct_interc_153_ +- direct_interc_154_ +- direct_interc_155_ +- direct_interc_156_ +- direct_interc_157_ +- direct_interc_158_ +- direct_interc_159_ +- direct_interc_15_ +- direct_interc_160_ +- direct_interc_161_ +- direct_interc_162_ +- direct_interc_163_ +- direct_interc_164_ +- direct_interc_165_ +- direct_interc_166_ +- direct_interc_167_ +- direct_interc_168_ +- direct_interc_169_ +- direct_interc_16_ +- direct_interc_170_ +- direct_interc_171_ +- direct_interc_172_ +- direct_interc_173_ +- direct_interc_174_ +- direct_interc_17_ +- direct_interc_18_ +- direct_interc_19_ +- direct_interc_1_ +- direct_interc_20_ +- direct_interc_21_ +- direct_interc_22_ +- direct_interc_23_ +- direct_interc_24_ +- direct_interc_25_ +- direct_interc_26_ +- direct_interc_27_ +- direct_interc_28_ +- direct_interc_29_ +- direct_interc_2_ +- direct_interc_30_ +- direct_interc_31_ +- direct_interc_32_ +- direct_interc_33_ +- direct_interc_34_ +- direct_interc_35_ +- direct_interc_36_ +- direct_interc_37_ +- direct_interc_38_ +- direct_interc_39_ +- direct_interc_3_ +- direct_interc_40_ +- direct_interc_41_ +- direct_interc_42_ +- direct_interc_43_ +- direct_interc_44_ +- direct_interc_45_ +- direct_interc_46_ +- direct_interc_47_ +- direct_interc_48_ +- direct_interc_49_ +- direct_interc_4_ +- direct_interc_50_ +- direct_interc_51_ +- direct_interc_52_ +- direct_interc_53_ +- direct_interc_54_ +- direct_interc_55_ +- direct_interc_56_ +- direct_interc_57_ +- direct_interc_58_ +- direct_interc_59_ +- direct_interc_5_ +- direct_interc_60_ +- direct_interc_61_ +- direct_interc_62_ +- direct_interc_63_ +- direct_interc_64_ +- direct_interc_65_ +- direct_interc_66_ +- direct_interc_67_ +- direct_interc_68_ +- direct_interc_69_ +- direct_interc_6_ +- direct_interc_70_ +- direct_interc_71_ +- direct_interc_72_ +- direct_interc_73_ +- direct_interc_74_ +- direct_interc_75_ +- direct_interc_76_ +- direct_interc_77_ +- direct_interc_78_ +- direct_interc_79_ +- direct_interc_7_ +- direct_interc_80_ +- direct_interc_81_ +- direct_interc_82_ +- direct_interc_83_ +- direct_interc_84_ +- direct_interc_85_ +- direct_interc_86_ +- direct_interc_87_ +- direct_interc_88_ +- direct_interc_89_ +- direct_interc_8_ +- direct_interc_90_ +- direct_interc_91_ +- direct_interc_92_ +- direct_interc_93_ +- direct_interc_94_ +- direct_interc_95_ +- direct_interc_96_ +- direct_interc_97_ +- direct_interc_98_ +- direct_interc_99_ +- direct_interc_9_ +grid_clb: +- grid_clb_1__1_ +- grid_clb_1__2_ +- grid_clb_1__3_ +- grid_clb_1__4_ +- grid_clb_1__5_ +- grid_clb_1__6_ +- grid_clb_1__7_ +- grid_clb_1__8_ +- grid_clb_2__1_ +- grid_clb_2__2_ +- grid_clb_2__3_ +- grid_clb_2__4_ +- grid_clb_2__5_ +- grid_clb_2__6_ +- grid_clb_2__7_ +- grid_clb_2__8_ +- grid_clb_3__1_ +- grid_clb_3__2_ +- grid_clb_3__3_ +- grid_clb_3__4_ +- grid_clb_3__5_ +- grid_clb_3__6_ +- grid_clb_3__7_ +- grid_clb_3__8_ +- grid_clb_4__1_ +- grid_clb_4__2_ +- grid_clb_4__3_ +- grid_clb_4__4_ +- grid_clb_4__5_ +- grid_clb_4__6_ +- grid_clb_4__7_ +- grid_clb_4__8_ +- grid_clb_5__1_ +- grid_clb_5__2_ +- grid_clb_5__3_ +- grid_clb_5__4_ +- grid_clb_5__5_ +- grid_clb_5__6_ +- grid_clb_5__7_ +- grid_clb_5__8_ +- grid_clb_6__1_ +- grid_clb_6__2_ +- grid_clb_6__3_ +- grid_clb_6__4_ +- grid_clb_6__5_ +- grid_clb_6__6_ +- grid_clb_6__7_ +- grid_clb_6__8_ +- grid_clb_7__1_ +- grid_clb_7__2_ +- grid_clb_7__3_ +- grid_clb_7__4_ +- grid_clb_7__5_ +- grid_clb_7__6_ +- grid_clb_7__7_ +- grid_clb_7__8_ +- grid_clb_8__1_ +- grid_clb_8__2_ +- grid_clb_8__3_ +- grid_clb_8__4_ +- grid_clb_8__5_ +- grid_clb_8__6_ +- grid_clb_8__7_ +- grid_clb_8__8_ +grid_io_bottom_bottom: +- grid_io_bottom_bottom_1__0_ +- grid_io_bottom_bottom_2__0_ +- grid_io_bottom_bottom_3__0_ +- grid_io_bottom_bottom_4__0_ +- grid_io_bottom_bottom_5__0_ +- grid_io_bottom_bottom_6__0_ +- grid_io_bottom_bottom_7__0_ +- grid_io_bottom_bottom_8__0_ +grid_io_left_left: +- grid_io_left_left_0__1_ +- grid_io_left_left_0__2_ +- grid_io_left_left_0__3_ +- grid_io_left_left_0__4_ +- grid_io_left_left_0__5_ +- grid_io_left_left_0__6_ +- grid_io_left_left_0__7_ +- grid_io_left_left_0__8_ +grid_io_right_right: +- grid_io_right_right_9__1_ +- grid_io_right_right_9__2_ +- grid_io_right_right_9__3_ +- grid_io_right_right_9__4_ +- grid_io_right_right_9__5_ +- grid_io_right_right_9__6_ +- grid_io_right_right_9__7_ +- grid_io_right_right_9__8_ +grid_io_top_top: +- grid_io_top_top_1__9_ +- grid_io_top_top_2__9_ +- grid_io_top_top_3__9_ +- grid_io_top_top_4__9_ +- grid_io_top_top_5__9_ +- grid_io_top_top_6__9_ +- grid_io_top_top_7__9_ +- grid_io_top_top_8__9_ +sb_0__0_: +- sb_0__0_ +sb_0__1_: +- sb_0__1_ +- sb_0__2_ +- sb_0__3_ +- sb_0__4_ +- sb_0__5_ +- sb_0__6_ +- sb_0__7_ +sb_0__8_: +- sb_0__8_ +sb_1__0_: +- sb_1__0_ +- sb_2__0_ +- sb_3__0_ +- sb_4__0_ +- sb_5__0_ +- sb_6__0_ +- sb_7__0_ +sb_1__1_: +- sb_1__1_ +- sb_1__2_ +- sb_1__3_ +- sb_1__4_ +- sb_1__5_ +- sb_1__6_ +- sb_1__7_ +- sb_2__1_ +- sb_2__2_ +- sb_2__3_ +- sb_2__4_ +- sb_2__5_ +- sb_2__6_ +- sb_2__7_ +- sb_3__1_ +- sb_3__2_ +- sb_3__3_ +- sb_3__4_ +- sb_3__5_ +- sb_3__6_ +- sb_3__7_ +- sb_4__1_ +- sb_4__2_ +- sb_4__3_ +- sb_4__4_ +- sb_4__5_ +- sb_4__6_ +- sb_4__7_ +- sb_5__1_ +- sb_5__2_ +- sb_5__3_ +- sb_5__4_ +- sb_5__5_ +- sb_5__6_ +- sb_5__7_ +- sb_6__1_ +- sb_6__2_ +- sb_6__3_ +- sb_6__4_ +- sb_6__5_ +- sb_6__6_ +- sb_6__7_ +- sb_7__1_ +- sb_7__2_ +- sb_7__3_ +- sb_7__4_ +- sb_7__5_ +- sb_7__6_ +- sb_7__7_ +sb_1__8_: +- sb_1__8_ +- sb_2__8_ +- sb_3__8_ +- sb_4__8_ +- sb_5__8_ +- sb_6__8_ +- sb_7__8_ +sb_8__0_: +- sb_8__0_ +sb_8__1_: +- sb_8__1_ +- sb_8__2_ +- sb_8__3_ +- sb_8__4_ +- sb_8__5_ +- sb_8__6_ +- sb_8__7_ +sb_8__8_: +- sb_8__8_ diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/CustomModules/custom_module.txt b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/CustomModules/custom_module.txt new file mode 100644 index 0000000..3834131 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/CustomModules/custom_module.txt @@ -0,0 +1 @@ +# Dummy file to list all custom modules used in this project \ No newline at end of file diff --git a/SOFA_A/SOFA_A_verilog/fabric_netlists.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/fabric_netlists.v similarity index 93% rename from SOFA_A/SOFA_A_verilog/fabric_netlists.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/fabric_netlists.v index 9844a7c..b117ff0 100644 --- a/SOFA_A/SOFA_A_verilog/fabric_netlists.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/fabric_netlists.v @@ -3,7 +3,6 @@ // Description: Fabric Netlist Summary // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps @@ -52,12 +51,19 @@ // ------ Include routing module netlists ----- `include "./SRC/routing/sb_0__0_.v" `include "./SRC/routing/sb_0__1_.v" +`include "./SRC/routing/sb_0__8_.v" `include "./SRC/routing/sb_1__0_.v" `include "./SRC/routing/sb_1__1_.v" +`include "./SRC/routing/sb_1__8_.v" +`include "./SRC/routing/sb_8__0_.v" +`include "./SRC/routing/sb_8__1_.v" +`include "./SRC/routing/sb_8__8_.v" `include "./SRC/routing/cbx_1__0_.v" `include "./SRC/routing/cbx_1__1_.v" +`include "./SRC/routing/cbx_1__8_.v" `include "./SRC/routing/cby_0__1_.v" `include "./SRC/routing/cby_1__1_.v" +`include "./SRC/routing/cby_8__1_.v" // ------ Include fabric top-level netlists ----- `include "./SRC/fpga_top.v" diff --git a/SOFA_A/SOFA_A_verilog/fpga_defines.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/fpga_defines.v similarity index 91% rename from SOFA_A/SOFA_A_verilog/fpga_defines.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/fpga_defines.v index f21d55d..5088338 100644 --- a/SOFA_A/SOFA_A_verilog/fpga_defines.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/fpga_defines.v @@ -3,7 +3,6 @@ // Description: Preprocessing flags to enable/disable features in FPGA Verilog modules // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/fpga_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/fpga_top.v new file mode 100644 index 0000000..eba438e --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/fpga_top.v @@ -0,0 +1,16968 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Top-level Verilog module for FPGA +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for fpga_top ----- +module fpga_top(clk, + Reset, + IO_ISOL_N, + pReset, + prog_clk, + Test_en, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + ccff_head, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] clk; +//----- GLOBAL PORTS ----- +input [0:0] Reset; +//----- GLOBAL PORTS ----- +input [0:0] IO_ISOL_N; +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GLOBAL PORTS ----- +input [0:0] Test_en; +//----- GPIN PORTS ----- +input [0:127] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; +//----- GPOUT PORTS ----- +output [0:127] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; +//----- GPOUT PORTS ----- +output [0:127] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__0__0_ccff_tail; +wire [0:29] cbx_1__0__0_chanx_left_out; +wire [0:29] cbx_1__0__0_chanx_right_out; +wire [0:0] cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__0__1_ccff_tail; +wire [0:29] cbx_1__0__1_chanx_left_out; +wire [0:29] cbx_1__0__1_chanx_right_out; +wire [0:0] cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__0__2_ccff_tail; +wire [0:29] cbx_1__0__2_chanx_left_out; +wire [0:29] cbx_1__0__2_chanx_right_out; +wire [0:0] cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__0__3_ccff_tail; +wire [0:29] cbx_1__0__3_chanx_left_out; +wire [0:29] cbx_1__0__3_chanx_right_out; +wire [0:0] cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__0__4_ccff_tail; +wire [0:29] cbx_1__0__4_chanx_left_out; +wire [0:29] cbx_1__0__4_chanx_right_out; +wire [0:0] cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__0__5_ccff_tail; +wire [0:29] cbx_1__0__5_chanx_left_out; +wire [0:29] cbx_1__0__5_chanx_right_out; +wire [0:0] cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__0__6_ccff_tail; +wire [0:29] cbx_1__0__6_chanx_left_out; +wire [0:29] cbx_1__0__6_chanx_right_out; +wire [0:0] cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__0__7_ccff_tail; +wire [0:29] cbx_1__0__7_chanx_left_out; +wire [0:29] cbx_1__0__7_chanx_right_out; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__0_ccff_tail; +wire [0:29] cbx_1__1__0_chanx_left_out; +wire [0:29] cbx_1__1__0_chanx_right_out; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__10_ccff_tail; +wire [0:29] cbx_1__1__10_chanx_left_out; +wire [0:29] cbx_1__1__10_chanx_right_out; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__11_ccff_tail; +wire [0:29] cbx_1__1__11_chanx_left_out; +wire [0:29] cbx_1__1__11_chanx_right_out; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__12_ccff_tail; +wire [0:29] cbx_1__1__12_chanx_left_out; +wire [0:29] cbx_1__1__12_chanx_right_out; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__13_ccff_tail; +wire [0:29] cbx_1__1__13_chanx_left_out; +wire [0:29] cbx_1__1__13_chanx_right_out; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__14_ccff_tail; +wire [0:29] cbx_1__1__14_chanx_left_out; +wire [0:29] cbx_1__1__14_chanx_right_out; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__15_ccff_tail; +wire [0:29] cbx_1__1__15_chanx_left_out; +wire [0:29] cbx_1__1__15_chanx_right_out; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__16_ccff_tail; +wire [0:29] cbx_1__1__16_chanx_left_out; +wire [0:29] cbx_1__1__16_chanx_right_out; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__17_ccff_tail; +wire [0:29] cbx_1__1__17_chanx_left_out; +wire [0:29] cbx_1__1__17_chanx_right_out; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__18_ccff_tail; +wire [0:29] cbx_1__1__18_chanx_left_out; +wire [0:29] cbx_1__1__18_chanx_right_out; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__19_ccff_tail; +wire [0:29] cbx_1__1__19_chanx_left_out; +wire [0:29] cbx_1__1__19_chanx_right_out; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__1_ccff_tail; +wire [0:29] cbx_1__1__1_chanx_left_out; +wire [0:29] cbx_1__1__1_chanx_right_out; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__20_ccff_tail; +wire [0:29] cbx_1__1__20_chanx_left_out; +wire [0:29] cbx_1__1__20_chanx_right_out; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__21_ccff_tail; +wire [0:29] cbx_1__1__21_chanx_left_out; +wire [0:29] cbx_1__1__21_chanx_right_out; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__22_ccff_tail; +wire [0:29] cbx_1__1__22_chanx_left_out; +wire [0:29] cbx_1__1__22_chanx_right_out; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__23_ccff_tail; +wire [0:29] cbx_1__1__23_chanx_left_out; +wire [0:29] cbx_1__1__23_chanx_right_out; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__24_ccff_tail; +wire [0:29] cbx_1__1__24_chanx_left_out; +wire [0:29] cbx_1__1__24_chanx_right_out; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__25_ccff_tail; +wire [0:29] cbx_1__1__25_chanx_left_out; +wire [0:29] cbx_1__1__25_chanx_right_out; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__26_ccff_tail; +wire [0:29] cbx_1__1__26_chanx_left_out; +wire [0:29] cbx_1__1__26_chanx_right_out; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__27_ccff_tail; +wire [0:29] cbx_1__1__27_chanx_left_out; +wire [0:29] cbx_1__1__27_chanx_right_out; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__28_ccff_tail; +wire [0:29] cbx_1__1__28_chanx_left_out; +wire [0:29] cbx_1__1__28_chanx_right_out; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__29_ccff_tail; +wire [0:29] cbx_1__1__29_chanx_left_out; +wire [0:29] cbx_1__1__29_chanx_right_out; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__2_ccff_tail; +wire [0:29] cbx_1__1__2_chanx_left_out; +wire [0:29] cbx_1__1__2_chanx_right_out; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__30_ccff_tail; +wire [0:29] cbx_1__1__30_chanx_left_out; +wire [0:29] cbx_1__1__30_chanx_right_out; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__31_ccff_tail; +wire [0:29] cbx_1__1__31_chanx_left_out; +wire [0:29] cbx_1__1__31_chanx_right_out; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__32_ccff_tail; +wire [0:29] cbx_1__1__32_chanx_left_out; +wire [0:29] cbx_1__1__32_chanx_right_out; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__33_ccff_tail; +wire [0:29] cbx_1__1__33_chanx_left_out; +wire [0:29] cbx_1__1__33_chanx_right_out; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__34_ccff_tail; +wire [0:29] cbx_1__1__34_chanx_left_out; +wire [0:29] cbx_1__1__34_chanx_right_out; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__35_ccff_tail; +wire [0:29] cbx_1__1__35_chanx_left_out; +wire [0:29] cbx_1__1__35_chanx_right_out; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__36_ccff_tail; +wire [0:29] cbx_1__1__36_chanx_left_out; +wire [0:29] cbx_1__1__36_chanx_right_out; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__37_ccff_tail; +wire [0:29] cbx_1__1__37_chanx_left_out; +wire [0:29] cbx_1__1__37_chanx_right_out; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__38_ccff_tail; +wire [0:29] cbx_1__1__38_chanx_left_out; +wire [0:29] cbx_1__1__38_chanx_right_out; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__39_ccff_tail; +wire [0:29] cbx_1__1__39_chanx_left_out; +wire [0:29] cbx_1__1__39_chanx_right_out; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__3_ccff_tail; +wire [0:29] cbx_1__1__3_chanx_left_out; +wire [0:29] cbx_1__1__3_chanx_right_out; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__40_ccff_tail; +wire [0:29] cbx_1__1__40_chanx_left_out; +wire [0:29] cbx_1__1__40_chanx_right_out; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__41_ccff_tail; +wire [0:29] cbx_1__1__41_chanx_left_out; +wire [0:29] cbx_1__1__41_chanx_right_out; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__42_ccff_tail; +wire [0:29] cbx_1__1__42_chanx_left_out; +wire [0:29] cbx_1__1__42_chanx_right_out; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__43_ccff_tail; +wire [0:29] cbx_1__1__43_chanx_left_out; +wire [0:29] cbx_1__1__43_chanx_right_out; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__44_ccff_tail; +wire [0:29] cbx_1__1__44_chanx_left_out; +wire [0:29] cbx_1__1__44_chanx_right_out; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__45_ccff_tail; +wire [0:29] cbx_1__1__45_chanx_left_out; +wire [0:29] cbx_1__1__45_chanx_right_out; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__46_ccff_tail; +wire [0:29] cbx_1__1__46_chanx_left_out; +wire [0:29] cbx_1__1__46_chanx_right_out; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__47_ccff_tail; +wire [0:29] cbx_1__1__47_chanx_left_out; +wire [0:29] cbx_1__1__47_chanx_right_out; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__48_ccff_tail; +wire [0:29] cbx_1__1__48_chanx_left_out; +wire [0:29] cbx_1__1__48_chanx_right_out; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__49_ccff_tail; +wire [0:29] cbx_1__1__49_chanx_left_out; +wire [0:29] cbx_1__1__49_chanx_right_out; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__4_ccff_tail; +wire [0:29] cbx_1__1__4_chanx_left_out; +wire [0:29] cbx_1__1__4_chanx_right_out; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__50_ccff_tail; +wire [0:29] cbx_1__1__50_chanx_left_out; +wire [0:29] cbx_1__1__50_chanx_right_out; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__51_ccff_tail; +wire [0:29] cbx_1__1__51_chanx_left_out; +wire [0:29] cbx_1__1__51_chanx_right_out; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__52_ccff_tail; +wire [0:29] cbx_1__1__52_chanx_left_out; +wire [0:29] cbx_1__1__52_chanx_right_out; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__53_ccff_tail; +wire [0:29] cbx_1__1__53_chanx_left_out; +wire [0:29] cbx_1__1__53_chanx_right_out; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__54_ccff_tail; +wire [0:29] cbx_1__1__54_chanx_left_out; +wire [0:29] cbx_1__1__54_chanx_right_out; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__55_ccff_tail; +wire [0:29] cbx_1__1__55_chanx_left_out; +wire [0:29] cbx_1__1__55_chanx_right_out; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__5_ccff_tail; +wire [0:29] cbx_1__1__5_chanx_left_out; +wire [0:29] cbx_1__1__5_chanx_right_out; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__6_ccff_tail; +wire [0:29] cbx_1__1__6_chanx_left_out; +wire [0:29] cbx_1__1__6_chanx_right_out; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__7_ccff_tail; +wire [0:29] cbx_1__1__7_chanx_left_out; +wire [0:29] cbx_1__1__7_chanx_right_out; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__8_ccff_tail; +wire [0:29] cbx_1__1__8_chanx_left_out; +wire [0:29] cbx_1__1__8_chanx_right_out; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__1__9_ccff_tail; +wire [0:29] cbx_1__1__9_chanx_left_out; +wire [0:29] cbx_1__1__9_chanx_right_out; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__8__0_ccff_tail; +wire [0:29] cbx_1__8__0_chanx_left_out; +wire [0:29] cbx_1__8__0_chanx_right_out; +wire [0:0] cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__8__1_ccff_tail; +wire [0:29] cbx_1__8__1_chanx_left_out; +wire [0:29] cbx_1__8__1_chanx_right_out; +wire [0:0] cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__8__2_ccff_tail; +wire [0:29] cbx_1__8__2_chanx_left_out; +wire [0:29] cbx_1__8__2_chanx_right_out; +wire [0:0] cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__8__3_ccff_tail; +wire [0:29] cbx_1__8__3_chanx_left_out; +wire [0:29] cbx_1__8__3_chanx_right_out; +wire [0:0] cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__8__4_ccff_tail; +wire [0:29] cbx_1__8__4_chanx_left_out; +wire [0:29] cbx_1__8__4_chanx_right_out; +wire [0:0] cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__8__5_ccff_tail; +wire [0:29] cbx_1__8__5_chanx_left_out; +wire [0:29] cbx_1__8__5_chanx_right_out; +wire [0:0] cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__8__6_ccff_tail; +wire [0:29] cbx_1__8__6_chanx_left_out; +wire [0:29] cbx_1__8__6_chanx_right_out; +wire [0:0] cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +wire [0:0] cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +wire [0:0] cbx_1__8__7_ccff_tail; +wire [0:29] cbx_1__8__7_chanx_left_out; +wire [0:29] cbx_1__8__7_chanx_right_out; +wire [0:0] cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_0__1__0_ccff_tail; +wire [0:29] cby_0__1__0_chany_bottom_out; +wire [0:29] cby_0__1__0_chany_top_out; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_0__1__1_ccff_tail; +wire [0:29] cby_0__1__1_chany_bottom_out; +wire [0:29] cby_0__1__1_chany_top_out; +wire [0:0] cby_0__1__1_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_0__1__1_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_0__1__1_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_0__1__1_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_0__1__2_ccff_tail; +wire [0:29] cby_0__1__2_chany_bottom_out; +wire [0:29] cby_0__1__2_chany_top_out; +wire [0:0] cby_0__1__2_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_0__1__2_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_0__1__2_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_0__1__2_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_0__1__3_ccff_tail; +wire [0:29] cby_0__1__3_chany_bottom_out; +wire [0:29] cby_0__1__3_chany_top_out; +wire [0:0] cby_0__1__3_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_0__1__3_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_0__1__3_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_0__1__3_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_0__1__4_ccff_tail; +wire [0:29] cby_0__1__4_chany_bottom_out; +wire [0:29] cby_0__1__4_chany_top_out; +wire [0:0] cby_0__1__4_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_0__1__4_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_0__1__4_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_0__1__4_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_0__1__5_ccff_tail; +wire [0:29] cby_0__1__5_chany_bottom_out; +wire [0:29] cby_0__1__5_chany_top_out; +wire [0:0] cby_0__1__5_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_0__1__5_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_0__1__5_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_0__1__5_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_0__1__6_ccff_tail; +wire [0:29] cby_0__1__6_chany_bottom_out; +wire [0:29] cby_0__1__6_chany_top_out; +wire [0:0] cby_0__1__6_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_0__1__6_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_0__1__6_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_0__1__6_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_0__1__7_ccff_tail; +wire [0:29] cby_0__1__7_chany_bottom_out; +wire [0:29] cby_0__1__7_chany_top_out; +wire [0:0] cby_0__1__7_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_0__1__7_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_0__1__7_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_0__1__7_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_1__1__0_ccff_tail; +wire [0:29] cby_1__1__0_chany_bottom_out; +wire [0:29] cby_1__1__0_chany_top_out; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__10_ccff_tail; +wire [0:29] cby_1__1__10_chany_bottom_out; +wire [0:29] cby_1__1__10_chany_top_out; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__11_ccff_tail; +wire [0:29] cby_1__1__11_chany_bottom_out; +wire [0:29] cby_1__1__11_chany_top_out; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__12_ccff_tail; +wire [0:29] cby_1__1__12_chany_bottom_out; +wire [0:29] cby_1__1__12_chany_top_out; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__13_ccff_tail; +wire [0:29] cby_1__1__13_chany_bottom_out; +wire [0:29] cby_1__1__13_chany_top_out; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__14_ccff_tail; +wire [0:29] cby_1__1__14_chany_bottom_out; +wire [0:29] cby_1__1__14_chany_top_out; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__15_ccff_tail; +wire [0:29] cby_1__1__15_chany_bottom_out; +wire [0:29] cby_1__1__15_chany_top_out; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__16_ccff_tail; +wire [0:29] cby_1__1__16_chany_bottom_out; +wire [0:29] cby_1__1__16_chany_top_out; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__17_ccff_tail; +wire [0:29] cby_1__1__17_chany_bottom_out; +wire [0:29] cby_1__1__17_chany_top_out; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__18_ccff_tail; +wire [0:29] cby_1__1__18_chany_bottom_out; +wire [0:29] cby_1__1__18_chany_top_out; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__19_ccff_tail; +wire [0:29] cby_1__1__19_chany_bottom_out; +wire [0:29] cby_1__1__19_chany_top_out; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__1_ccff_tail; +wire [0:29] cby_1__1__1_chany_bottom_out; +wire [0:29] cby_1__1__1_chany_top_out; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__20_ccff_tail; +wire [0:29] cby_1__1__20_chany_bottom_out; +wire [0:29] cby_1__1__20_chany_top_out; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__21_ccff_tail; +wire [0:29] cby_1__1__21_chany_bottom_out; +wire [0:29] cby_1__1__21_chany_top_out; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__22_ccff_tail; +wire [0:29] cby_1__1__22_chany_bottom_out; +wire [0:29] cby_1__1__22_chany_top_out; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__23_ccff_tail; +wire [0:29] cby_1__1__23_chany_bottom_out; +wire [0:29] cby_1__1__23_chany_top_out; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__24_ccff_tail; +wire [0:29] cby_1__1__24_chany_bottom_out; +wire [0:29] cby_1__1__24_chany_top_out; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__25_ccff_tail; +wire [0:29] cby_1__1__25_chany_bottom_out; +wire [0:29] cby_1__1__25_chany_top_out; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__26_ccff_tail; +wire [0:29] cby_1__1__26_chany_bottom_out; +wire [0:29] cby_1__1__26_chany_top_out; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__27_ccff_tail; +wire [0:29] cby_1__1__27_chany_bottom_out; +wire [0:29] cby_1__1__27_chany_top_out; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__28_ccff_tail; +wire [0:29] cby_1__1__28_chany_bottom_out; +wire [0:29] cby_1__1__28_chany_top_out; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__29_ccff_tail; +wire [0:29] cby_1__1__29_chany_bottom_out; +wire [0:29] cby_1__1__29_chany_top_out; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__2_ccff_tail; +wire [0:29] cby_1__1__2_chany_bottom_out; +wire [0:29] cby_1__1__2_chany_top_out; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__30_ccff_tail; +wire [0:29] cby_1__1__30_chany_bottom_out; +wire [0:29] cby_1__1__30_chany_top_out; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__31_ccff_tail; +wire [0:29] cby_1__1__31_chany_bottom_out; +wire [0:29] cby_1__1__31_chany_top_out; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__32_ccff_tail; +wire [0:29] cby_1__1__32_chany_bottom_out; +wire [0:29] cby_1__1__32_chany_top_out; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__33_ccff_tail; +wire [0:29] cby_1__1__33_chany_bottom_out; +wire [0:29] cby_1__1__33_chany_top_out; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__34_ccff_tail; +wire [0:29] cby_1__1__34_chany_bottom_out; +wire [0:29] cby_1__1__34_chany_top_out; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__35_ccff_tail; +wire [0:29] cby_1__1__35_chany_bottom_out; +wire [0:29] cby_1__1__35_chany_top_out; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__36_ccff_tail; +wire [0:29] cby_1__1__36_chany_bottom_out; +wire [0:29] cby_1__1__36_chany_top_out; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__37_ccff_tail; +wire [0:29] cby_1__1__37_chany_bottom_out; +wire [0:29] cby_1__1__37_chany_top_out; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__38_ccff_tail; +wire [0:29] cby_1__1__38_chany_bottom_out; +wire [0:29] cby_1__1__38_chany_top_out; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__39_ccff_tail; +wire [0:29] cby_1__1__39_chany_bottom_out; +wire [0:29] cby_1__1__39_chany_top_out; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__3_ccff_tail; +wire [0:29] cby_1__1__3_chany_bottom_out; +wire [0:29] cby_1__1__3_chany_top_out; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__40_ccff_tail; +wire [0:29] cby_1__1__40_chany_bottom_out; +wire [0:29] cby_1__1__40_chany_top_out; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__41_ccff_tail; +wire [0:29] cby_1__1__41_chany_bottom_out; +wire [0:29] cby_1__1__41_chany_top_out; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__42_ccff_tail; +wire [0:29] cby_1__1__42_chany_bottom_out; +wire [0:29] cby_1__1__42_chany_top_out; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__43_ccff_tail; +wire [0:29] cby_1__1__43_chany_bottom_out; +wire [0:29] cby_1__1__43_chany_top_out; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__44_ccff_tail; +wire [0:29] cby_1__1__44_chany_bottom_out; +wire [0:29] cby_1__1__44_chany_top_out; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__45_ccff_tail; +wire [0:29] cby_1__1__45_chany_bottom_out; +wire [0:29] cby_1__1__45_chany_top_out; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__46_ccff_tail; +wire [0:29] cby_1__1__46_chany_bottom_out; +wire [0:29] cby_1__1__46_chany_top_out; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__47_ccff_tail; +wire [0:29] cby_1__1__47_chany_bottom_out; +wire [0:29] cby_1__1__47_chany_top_out; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__48_ccff_tail; +wire [0:29] cby_1__1__48_chany_bottom_out; +wire [0:29] cby_1__1__48_chany_top_out; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__49_ccff_tail; +wire [0:29] cby_1__1__49_chany_bottom_out; +wire [0:29] cby_1__1__49_chany_top_out; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__4_ccff_tail; +wire [0:29] cby_1__1__4_chany_bottom_out; +wire [0:29] cby_1__1__4_chany_top_out; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__50_ccff_tail; +wire [0:29] cby_1__1__50_chany_bottom_out; +wire [0:29] cby_1__1__50_chany_top_out; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__51_ccff_tail; +wire [0:29] cby_1__1__51_chany_bottom_out; +wire [0:29] cby_1__1__51_chany_top_out; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__52_ccff_tail; +wire [0:29] cby_1__1__52_chany_bottom_out; +wire [0:29] cby_1__1__52_chany_top_out; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__53_ccff_tail; +wire [0:29] cby_1__1__53_chany_bottom_out; +wire [0:29] cby_1__1__53_chany_top_out; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__54_ccff_tail; +wire [0:29] cby_1__1__54_chany_bottom_out; +wire [0:29] cby_1__1__54_chany_top_out; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__55_ccff_tail; +wire [0:29] cby_1__1__55_chany_bottom_out; +wire [0:29] cby_1__1__55_chany_top_out; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__5_ccff_tail; +wire [0:29] cby_1__1__5_chany_bottom_out; +wire [0:29] cby_1__1__5_chany_top_out; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__6_ccff_tail; +wire [0:29] cby_1__1__6_chany_bottom_out; +wire [0:29] cby_1__1__6_chany_top_out; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__7_ccff_tail; +wire [0:29] cby_1__1__7_chany_bottom_out; +wire [0:29] cby_1__1__7_chany_top_out; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__8_ccff_tail; +wire [0:29] cby_1__1__8_chany_bottom_out; +wire [0:29] cby_1__1__8_chany_top_out; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_1__1__9_ccff_tail; +wire [0:29] cby_1__1__9_chany_bottom_out; +wire [0:29] cby_1__1__9_chany_top_out; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_8__1__0_ccff_tail; +wire [0:29] cby_8__1__0_chany_bottom_out; +wire [0:29] cby_8__1__0_chany_top_out; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_8__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_8__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_8__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_8__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_8__1__1_ccff_tail; +wire [0:29] cby_8__1__1_chany_bottom_out; +wire [0:29] cby_8__1__1_chany_top_out; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_8__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_8__1__1_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_8__1__1_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_8__1__1_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_8__1__2_ccff_tail; +wire [0:29] cby_8__1__2_chany_bottom_out; +wire [0:29] cby_8__1__2_chany_top_out; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_8__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_8__1__2_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_8__1__2_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_8__1__2_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_8__1__3_ccff_tail; +wire [0:29] cby_8__1__3_chany_bottom_out; +wire [0:29] cby_8__1__3_chany_top_out; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_8__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_8__1__3_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_8__1__3_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_8__1__3_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_8__1__4_ccff_tail; +wire [0:29] cby_8__1__4_chany_bottom_out; +wire [0:29] cby_8__1__4_chany_top_out; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_8__1__4_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_8__1__4_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_8__1__4_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_8__1__4_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_8__1__5_ccff_tail; +wire [0:29] cby_8__1__5_chany_bottom_out; +wire [0:29] cby_8__1__5_chany_top_out; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_8__1__5_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_8__1__5_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_8__1__5_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_8__1__5_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_8__1__6_ccff_tail; +wire [0:29] cby_8__1__6_chany_bottom_out; +wire [0:29] cby_8__1__6_chany_top_out; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_8__1__6_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_8__1__6_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_8__1__6_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_8__1__6_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_8__1__7_ccff_tail; +wire [0:29] cby_8__1__7_chany_bottom_out; +wire [0:29] cby_8__1__7_chany_top_out; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +wire [0:0] cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +wire [0:0] cby_8__1__7_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_8__1__7_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_8__1__7_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_8__1__7_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] direct_interc_0_out; +wire [0:0] direct_interc_100_out; +wire [0:0] direct_interc_101_out; +wire [0:0] direct_interc_102_out; +wire [0:0] direct_interc_103_out; +wire [0:0] direct_interc_104_out; +wire [0:0] direct_interc_105_out; +wire [0:0] direct_interc_106_out; +wire [0:0] direct_interc_107_out; +wire [0:0] direct_interc_108_out; +wire [0:0] direct_interc_109_out; +wire [0:0] direct_interc_10_out; +wire [0:0] direct_interc_110_out; +wire [0:0] direct_interc_111_out; +wire [0:0] direct_interc_112_out; +wire [0:0] direct_interc_113_out; +wire [0:0] direct_interc_114_out; +wire [0:0] direct_interc_115_out; +wire [0:0] direct_interc_116_out; +wire [0:0] direct_interc_117_out; +wire [0:0] direct_interc_118_out; +wire [0:0] direct_interc_119_out; +wire [0:0] direct_interc_11_out; +wire [0:0] direct_interc_120_out; +wire [0:0] direct_interc_121_out; +wire [0:0] direct_interc_122_out; +wire [0:0] direct_interc_123_out; +wire [0:0] direct_interc_124_out; +wire [0:0] direct_interc_125_out; +wire [0:0] direct_interc_126_out; +wire [0:0] direct_interc_127_out; +wire [0:0] direct_interc_128_out; +wire [0:0] direct_interc_129_out; +wire [0:0] direct_interc_12_out; +wire [0:0] direct_interc_130_out; +wire [0:0] direct_interc_131_out; +wire [0:0] direct_interc_132_out; +wire [0:0] direct_interc_133_out; +wire [0:0] direct_interc_134_out; +wire [0:0] direct_interc_135_out; +wire [0:0] direct_interc_136_out; +wire [0:0] direct_interc_137_out; +wire [0:0] direct_interc_138_out; +wire [0:0] direct_interc_139_out; +wire [0:0] direct_interc_13_out; +wire [0:0] direct_interc_140_out; +wire [0:0] direct_interc_141_out; +wire [0:0] direct_interc_142_out; +wire [0:0] direct_interc_143_out; +wire [0:0] direct_interc_144_out; +wire [0:0] direct_interc_145_out; +wire [0:0] direct_interc_146_out; +wire [0:0] direct_interc_147_out; +wire [0:0] direct_interc_148_out; +wire [0:0] direct_interc_149_out; +wire [0:0] direct_interc_14_out; +wire [0:0] direct_interc_150_out; +wire [0:0] direct_interc_151_out; +wire [0:0] direct_interc_152_out; +wire [0:0] direct_interc_153_out; +wire [0:0] direct_interc_154_out; +wire [0:0] direct_interc_155_out; +wire [0:0] direct_interc_156_out; +wire [0:0] direct_interc_157_out; +wire [0:0] direct_interc_158_out; +wire [0:0] direct_interc_159_out; +wire [0:0] direct_interc_15_out; +wire [0:0] direct_interc_160_out; +wire [0:0] direct_interc_161_out; +wire [0:0] direct_interc_162_out; +wire [0:0] direct_interc_163_out; +wire [0:0] direct_interc_164_out; +wire [0:0] direct_interc_165_out; +wire [0:0] direct_interc_166_out; +wire [0:0] direct_interc_167_out; +wire [0:0] direct_interc_168_out; +wire [0:0] direct_interc_169_out; +wire [0:0] direct_interc_16_out; +wire [0:0] direct_interc_170_out; +wire [0:0] direct_interc_171_out; +wire [0:0] direct_interc_172_out; +wire [0:0] direct_interc_173_out; +wire [0:0] direct_interc_174_out; +wire [0:0] direct_interc_17_out; +wire [0:0] direct_interc_18_out; +wire [0:0] direct_interc_19_out; +wire [0:0] direct_interc_1_out; +wire [0:0] direct_interc_20_out; +wire [0:0] direct_interc_21_out; +wire [0:0] direct_interc_22_out; +wire [0:0] direct_interc_23_out; +wire [0:0] direct_interc_24_out; +wire [0:0] direct_interc_25_out; +wire [0:0] direct_interc_26_out; +wire [0:0] direct_interc_27_out; +wire [0:0] direct_interc_28_out; +wire [0:0] direct_interc_29_out; +wire [0:0] direct_interc_2_out; +wire [0:0] direct_interc_30_out; +wire [0:0] direct_interc_31_out; +wire [0:0] direct_interc_32_out; +wire [0:0] direct_interc_33_out; +wire [0:0] direct_interc_34_out; +wire [0:0] direct_interc_35_out; +wire [0:0] direct_interc_36_out; +wire [0:0] direct_interc_37_out; +wire [0:0] direct_interc_38_out; +wire [0:0] direct_interc_39_out; +wire [0:0] direct_interc_3_out; +wire [0:0] direct_interc_40_out; +wire [0:0] direct_interc_41_out; +wire [0:0] direct_interc_42_out; +wire [0:0] direct_interc_43_out; +wire [0:0] direct_interc_44_out; +wire [0:0] direct_interc_45_out; +wire [0:0] direct_interc_46_out; +wire [0:0] direct_interc_47_out; +wire [0:0] direct_interc_48_out; +wire [0:0] direct_interc_49_out; +wire [0:0] direct_interc_4_out; +wire [0:0] direct_interc_50_out; +wire [0:0] direct_interc_51_out; +wire [0:0] direct_interc_52_out; +wire [0:0] direct_interc_53_out; +wire [0:0] direct_interc_54_out; +wire [0:0] direct_interc_55_out; +wire [0:0] direct_interc_56_out; +wire [0:0] direct_interc_57_out; +wire [0:0] direct_interc_58_out; +wire [0:0] direct_interc_59_out; +wire [0:0] direct_interc_5_out; +wire [0:0] direct_interc_60_out; +wire [0:0] direct_interc_61_out; +wire [0:0] direct_interc_62_out; +wire [0:0] direct_interc_63_out; +wire [0:0] direct_interc_64_out; +wire [0:0] direct_interc_65_out; +wire [0:0] direct_interc_66_out; +wire [0:0] direct_interc_67_out; +wire [0:0] direct_interc_68_out; +wire [0:0] direct_interc_69_out; +wire [0:0] direct_interc_6_out; +wire [0:0] direct_interc_70_out; +wire [0:0] direct_interc_71_out; +wire [0:0] direct_interc_72_out; +wire [0:0] direct_interc_73_out; +wire [0:0] direct_interc_74_out; +wire [0:0] direct_interc_75_out; +wire [0:0] direct_interc_76_out; +wire [0:0] direct_interc_77_out; +wire [0:0] direct_interc_78_out; +wire [0:0] direct_interc_79_out; +wire [0:0] direct_interc_7_out; +wire [0:0] direct_interc_80_out; +wire [0:0] direct_interc_81_out; +wire [0:0] direct_interc_82_out; +wire [0:0] direct_interc_83_out; +wire [0:0] direct_interc_84_out; +wire [0:0] direct_interc_85_out; +wire [0:0] direct_interc_86_out; +wire [0:0] direct_interc_87_out; +wire [0:0] direct_interc_88_out; +wire [0:0] direct_interc_89_out; +wire [0:0] direct_interc_8_out; +wire [0:0] direct_interc_90_out; +wire [0:0] direct_interc_91_out; +wire [0:0] direct_interc_92_out; +wire [0:0] direct_interc_93_out; +wire [0:0] direct_interc_94_out; +wire [0:0] direct_interc_95_out; +wire [0:0] direct_interc_96_out; +wire [0:0] direct_interc_97_out; +wire [0:0] direct_interc_98_out; +wire [0:0] direct_interc_99_out; +wire [0:0] direct_interc_9_out; +wire [0:0] grid_clb_0_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_0_ccff_tail; +wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_10_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_10_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_10_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_10_ccff_tail; +wire [0:0] grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_10_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_10_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_10_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_10_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_10_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_10_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_11_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_11_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_11_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_11_ccff_tail; +wire [0:0] grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_11_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_11_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_11_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_11_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_11_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_11_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_12_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_12_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_12_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_12_ccff_tail; +wire [0:0] grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_12_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_12_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_12_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_12_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_12_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_12_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_13_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_13_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_13_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_13_ccff_tail; +wire [0:0] grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_13_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_13_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_13_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_13_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_13_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_13_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_14_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_14_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_14_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_14_ccff_tail; +wire [0:0] grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_14_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_14_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_14_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_14_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_14_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_14_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_15_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_15_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_15_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_15_ccff_tail; +wire [0:0] grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_15_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_15_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_15_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_15_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_15_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_15_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_15_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_15_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_15_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_16_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_16_ccff_tail; +wire [0:0] grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_16_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_16_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_16_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_16_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_16_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_16_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_17_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_17_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_17_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_17_ccff_tail; +wire [0:0] grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_17_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_17_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_17_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_17_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_17_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_17_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_18_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_18_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_18_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_18_ccff_tail; +wire [0:0] grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_18_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_18_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_18_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_18_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_18_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_18_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_19_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_19_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_19_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_19_ccff_tail; +wire [0:0] grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_19_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_19_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_19_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_19_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_19_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_19_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; +wire [0:0] grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; +wire [0:0] grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_sc_in_0_; +wire [0:0] grid_clb_1_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_1_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_1_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_1_ccff_tail; +wire [0:0] grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_1_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_1_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_1_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_1_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_1_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_1_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_1_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_1_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_1_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_20_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_20_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_20_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_20_ccff_tail; +wire [0:0] grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_20_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_20_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_20_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_20_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_20_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_20_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_21_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_21_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_21_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_21_ccff_tail; +wire [0:0] grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_21_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_21_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_21_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_21_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_21_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_21_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_22_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_22_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_22_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_22_ccff_tail; +wire [0:0] grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_22_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_22_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_22_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_22_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_22_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_22_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_23_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_23_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_23_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_23_ccff_tail; +wire [0:0] grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_23_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_23_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_23_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_23_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_23_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_23_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_23_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_23_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_23_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_24_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_24_ccff_tail; +wire [0:0] grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_24_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_24_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_24_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_24_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_24_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_24_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_25_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_25_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_25_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_25_ccff_tail; +wire [0:0] grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_25_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_25_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_25_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_25_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_25_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_25_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_26_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_26_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_26_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_26_ccff_tail; +wire [0:0] grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_26_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_26_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_26_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_26_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_26_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_26_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_27_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_27_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_27_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_27_ccff_tail; +wire [0:0] grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_27_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_27_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_27_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_27_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_27_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_27_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_28_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_28_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_28_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_28_ccff_tail; +wire [0:0] grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_28_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_28_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_28_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_28_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_28_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_28_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_29_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_29_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_29_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_29_ccff_tail; +wire [0:0] grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_29_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_29_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_29_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_29_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_29_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_29_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; +wire [0:0] grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; +wire [0:0] grid_clb_2_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_2_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_2_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_2_ccff_tail; +wire [0:0] grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_2_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_2_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_2_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_2_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_2_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_2_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_2_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_2_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_2_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_30_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_30_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_30_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_30_ccff_tail; +wire [0:0] grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_30_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_30_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_30_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_30_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_30_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_30_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_31_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_31_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_31_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_31_ccff_tail; +wire [0:0] grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_31_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_31_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_31_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_31_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_31_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_31_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_31_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_31_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_31_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_32_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_32_ccff_tail; +wire [0:0] grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_32_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_32_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_32_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_32_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_32_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_32_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_33_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_33_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_33_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_33_ccff_tail; +wire [0:0] grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_33_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_33_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_33_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_33_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_33_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_33_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_34_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_34_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_34_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_34_ccff_tail; +wire [0:0] grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_34_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_34_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_34_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_34_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_34_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_34_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_35_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_35_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_35_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_35_ccff_tail; +wire [0:0] grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_35_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_35_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_35_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_35_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_35_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_35_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_36_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_36_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_36_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_36_ccff_tail; +wire [0:0] grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_36_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_36_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_36_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_36_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_36_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_36_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_37_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_37_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_37_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_37_ccff_tail; +wire [0:0] grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_37_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_37_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_37_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_37_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_37_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_37_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_38_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_38_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_38_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_38_ccff_tail; +wire [0:0] grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_38_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_38_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_38_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_38_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_38_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_38_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_39_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_39_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_39_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_39_ccff_tail; +wire [0:0] grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_39_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_39_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_39_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_39_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_39_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_39_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_39_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_39_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_39_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; +wire [0:0] grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; +wire [0:0] grid_clb_3_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_3_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_3_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_3_ccff_tail; +wire [0:0] grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_3_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_3_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_3_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_3_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_3_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_3_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_3_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_3_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_3_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_40_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_40_ccff_tail; +wire [0:0] grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_40_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_40_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_40_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_40_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_40_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_40_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_41_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_41_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_41_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_41_ccff_tail; +wire [0:0] grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_41_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_41_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_41_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_41_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_41_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_41_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_42_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_42_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_42_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_42_ccff_tail; +wire [0:0] grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_42_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_42_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_42_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_42_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_42_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_42_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_43_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_43_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_43_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_43_ccff_tail; +wire [0:0] grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_43_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_43_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_43_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_43_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_43_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_43_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_44_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_44_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_44_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_44_ccff_tail; +wire [0:0] grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_44_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_44_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_44_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_44_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_44_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_44_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_45_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_45_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_45_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_45_ccff_tail; +wire [0:0] grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_45_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_45_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_45_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_45_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_45_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_45_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_46_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_46_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_46_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_46_ccff_tail; +wire [0:0] grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_46_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_46_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_46_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_46_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_46_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_46_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_47_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_47_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_47_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_47_ccff_tail; +wire [0:0] grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_47_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_47_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_47_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_47_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_47_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_47_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_47_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_47_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_47_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_48_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_48_ccff_tail; +wire [0:0] grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_48_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_48_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_48_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_48_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_48_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_48_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_49_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_49_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_49_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_49_ccff_tail; +wire [0:0] grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_49_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_49_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_49_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_49_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_49_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_49_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; +wire [0:0] grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; +wire [0:0] grid_clb_4_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_4_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_4_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_4_ccff_tail; +wire [0:0] grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_4_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_4_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_4_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_4_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_4_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_4_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_4_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_4_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_4_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_50_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_50_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_50_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_50_ccff_tail; +wire [0:0] grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_50_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_50_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_50_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_50_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_50_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_50_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_51_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_51_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_51_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_51_ccff_tail; +wire [0:0] grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_51_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_51_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_51_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_51_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_51_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_51_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_52_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_52_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_52_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_52_ccff_tail; +wire [0:0] grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_52_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_52_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_52_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_52_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_52_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_52_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_53_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_53_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_53_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_53_ccff_tail; +wire [0:0] grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_53_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_53_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_53_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_53_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_53_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_53_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_54_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_54_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_54_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_54_ccff_tail; +wire [0:0] grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_54_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_54_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_54_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_54_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_54_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_54_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_55_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_55_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_55_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_55_ccff_tail; +wire [0:0] grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_55_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_55_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_55_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_55_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_55_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_55_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_55_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_55_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_55_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_56_ccff_tail; +wire [0:0] grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_56_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_56_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_56_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_56_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_56_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_56_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_57_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_57_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_57_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_57_ccff_tail; +wire [0:0] grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_57_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_57_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_57_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_57_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_57_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_57_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_58_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_58_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_58_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_58_ccff_tail; +wire [0:0] grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_58_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_58_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_58_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_58_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_58_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_58_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_59_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_59_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_59_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_59_ccff_tail; +wire [0:0] grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_59_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_59_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_59_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_59_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_59_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_59_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; +wire [0:0] grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; +wire [0:0] grid_clb_5_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_5_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_5_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_5_ccff_tail; +wire [0:0] grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_5_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_5_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_5_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_5_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_5_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_5_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_5_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_5_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_5_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_60_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_60_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_60_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_60_ccff_tail; +wire [0:0] grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_60_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_60_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_60_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_60_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_60_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_60_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_61_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_61_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_61_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_61_ccff_tail; +wire [0:0] grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_61_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_61_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_61_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_61_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_61_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_61_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_62_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_62_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_62_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_62_ccff_tail; +wire [0:0] grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_62_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_62_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_62_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_62_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_62_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_62_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_63_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_63_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_63_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_63_ccff_tail; +wire [0:0] grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_63_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_63_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_63_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_63_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_63_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_63_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_63_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_63_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_63_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; +wire [0:0] grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; +wire [0:0] grid_clb_6_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_6_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_6_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_6_ccff_tail; +wire [0:0] grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_6_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_6_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_6_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_6_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_6_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_6_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_6_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_6_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_6_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; +wire [0:0] grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; +wire [0:0] grid_clb_7_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_7_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_7_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_7_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_7_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_7_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_7_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_7_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_7_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_7_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_7_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_7_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; +wire [0:0] grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; +wire [0:0] grid_clb_8_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_8_ccff_tail; +wire [0:0] grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_8_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_8_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_8_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_8_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_8_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_8_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_clb_9_bottom_width_0_height_0_subtile_0__pin_cout_0_; +wire [0:0] grid_clb_9_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; +wire [0:0] grid_clb_9_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; +wire [0:0] grid_clb_9_ccff_tail; +wire [0:0] grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_; +wire [0:0] grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_; +wire [0:0] grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_; +wire [0:0] grid_clb_9_right_width_0_height_0_subtile_0__pin_O_13_; +wire [0:0] grid_clb_9_right_width_0_height_0_subtile_0__pin_O_14_; +wire [0:0] grid_clb_9_right_width_0_height_0_subtile_0__pin_O_15_; +wire [0:0] grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_; +wire [0:0] grid_clb_9_right_width_0_height_0_subtile_0__pin_O_9_; +wire [0:0] grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_clb_9_top_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_9_top_width_0_height_0_subtile_0__pin_O_4_; +wire [0:0] grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_; +wire [0:0] grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_; +wire [0:0] grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_; +wire [0:0] grid_io_bottom_bottom_0_ccff_tail; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_1_ccff_tail; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_2_ccff_tail; +wire [0:0] grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_2_top_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_3_ccff_tail; +wire [0:0] grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_3_top_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_4_ccff_tail; +wire [0:0] grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_4_top_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_5_ccff_tail; +wire [0:0] grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_5_top_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_6_ccff_tail; +wire [0:0] grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_6_top_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_7_ccff_tail; +wire [0:0] grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_bottom_bottom_7_top_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_left_left_0_ccff_tail; +wire [0:0] grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_left_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_left_left_1_ccff_tail; +wire [0:0] grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_left_left_1_right_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_left_left_2_ccff_tail; +wire [0:0] grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_left_left_2_right_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_left_left_3_ccff_tail; +wire [0:0] grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_left_left_3_right_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_left_left_4_ccff_tail; +wire [0:0] grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_left_left_4_right_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_left_left_5_ccff_tail; +wire [0:0] grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_left_left_5_right_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_left_left_6_ccff_tail; +wire [0:0] grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_left_left_6_right_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_left_left_7_ccff_tail; +wire [0:0] grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_left_left_7_right_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_right_right_0_ccff_tail; +wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_right_right_1_ccff_tail; +wire [0:0] grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_right_right_1_left_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_right_right_2_ccff_tail; +wire [0:0] grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_right_right_2_left_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_right_right_3_ccff_tail; +wire [0:0] grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_right_right_3_left_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_right_right_4_ccff_tail; +wire [0:0] grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_right_right_4_left_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_right_right_5_ccff_tail; +wire [0:0] grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_right_right_5_left_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_right_right_6_ccff_tail; +wire [0:0] grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_right_right_6_left_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_right_right_7_ccff_tail; +wire [0:0] grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_right_right_7_left_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_top_top_0_ccff_tail; +wire [0:0] grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_top_top_1_ccff_tail; +wire [0:0] grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_top_top_2_ccff_tail; +wire [0:0] grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_top_top_3_ccff_tail; +wire [0:0] grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_top_top_4_ccff_tail; +wire [0:0] grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_top_top_5_ccff_tail; +wire [0:0] grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_top_top_6_ccff_tail; +wire [0:0] grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_top_top_7_ccff_tail; +wire [0:0] sb_0__0__0_ccff_tail; +wire [0:29] sb_0__0__0_chanx_right_out; +wire [0:29] sb_0__0__0_chany_top_out; +wire [0:0] sb_0__1__0_ccff_tail; +wire [0:29] sb_0__1__0_chanx_right_out; +wire [0:29] sb_0__1__0_chany_bottom_out; +wire [0:29] sb_0__1__0_chany_top_out; +wire [0:0] sb_0__1__1_ccff_tail; +wire [0:29] sb_0__1__1_chanx_right_out; +wire [0:29] sb_0__1__1_chany_bottom_out; +wire [0:29] sb_0__1__1_chany_top_out; +wire [0:0] sb_0__1__2_ccff_tail; +wire [0:29] sb_0__1__2_chanx_right_out; +wire [0:29] sb_0__1__2_chany_bottom_out; +wire [0:29] sb_0__1__2_chany_top_out; +wire [0:0] sb_0__1__3_ccff_tail; +wire [0:29] sb_0__1__3_chanx_right_out; +wire [0:29] sb_0__1__3_chany_bottom_out; +wire [0:29] sb_0__1__3_chany_top_out; +wire [0:0] sb_0__1__4_ccff_tail; +wire [0:29] sb_0__1__4_chanx_right_out; +wire [0:29] sb_0__1__4_chany_bottom_out; +wire [0:29] sb_0__1__4_chany_top_out; +wire [0:0] sb_0__1__5_ccff_tail; +wire [0:29] sb_0__1__5_chanx_right_out; +wire [0:29] sb_0__1__5_chany_bottom_out; +wire [0:29] sb_0__1__5_chany_top_out; +wire [0:0] sb_0__1__6_ccff_tail; +wire [0:29] sb_0__1__6_chanx_right_out; +wire [0:29] sb_0__1__6_chany_bottom_out; +wire [0:29] sb_0__1__6_chany_top_out; +wire [0:0] sb_0__8__0_ccff_tail; +wire [0:29] sb_0__8__0_chanx_right_out; +wire [0:29] sb_0__8__0_chany_bottom_out; +wire [0:0] sb_1__0__0_ccff_tail; +wire [0:29] sb_1__0__0_chanx_left_out; +wire [0:29] sb_1__0__0_chanx_right_out; +wire [0:29] sb_1__0__0_chany_top_out; +wire [0:0] sb_1__0__1_ccff_tail; +wire [0:29] sb_1__0__1_chanx_left_out; +wire [0:29] sb_1__0__1_chanx_right_out; +wire [0:29] sb_1__0__1_chany_top_out; +wire [0:0] sb_1__0__2_ccff_tail; +wire [0:29] sb_1__0__2_chanx_left_out; +wire [0:29] sb_1__0__2_chanx_right_out; +wire [0:29] sb_1__0__2_chany_top_out; +wire [0:0] sb_1__0__3_ccff_tail; +wire [0:29] sb_1__0__3_chanx_left_out; +wire [0:29] sb_1__0__3_chanx_right_out; +wire [0:29] sb_1__0__3_chany_top_out; +wire [0:0] sb_1__0__4_ccff_tail; +wire [0:29] sb_1__0__4_chanx_left_out; +wire [0:29] sb_1__0__4_chanx_right_out; +wire [0:29] sb_1__0__4_chany_top_out; +wire [0:0] sb_1__0__5_ccff_tail; +wire [0:29] sb_1__0__5_chanx_left_out; +wire [0:29] sb_1__0__5_chanx_right_out; +wire [0:29] sb_1__0__5_chany_top_out; +wire [0:0] sb_1__0__6_ccff_tail; +wire [0:29] sb_1__0__6_chanx_left_out; +wire [0:29] sb_1__0__6_chanx_right_out; +wire [0:29] sb_1__0__6_chany_top_out; +wire [0:0] sb_1__1__0_ccff_tail; +wire [0:29] sb_1__1__0_chanx_left_out; +wire [0:29] sb_1__1__0_chanx_right_out; +wire [0:29] sb_1__1__0_chany_bottom_out; +wire [0:29] sb_1__1__0_chany_top_out; +wire [0:0] sb_1__1__10_ccff_tail; +wire [0:29] sb_1__1__10_chanx_left_out; +wire [0:29] sb_1__1__10_chanx_right_out; +wire [0:29] sb_1__1__10_chany_bottom_out; +wire [0:29] sb_1__1__10_chany_top_out; +wire [0:0] sb_1__1__11_ccff_tail; +wire [0:29] sb_1__1__11_chanx_left_out; +wire [0:29] sb_1__1__11_chanx_right_out; +wire [0:29] sb_1__1__11_chany_bottom_out; +wire [0:29] sb_1__1__11_chany_top_out; +wire [0:0] sb_1__1__12_ccff_tail; +wire [0:29] sb_1__1__12_chanx_left_out; +wire [0:29] sb_1__1__12_chanx_right_out; +wire [0:29] sb_1__1__12_chany_bottom_out; +wire [0:29] sb_1__1__12_chany_top_out; +wire [0:0] sb_1__1__13_ccff_tail; +wire [0:29] sb_1__1__13_chanx_left_out; +wire [0:29] sb_1__1__13_chanx_right_out; +wire [0:29] sb_1__1__13_chany_bottom_out; +wire [0:29] sb_1__1__13_chany_top_out; +wire [0:0] sb_1__1__14_ccff_tail; +wire [0:29] sb_1__1__14_chanx_left_out; +wire [0:29] sb_1__1__14_chanx_right_out; +wire [0:29] sb_1__1__14_chany_bottom_out; +wire [0:29] sb_1__1__14_chany_top_out; +wire [0:0] sb_1__1__15_ccff_tail; +wire [0:29] sb_1__1__15_chanx_left_out; +wire [0:29] sb_1__1__15_chanx_right_out; +wire [0:29] sb_1__1__15_chany_bottom_out; +wire [0:29] sb_1__1__15_chany_top_out; +wire [0:0] sb_1__1__16_ccff_tail; +wire [0:29] sb_1__1__16_chanx_left_out; +wire [0:29] sb_1__1__16_chanx_right_out; +wire [0:29] sb_1__1__16_chany_bottom_out; +wire [0:29] sb_1__1__16_chany_top_out; +wire [0:0] sb_1__1__17_ccff_tail; +wire [0:29] sb_1__1__17_chanx_left_out; +wire [0:29] sb_1__1__17_chanx_right_out; +wire [0:29] sb_1__1__17_chany_bottom_out; +wire [0:29] sb_1__1__17_chany_top_out; +wire [0:0] sb_1__1__18_ccff_tail; +wire [0:29] sb_1__1__18_chanx_left_out; +wire [0:29] sb_1__1__18_chanx_right_out; +wire [0:29] sb_1__1__18_chany_bottom_out; +wire [0:29] sb_1__1__18_chany_top_out; +wire [0:0] sb_1__1__19_ccff_tail; +wire [0:29] sb_1__1__19_chanx_left_out; +wire [0:29] sb_1__1__19_chanx_right_out; +wire [0:29] sb_1__1__19_chany_bottom_out; +wire [0:29] sb_1__1__19_chany_top_out; +wire [0:0] sb_1__1__1_ccff_tail; +wire [0:29] sb_1__1__1_chanx_left_out; +wire [0:29] sb_1__1__1_chanx_right_out; +wire [0:29] sb_1__1__1_chany_bottom_out; +wire [0:29] sb_1__1__1_chany_top_out; +wire [0:0] sb_1__1__20_ccff_tail; +wire [0:29] sb_1__1__20_chanx_left_out; +wire [0:29] sb_1__1__20_chanx_right_out; +wire [0:29] sb_1__1__20_chany_bottom_out; +wire [0:29] sb_1__1__20_chany_top_out; +wire [0:0] sb_1__1__21_ccff_tail; +wire [0:29] sb_1__1__21_chanx_left_out; +wire [0:29] sb_1__1__21_chanx_right_out; +wire [0:29] sb_1__1__21_chany_bottom_out; +wire [0:29] sb_1__1__21_chany_top_out; +wire [0:0] sb_1__1__22_ccff_tail; +wire [0:29] sb_1__1__22_chanx_left_out; +wire [0:29] sb_1__1__22_chanx_right_out; +wire [0:29] sb_1__1__22_chany_bottom_out; +wire [0:29] sb_1__1__22_chany_top_out; +wire [0:0] sb_1__1__23_ccff_tail; +wire [0:29] sb_1__1__23_chanx_left_out; +wire [0:29] sb_1__1__23_chanx_right_out; +wire [0:29] sb_1__1__23_chany_bottom_out; +wire [0:29] sb_1__1__23_chany_top_out; +wire [0:0] sb_1__1__24_ccff_tail; +wire [0:29] sb_1__1__24_chanx_left_out; +wire [0:29] sb_1__1__24_chanx_right_out; +wire [0:29] sb_1__1__24_chany_bottom_out; +wire [0:29] sb_1__1__24_chany_top_out; +wire [0:0] sb_1__1__25_ccff_tail; +wire [0:29] sb_1__1__25_chanx_left_out; +wire [0:29] sb_1__1__25_chanx_right_out; +wire [0:29] sb_1__1__25_chany_bottom_out; +wire [0:29] sb_1__1__25_chany_top_out; +wire [0:0] sb_1__1__26_ccff_tail; +wire [0:29] sb_1__1__26_chanx_left_out; +wire [0:29] sb_1__1__26_chanx_right_out; +wire [0:29] sb_1__1__26_chany_bottom_out; +wire [0:29] sb_1__1__26_chany_top_out; +wire [0:0] sb_1__1__27_ccff_tail; +wire [0:29] sb_1__1__27_chanx_left_out; +wire [0:29] sb_1__1__27_chanx_right_out; +wire [0:29] sb_1__1__27_chany_bottom_out; +wire [0:29] sb_1__1__27_chany_top_out; +wire [0:0] sb_1__1__28_ccff_tail; +wire [0:29] sb_1__1__28_chanx_left_out; +wire [0:29] sb_1__1__28_chanx_right_out; +wire [0:29] sb_1__1__28_chany_bottom_out; +wire [0:29] sb_1__1__28_chany_top_out; +wire [0:0] sb_1__1__29_ccff_tail; +wire [0:29] sb_1__1__29_chanx_left_out; +wire [0:29] sb_1__1__29_chanx_right_out; +wire [0:29] sb_1__1__29_chany_bottom_out; +wire [0:29] sb_1__1__29_chany_top_out; +wire [0:0] sb_1__1__2_ccff_tail; +wire [0:29] sb_1__1__2_chanx_left_out; +wire [0:29] sb_1__1__2_chanx_right_out; +wire [0:29] sb_1__1__2_chany_bottom_out; +wire [0:29] sb_1__1__2_chany_top_out; +wire [0:0] sb_1__1__30_ccff_tail; +wire [0:29] sb_1__1__30_chanx_left_out; +wire [0:29] sb_1__1__30_chanx_right_out; +wire [0:29] sb_1__1__30_chany_bottom_out; +wire [0:29] sb_1__1__30_chany_top_out; +wire [0:0] sb_1__1__31_ccff_tail; +wire [0:29] sb_1__1__31_chanx_left_out; +wire [0:29] sb_1__1__31_chanx_right_out; +wire [0:29] sb_1__1__31_chany_bottom_out; +wire [0:29] sb_1__1__31_chany_top_out; +wire [0:0] sb_1__1__32_ccff_tail; +wire [0:29] sb_1__1__32_chanx_left_out; +wire [0:29] sb_1__1__32_chanx_right_out; +wire [0:29] sb_1__1__32_chany_bottom_out; +wire [0:29] sb_1__1__32_chany_top_out; +wire [0:0] sb_1__1__33_ccff_tail; +wire [0:29] sb_1__1__33_chanx_left_out; +wire [0:29] sb_1__1__33_chanx_right_out; +wire [0:29] sb_1__1__33_chany_bottom_out; +wire [0:29] sb_1__1__33_chany_top_out; +wire [0:0] sb_1__1__34_ccff_tail; +wire [0:29] sb_1__1__34_chanx_left_out; +wire [0:29] sb_1__1__34_chanx_right_out; +wire [0:29] sb_1__1__34_chany_bottom_out; +wire [0:29] sb_1__1__34_chany_top_out; +wire [0:0] sb_1__1__35_ccff_tail; +wire [0:29] sb_1__1__35_chanx_left_out; +wire [0:29] sb_1__1__35_chanx_right_out; +wire [0:29] sb_1__1__35_chany_bottom_out; +wire [0:29] sb_1__1__35_chany_top_out; +wire [0:0] sb_1__1__36_ccff_tail; +wire [0:29] sb_1__1__36_chanx_left_out; +wire [0:29] sb_1__1__36_chanx_right_out; +wire [0:29] sb_1__1__36_chany_bottom_out; +wire [0:29] sb_1__1__36_chany_top_out; +wire [0:0] sb_1__1__37_ccff_tail; +wire [0:29] sb_1__1__37_chanx_left_out; +wire [0:29] sb_1__1__37_chanx_right_out; +wire [0:29] sb_1__1__37_chany_bottom_out; +wire [0:29] sb_1__1__37_chany_top_out; +wire [0:0] sb_1__1__38_ccff_tail; +wire [0:29] sb_1__1__38_chanx_left_out; +wire [0:29] sb_1__1__38_chanx_right_out; +wire [0:29] sb_1__1__38_chany_bottom_out; +wire [0:29] sb_1__1__38_chany_top_out; +wire [0:0] sb_1__1__39_ccff_tail; +wire [0:29] sb_1__1__39_chanx_left_out; +wire [0:29] sb_1__1__39_chanx_right_out; +wire [0:29] sb_1__1__39_chany_bottom_out; +wire [0:29] sb_1__1__39_chany_top_out; +wire [0:0] sb_1__1__3_ccff_tail; +wire [0:29] sb_1__1__3_chanx_left_out; +wire [0:29] sb_1__1__3_chanx_right_out; +wire [0:29] sb_1__1__3_chany_bottom_out; +wire [0:29] sb_1__1__3_chany_top_out; +wire [0:0] sb_1__1__40_ccff_tail; +wire [0:29] sb_1__1__40_chanx_left_out; +wire [0:29] sb_1__1__40_chanx_right_out; +wire [0:29] sb_1__1__40_chany_bottom_out; +wire [0:29] sb_1__1__40_chany_top_out; +wire [0:0] sb_1__1__41_ccff_tail; +wire [0:29] sb_1__1__41_chanx_left_out; +wire [0:29] sb_1__1__41_chanx_right_out; +wire [0:29] sb_1__1__41_chany_bottom_out; +wire [0:29] sb_1__1__41_chany_top_out; +wire [0:0] sb_1__1__42_ccff_tail; +wire [0:29] sb_1__1__42_chanx_left_out; +wire [0:29] sb_1__1__42_chanx_right_out; +wire [0:29] sb_1__1__42_chany_bottom_out; +wire [0:29] sb_1__1__42_chany_top_out; +wire [0:0] sb_1__1__43_ccff_tail; +wire [0:29] sb_1__1__43_chanx_left_out; +wire [0:29] sb_1__1__43_chanx_right_out; +wire [0:29] sb_1__1__43_chany_bottom_out; +wire [0:29] sb_1__1__43_chany_top_out; +wire [0:0] sb_1__1__44_ccff_tail; +wire [0:29] sb_1__1__44_chanx_left_out; +wire [0:29] sb_1__1__44_chanx_right_out; +wire [0:29] sb_1__1__44_chany_bottom_out; +wire [0:29] sb_1__1__44_chany_top_out; +wire [0:0] sb_1__1__45_ccff_tail; +wire [0:29] sb_1__1__45_chanx_left_out; +wire [0:29] sb_1__1__45_chanx_right_out; +wire [0:29] sb_1__1__45_chany_bottom_out; +wire [0:29] sb_1__1__45_chany_top_out; +wire [0:0] sb_1__1__46_ccff_tail; +wire [0:29] sb_1__1__46_chanx_left_out; +wire [0:29] sb_1__1__46_chanx_right_out; +wire [0:29] sb_1__1__46_chany_bottom_out; +wire [0:29] sb_1__1__46_chany_top_out; +wire [0:0] sb_1__1__47_ccff_tail; +wire [0:29] sb_1__1__47_chanx_left_out; +wire [0:29] sb_1__1__47_chanx_right_out; +wire [0:29] sb_1__1__47_chany_bottom_out; +wire [0:29] sb_1__1__47_chany_top_out; +wire [0:0] sb_1__1__48_ccff_tail; +wire [0:29] sb_1__1__48_chanx_left_out; +wire [0:29] sb_1__1__48_chanx_right_out; +wire [0:29] sb_1__1__48_chany_bottom_out; +wire [0:29] sb_1__1__48_chany_top_out; +wire [0:0] sb_1__1__4_ccff_tail; +wire [0:29] sb_1__1__4_chanx_left_out; +wire [0:29] sb_1__1__4_chanx_right_out; +wire [0:29] sb_1__1__4_chany_bottom_out; +wire [0:29] sb_1__1__4_chany_top_out; +wire [0:0] sb_1__1__5_ccff_tail; +wire [0:29] sb_1__1__5_chanx_left_out; +wire [0:29] sb_1__1__5_chanx_right_out; +wire [0:29] sb_1__1__5_chany_bottom_out; +wire [0:29] sb_1__1__5_chany_top_out; +wire [0:0] sb_1__1__6_ccff_tail; +wire [0:29] sb_1__1__6_chanx_left_out; +wire [0:29] sb_1__1__6_chanx_right_out; +wire [0:29] sb_1__1__6_chany_bottom_out; +wire [0:29] sb_1__1__6_chany_top_out; +wire [0:0] sb_1__1__7_ccff_tail; +wire [0:29] sb_1__1__7_chanx_left_out; +wire [0:29] sb_1__1__7_chanx_right_out; +wire [0:29] sb_1__1__7_chany_bottom_out; +wire [0:29] sb_1__1__7_chany_top_out; +wire [0:0] sb_1__1__8_ccff_tail; +wire [0:29] sb_1__1__8_chanx_left_out; +wire [0:29] sb_1__1__8_chanx_right_out; +wire [0:29] sb_1__1__8_chany_bottom_out; +wire [0:29] sb_1__1__8_chany_top_out; +wire [0:0] sb_1__1__9_ccff_tail; +wire [0:29] sb_1__1__9_chanx_left_out; +wire [0:29] sb_1__1__9_chanx_right_out; +wire [0:29] sb_1__1__9_chany_bottom_out; +wire [0:29] sb_1__1__9_chany_top_out; +wire [0:0] sb_1__8__0_ccff_tail; +wire [0:29] sb_1__8__0_chanx_left_out; +wire [0:29] sb_1__8__0_chanx_right_out; +wire [0:29] sb_1__8__0_chany_bottom_out; +wire [0:0] sb_1__8__1_ccff_tail; +wire [0:29] sb_1__8__1_chanx_left_out; +wire [0:29] sb_1__8__1_chanx_right_out; +wire [0:29] sb_1__8__1_chany_bottom_out; +wire [0:0] sb_1__8__2_ccff_tail; +wire [0:29] sb_1__8__2_chanx_left_out; +wire [0:29] sb_1__8__2_chanx_right_out; +wire [0:29] sb_1__8__2_chany_bottom_out; +wire [0:0] sb_1__8__3_ccff_tail; +wire [0:29] sb_1__8__3_chanx_left_out; +wire [0:29] sb_1__8__3_chanx_right_out; +wire [0:29] sb_1__8__3_chany_bottom_out; +wire [0:0] sb_1__8__4_ccff_tail; +wire [0:29] sb_1__8__4_chanx_left_out; +wire [0:29] sb_1__8__4_chanx_right_out; +wire [0:29] sb_1__8__4_chany_bottom_out; +wire [0:0] sb_1__8__5_ccff_tail; +wire [0:29] sb_1__8__5_chanx_left_out; +wire [0:29] sb_1__8__5_chanx_right_out; +wire [0:29] sb_1__8__5_chany_bottom_out; +wire [0:0] sb_1__8__6_ccff_tail; +wire [0:29] sb_1__8__6_chanx_left_out; +wire [0:29] sb_1__8__6_chanx_right_out; +wire [0:29] sb_1__8__6_chany_bottom_out; +wire [0:0] sb_8__0__0_ccff_tail; +wire [0:29] sb_8__0__0_chanx_left_out; +wire [0:29] sb_8__0__0_chany_top_out; +wire [0:0] sb_8__1__0_ccff_tail; +wire [0:29] sb_8__1__0_chanx_left_out; +wire [0:29] sb_8__1__0_chany_bottom_out; +wire [0:29] sb_8__1__0_chany_top_out; +wire [0:0] sb_8__1__1_ccff_tail; +wire [0:29] sb_8__1__1_chanx_left_out; +wire [0:29] sb_8__1__1_chany_bottom_out; +wire [0:29] sb_8__1__1_chany_top_out; +wire [0:0] sb_8__1__2_ccff_tail; +wire [0:29] sb_8__1__2_chanx_left_out; +wire [0:29] sb_8__1__2_chany_bottom_out; +wire [0:29] sb_8__1__2_chany_top_out; +wire [0:0] sb_8__1__3_ccff_tail; +wire [0:29] sb_8__1__3_chanx_left_out; +wire [0:29] sb_8__1__3_chany_bottom_out; +wire [0:29] sb_8__1__3_chany_top_out; +wire [0:0] sb_8__1__4_ccff_tail; +wire [0:29] sb_8__1__4_chanx_left_out; +wire [0:29] sb_8__1__4_chany_bottom_out; +wire [0:29] sb_8__1__4_chany_top_out; +wire [0:0] sb_8__1__5_ccff_tail; +wire [0:29] sb_8__1__5_chanx_left_out; +wire [0:29] sb_8__1__5_chany_bottom_out; +wire [0:29] sb_8__1__5_chany_top_out; +wire [0:0] sb_8__1__6_ccff_tail; +wire [0:29] sb_8__1__6_chanx_left_out; +wire [0:29] sb_8__1__6_chany_bottom_out; +wire [0:29] sb_8__1__6_chany_top_out; +wire [0:0] sb_8__8__0_ccff_tail; +wire [0:29] sb_8__8__0_chanx_left_out; +wire [0:29] sb_8__8__0_chany_bottom_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + grid_io_top_top grid_io_top_top_1__9_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:3]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__0_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_0_ccff_tail)); + + grid_io_top_top grid_io_top_top_2__9_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4:7]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4:7]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4:7]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__1_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_1_ccff_tail)); + + grid_io_top_top grid_io_top_top_3__9_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8:11]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8:11]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8:11]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__2_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_2_ccff_tail)); + + grid_io_top_top grid_io_top_top_4__9_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12:15]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12:15]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12:15]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__3_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_3_ccff_tail)); + + grid_io_top_top grid_io_top_top_5__9_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16:19]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16:19]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16:19]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__4_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_4_ccff_tail)); + + grid_io_top_top grid_io_top_top_6__9_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20:23]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20:23]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20:23]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__5_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_5_ccff_tail)); + + grid_io_top_top grid_io_top_top_7__9_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24:27]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24:27]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24:27]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__6_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_6_ccff_tail)); + + grid_io_top_top grid_io_top_top_8__9_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28:31]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28:31]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28:31]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__7_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_7_ccff_tail)); + + grid_io_right_right grid_io_right_right_9__8_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32:35]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32:35]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32:35]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_1_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_0_ccff_tail)); + + grid_io_right_right grid_io_right_right_9__7_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36:39]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36:39]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36:39]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_2_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_1_ccff_tail)); + + grid_io_right_right grid_io_right_right_9__6_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40:43]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40:43]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40:43]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_3_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_2_ccff_tail)); + + grid_io_right_right grid_io_right_right_9__5_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44:47]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44:47]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44:47]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_4_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_3_ccff_tail)); + + grid_io_right_right grid_io_right_right_9__4_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48:51]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48:51]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48:51]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_5_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_4_ccff_tail)); + + grid_io_right_right grid_io_right_right_9__3_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52:55]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52:55]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52:55]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_6_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_5_ccff_tail)); + + grid_io_right_right grid_io_right_right_9__2_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56:59]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56:59]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56:59]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_7_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_6_ccff_tail)); + + grid_io_right_right grid_io_right_right_9__1_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60:63]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60:63]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60:63]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_0_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_7_ccff_tail)); + + grid_io_bottom_bottom grid_io_bottom_bottom_8__0_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64:67]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64:67]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64:67]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_1_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_0_ccff_tail)); + + grid_io_bottom_bottom grid_io_bottom_bottom_7__0_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68:71]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68:71]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68:71]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_2_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_1_ccff_tail)); + + grid_io_bottom_bottom grid_io_bottom_bottom_6__0_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72:75]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72:75]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72:75]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_3_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_2_ccff_tail)); + + grid_io_bottom_bottom grid_io_bottom_bottom_5__0_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76:79]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76:79]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76:79]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_4_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_3_ccff_tail)); + + grid_io_bottom_bottom grid_io_bottom_bottom_4__0_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80:83]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80:83]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80:83]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_5_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_4_ccff_tail)); + + grid_io_bottom_bottom grid_io_bottom_bottom_3__0_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84:87]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84:87]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84:87]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_6_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_5_ccff_tail)); + + grid_io_bottom_bottom grid_io_bottom_bottom_2__0_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88:91]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88:91]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88:91]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_7_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_6_ccff_tail)); + + grid_io_bottom_bottom grid_io_bottom_bottom_1__0_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92:95]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92:95]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92:95]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(ccff_head), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_7_ccff_tail)); + + grid_io_left_left grid_io_left_left_0__1_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96:99]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96:99]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96:99]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__0_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_0_ccff_tail)); + + grid_io_left_left grid_io_left_left_0__2_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100:103]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100:103]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100:103]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__1_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_1_ccff_tail)); + + grid_io_left_left grid_io_left_left_0__3_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104:107]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104:107]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104:107]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__2_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_2_ccff_tail)); + + grid_io_left_left grid_io_left_left_0__4_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108:111]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108:111]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108:111]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__3_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_3_ccff_tail)); + + grid_io_left_left grid_io_left_left_0__5_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112:115]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112:115]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112:115]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__4_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_4_ccff_tail)); + + grid_io_left_left grid_io_left_left_0__6_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116:119]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116:119]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116:119]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__5_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_5_ccff_tail)); + + grid_io_left_left grid_io_left_left_0__7_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120:123]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120:123]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120:123]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__6_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_6_ccff_tail)); + + grid_io_left_left grid_io_left_left_0__8_ ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124:127]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124:127]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124:127]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__7_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_7_ccff_tail)); + + grid_clb grid_clb_1__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_56_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_112_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_0_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__0_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_0_ccff_tail)); + + grid_clb grid_clb_1__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_57_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_113_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_1_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__1_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_1_ccff_tail)); + + grid_clb grid_clb_1__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_58_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_114_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_2_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__2_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_2_ccff_tail)); + + grid_clb grid_clb_1__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_59_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_115_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_3_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__3_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_3_ccff_tail)); + + grid_clb grid_clb_1__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_60_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_116_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_4_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__4_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_4_ccff_tail)); + + grid_clb grid_clb_1__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_61_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_117_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_5_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__5_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_5_ccff_tail)); + + grid_clb grid_clb_1__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_62_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_118_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_6_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__6_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_6_ccff_tail)); + + grid_clb grid_clb_1__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_sc_in_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__7_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(ccff_tail)); + + grid_clb grid_clb_2__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_63_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_119_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_7_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__8_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_8_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_8_ccff_tail)); + + grid_clb grid_clb_2__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_64_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_120_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_8_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__9_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_9_ccff_tail)); + + grid_clb grid_clb_2__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_65_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_121_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_9_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__10_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_10_ccff_tail)); + + grid_clb grid_clb_2__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_66_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_122_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_10_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__11_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_11_ccff_tail)); + + grid_clb grid_clb_2__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_67_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_123_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_11_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__12_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_12_ccff_tail)); + + grid_clb grid_clb_2__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_68_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_124_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_12_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__13_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_13_ccff_tail)); + + grid_clb grid_clb_2__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_69_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_125_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_13_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__14_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_14_ccff_tail)); + + grid_clb grid_clb_2__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_168_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__15_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_15_ccff_tail)); + + grid_clb grid_clb_3__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_70_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_126_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_14_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__16_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_16_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_16_ccff_tail)); + + grid_clb grid_clb_3__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_71_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_127_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_15_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__17_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_17_ccff_tail)); + + grid_clb grid_clb_3__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_72_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_128_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_16_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__18_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_18_ccff_tail)); + + grid_clb grid_clb_3__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_73_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_129_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_17_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__19_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_19_ccff_tail)); + + grid_clb grid_clb_3__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_74_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_130_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_18_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__20_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_20_ccff_tail)); + + grid_clb grid_clb_3__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_75_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_131_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_19_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__21_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_21_ccff_tail)); + + grid_clb grid_clb_3__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_76_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_132_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_20_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__22_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_22_ccff_tail)); + + grid_clb grid_clb_3__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_169_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__23_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_23_ccff_tail)); + + grid_clb grid_clb_4__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_77_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_133_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_21_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__24_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_24_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_24_ccff_tail)); + + grid_clb grid_clb_4__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_78_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_134_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_22_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__25_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_25_ccff_tail)); + + grid_clb grid_clb_4__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_79_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_135_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_23_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__26_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_26_ccff_tail)); + + grid_clb grid_clb_4__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_80_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_136_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_24_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__27_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_27_ccff_tail)); + + grid_clb grid_clb_4__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_81_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_137_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_25_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__28_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_28_ccff_tail)); + + grid_clb grid_clb_4__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_82_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_138_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_26_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__29_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_29_ccff_tail)); + + grid_clb grid_clb_4__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_83_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_139_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_27_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__30_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_30_ccff_tail)); + + grid_clb grid_clb_4__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_170_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__31_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_31_ccff_tail)); + + grid_clb grid_clb_5__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_84_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_140_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_28_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__32_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_32_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_32_ccff_tail)); + + grid_clb grid_clb_5__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_85_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_141_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_29_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__33_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_33_ccff_tail)); + + grid_clb grid_clb_5__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_86_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_142_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_30_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__34_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_34_ccff_tail)); + + grid_clb grid_clb_5__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_87_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_143_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_31_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__35_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_35_ccff_tail)); + + grid_clb grid_clb_5__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_88_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_144_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_32_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__36_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_36_ccff_tail)); + + grid_clb grid_clb_5__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_89_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_145_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_33_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__37_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_37_ccff_tail)); + + grid_clb grid_clb_5__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_90_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_146_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_34_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__38_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_38_ccff_tail)); + + grid_clb grid_clb_5__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_171_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__39_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_39_ccff_tail)); + + grid_clb grid_clb_6__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_91_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_147_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_35_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__40_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_40_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_40_ccff_tail)); + + grid_clb grid_clb_6__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_92_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_148_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_36_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__41_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_41_ccff_tail)); + + grid_clb grid_clb_6__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_93_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_149_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_37_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__42_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_42_ccff_tail)); + + grid_clb grid_clb_6__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_94_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_150_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_38_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__43_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_43_ccff_tail)); + + grid_clb grid_clb_6__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_95_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_151_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_39_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__44_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_44_ccff_tail)); + + grid_clb grid_clb_6__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_96_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_152_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_40_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__45_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_45_ccff_tail)); + + grid_clb grid_clb_6__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_97_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_153_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_41_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__46_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_46_ccff_tail)); + + grid_clb grid_clb_6__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_172_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__47_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_47_ccff_tail)); + + grid_clb grid_clb_7__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_98_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_154_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_42_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__48_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_48_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_48_ccff_tail)); + + grid_clb grid_clb_7__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_99_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_155_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_43_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__49_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_49_ccff_tail)); + + grid_clb grid_clb_7__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_100_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_156_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_44_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__50_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_50_ccff_tail)); + + grid_clb grid_clb_7__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_101_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_157_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_45_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__51_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_51_ccff_tail)); + + grid_clb grid_clb_7__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_102_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_158_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_46_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__52_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_52_ccff_tail)); + + grid_clb grid_clb_7__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_103_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_159_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_47_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__53_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_53_ccff_tail)); + + grid_clb grid_clb_7__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_104_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_160_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_48_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__54_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_54_ccff_tail)); + + grid_clb grid_clb_7__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_173_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__55_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_55_ccff_tail)); + + grid_clb grid_clb_8__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_105_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_161_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_49_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__0_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_56_ccff_tail)); + + grid_clb grid_clb_8__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_106_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_162_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_50_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__1_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_57_ccff_tail)); + + grid_clb grid_clb_8__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_107_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_163_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_51_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__2_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_58_ccff_tail)); + + grid_clb grid_clb_8__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_108_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_164_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_52_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__3_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_59_ccff_tail)); + + grid_clb grid_clb_8__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_109_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_165_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_53_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__4_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_60_ccff_tail)); + + grid_clb grid_clb_8__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_110_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_166_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_54_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__5_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_61_ccff_tail)); + + grid_clb grid_clb_8__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_111_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_167_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_55_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__6_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_62_ccff_tail)); + + grid_clb grid_clb_8__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_174_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__7_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_63_ccff_tail)); + + sb_0__0_ sb_0__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__0_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__0__0_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_1_ccff_tail), + .chany_top_out(sb_0__0__0_chany_top_out[0:29]), + .chanx_right_out(sb_0__0__0_chanx_right_out[0:29]), + .ccff_tail(sb_0__0__0_ccff_tail)); + + sb_0__1_ sb_0__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__1_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__0_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__0_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_2_ccff_tail), + .chany_top_out(sb_0__1__0_chany_top_out[0:29]), + .chanx_right_out(sb_0__1__0_chanx_right_out[0:29]), + .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:29]), + .ccff_tail(sb_0__1__0_ccff_tail)); + + sb_0__1_ sb_0__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__2_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__1_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__1_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_3_ccff_tail), + .chany_top_out(sb_0__1__1_chany_top_out[0:29]), + .chanx_right_out(sb_0__1__1_chanx_right_out[0:29]), + .chany_bottom_out(sb_0__1__1_chany_bottom_out[0:29]), + .ccff_tail(sb_0__1__1_ccff_tail)); + + sb_0__1_ sb_0__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__3_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__2_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__2_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_4_ccff_tail), + .chany_top_out(sb_0__1__2_chany_top_out[0:29]), + .chanx_right_out(sb_0__1__2_chanx_right_out[0:29]), + .chany_bottom_out(sb_0__1__2_chany_bottom_out[0:29]), + .ccff_tail(sb_0__1__2_ccff_tail)); + + sb_0__1_ sb_0__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__4_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__3_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__3_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_5_ccff_tail), + .chany_top_out(sb_0__1__3_chany_top_out[0:29]), + .chanx_right_out(sb_0__1__3_chanx_right_out[0:29]), + .chany_bottom_out(sb_0__1__3_chany_bottom_out[0:29]), + .ccff_tail(sb_0__1__3_ccff_tail)); + + sb_0__1_ sb_0__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__5_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__4_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__4_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_6_ccff_tail), + .chany_top_out(sb_0__1__4_chany_top_out[0:29]), + .chanx_right_out(sb_0__1__4_chanx_right_out[0:29]), + .chany_bottom_out(sb_0__1__4_chany_bottom_out[0:29]), + .ccff_tail(sb_0__1__4_ccff_tail)); + + sb_0__1_ sb_0__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__6_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__5_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__5_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_7_ccff_tail), + .chany_top_out(sb_0__1__5_chany_top_out[0:29]), + .chanx_right_out(sb_0__1__5_chanx_right_out[0:29]), + .chany_bottom_out(sb_0__1__5_chany_bottom_out[0:29]), + .ccff_tail(sb_0__1__5_ccff_tail)); + + sb_0__1_ sb_0__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__7_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__6_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__6_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(sb_0__8__0_ccff_tail), + .chany_top_out(sb_0__1__6_chany_top_out[0:29]), + .chanx_right_out(sb_0__1__6_chanx_right_out[0:29]), + .chany_bottom_out(sb_0__1__6_chany_bottom_out[0:29]), + .ccff_tail(sb_0__1__6_ccff_tail)); + + sb_0__8_ sb_0__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__0_chanx_left_out[0:29]), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__7_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_top_top_0_ccff_tail), + .chanx_right_out(sb_0__8__0_chanx_right_out[0:29]), + .chany_bottom_out(sb_0__8__0_chany_bottom_out[0:29]), + .ccff_tail(sb_0__8__0_ccff_tail)); + + sb_1__0_ sb_1__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__0_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__1_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__0_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_0_ccff_tail), + .chany_top_out(sb_1__0__0_chany_top_out[0:29]), + .chanx_right_out(sb_1__0__0_chanx_right_out[0:29]), + .chanx_left_out(sb_1__0__0_chanx_left_out[0:29]), + .ccff_tail(sb_1__0__0_ccff_tail)); + + sb_1__0_ sb_2__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__8_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__2_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__1_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_0_ccff_tail), + .chany_top_out(sb_1__0__1_chany_top_out[0:29]), + .chanx_right_out(sb_1__0__1_chanx_right_out[0:29]), + .chanx_left_out(sb_1__0__1_chanx_left_out[0:29]), + .ccff_tail(sb_1__0__1_ccff_tail)); + + sb_1__0_ sb_3__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__16_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__3_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__2_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_8_ccff_tail), + .chany_top_out(sb_1__0__2_chany_top_out[0:29]), + .chanx_right_out(sb_1__0__2_chanx_right_out[0:29]), + .chanx_left_out(sb_1__0__2_chanx_left_out[0:29]), + .ccff_tail(sb_1__0__2_ccff_tail)); + + sb_1__0_ sb_4__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__24_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__4_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__3_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_16_ccff_tail), + .chany_top_out(sb_1__0__3_chany_top_out[0:29]), + .chanx_right_out(sb_1__0__3_chanx_right_out[0:29]), + .chanx_left_out(sb_1__0__3_chanx_left_out[0:29]), + .ccff_tail(sb_1__0__3_ccff_tail)); + + sb_1__0_ sb_5__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__32_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__5_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__4_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_24_ccff_tail), + .chany_top_out(sb_1__0__4_chany_top_out[0:29]), + .chanx_right_out(sb_1__0__4_chanx_right_out[0:29]), + .chanx_left_out(sb_1__0__4_chanx_left_out[0:29]), + .ccff_tail(sb_1__0__4_ccff_tail)); + + sb_1__0_ sb_6__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__40_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__6_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__5_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_32_ccff_tail), + .chany_top_out(sb_1__0__5_chany_top_out[0:29]), + .chanx_right_out(sb_1__0__5_chanx_right_out[0:29]), + .chanx_left_out(sb_1__0__5_chanx_left_out[0:29]), + .ccff_tail(sb_1__0__5_ccff_tail)); + + sb_1__0_ sb_7__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__48_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__7_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__6_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_40_ccff_tail), + .chany_top_out(sb_1__0__6_chany_top_out[0:29]), + .chanx_right_out(sb_1__0__6_chanx_right_out[0:29]), + .chanx_left_out(sb_1__0__6_chanx_left_out[0:29]), + .ccff_tail(sb_1__0__6_ccff_tail)); + + sb_1__1_ sb_1__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__1_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__7_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__0_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__0_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_9_ccff_tail), + .chany_top_out(sb_1__1__0_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__0_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__0_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__0_ccff_tail)); + + sb_1__1_ sb_1__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__2_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__8_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__1_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__1_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_1_ccff_tail), + .chany_top_out(sb_1__1__1_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__1_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__1_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__1_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__1_ccff_tail)); + + sb_1__1_ sb_1__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__3_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__9_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__2_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__2_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_11_ccff_tail), + .chany_top_out(sb_1__1__2_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__2_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__2_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__2_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__2_ccff_tail)); + + sb_1__1_ sb_1__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__4_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__10_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__3_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__3_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_3_ccff_tail), + .chany_top_out(sb_1__1__3_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__3_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__3_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__3_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__3_ccff_tail)); + + sb_1__1_ sb_1__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__5_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__11_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__4_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__4_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_13_ccff_tail), + .chany_top_out(sb_1__1__4_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__4_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__4_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__4_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__4_ccff_tail)); + + sb_1__1_ sb_1__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__6_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__12_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__5_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__5_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_5_ccff_tail), + .chany_top_out(sb_1__1__5_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__5_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__5_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__5_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__5_ccff_tail)); + + sb_1__1_ sb_1__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__7_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__13_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__6_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__6_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_15_ccff_tail), + .chany_top_out(sb_1__1__6_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__6_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__6_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__6_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__6_ccff_tail)); + + sb_1__1_ sb_2__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__9_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__14_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__8_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__7_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_17_ccff_tail), + .chany_top_out(sb_1__1__7_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__7_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__7_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__7_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__7_ccff_tail)); + + sb_1__1_ sb_2__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__10_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__15_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__9_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__8_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_2_ccff_tail), + .chany_top_out(sb_1__1__8_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__8_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__8_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__8_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__8_ccff_tail)); + + sb_1__1_ sb_2__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__11_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__16_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__10_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__9_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_19_ccff_tail), + .chany_top_out(sb_1__1__9_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__9_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__9_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__9_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__9_ccff_tail)); + + sb_1__1_ sb_2__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__12_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__17_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__11_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__10_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_4_ccff_tail), + .chany_top_out(sb_1__1__10_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__10_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__10_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__10_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__10_ccff_tail)); + + sb_1__1_ sb_2__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__13_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__18_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__12_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__11_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_21_ccff_tail), + .chany_top_out(sb_1__1__11_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__11_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__11_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__11_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__11_ccff_tail)); + + sb_1__1_ sb_2__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__14_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__19_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__13_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__12_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_6_ccff_tail), + .chany_top_out(sb_1__1__12_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__12_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__12_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__12_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__12_ccff_tail)); + + sb_1__1_ sb_2__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__15_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__20_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__14_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__13_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_23_ccff_tail), + .chany_top_out(sb_1__1__13_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__13_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__13_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__13_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__13_ccff_tail)); + + sb_1__1_ sb_3__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__17_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__21_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__16_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__14_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_25_ccff_tail), + .chany_top_out(sb_1__1__14_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__14_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__14_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__14_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__14_ccff_tail)); + + sb_1__1_ sb_3__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__18_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__22_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__17_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__15_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_10_ccff_tail), + .chany_top_out(sb_1__1__15_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__15_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__15_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__15_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__15_ccff_tail)); + + sb_1__1_ sb_3__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__19_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__23_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__18_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__16_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_27_ccff_tail), + .chany_top_out(sb_1__1__16_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__16_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__16_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__16_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__16_ccff_tail)); + + sb_1__1_ sb_3__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__20_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__24_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__19_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__17_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_12_ccff_tail), + .chany_top_out(sb_1__1__17_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__17_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__17_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__17_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__17_ccff_tail)); + + sb_1__1_ sb_3__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__21_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__25_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__20_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__18_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_29_ccff_tail), + .chany_top_out(sb_1__1__18_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__18_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__18_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__18_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__18_ccff_tail)); + + sb_1__1_ sb_3__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__22_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__26_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__21_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__19_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_14_ccff_tail), + .chany_top_out(sb_1__1__19_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__19_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__19_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__19_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__19_ccff_tail)); + + sb_1__1_ sb_3__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__23_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__27_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__22_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__20_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_31_ccff_tail), + .chany_top_out(sb_1__1__20_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__20_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__20_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__20_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__20_ccff_tail)); + + sb_1__1_ sb_4__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__25_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__28_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__24_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__21_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_33_ccff_tail), + .chany_top_out(sb_1__1__21_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__21_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__21_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__21_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__21_ccff_tail)); + + sb_1__1_ sb_4__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__26_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__29_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__25_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__22_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_18_ccff_tail), + .chany_top_out(sb_1__1__22_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__22_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__22_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__22_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__22_ccff_tail)); + + sb_1__1_ sb_4__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__27_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__30_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__26_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__23_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_35_ccff_tail), + .chany_top_out(sb_1__1__23_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__23_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__23_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__23_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__23_ccff_tail)); + + sb_1__1_ sb_4__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__28_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__31_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__27_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__24_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_20_ccff_tail), + .chany_top_out(sb_1__1__24_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__24_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__24_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__24_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__24_ccff_tail)); + + sb_1__1_ sb_4__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__29_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__32_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__28_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__25_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_37_ccff_tail), + .chany_top_out(sb_1__1__25_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__25_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__25_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__25_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__25_ccff_tail)); + + sb_1__1_ sb_4__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__30_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__33_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__29_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__26_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_22_ccff_tail), + .chany_top_out(sb_1__1__26_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__26_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__26_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__26_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__26_ccff_tail)); + + sb_1__1_ sb_4__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__31_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__34_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__30_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__27_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_39_ccff_tail), + .chany_top_out(sb_1__1__27_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__27_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__27_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__27_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__27_ccff_tail)); + + sb_1__1_ sb_5__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__33_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__35_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__32_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__28_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_41_ccff_tail), + .chany_top_out(sb_1__1__28_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__28_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__28_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__28_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__28_ccff_tail)); + + sb_1__1_ sb_5__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__34_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__36_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__33_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__29_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_26_ccff_tail), + .chany_top_out(sb_1__1__29_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__29_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__29_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__29_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__29_ccff_tail)); + + sb_1__1_ sb_5__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__35_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__37_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__34_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__30_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_43_ccff_tail), + .chany_top_out(sb_1__1__30_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__30_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__30_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__30_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__30_ccff_tail)); + + sb_1__1_ sb_5__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__36_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__38_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__35_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__31_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_28_ccff_tail), + .chany_top_out(sb_1__1__31_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__31_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__31_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__31_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__31_ccff_tail)); + + sb_1__1_ sb_5__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__37_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__39_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__36_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__32_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_45_ccff_tail), + .chany_top_out(sb_1__1__32_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__32_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__32_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__32_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__32_ccff_tail)); + + sb_1__1_ sb_5__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__38_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__40_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__37_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__33_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_30_ccff_tail), + .chany_top_out(sb_1__1__33_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__33_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__33_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__33_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__33_ccff_tail)); + + sb_1__1_ sb_5__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__39_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__41_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__38_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__34_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_47_ccff_tail), + .chany_top_out(sb_1__1__34_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__34_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__34_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__34_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__34_ccff_tail)); + + sb_1__1_ sb_6__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__41_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__42_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__40_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__35_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_49_ccff_tail), + .chany_top_out(sb_1__1__35_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__35_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__35_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__35_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__35_ccff_tail)); + + sb_1__1_ sb_6__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__42_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__43_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__41_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__36_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_34_ccff_tail), + .chany_top_out(sb_1__1__36_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__36_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__36_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__36_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__36_ccff_tail)); + + sb_1__1_ sb_6__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__43_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__44_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__42_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__37_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_51_ccff_tail), + .chany_top_out(sb_1__1__37_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__37_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__37_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__37_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__37_ccff_tail)); + + sb_1__1_ sb_6__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__44_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__45_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__43_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__38_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_36_ccff_tail), + .chany_top_out(sb_1__1__38_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__38_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__38_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__38_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__38_ccff_tail)); + + sb_1__1_ sb_6__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__45_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__46_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__44_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__39_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_53_ccff_tail), + .chany_top_out(sb_1__1__39_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__39_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__39_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__39_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__39_ccff_tail)); + + sb_1__1_ sb_6__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__46_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__47_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__45_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__40_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_38_ccff_tail), + .chany_top_out(sb_1__1__40_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__40_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__40_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__40_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__40_ccff_tail)); + + sb_1__1_ sb_6__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__47_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__48_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__46_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__41_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_55_ccff_tail), + .chany_top_out(sb_1__1__41_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__41_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__41_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__41_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__41_ccff_tail)); + + sb_1__1_ sb_7__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__49_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__49_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__48_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__42_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_57_ccff_tail), + .chany_top_out(sb_1__1__42_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__42_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__42_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__42_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__42_ccff_tail)); + + sb_1__1_ sb_7__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__50_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__50_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__49_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__43_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_42_ccff_tail), + .chany_top_out(sb_1__1__43_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__43_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__43_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__43_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__43_ccff_tail)); + + sb_1__1_ sb_7__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__51_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__51_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__50_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__44_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_59_ccff_tail), + .chany_top_out(sb_1__1__44_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__44_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__44_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__44_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__44_ccff_tail)); + + sb_1__1_ sb_7__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__52_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__52_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__51_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__45_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_44_ccff_tail), + .chany_top_out(sb_1__1__45_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__45_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__45_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__45_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__45_ccff_tail)); + + sb_1__1_ sb_7__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__53_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__53_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__52_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__46_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_61_ccff_tail), + .chany_top_out(sb_1__1__46_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__46_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__46_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__46_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__46_ccff_tail)); + + sb_1__1_ sb_7__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__54_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__54_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__53_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__47_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_46_ccff_tail), + .chany_top_out(sb_1__1__47_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__47_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__47_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__47_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__47_ccff_tail)); + + sb_1__1_ sb_7__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__55_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__55_chanx_left_out[0:29]), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__54_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__48_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_63_ccff_tail), + .chany_top_out(sb_1__1__48_chany_top_out[0:29]), + .chanx_right_out(sb_1__1__48_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__1__48_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__1__48_chanx_left_out[0:29]), + .ccff_tail(sb_1__1__48_ccff_tail)); + + sb_1__8_ sb_1__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__1_chanx_left_out[0:29]), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__7_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__0_chanx_right_out[0:29]), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_1_ccff_tail), + .chanx_right_out(sb_1__8__0_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__8__0_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__8__0_chanx_left_out[0:29]), + .ccff_tail(sb_1__8__0_ccff_tail)); + + sb_1__8_ sb_2__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__2_chanx_left_out[0:29]), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__15_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__1_chanx_right_out[0:29]), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_2_ccff_tail), + .chanx_right_out(sb_1__8__1_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__8__1_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__8__1_chanx_left_out[0:29]), + .ccff_tail(sb_1__8__1_ccff_tail)); + + sb_1__8_ sb_3__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__3_chanx_left_out[0:29]), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__23_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__2_chanx_right_out[0:29]), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_3_ccff_tail), + .chanx_right_out(sb_1__8__2_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__8__2_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__8__2_chanx_left_out[0:29]), + .ccff_tail(sb_1__8__2_ccff_tail)); + + sb_1__8_ sb_4__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__4_chanx_left_out[0:29]), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__31_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__3_chanx_right_out[0:29]), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_4_ccff_tail), + .chanx_right_out(sb_1__8__3_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__8__3_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__8__3_chanx_left_out[0:29]), + .ccff_tail(sb_1__8__3_ccff_tail)); + + sb_1__8_ sb_5__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__5_chanx_left_out[0:29]), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__39_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__4_chanx_right_out[0:29]), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_5_ccff_tail), + .chanx_right_out(sb_1__8__4_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__8__4_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__8__4_chanx_left_out[0:29]), + .ccff_tail(sb_1__8__4_ccff_tail)); + + sb_1__8_ sb_6__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__6_chanx_left_out[0:29]), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__47_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__5_chanx_right_out[0:29]), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_6_ccff_tail), + .chanx_right_out(sb_1__8__5_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__8__5_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__8__5_chanx_left_out[0:29]), + .ccff_tail(sb_1__8__5_ccff_tail)); + + sb_1__8_ sb_7__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__7_chanx_left_out[0:29]), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__55_chany_top_out[0:29]), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__6_chanx_right_out[0:29]), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_7_ccff_tail), + .chanx_right_out(sb_1__8__6_chanx_right_out[0:29]), + .chany_bottom_out(sb_1__8__6_chany_bottom_out[0:29]), + .chanx_left_out(sb_1__8__6_chanx_left_out[0:29]), + .ccff_tail(sb_1__8__6_ccff_tail)); + + sb_8__0_ sb_8__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__0_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__7_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_48_ccff_tail), + .chany_top_out(sb_8__0__0_chany_top_out[0:29]), + .chanx_left_out(sb_8__0__0_chanx_left_out[0:29]), + .ccff_tail(sb_8__0__0_ccff_tail)); + + sb_8__1_ sb_8__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__1_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__0_chany_top_out[0:29]), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__49_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_56_ccff_tail), + .chany_top_out(sb_8__1__0_chany_top_out[0:29]), + .chany_bottom_out(sb_8__1__0_chany_bottom_out[0:29]), + .chanx_left_out(sb_8__1__0_chanx_left_out[0:29]), + .ccff_tail(sb_8__1__0_ccff_tail)); + + sb_8__1_ sb_8__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__2_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__1_chany_top_out[0:29]), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__50_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_50_ccff_tail), + .chany_top_out(sb_8__1__1_chany_top_out[0:29]), + .chany_bottom_out(sb_8__1__1_chany_bottom_out[0:29]), + .chanx_left_out(sb_8__1__1_chanx_left_out[0:29]), + .ccff_tail(sb_8__1__1_ccff_tail)); + + sb_8__1_ sb_8__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__3_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__2_chany_top_out[0:29]), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__51_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_58_ccff_tail), + .chany_top_out(sb_8__1__2_chany_top_out[0:29]), + .chany_bottom_out(sb_8__1__2_chany_bottom_out[0:29]), + .chanx_left_out(sb_8__1__2_chanx_left_out[0:29]), + .ccff_tail(sb_8__1__2_ccff_tail)); + + sb_8__1_ sb_8__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__4_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__3_chany_top_out[0:29]), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__52_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_52_ccff_tail), + .chany_top_out(sb_8__1__3_chany_top_out[0:29]), + .chany_bottom_out(sb_8__1__3_chany_bottom_out[0:29]), + .chanx_left_out(sb_8__1__3_chanx_left_out[0:29]), + .ccff_tail(sb_8__1__3_ccff_tail)); + + sb_8__1_ sb_8__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__5_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__4_chany_top_out[0:29]), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__53_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_60_ccff_tail), + .chany_top_out(sb_8__1__4_chany_top_out[0:29]), + .chany_bottom_out(sb_8__1__4_chany_bottom_out[0:29]), + .chanx_left_out(sb_8__1__4_chanx_left_out[0:29]), + .ccff_tail(sb_8__1__4_ccff_tail)); + + sb_8__1_ sb_8__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__6_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__5_chany_top_out[0:29]), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__54_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_54_ccff_tail), + .chany_top_out(sb_8__1__5_chany_top_out[0:29]), + .chany_bottom_out(sb_8__1__5_chany_bottom_out[0:29]), + .chanx_left_out(sb_8__1__5_chanx_left_out[0:29]), + .ccff_tail(sb_8__1__5_ccff_tail)); + + sb_8__1_ sb_8__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__7_chany_bottom_out[0:29]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__6_chany_top_out[0:29]), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__55_chanx_right_out[0:29]), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_62_ccff_tail), + .chany_top_out(sb_8__1__6_chany_top_out[0:29]), + .chany_bottom_out(sb_8__1__6_chany_bottom_out[0:29]), + .chanx_left_out(sb_8__1__6_chanx_left_out[0:29]), + .ccff_tail(sb_8__1__6_ccff_tail)); + + sb_8__8_ sb_8__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(cby_8__1__7_chany_top_out[0:29]), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__7_chanx_right_out[0:29]), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_right_right_0_ccff_tail), + .chany_bottom_out(sb_8__8__0_chany_bottom_out[0:29]), + .chanx_left_out(sb_8__8__0_chanx_left_out[0:29]), + .ccff_tail(sb_8__8__0_ccff_tail)); + + cbx_1__0_ cbx_1__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__0__0_chanx_right_out[0:29]), + .chanx_right_in(sb_1__0__0_chanx_left_out[0:29]), + .ccff_head(sb_1__0__0_ccff_tail), + .chanx_left_out(cbx_1__0__0_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__0__0_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__0_ccff_tail)); + + cbx_1__0_ cbx_2__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__0_chanx_right_out[0:29]), + .chanx_right_in(sb_1__0__1_chanx_left_out[0:29]), + .ccff_head(sb_1__0__1_ccff_tail), + .chanx_left_out(cbx_1__0__1_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__0__1_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__1_ccff_tail)); + + cbx_1__0_ cbx_3__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__1_chanx_right_out[0:29]), + .chanx_right_in(sb_1__0__2_chanx_left_out[0:29]), + .ccff_head(sb_1__0__2_ccff_tail), + .chanx_left_out(cbx_1__0__2_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__0__2_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__2_ccff_tail)); + + cbx_1__0_ cbx_4__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__2_chanx_right_out[0:29]), + .chanx_right_in(sb_1__0__3_chanx_left_out[0:29]), + .ccff_head(sb_1__0__3_ccff_tail), + .chanx_left_out(cbx_1__0__3_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__0__3_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__3_ccff_tail)); + + cbx_1__0_ cbx_5__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__3_chanx_right_out[0:29]), + .chanx_right_in(sb_1__0__4_chanx_left_out[0:29]), + .ccff_head(sb_1__0__4_ccff_tail), + .chanx_left_out(cbx_1__0__4_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__0__4_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__4_ccff_tail)); + + cbx_1__0_ cbx_6__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__4_chanx_right_out[0:29]), + .chanx_right_in(sb_1__0__5_chanx_left_out[0:29]), + .ccff_head(sb_1__0__5_ccff_tail), + .chanx_left_out(cbx_1__0__5_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__0__5_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__5_ccff_tail)); + + cbx_1__0_ cbx_7__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__5_chanx_right_out[0:29]), + .chanx_right_in(sb_1__0__6_chanx_left_out[0:29]), + .ccff_head(sb_1__0__6_ccff_tail), + .chanx_left_out(cbx_1__0__6_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__0__6_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__6_ccff_tail)); + + cbx_1__0_ cbx_8__0_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__6_chanx_right_out[0:29]), + .chanx_right_in(sb_8__0__0_chanx_left_out[0:29]), + .ccff_head(sb_8__0__0_ccff_tail), + .chanx_left_out(cbx_1__0__7_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__0__7_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__7_ccff_tail)); + + cbx_1__1_ cbx_1__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__0_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__0_chanx_left_out[0:29]), + .ccff_head(sb_1__1__0_ccff_tail), + .chanx_left_out(cbx_1__1__0_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__0_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__0_ccff_tail)); + + cbx_1__1_ cbx_1__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__1_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__1_chanx_left_out[0:29]), + .ccff_head(sb_1__1__1_ccff_tail), + .chanx_left_out(cbx_1__1__1_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__1_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__1_ccff_tail)); + + cbx_1__1_ cbx_1__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__2_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__2_chanx_left_out[0:29]), + .ccff_head(sb_1__1__2_ccff_tail), + .chanx_left_out(cbx_1__1__2_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__2_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__2_ccff_tail)); + + cbx_1__1_ cbx_1__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__3_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__3_chanx_left_out[0:29]), + .ccff_head(sb_1__1__3_ccff_tail), + .chanx_left_out(cbx_1__1__3_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__3_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__3_ccff_tail)); + + cbx_1__1_ cbx_1__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__4_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__4_chanx_left_out[0:29]), + .ccff_head(sb_1__1__4_ccff_tail), + .chanx_left_out(cbx_1__1__4_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__4_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__4_ccff_tail)); + + cbx_1__1_ cbx_1__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__5_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__5_chanx_left_out[0:29]), + .ccff_head(sb_1__1__5_ccff_tail), + .chanx_left_out(cbx_1__1__5_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__5_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__5_ccff_tail)); + + cbx_1__1_ cbx_1__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__6_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__6_chanx_left_out[0:29]), + .ccff_head(sb_1__1__6_ccff_tail), + .chanx_left_out(cbx_1__1__6_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__6_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__6_ccff_tail)); + + cbx_1__1_ cbx_2__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__0_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__7_chanx_left_out[0:29]), + .ccff_head(sb_1__1__7_ccff_tail), + .chanx_left_out(cbx_1__1__7_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__7_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__7_ccff_tail)); + + cbx_1__1_ cbx_2__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__1_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__8_chanx_left_out[0:29]), + .ccff_head(sb_1__1__8_ccff_tail), + .chanx_left_out(cbx_1__1__8_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__8_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__8_ccff_tail)); + + cbx_1__1_ cbx_2__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__2_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__9_chanx_left_out[0:29]), + .ccff_head(sb_1__1__9_ccff_tail), + .chanx_left_out(cbx_1__1__9_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__9_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__9_ccff_tail)); + + cbx_1__1_ cbx_2__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__3_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__10_chanx_left_out[0:29]), + .ccff_head(sb_1__1__10_ccff_tail), + .chanx_left_out(cbx_1__1__10_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__10_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__10_ccff_tail)); + + cbx_1__1_ cbx_2__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__4_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__11_chanx_left_out[0:29]), + .ccff_head(sb_1__1__11_ccff_tail), + .chanx_left_out(cbx_1__1__11_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__11_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__11_ccff_tail)); + + cbx_1__1_ cbx_2__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__5_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__12_chanx_left_out[0:29]), + .ccff_head(sb_1__1__12_ccff_tail), + .chanx_left_out(cbx_1__1__12_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__12_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__12_ccff_tail)); + + cbx_1__1_ cbx_2__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__6_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__13_chanx_left_out[0:29]), + .ccff_head(sb_1__1__13_ccff_tail), + .chanx_left_out(cbx_1__1__13_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__13_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__13_ccff_tail)); + + cbx_1__1_ cbx_3__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__7_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__14_chanx_left_out[0:29]), + .ccff_head(sb_1__1__14_ccff_tail), + .chanx_left_out(cbx_1__1__14_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__14_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__14_ccff_tail)); + + cbx_1__1_ cbx_3__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__8_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__15_chanx_left_out[0:29]), + .ccff_head(sb_1__1__15_ccff_tail), + .chanx_left_out(cbx_1__1__15_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__15_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__15_ccff_tail)); + + cbx_1__1_ cbx_3__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__9_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__16_chanx_left_out[0:29]), + .ccff_head(sb_1__1__16_ccff_tail), + .chanx_left_out(cbx_1__1__16_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__16_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__16_ccff_tail)); + + cbx_1__1_ cbx_3__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__10_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__17_chanx_left_out[0:29]), + .ccff_head(sb_1__1__17_ccff_tail), + .chanx_left_out(cbx_1__1__17_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__17_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__17_ccff_tail)); + + cbx_1__1_ cbx_3__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__11_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__18_chanx_left_out[0:29]), + .ccff_head(sb_1__1__18_ccff_tail), + .chanx_left_out(cbx_1__1__18_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__18_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__18_ccff_tail)); + + cbx_1__1_ cbx_3__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__12_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__19_chanx_left_out[0:29]), + .ccff_head(sb_1__1__19_ccff_tail), + .chanx_left_out(cbx_1__1__19_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__19_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__19_ccff_tail)); + + cbx_1__1_ cbx_3__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__13_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__20_chanx_left_out[0:29]), + .ccff_head(sb_1__1__20_ccff_tail), + .chanx_left_out(cbx_1__1__20_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__20_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__20_ccff_tail)); + + cbx_1__1_ cbx_4__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__14_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__21_chanx_left_out[0:29]), + .ccff_head(sb_1__1__21_ccff_tail), + .chanx_left_out(cbx_1__1__21_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__21_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__21_ccff_tail)); + + cbx_1__1_ cbx_4__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__15_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__22_chanx_left_out[0:29]), + .ccff_head(sb_1__1__22_ccff_tail), + .chanx_left_out(cbx_1__1__22_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__22_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__22_ccff_tail)); + + cbx_1__1_ cbx_4__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__16_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__23_chanx_left_out[0:29]), + .ccff_head(sb_1__1__23_ccff_tail), + .chanx_left_out(cbx_1__1__23_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__23_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__23_ccff_tail)); + + cbx_1__1_ cbx_4__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__17_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__24_chanx_left_out[0:29]), + .ccff_head(sb_1__1__24_ccff_tail), + .chanx_left_out(cbx_1__1__24_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__24_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__24_ccff_tail)); + + cbx_1__1_ cbx_4__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__18_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__25_chanx_left_out[0:29]), + .ccff_head(sb_1__1__25_ccff_tail), + .chanx_left_out(cbx_1__1__25_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__25_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__25_ccff_tail)); + + cbx_1__1_ cbx_4__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__19_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__26_chanx_left_out[0:29]), + .ccff_head(sb_1__1__26_ccff_tail), + .chanx_left_out(cbx_1__1__26_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__26_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__26_ccff_tail)); + + cbx_1__1_ cbx_4__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__20_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__27_chanx_left_out[0:29]), + .ccff_head(sb_1__1__27_ccff_tail), + .chanx_left_out(cbx_1__1__27_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__27_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__27_ccff_tail)); + + cbx_1__1_ cbx_5__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__21_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__28_chanx_left_out[0:29]), + .ccff_head(sb_1__1__28_ccff_tail), + .chanx_left_out(cbx_1__1__28_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__28_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__28_ccff_tail)); + + cbx_1__1_ cbx_5__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__22_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__29_chanx_left_out[0:29]), + .ccff_head(sb_1__1__29_ccff_tail), + .chanx_left_out(cbx_1__1__29_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__29_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__29_ccff_tail)); + + cbx_1__1_ cbx_5__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__23_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__30_chanx_left_out[0:29]), + .ccff_head(sb_1__1__30_ccff_tail), + .chanx_left_out(cbx_1__1__30_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__30_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__30_ccff_tail)); + + cbx_1__1_ cbx_5__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__24_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__31_chanx_left_out[0:29]), + .ccff_head(sb_1__1__31_ccff_tail), + .chanx_left_out(cbx_1__1__31_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__31_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__31_ccff_tail)); + + cbx_1__1_ cbx_5__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__25_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__32_chanx_left_out[0:29]), + .ccff_head(sb_1__1__32_ccff_tail), + .chanx_left_out(cbx_1__1__32_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__32_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__32_ccff_tail)); + + cbx_1__1_ cbx_5__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__26_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__33_chanx_left_out[0:29]), + .ccff_head(sb_1__1__33_ccff_tail), + .chanx_left_out(cbx_1__1__33_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__33_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__33_ccff_tail)); + + cbx_1__1_ cbx_5__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__27_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__34_chanx_left_out[0:29]), + .ccff_head(sb_1__1__34_ccff_tail), + .chanx_left_out(cbx_1__1__34_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__34_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__34_ccff_tail)); + + cbx_1__1_ cbx_6__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__28_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__35_chanx_left_out[0:29]), + .ccff_head(sb_1__1__35_ccff_tail), + .chanx_left_out(cbx_1__1__35_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__35_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__35_ccff_tail)); + + cbx_1__1_ cbx_6__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__29_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__36_chanx_left_out[0:29]), + .ccff_head(sb_1__1__36_ccff_tail), + .chanx_left_out(cbx_1__1__36_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__36_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__36_ccff_tail)); + + cbx_1__1_ cbx_6__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__30_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__37_chanx_left_out[0:29]), + .ccff_head(sb_1__1__37_ccff_tail), + .chanx_left_out(cbx_1__1__37_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__37_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__37_ccff_tail)); + + cbx_1__1_ cbx_6__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__31_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__38_chanx_left_out[0:29]), + .ccff_head(sb_1__1__38_ccff_tail), + .chanx_left_out(cbx_1__1__38_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__38_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__38_ccff_tail)); + + cbx_1__1_ cbx_6__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__32_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__39_chanx_left_out[0:29]), + .ccff_head(sb_1__1__39_ccff_tail), + .chanx_left_out(cbx_1__1__39_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__39_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__39_ccff_tail)); + + cbx_1__1_ cbx_6__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__33_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__40_chanx_left_out[0:29]), + .ccff_head(sb_1__1__40_ccff_tail), + .chanx_left_out(cbx_1__1__40_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__40_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__40_ccff_tail)); + + cbx_1__1_ cbx_6__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__34_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__41_chanx_left_out[0:29]), + .ccff_head(sb_1__1__41_ccff_tail), + .chanx_left_out(cbx_1__1__41_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__41_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__41_ccff_tail)); + + cbx_1__1_ cbx_7__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__35_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__42_chanx_left_out[0:29]), + .ccff_head(sb_1__1__42_ccff_tail), + .chanx_left_out(cbx_1__1__42_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__42_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__42_ccff_tail)); + + cbx_1__1_ cbx_7__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__36_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__43_chanx_left_out[0:29]), + .ccff_head(sb_1__1__43_ccff_tail), + .chanx_left_out(cbx_1__1__43_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__43_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__43_ccff_tail)); + + cbx_1__1_ cbx_7__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__37_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__44_chanx_left_out[0:29]), + .ccff_head(sb_1__1__44_ccff_tail), + .chanx_left_out(cbx_1__1__44_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__44_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__44_ccff_tail)); + + cbx_1__1_ cbx_7__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__38_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__45_chanx_left_out[0:29]), + .ccff_head(sb_1__1__45_ccff_tail), + .chanx_left_out(cbx_1__1__45_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__45_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__45_ccff_tail)); + + cbx_1__1_ cbx_7__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__39_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__46_chanx_left_out[0:29]), + .ccff_head(sb_1__1__46_ccff_tail), + .chanx_left_out(cbx_1__1__46_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__46_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__46_ccff_tail)); + + cbx_1__1_ cbx_7__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__40_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__47_chanx_left_out[0:29]), + .ccff_head(sb_1__1__47_ccff_tail), + .chanx_left_out(cbx_1__1__47_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__47_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__47_ccff_tail)); + + cbx_1__1_ cbx_7__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__41_chanx_right_out[0:29]), + .chanx_right_in(sb_1__1__48_chanx_left_out[0:29]), + .ccff_head(sb_1__1__48_ccff_tail), + .chanx_left_out(cbx_1__1__48_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__48_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__48_ccff_tail)); + + cbx_1__1_ cbx_8__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__42_chanx_right_out[0:29]), + .chanx_right_in(sb_8__1__0_chanx_left_out[0:29]), + .ccff_head(sb_8__1__0_ccff_tail), + .chanx_left_out(cbx_1__1__49_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__49_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__49_ccff_tail)); + + cbx_1__1_ cbx_8__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__43_chanx_right_out[0:29]), + .chanx_right_in(sb_8__1__1_chanx_left_out[0:29]), + .ccff_head(sb_8__1__1_ccff_tail), + .chanx_left_out(cbx_1__1__50_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__50_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__50_ccff_tail)); + + cbx_1__1_ cbx_8__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__44_chanx_right_out[0:29]), + .chanx_right_in(sb_8__1__2_chanx_left_out[0:29]), + .ccff_head(sb_8__1__2_ccff_tail), + .chanx_left_out(cbx_1__1__51_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__51_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__51_ccff_tail)); + + cbx_1__1_ cbx_8__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__45_chanx_right_out[0:29]), + .chanx_right_in(sb_8__1__3_chanx_left_out[0:29]), + .ccff_head(sb_8__1__3_ccff_tail), + .chanx_left_out(cbx_1__1__52_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__52_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__52_ccff_tail)); + + cbx_1__1_ cbx_8__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__46_chanx_right_out[0:29]), + .chanx_right_in(sb_8__1__4_chanx_left_out[0:29]), + .ccff_head(sb_8__1__4_ccff_tail), + .chanx_left_out(cbx_1__1__53_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__53_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__53_ccff_tail)); + + cbx_1__1_ cbx_8__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__47_chanx_right_out[0:29]), + .chanx_right_in(sb_8__1__5_chanx_left_out[0:29]), + .ccff_head(sb_8__1__5_ccff_tail), + .chanx_left_out(cbx_1__1__54_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__54_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__54_ccff_tail)); + + cbx_1__1_ cbx_8__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__48_chanx_right_out[0:29]), + .chanx_right_in(sb_8__1__6_chanx_left_out[0:29]), + .ccff_head(sb_8__1__6_ccff_tail), + .chanx_left_out(cbx_1__1__55_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__1__55_chanx_right_out[0:29]), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__55_ccff_tail)); + + cbx_1__8_ cbx_1__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__8__0_chanx_right_out[0:29]), + .chanx_right_in(sb_1__8__0_chanx_left_out[0:29]), + .ccff_head(sb_1__8__0_ccff_tail), + .chanx_left_out(cbx_1__8__0_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__8__0_chanx_right_out[0:29]), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__0_ccff_tail)); + + cbx_1__8_ cbx_2__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__0_chanx_right_out[0:29]), + .chanx_right_in(sb_1__8__1_chanx_left_out[0:29]), + .ccff_head(sb_1__8__1_ccff_tail), + .chanx_left_out(cbx_1__8__1_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__8__1_chanx_right_out[0:29]), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__1_ccff_tail)); + + cbx_1__8_ cbx_3__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__1_chanx_right_out[0:29]), + .chanx_right_in(sb_1__8__2_chanx_left_out[0:29]), + .ccff_head(sb_1__8__2_ccff_tail), + .chanx_left_out(cbx_1__8__2_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__8__2_chanx_right_out[0:29]), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__2_ccff_tail)); + + cbx_1__8_ cbx_4__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__2_chanx_right_out[0:29]), + .chanx_right_in(sb_1__8__3_chanx_left_out[0:29]), + .ccff_head(sb_1__8__3_ccff_tail), + .chanx_left_out(cbx_1__8__3_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__8__3_chanx_right_out[0:29]), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__3_ccff_tail)); + + cbx_1__8_ cbx_5__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__3_chanx_right_out[0:29]), + .chanx_right_in(sb_1__8__4_chanx_left_out[0:29]), + .ccff_head(sb_1__8__4_ccff_tail), + .chanx_left_out(cbx_1__8__4_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__8__4_chanx_right_out[0:29]), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__4_ccff_tail)); + + cbx_1__8_ cbx_6__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__4_chanx_right_out[0:29]), + .chanx_right_in(sb_1__8__5_chanx_left_out[0:29]), + .ccff_head(sb_1__8__5_ccff_tail), + .chanx_left_out(cbx_1__8__5_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__8__5_chanx_right_out[0:29]), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__5_ccff_tail)); + + cbx_1__8_ cbx_7__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__5_chanx_right_out[0:29]), + .chanx_right_in(sb_1__8__6_chanx_left_out[0:29]), + .ccff_head(sb_1__8__6_ccff_tail), + .chanx_left_out(cbx_1__8__6_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__8__6_chanx_right_out[0:29]), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__6_ccff_tail)); + + cbx_1__8_ cbx_8__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__6_chanx_right_out[0:29]), + .chanx_right_in(sb_8__8__0_chanx_left_out[0:29]), + .ccff_head(sb_8__8__0_ccff_tail), + .chanx_left_out(cbx_1__8__7_chanx_left_out[0:29]), + .chanx_right_out(cbx_1__8__7_chanx_right_out[0:29]), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__7_ccff_tail)); + + cby_0__1_ cby_0__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__0__0_chany_top_out[0:29]), + .chany_top_in(sb_0__1__0_chany_bottom_out[0:29]), + .ccff_head(sb_0__0__0_ccff_tail), + .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:29]), + .chany_top_out(cby_0__1__0_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__0_ccff_tail)); + + cby_0__1_ cby_0__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__0_chany_top_out[0:29]), + .chany_top_in(sb_0__1__1_chany_bottom_out[0:29]), + .ccff_head(sb_0__1__0_ccff_tail), + .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:29]), + .chany_top_out(cby_0__1__1_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__1_ccff_tail)); + + cby_0__1_ cby_0__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__1_chany_top_out[0:29]), + .chany_top_in(sb_0__1__2_chany_bottom_out[0:29]), + .ccff_head(sb_0__1__1_ccff_tail), + .chany_bottom_out(cby_0__1__2_chany_bottom_out[0:29]), + .chany_top_out(cby_0__1__2_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__2_ccff_tail)); + + cby_0__1_ cby_0__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__2_chany_top_out[0:29]), + .chany_top_in(sb_0__1__3_chany_bottom_out[0:29]), + .ccff_head(sb_0__1__2_ccff_tail), + .chany_bottom_out(cby_0__1__3_chany_bottom_out[0:29]), + .chany_top_out(cby_0__1__3_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__3_ccff_tail)); + + cby_0__1_ cby_0__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__3_chany_top_out[0:29]), + .chany_top_in(sb_0__1__4_chany_bottom_out[0:29]), + .ccff_head(sb_0__1__3_ccff_tail), + .chany_bottom_out(cby_0__1__4_chany_bottom_out[0:29]), + .chany_top_out(cby_0__1__4_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__4_ccff_tail)); + + cby_0__1_ cby_0__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__4_chany_top_out[0:29]), + .chany_top_in(sb_0__1__5_chany_bottom_out[0:29]), + .ccff_head(sb_0__1__4_ccff_tail), + .chany_bottom_out(cby_0__1__5_chany_bottom_out[0:29]), + .chany_top_out(cby_0__1__5_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__5_ccff_tail)); + + cby_0__1_ cby_0__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__5_chany_top_out[0:29]), + .chany_top_in(sb_0__1__6_chany_bottom_out[0:29]), + .ccff_head(sb_0__1__5_ccff_tail), + .chany_bottom_out(cby_0__1__6_chany_bottom_out[0:29]), + .chany_top_out(cby_0__1__6_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__6_ccff_tail)); + + cby_0__1_ cby_0__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__6_chany_top_out[0:29]), + .chany_top_in(sb_0__8__0_chany_bottom_out[0:29]), + .ccff_head(sb_0__1__6_ccff_tail), + .chany_bottom_out(cby_0__1__7_chany_bottom_out[0:29]), + .chany_top_out(cby_0__1__7_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__7_ccff_tail)); + + cby_1__1_ cby_1__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__0_chany_top_out[0:29]), + .chany_top_in(sb_1__1__0_chany_bottom_out[0:29]), + .ccff_head(cbx_1__0__0_ccff_tail), + .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__0_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__0_ccff_tail)); + + cby_1__1_ cby_1__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__0_chany_top_out[0:29]), + .chany_top_in(sb_1__1__1_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__0_ccff_tail), + .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__1_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__1_ccff_tail)); + + cby_1__1_ cby_1__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__1_chany_top_out[0:29]), + .chany_top_in(sb_1__1__2_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__1_ccff_tail), + .chany_bottom_out(cby_1__1__2_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__2_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__2_ccff_tail)); + + cby_1__1_ cby_1__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__2_chany_top_out[0:29]), + .chany_top_in(sb_1__1__3_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__2_ccff_tail), + .chany_bottom_out(cby_1__1__3_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__3_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__3_ccff_tail)); + + cby_1__1_ cby_1__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__3_chany_top_out[0:29]), + .chany_top_in(sb_1__1__4_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__3_ccff_tail), + .chany_bottom_out(cby_1__1__4_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__4_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__4_ccff_tail)); + + cby_1__1_ cby_1__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__4_chany_top_out[0:29]), + .chany_top_in(sb_1__1__5_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__4_ccff_tail), + .chany_bottom_out(cby_1__1__5_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__5_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__5_ccff_tail)); + + cby_1__1_ cby_1__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__5_chany_top_out[0:29]), + .chany_top_in(sb_1__1__6_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__5_ccff_tail), + .chany_bottom_out(cby_1__1__6_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__6_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__6_ccff_tail)); + + cby_1__1_ cby_1__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__6_chany_top_out[0:29]), + .chany_top_in(sb_1__8__0_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__6_ccff_tail), + .chany_bottom_out(cby_1__1__7_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__7_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__7_ccff_tail)); + + cby_1__1_ cby_2__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__1_chany_top_out[0:29]), + .chany_top_in(sb_1__1__7_chany_bottom_out[0:29]), + .ccff_head(cbx_1__0__1_ccff_tail), + .chany_bottom_out(cby_1__1__8_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__8_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__8_ccff_tail)); + + cby_1__1_ cby_2__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__7_chany_top_out[0:29]), + .chany_top_in(sb_1__1__8_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__7_ccff_tail), + .chany_bottom_out(cby_1__1__9_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__9_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__9_ccff_tail)); + + cby_1__1_ cby_2__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__8_chany_top_out[0:29]), + .chany_top_in(sb_1__1__9_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__8_ccff_tail), + .chany_bottom_out(cby_1__1__10_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__10_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__10_ccff_tail)); + + cby_1__1_ cby_2__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__9_chany_top_out[0:29]), + .chany_top_in(sb_1__1__10_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__9_ccff_tail), + .chany_bottom_out(cby_1__1__11_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__11_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__11_ccff_tail)); + + cby_1__1_ cby_2__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__10_chany_top_out[0:29]), + .chany_top_in(sb_1__1__11_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__10_ccff_tail), + .chany_bottom_out(cby_1__1__12_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__12_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__12_ccff_tail)); + + cby_1__1_ cby_2__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__11_chany_top_out[0:29]), + .chany_top_in(sb_1__1__12_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__11_ccff_tail), + .chany_bottom_out(cby_1__1__13_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__13_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__13_ccff_tail)); + + cby_1__1_ cby_2__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__12_chany_top_out[0:29]), + .chany_top_in(sb_1__1__13_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__12_ccff_tail), + .chany_bottom_out(cby_1__1__14_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__14_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__14_ccff_tail)); + + cby_1__1_ cby_2__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__13_chany_top_out[0:29]), + .chany_top_in(sb_1__8__1_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__13_ccff_tail), + .chany_bottom_out(cby_1__1__15_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__15_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__15_ccff_tail)); + + cby_1__1_ cby_3__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__2_chany_top_out[0:29]), + .chany_top_in(sb_1__1__14_chany_bottom_out[0:29]), + .ccff_head(cbx_1__0__2_ccff_tail), + .chany_bottom_out(cby_1__1__16_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__16_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__16_ccff_tail)); + + cby_1__1_ cby_3__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__14_chany_top_out[0:29]), + .chany_top_in(sb_1__1__15_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__14_ccff_tail), + .chany_bottom_out(cby_1__1__17_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__17_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__17_ccff_tail)); + + cby_1__1_ cby_3__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__15_chany_top_out[0:29]), + .chany_top_in(sb_1__1__16_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__15_ccff_tail), + .chany_bottom_out(cby_1__1__18_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__18_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__18_ccff_tail)); + + cby_1__1_ cby_3__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__16_chany_top_out[0:29]), + .chany_top_in(sb_1__1__17_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__16_ccff_tail), + .chany_bottom_out(cby_1__1__19_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__19_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__19_ccff_tail)); + + cby_1__1_ cby_3__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__17_chany_top_out[0:29]), + .chany_top_in(sb_1__1__18_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__17_ccff_tail), + .chany_bottom_out(cby_1__1__20_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__20_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__20_ccff_tail)); + + cby_1__1_ cby_3__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__18_chany_top_out[0:29]), + .chany_top_in(sb_1__1__19_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__18_ccff_tail), + .chany_bottom_out(cby_1__1__21_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__21_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__21_ccff_tail)); + + cby_1__1_ cby_3__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__19_chany_top_out[0:29]), + .chany_top_in(sb_1__1__20_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__19_ccff_tail), + .chany_bottom_out(cby_1__1__22_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__22_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__22_ccff_tail)); + + cby_1__1_ cby_3__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__20_chany_top_out[0:29]), + .chany_top_in(sb_1__8__2_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__20_ccff_tail), + .chany_bottom_out(cby_1__1__23_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__23_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__23_ccff_tail)); + + cby_1__1_ cby_4__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__3_chany_top_out[0:29]), + .chany_top_in(sb_1__1__21_chany_bottom_out[0:29]), + .ccff_head(cbx_1__0__3_ccff_tail), + .chany_bottom_out(cby_1__1__24_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__24_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__24_ccff_tail)); + + cby_1__1_ cby_4__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__21_chany_top_out[0:29]), + .chany_top_in(sb_1__1__22_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__21_ccff_tail), + .chany_bottom_out(cby_1__1__25_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__25_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__25_ccff_tail)); + + cby_1__1_ cby_4__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__22_chany_top_out[0:29]), + .chany_top_in(sb_1__1__23_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__22_ccff_tail), + .chany_bottom_out(cby_1__1__26_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__26_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__26_ccff_tail)); + + cby_1__1_ cby_4__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__23_chany_top_out[0:29]), + .chany_top_in(sb_1__1__24_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__23_ccff_tail), + .chany_bottom_out(cby_1__1__27_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__27_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__27_ccff_tail)); + + cby_1__1_ cby_4__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__24_chany_top_out[0:29]), + .chany_top_in(sb_1__1__25_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__24_ccff_tail), + .chany_bottom_out(cby_1__1__28_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__28_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__28_ccff_tail)); + + cby_1__1_ cby_4__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__25_chany_top_out[0:29]), + .chany_top_in(sb_1__1__26_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__25_ccff_tail), + .chany_bottom_out(cby_1__1__29_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__29_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__29_ccff_tail)); + + cby_1__1_ cby_4__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__26_chany_top_out[0:29]), + .chany_top_in(sb_1__1__27_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__26_ccff_tail), + .chany_bottom_out(cby_1__1__30_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__30_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__30_ccff_tail)); + + cby_1__1_ cby_4__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__27_chany_top_out[0:29]), + .chany_top_in(sb_1__8__3_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__27_ccff_tail), + .chany_bottom_out(cby_1__1__31_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__31_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__31_ccff_tail)); + + cby_1__1_ cby_5__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__4_chany_top_out[0:29]), + .chany_top_in(sb_1__1__28_chany_bottom_out[0:29]), + .ccff_head(cbx_1__0__4_ccff_tail), + .chany_bottom_out(cby_1__1__32_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__32_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__32_ccff_tail)); + + cby_1__1_ cby_5__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__28_chany_top_out[0:29]), + .chany_top_in(sb_1__1__29_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__28_ccff_tail), + .chany_bottom_out(cby_1__1__33_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__33_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__33_ccff_tail)); + + cby_1__1_ cby_5__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__29_chany_top_out[0:29]), + .chany_top_in(sb_1__1__30_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__29_ccff_tail), + .chany_bottom_out(cby_1__1__34_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__34_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__34_ccff_tail)); + + cby_1__1_ cby_5__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__30_chany_top_out[0:29]), + .chany_top_in(sb_1__1__31_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__30_ccff_tail), + .chany_bottom_out(cby_1__1__35_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__35_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__35_ccff_tail)); + + cby_1__1_ cby_5__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__31_chany_top_out[0:29]), + .chany_top_in(sb_1__1__32_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__31_ccff_tail), + .chany_bottom_out(cby_1__1__36_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__36_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__36_ccff_tail)); + + cby_1__1_ cby_5__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__32_chany_top_out[0:29]), + .chany_top_in(sb_1__1__33_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__32_ccff_tail), + .chany_bottom_out(cby_1__1__37_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__37_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__37_ccff_tail)); + + cby_1__1_ cby_5__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__33_chany_top_out[0:29]), + .chany_top_in(sb_1__1__34_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__33_ccff_tail), + .chany_bottom_out(cby_1__1__38_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__38_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__38_ccff_tail)); + + cby_1__1_ cby_5__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__34_chany_top_out[0:29]), + .chany_top_in(sb_1__8__4_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__34_ccff_tail), + .chany_bottom_out(cby_1__1__39_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__39_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__39_ccff_tail)); + + cby_1__1_ cby_6__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__5_chany_top_out[0:29]), + .chany_top_in(sb_1__1__35_chany_bottom_out[0:29]), + .ccff_head(cbx_1__0__5_ccff_tail), + .chany_bottom_out(cby_1__1__40_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__40_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__40_ccff_tail)); + + cby_1__1_ cby_6__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__35_chany_top_out[0:29]), + .chany_top_in(sb_1__1__36_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__35_ccff_tail), + .chany_bottom_out(cby_1__1__41_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__41_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__41_ccff_tail)); + + cby_1__1_ cby_6__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__36_chany_top_out[0:29]), + .chany_top_in(sb_1__1__37_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__36_ccff_tail), + .chany_bottom_out(cby_1__1__42_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__42_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__42_ccff_tail)); + + cby_1__1_ cby_6__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__37_chany_top_out[0:29]), + .chany_top_in(sb_1__1__38_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__37_ccff_tail), + .chany_bottom_out(cby_1__1__43_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__43_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__43_ccff_tail)); + + cby_1__1_ cby_6__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__38_chany_top_out[0:29]), + .chany_top_in(sb_1__1__39_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__38_ccff_tail), + .chany_bottom_out(cby_1__1__44_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__44_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__44_ccff_tail)); + + cby_1__1_ cby_6__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__39_chany_top_out[0:29]), + .chany_top_in(sb_1__1__40_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__39_ccff_tail), + .chany_bottom_out(cby_1__1__45_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__45_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__45_ccff_tail)); + + cby_1__1_ cby_6__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__40_chany_top_out[0:29]), + .chany_top_in(sb_1__1__41_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__40_ccff_tail), + .chany_bottom_out(cby_1__1__46_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__46_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__46_ccff_tail)); + + cby_1__1_ cby_6__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__41_chany_top_out[0:29]), + .chany_top_in(sb_1__8__5_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__41_ccff_tail), + .chany_bottom_out(cby_1__1__47_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__47_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__47_ccff_tail)); + + cby_1__1_ cby_7__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__6_chany_top_out[0:29]), + .chany_top_in(sb_1__1__42_chany_bottom_out[0:29]), + .ccff_head(cbx_1__0__6_ccff_tail), + .chany_bottom_out(cby_1__1__48_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__48_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__48_ccff_tail)); + + cby_1__1_ cby_7__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__42_chany_top_out[0:29]), + .chany_top_in(sb_1__1__43_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__42_ccff_tail), + .chany_bottom_out(cby_1__1__49_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__49_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__49_ccff_tail)); + + cby_1__1_ cby_7__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__43_chany_top_out[0:29]), + .chany_top_in(sb_1__1__44_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__43_ccff_tail), + .chany_bottom_out(cby_1__1__50_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__50_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__50_ccff_tail)); + + cby_1__1_ cby_7__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__44_chany_top_out[0:29]), + .chany_top_in(sb_1__1__45_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__44_ccff_tail), + .chany_bottom_out(cby_1__1__51_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__51_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__51_ccff_tail)); + + cby_1__1_ cby_7__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__45_chany_top_out[0:29]), + .chany_top_in(sb_1__1__46_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__45_ccff_tail), + .chany_bottom_out(cby_1__1__52_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__52_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__52_ccff_tail)); + + cby_1__1_ cby_7__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__46_chany_top_out[0:29]), + .chany_top_in(sb_1__1__47_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__46_ccff_tail), + .chany_bottom_out(cby_1__1__53_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__53_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__53_ccff_tail)); + + cby_1__1_ cby_7__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__47_chany_top_out[0:29]), + .chany_top_in(sb_1__1__48_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__47_ccff_tail), + .chany_bottom_out(cby_1__1__54_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__54_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__54_ccff_tail)); + + cby_1__1_ cby_7__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__48_chany_top_out[0:29]), + .chany_top_in(sb_1__8__6_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__48_ccff_tail), + .chany_bottom_out(cby_1__1__55_chany_bottom_out[0:29]), + .chany_top_out(cby_1__1__55_chany_top_out[0:29]), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__55_ccff_tail)); + + cby_8__1_ cby_8__1_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__0__0_chany_top_out[0:29]), + .chany_top_in(sb_8__1__0_chany_bottom_out[0:29]), + .ccff_head(cbx_1__0__7_ccff_tail), + .chany_bottom_out(cby_8__1__0_chany_bottom_out[0:29]), + .chany_top_out(cby_8__1__0_chany_top_out[0:29]), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__0_ccff_tail)); + + cby_8__1_ cby_8__2_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__0_chany_top_out[0:29]), + .chany_top_in(sb_8__1__1_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__49_ccff_tail), + .chany_bottom_out(cby_8__1__1_chany_bottom_out[0:29]), + .chany_top_out(cby_8__1__1_chany_top_out[0:29]), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__1_ccff_tail)); + + cby_8__1_ cby_8__3_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__1_chany_top_out[0:29]), + .chany_top_in(sb_8__1__2_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__50_ccff_tail), + .chany_bottom_out(cby_8__1__2_chany_bottom_out[0:29]), + .chany_top_out(cby_8__1__2_chany_top_out[0:29]), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__2_ccff_tail)); + + cby_8__1_ cby_8__4_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__2_chany_top_out[0:29]), + .chany_top_in(sb_8__1__3_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__51_ccff_tail), + .chany_bottom_out(cby_8__1__3_chany_bottom_out[0:29]), + .chany_top_out(cby_8__1__3_chany_top_out[0:29]), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__3_ccff_tail)); + + cby_8__1_ cby_8__5_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__3_chany_top_out[0:29]), + .chany_top_in(sb_8__1__4_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__52_ccff_tail), + .chany_bottom_out(cby_8__1__4_chany_bottom_out[0:29]), + .chany_top_out(cby_8__1__4_chany_top_out[0:29]), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__4_ccff_tail)); + + cby_8__1_ cby_8__6_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__4_chany_top_out[0:29]), + .chany_top_in(sb_8__1__5_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__53_ccff_tail), + .chany_bottom_out(cby_8__1__5_chany_bottom_out[0:29]), + .chany_top_out(cby_8__1__5_chany_top_out[0:29]), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__5_ccff_tail)); + + cby_8__1_ cby_8__7_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__5_chany_top_out[0:29]), + .chany_top_in(sb_8__1__6_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__54_ccff_tail), + .chany_bottom_out(cby_8__1__6_chany_bottom_out[0:29]), + .chany_top_out(cby_8__1__6_chany_top_out[0:29]), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__6_ccff_tail)); + + cby_8__1_ cby_8__8_ ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__6_chany_top_out[0:29]), + .chany_top_in(sb_8__8__0_chany_bottom_out[0:29]), + .ccff_head(cbx_1__1__55_ccff_tail), + .chany_bottom_out(cby_8__1__7_chany_bottom_out[0:29]), + .chany_top_out(cby_8__1__7_chany_top_out[0:29]), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__7_ccff_tail)); + + direct_interc direct_interc_0_ ( + .in(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_0_out)); + + direct_interc direct_interc_1_ ( + .in(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_1_out)); + + direct_interc direct_interc_2_ ( + .in(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_2_out)); + + direct_interc direct_interc_3_ ( + .in(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_3_out)); + + direct_interc direct_interc_4_ ( + .in(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_4_out)); + + direct_interc direct_interc_5_ ( + .in(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_5_out)); + + direct_interc direct_interc_6_ ( + .in(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_6_out)); + + direct_interc direct_interc_7_ ( + .in(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_7_out)); + + direct_interc direct_interc_8_ ( + .in(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_8_out)); + + direct_interc direct_interc_9_ ( + .in(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_9_out)); + + direct_interc direct_interc_10_ ( + .in(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_10_out)); + + direct_interc direct_interc_11_ ( + .in(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_11_out)); + + direct_interc direct_interc_12_ ( + .in(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_12_out)); + + direct_interc direct_interc_13_ ( + .in(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_13_out)); + + direct_interc direct_interc_14_ ( + .in(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_14_out)); + + direct_interc direct_interc_15_ ( + .in(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_15_out)); + + direct_interc direct_interc_16_ ( + .in(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_16_out)); + + direct_interc direct_interc_17_ ( + .in(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_17_out)); + + direct_interc direct_interc_18_ ( + .in(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_18_out)); + + direct_interc direct_interc_19_ ( + .in(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_19_out)); + + direct_interc direct_interc_20_ ( + .in(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_20_out)); + + direct_interc direct_interc_21_ ( + .in(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_21_out)); + + direct_interc direct_interc_22_ ( + .in(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_22_out)); + + direct_interc direct_interc_23_ ( + .in(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_23_out)); + + direct_interc direct_interc_24_ ( + .in(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_24_out)); + + direct_interc direct_interc_25_ ( + .in(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_25_out)); + + direct_interc direct_interc_26_ ( + .in(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_26_out)); + + direct_interc direct_interc_27_ ( + .in(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_27_out)); + + direct_interc direct_interc_28_ ( + .in(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_28_out)); + + direct_interc direct_interc_29_ ( + .in(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_29_out)); + + direct_interc direct_interc_30_ ( + .in(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_30_out)); + + direct_interc direct_interc_31_ ( + .in(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_31_out)); + + direct_interc direct_interc_32_ ( + .in(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_32_out)); + + direct_interc direct_interc_33_ ( + .in(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_33_out)); + + direct_interc direct_interc_34_ ( + .in(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_34_out)); + + direct_interc direct_interc_35_ ( + .in(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_35_out)); + + direct_interc direct_interc_36_ ( + .in(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_36_out)); + + direct_interc direct_interc_37_ ( + .in(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_37_out)); + + direct_interc direct_interc_38_ ( + .in(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_38_out)); + + direct_interc direct_interc_39_ ( + .in(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_39_out)); + + direct_interc direct_interc_40_ ( + .in(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_40_out)); + + direct_interc direct_interc_41_ ( + .in(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_41_out)); + + direct_interc direct_interc_42_ ( + .in(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_42_out)); + + direct_interc direct_interc_43_ ( + .in(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_43_out)); + + direct_interc direct_interc_44_ ( + .in(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_44_out)); + + direct_interc direct_interc_45_ ( + .in(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_45_out)); + + direct_interc direct_interc_46_ ( + .in(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_46_out)); + + direct_interc direct_interc_47_ ( + .in(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_47_out)); + + direct_interc direct_interc_48_ ( + .in(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_48_out)); + + direct_interc direct_interc_49_ ( + .in(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_49_out)); + + direct_interc direct_interc_50_ ( + .in(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_50_out)); + + direct_interc direct_interc_51_ ( + .in(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_51_out)); + + direct_interc direct_interc_52_ ( + .in(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_52_out)); + + direct_interc direct_interc_53_ ( + .in(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_53_out)); + + direct_interc direct_interc_54_ ( + .in(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_54_out)); + + direct_interc direct_interc_55_ ( + .in(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_55_out)); + + direct_interc direct_interc_56_ ( + .in(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_56_out)); + + direct_interc direct_interc_57_ ( + .in(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_57_out)); + + direct_interc direct_interc_58_ ( + .in(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_58_out)); + + direct_interc direct_interc_59_ ( + .in(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_59_out)); + + direct_interc direct_interc_60_ ( + .in(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_60_out)); + + direct_interc direct_interc_61_ ( + .in(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_61_out)); + + direct_interc direct_interc_62_ ( + .in(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_62_out)); + + direct_interc direct_interc_63_ ( + .in(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_63_out)); + + direct_interc direct_interc_64_ ( + .in(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_64_out)); + + direct_interc direct_interc_65_ ( + .in(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_65_out)); + + direct_interc direct_interc_66_ ( + .in(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_66_out)); + + direct_interc direct_interc_67_ ( + .in(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_67_out)); + + direct_interc direct_interc_68_ ( + .in(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_68_out)); + + direct_interc direct_interc_69_ ( + .in(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_69_out)); + + direct_interc direct_interc_70_ ( + .in(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_70_out)); + + direct_interc direct_interc_71_ ( + .in(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_71_out)); + + direct_interc direct_interc_72_ ( + .in(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_72_out)); + + direct_interc direct_interc_73_ ( + .in(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_73_out)); + + direct_interc direct_interc_74_ ( + .in(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_74_out)); + + direct_interc direct_interc_75_ ( + .in(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_75_out)); + + direct_interc direct_interc_76_ ( + .in(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_76_out)); + + direct_interc direct_interc_77_ ( + .in(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_77_out)); + + direct_interc direct_interc_78_ ( + .in(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_78_out)); + + direct_interc direct_interc_79_ ( + .in(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_79_out)); + + direct_interc direct_interc_80_ ( + .in(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_80_out)); + + direct_interc direct_interc_81_ ( + .in(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_81_out)); + + direct_interc direct_interc_82_ ( + .in(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_82_out)); + + direct_interc direct_interc_83_ ( + .in(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_83_out)); + + direct_interc direct_interc_84_ ( + .in(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_84_out)); + + direct_interc direct_interc_85_ ( + .in(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_85_out)); + + direct_interc direct_interc_86_ ( + .in(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_86_out)); + + direct_interc direct_interc_87_ ( + .in(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_87_out)); + + direct_interc direct_interc_88_ ( + .in(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_88_out)); + + direct_interc direct_interc_89_ ( + .in(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_89_out)); + + direct_interc direct_interc_90_ ( + .in(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_90_out)); + + direct_interc direct_interc_91_ ( + .in(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_91_out)); + + direct_interc direct_interc_92_ ( + .in(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_92_out)); + + direct_interc direct_interc_93_ ( + .in(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_93_out)); + + direct_interc direct_interc_94_ ( + .in(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_94_out)); + + direct_interc direct_interc_95_ ( + .in(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_95_out)); + + direct_interc direct_interc_96_ ( + .in(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_96_out)); + + direct_interc direct_interc_97_ ( + .in(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_97_out)); + + direct_interc direct_interc_98_ ( + .in(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_98_out)); + + direct_interc direct_interc_99_ ( + .in(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_99_out)); + + direct_interc direct_interc_100_ ( + .in(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_100_out)); + + direct_interc direct_interc_101_ ( + .in(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_101_out)); + + direct_interc direct_interc_102_ ( + .in(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_102_out)); + + direct_interc direct_interc_103_ ( + .in(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_103_out)); + + direct_interc direct_interc_104_ ( + .in(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_104_out)); + + direct_interc direct_interc_105_ ( + .in(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_105_out)); + + direct_interc direct_interc_106_ ( + .in(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_106_out)); + + direct_interc direct_interc_107_ ( + .in(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_107_out)); + + direct_interc direct_interc_108_ ( + .in(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_108_out)); + + direct_interc direct_interc_109_ ( + .in(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_109_out)); + + direct_interc direct_interc_110_ ( + .in(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_110_out)); + + direct_interc direct_interc_111_ ( + .in(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_111_out)); + + direct_interc direct_interc_112_ ( + .in(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_112_out)); + + direct_interc direct_interc_113_ ( + .in(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_113_out)); + + direct_interc direct_interc_114_ ( + .in(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_114_out)); + + direct_interc direct_interc_115_ ( + .in(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_115_out)); + + direct_interc direct_interc_116_ ( + .in(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_116_out)); + + direct_interc direct_interc_117_ ( + .in(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_117_out)); + + direct_interc direct_interc_118_ ( + .in(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_118_out)); + + direct_interc direct_interc_119_ ( + .in(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_119_out)); + + direct_interc direct_interc_120_ ( + .in(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_120_out)); + + direct_interc direct_interc_121_ ( + .in(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_121_out)); + + direct_interc direct_interc_122_ ( + .in(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_122_out)); + + direct_interc direct_interc_123_ ( + .in(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_123_out)); + + direct_interc direct_interc_124_ ( + .in(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_124_out)); + + direct_interc direct_interc_125_ ( + .in(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_125_out)); + + direct_interc direct_interc_126_ ( + .in(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_126_out)); + + direct_interc direct_interc_127_ ( + .in(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_127_out)); + + direct_interc direct_interc_128_ ( + .in(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_128_out)); + + direct_interc direct_interc_129_ ( + .in(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_129_out)); + + direct_interc direct_interc_130_ ( + .in(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_130_out)); + + direct_interc direct_interc_131_ ( + .in(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_131_out)); + + direct_interc direct_interc_132_ ( + .in(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_132_out)); + + direct_interc direct_interc_133_ ( + .in(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_133_out)); + + direct_interc direct_interc_134_ ( + .in(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_134_out)); + + direct_interc direct_interc_135_ ( + .in(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_135_out)); + + direct_interc direct_interc_136_ ( + .in(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_136_out)); + + direct_interc direct_interc_137_ ( + .in(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_137_out)); + + direct_interc direct_interc_138_ ( + .in(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_138_out)); + + direct_interc direct_interc_139_ ( + .in(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_139_out)); + + direct_interc direct_interc_140_ ( + .in(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_140_out)); + + direct_interc direct_interc_141_ ( + .in(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_141_out)); + + direct_interc direct_interc_142_ ( + .in(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_142_out)); + + direct_interc direct_interc_143_ ( + .in(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_143_out)); + + direct_interc direct_interc_144_ ( + .in(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_144_out)); + + direct_interc direct_interc_145_ ( + .in(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_145_out)); + + direct_interc direct_interc_146_ ( + .in(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_146_out)); + + direct_interc direct_interc_147_ ( + .in(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_147_out)); + + direct_interc direct_interc_148_ ( + .in(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_148_out)); + + direct_interc direct_interc_149_ ( + .in(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_149_out)); + + direct_interc direct_interc_150_ ( + .in(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_150_out)); + + direct_interc direct_interc_151_ ( + .in(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_151_out)); + + direct_interc direct_interc_152_ ( + .in(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_152_out)); + + direct_interc direct_interc_153_ ( + .in(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_153_out)); + + direct_interc direct_interc_154_ ( + .in(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_154_out)); + + direct_interc direct_interc_155_ ( + .in(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_155_out)); + + direct_interc direct_interc_156_ ( + .in(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_156_out)); + + direct_interc direct_interc_157_ ( + .in(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_157_out)); + + direct_interc direct_interc_158_ ( + .in(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_158_out)); + + direct_interc direct_interc_159_ ( + .in(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_159_out)); + + direct_interc direct_interc_160_ ( + .in(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_160_out)); + + direct_interc direct_interc_161_ ( + .in(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_161_out)); + + direct_interc direct_interc_162_ ( + .in(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_162_out)); + + direct_interc direct_interc_163_ ( + .in(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_163_out)); + + direct_interc direct_interc_164_ ( + .in(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_164_out)); + + direct_interc direct_interc_165_ ( + .in(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_165_out)); + + direct_interc direct_interc_166_ ( + .in(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_166_out)); + + direct_interc direct_interc_167_ ( + .in(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_167_out)); + + direct_interc direct_interc_168_ ( + .in(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_168_out)); + + direct_interc direct_interc_169_ ( + .in(grid_clb_8_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_169_out)); + + direct_interc direct_interc_170_ ( + .in(grid_clb_16_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_170_out)); + + direct_interc direct_interc_171_ ( + .in(grid_clb_24_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_171_out)); + + direct_interc direct_interc_172_ ( + .in(grid_clb_32_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_172_out)); + + direct_interc direct_interc_173_ ( + .in(grid_clb_40_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_173_out)); + + direct_interc direct_interc_174_ ( + .in(grid_clb_48_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_174_out)); + +endmodule +// ----- END Verilog module for fpga_top ----- + +//----- Default net type ----- +`default_nettype none + + + + diff --git a/SOFA_A/SOFA_A_verilog/lb/grid_clb.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_clb.v similarity index 99% rename from SOFA_A/SOFA_A_verilog/lb/grid_clb.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_clb.v index a63af14..0c2ef08 100644 --- a/SOFA_A/SOFA_A_verilog/lb/grid_clb.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_clb.v @@ -3,7 +3,6 @@ // Description: Verilog modules for physical tile: clb] // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/lb/grid_io_bottom_bottom.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_bottom_bottom.v similarity index 52% rename from SOFA_A/SOFA_A_verilog/lb/grid_io_bottom_bottom.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_bottom_bottom.v index 6b6cddb..ae56398 100644 --- a/SOFA_A/SOFA_A_verilog/lb/grid_io_bottom_bottom.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_bottom_bottom.v @@ -3,7 +3,6 @@ // Description: Verilog modules for physical tile: io_bottom] // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps @@ -23,21 +22,11 @@ module grid_io_bottom_bottom(IO_ISOL_N, top_width_0_height_0_subtile_1__pin_outpad_0_, top_width_0_height_0_subtile_2__pin_outpad_0_, top_width_0_height_0_subtile_3__pin_outpad_0_, - top_width_0_height_0_subtile_4__pin_outpad_0_, - top_width_0_height_0_subtile_5__pin_outpad_0_, - top_width_0_height_0_subtile_6__pin_outpad_0_, - top_width_0_height_0_subtile_7__pin_outpad_0_, - top_width_0_height_0_subtile_8__pin_outpad_0_, ccff_head, top_width_0_height_0_subtile_0__pin_inpad_0_, top_width_0_height_0_subtile_1__pin_inpad_0_, top_width_0_height_0_subtile_2__pin_inpad_0_, top_width_0_height_0_subtile_3__pin_inpad_0_, - top_width_0_height_0_subtile_4__pin_inpad_0_, - top_width_0_height_0_subtile_5__pin_inpad_0_, - top_width_0_height_0_subtile_6__pin_inpad_0_, - top_width_0_height_0_subtile_7__pin_inpad_0_, - top_width_0_height_0_subtile_8__pin_inpad_0_, ccff_tail); //----- GLOBAL PORTS ----- input [0:0] IO_ISOL_N; @@ -46,11 +35,11 @@ input [0:0] pReset; //----- GLOBAL PORTS ----- input [0:0] prog_clk; //----- GPIN PORTS ----- -input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; +input [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; //----- GPOUT PORTS ----- -output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; +output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; //----- GPOUT PORTS ----- -output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; +output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; //----- INPUT PORTS ----- input [0:0] top_width_0_height_0_subtile_0__pin_outpad_0_; //----- INPUT PORTS ----- @@ -60,16 +49,6 @@ input [0:0] top_width_0_height_0_subtile_2__pin_outpad_0_; //----- INPUT PORTS ----- input [0:0] top_width_0_height_0_subtile_3__pin_outpad_0_; //----- INPUT PORTS ----- -input [0:0] top_width_0_height_0_subtile_4__pin_outpad_0_; -//----- INPUT PORTS ----- -input [0:0] top_width_0_height_0_subtile_5__pin_outpad_0_; -//----- INPUT PORTS ----- -input [0:0] top_width_0_height_0_subtile_6__pin_outpad_0_; -//----- INPUT PORTS ----- -input [0:0] top_width_0_height_0_subtile_7__pin_outpad_0_; -//----- INPUT PORTS ----- -input [0:0] top_width_0_height_0_subtile_8__pin_outpad_0_; -//----- INPUT PORTS ----- input [0:0] ccff_head; //----- OUTPUT PORTS ----- output [0:0] top_width_0_height_0_subtile_0__pin_inpad_0_; @@ -80,16 +59,6 @@ output [0:0] top_width_0_height_0_subtile_2__pin_inpad_0_; //----- OUTPUT PORTS ----- output [0:0] top_width_0_height_0_subtile_3__pin_inpad_0_; //----- OUTPUT PORTS ----- -output [0:0] top_width_0_height_0_subtile_4__pin_inpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] top_width_0_height_0_subtile_5__pin_inpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] top_width_0_height_0_subtile_6__pin_inpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] top_width_0_height_0_subtile_7__pin_inpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] top_width_0_height_0_subtile_8__pin_inpad_0_; -//----- OUTPUT PORTS ----- output [0:0] ccff_tail; //----- BEGIN wire-connection ports ----- @@ -103,11 +72,6 @@ output [0:0] ccff_tail; wire [0:0] logical_tile_io_mode_io__0_ccff_tail; wire [0:0] logical_tile_io_mode_io__1_ccff_tail; wire [0:0] logical_tile_io_mode_io__2_ccff_tail; -wire [0:0] logical_tile_io_mode_io__3_ccff_tail; -wire [0:0] logical_tile_io_mode_io__4_ccff_tail; -wire [0:0] logical_tile_io_mode_io__5_ccff_tail; -wire [0:0] logical_tile_io_mode_io__6_ccff_tail; -wire [0:0] logical_tile_io_mode_io__7_ccff_tail; // ----- BEGIN Local short connections ----- // ----- END Local short connections ----- @@ -160,66 +124,6 @@ wire [0:0] logical_tile_io_mode_io__7_ccff_tail; .io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_), .ccff_head(logical_tile_io_mode_io__2_ccff_tail), .io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_), - .ccff_tail(logical_tile_io_mode_io__3_ccff_tail)); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__4 ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4]), - .io_outpad(top_width_0_height_0_subtile_4__pin_outpad_0_), - .ccff_head(logical_tile_io_mode_io__3_ccff_tail), - .io_inpad(top_width_0_height_0_subtile_4__pin_inpad_0_), - .ccff_tail(logical_tile_io_mode_io__4_ccff_tail)); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5]), - .io_outpad(top_width_0_height_0_subtile_5__pin_outpad_0_), - .ccff_head(logical_tile_io_mode_io__4_ccff_tail), - .io_inpad(top_width_0_height_0_subtile_5__pin_inpad_0_), - .ccff_tail(logical_tile_io_mode_io__5_ccff_tail)); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__6 ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6]), - .io_outpad(top_width_0_height_0_subtile_6__pin_outpad_0_), - .ccff_head(logical_tile_io_mode_io__5_ccff_tail), - .io_inpad(top_width_0_height_0_subtile_6__pin_inpad_0_), - .ccff_tail(logical_tile_io_mode_io__6_ccff_tail)); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__7 ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7]), - .io_outpad(top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(logical_tile_io_mode_io__6_ccff_tail), - .io_inpad(top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_tail(logical_tile_io_mode_io__7_ccff_tail)); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8]), - .io_outpad(top_width_0_height_0_subtile_8__pin_outpad_0_), - .ccff_head(logical_tile_io_mode_io__7_ccff_tail), - .io_inpad(top_width_0_height_0_subtile_8__pin_inpad_0_), .ccff_tail(ccff_tail)); endmodule diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_left_left.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_left_left.v new file mode 100644 index 0000000..aa5a5fc --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_left_left.v @@ -0,0 +1,138 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for physical tile: io_left] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ----- BEGIN Grid Verilog module: grid_io_left_left ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for grid_io_left_left ----- +module grid_io_left_left(IO_ISOL_N, + pReset, + prog_clk, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + right_width_0_height_0_subtile_0__pin_outpad_0_, + right_width_0_height_0_subtile_1__pin_outpad_0_, + right_width_0_height_0_subtile_2__pin_outpad_0_, + right_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_head, + right_width_0_height_0_subtile_0__pin_inpad_0_, + right_width_0_height_0_subtile_1__pin_inpad_0_, + right_width_0_height_0_subtile_2__pin_inpad_0_, + right_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] IO_ISOL_N; +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GPIN PORTS ----- +input [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; +//----- GPOUT PORTS ----- +output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; +//----- GPOUT PORTS ----- +output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_0__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_1__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_2__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_3__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_0__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_1__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_2__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_3__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] logical_tile_io_mode_io__0_ccff_tail; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]), + .io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]), + .io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]), + .io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]), + .io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail)); + +endmodule +// ----- END Verilog module for grid_io_left_left ----- + +//----- Default net type ----- +`default_nettype none + + + +// ----- END Grid Verilog module: grid_io_left_left ----- + diff --git a/SOFA_A/SOFA_A_verilog/lb/grid_io_right_right.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_right_right.v similarity index 57% rename from SOFA_A/SOFA_A_verilog/lb/grid_io_right_right.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_right_right.v index 5c5eb51..99419bc 100644 --- a/SOFA_A/SOFA_A_verilog/lb/grid_io_right_right.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_right_right.v @@ -3,7 +3,6 @@ // Description: Verilog modules for physical tile: io_right] // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps @@ -23,19 +22,11 @@ module grid_io_right_right(IO_ISOL_N, left_width_0_height_0_subtile_1__pin_outpad_0_, left_width_0_height_0_subtile_2__pin_outpad_0_, left_width_0_height_0_subtile_3__pin_outpad_0_, - left_width_0_height_0_subtile_4__pin_outpad_0_, - left_width_0_height_0_subtile_5__pin_outpad_0_, - left_width_0_height_0_subtile_6__pin_outpad_0_, - left_width_0_height_0_subtile_7__pin_outpad_0_, ccff_head, left_width_0_height_0_subtile_0__pin_inpad_0_, left_width_0_height_0_subtile_1__pin_inpad_0_, left_width_0_height_0_subtile_2__pin_inpad_0_, left_width_0_height_0_subtile_3__pin_inpad_0_, - left_width_0_height_0_subtile_4__pin_inpad_0_, - left_width_0_height_0_subtile_5__pin_inpad_0_, - left_width_0_height_0_subtile_6__pin_inpad_0_, - left_width_0_height_0_subtile_7__pin_inpad_0_, ccff_tail); //----- GLOBAL PORTS ----- input [0:0] IO_ISOL_N; @@ -44,11 +35,11 @@ input [0:0] pReset; //----- GLOBAL PORTS ----- input [0:0] prog_clk; //----- GPIN PORTS ----- -input [0:7] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; +input [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; //----- GPOUT PORTS ----- -output [0:7] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; +output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; //----- GPOUT PORTS ----- -output [0:7] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; +output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; //----- INPUT PORTS ----- input [0:0] left_width_0_height_0_subtile_0__pin_outpad_0_; //----- INPUT PORTS ----- @@ -58,14 +49,6 @@ input [0:0] left_width_0_height_0_subtile_2__pin_outpad_0_; //----- INPUT PORTS ----- input [0:0] left_width_0_height_0_subtile_3__pin_outpad_0_; //----- INPUT PORTS ----- -input [0:0] left_width_0_height_0_subtile_4__pin_outpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_width_0_height_0_subtile_5__pin_outpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_width_0_height_0_subtile_6__pin_outpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_width_0_height_0_subtile_7__pin_outpad_0_; -//----- INPUT PORTS ----- input [0:0] ccff_head; //----- OUTPUT PORTS ----- output [0:0] left_width_0_height_0_subtile_0__pin_inpad_0_; @@ -76,14 +59,6 @@ output [0:0] left_width_0_height_0_subtile_2__pin_inpad_0_; //----- OUTPUT PORTS ----- output [0:0] left_width_0_height_0_subtile_3__pin_inpad_0_; //----- OUTPUT PORTS ----- -output [0:0] left_width_0_height_0_subtile_4__pin_inpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] left_width_0_height_0_subtile_5__pin_inpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] left_width_0_height_0_subtile_6__pin_inpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] left_width_0_height_0_subtile_7__pin_inpad_0_; -//----- OUTPUT PORTS ----- output [0:0] ccff_tail; //----- BEGIN wire-connection ports ----- @@ -97,10 +72,6 @@ output [0:0] ccff_tail; wire [0:0] logical_tile_io_mode_io__0_ccff_tail; wire [0:0] logical_tile_io_mode_io__1_ccff_tail; wire [0:0] logical_tile_io_mode_io__2_ccff_tail; -wire [0:0] logical_tile_io_mode_io__3_ccff_tail; -wire [0:0] logical_tile_io_mode_io__4_ccff_tail; -wire [0:0] logical_tile_io_mode_io__5_ccff_tail; -wire [0:0] logical_tile_io_mode_io__6_ccff_tail; // ----- BEGIN Local short connections ----- // ----- END Local short connections ----- @@ -153,54 +124,6 @@ wire [0:0] logical_tile_io_mode_io__6_ccff_tail; .io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_), .ccff_head(logical_tile_io_mode_io__2_ccff_tail), .io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_), - .ccff_tail(logical_tile_io_mode_io__3_ccff_tail)); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__4 ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4]), - .io_outpad(left_width_0_height_0_subtile_4__pin_outpad_0_), - .ccff_head(logical_tile_io_mode_io__3_ccff_tail), - .io_inpad(left_width_0_height_0_subtile_4__pin_inpad_0_), - .ccff_tail(logical_tile_io_mode_io__4_ccff_tail)); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5]), - .io_outpad(left_width_0_height_0_subtile_5__pin_outpad_0_), - .ccff_head(logical_tile_io_mode_io__4_ccff_tail), - .io_inpad(left_width_0_height_0_subtile_5__pin_inpad_0_), - .ccff_tail(logical_tile_io_mode_io__5_ccff_tail)); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__6 ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6]), - .io_outpad(left_width_0_height_0_subtile_6__pin_outpad_0_), - .ccff_head(logical_tile_io_mode_io__5_ccff_tail), - .io_inpad(left_width_0_height_0_subtile_6__pin_inpad_0_), - .ccff_tail(logical_tile_io_mode_io__6_ccff_tail)); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__7 ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7]), - .io_outpad(left_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(logical_tile_io_mode_io__6_ccff_tail), - .io_inpad(left_width_0_height_0_subtile_7__pin_inpad_0_), .ccff_tail(ccff_tail)); endmodule diff --git a/SOFA_A/SOFA_A_verilog/lb/grid_io_top_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_top_top.v similarity index 57% rename from SOFA_A/SOFA_A_verilog/lb/grid_io_top_top.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_top_top.v index 58809c0..72db158 100644 --- a/SOFA_A/SOFA_A_verilog/lb/grid_io_top_top.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_top_top.v @@ -3,7 +3,6 @@ // Description: Verilog modules for physical tile: io_top] // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps @@ -23,19 +22,11 @@ module grid_io_top_top(IO_ISOL_N, bottom_width_0_height_0_subtile_1__pin_outpad_0_, bottom_width_0_height_0_subtile_2__pin_outpad_0_, bottom_width_0_height_0_subtile_3__pin_outpad_0_, - bottom_width_0_height_0_subtile_4__pin_outpad_0_, - bottom_width_0_height_0_subtile_5__pin_outpad_0_, - bottom_width_0_height_0_subtile_6__pin_outpad_0_, - bottom_width_0_height_0_subtile_7__pin_outpad_0_, ccff_head, bottom_width_0_height_0_subtile_0__pin_inpad_0_, bottom_width_0_height_0_subtile_1__pin_inpad_0_, bottom_width_0_height_0_subtile_2__pin_inpad_0_, bottom_width_0_height_0_subtile_3__pin_inpad_0_, - bottom_width_0_height_0_subtile_4__pin_inpad_0_, - bottom_width_0_height_0_subtile_5__pin_inpad_0_, - bottom_width_0_height_0_subtile_6__pin_inpad_0_, - bottom_width_0_height_0_subtile_7__pin_inpad_0_, ccff_tail); //----- GLOBAL PORTS ----- input [0:0] IO_ISOL_N; @@ -44,11 +35,11 @@ input [0:0] pReset; //----- GLOBAL PORTS ----- input [0:0] prog_clk; //----- GPIN PORTS ----- -input [0:7] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; +input [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; //----- GPOUT PORTS ----- -output [0:7] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; +output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; //----- GPOUT PORTS ----- -output [0:7] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; +output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; //----- INPUT PORTS ----- input [0:0] bottom_width_0_height_0_subtile_0__pin_outpad_0_; //----- INPUT PORTS ----- @@ -58,14 +49,6 @@ input [0:0] bottom_width_0_height_0_subtile_2__pin_outpad_0_; //----- INPUT PORTS ----- input [0:0] bottom_width_0_height_0_subtile_3__pin_outpad_0_; //----- INPUT PORTS ----- -input [0:0] bottom_width_0_height_0_subtile_4__pin_outpad_0_; -//----- INPUT PORTS ----- -input [0:0] bottom_width_0_height_0_subtile_5__pin_outpad_0_; -//----- INPUT PORTS ----- -input [0:0] bottom_width_0_height_0_subtile_6__pin_outpad_0_; -//----- INPUT PORTS ----- -input [0:0] bottom_width_0_height_0_subtile_7__pin_outpad_0_; -//----- INPUT PORTS ----- input [0:0] ccff_head; //----- OUTPUT PORTS ----- output [0:0] bottom_width_0_height_0_subtile_0__pin_inpad_0_; @@ -76,14 +59,6 @@ output [0:0] bottom_width_0_height_0_subtile_2__pin_inpad_0_; //----- OUTPUT PORTS ----- output [0:0] bottom_width_0_height_0_subtile_3__pin_inpad_0_; //----- OUTPUT PORTS ----- -output [0:0] bottom_width_0_height_0_subtile_4__pin_inpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_width_0_height_0_subtile_5__pin_inpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_width_0_height_0_subtile_6__pin_inpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_width_0_height_0_subtile_7__pin_inpad_0_; -//----- OUTPUT PORTS ----- output [0:0] ccff_tail; //----- BEGIN wire-connection ports ----- @@ -97,10 +72,6 @@ output [0:0] ccff_tail; wire [0:0] logical_tile_io_mode_io__0_ccff_tail; wire [0:0] logical_tile_io_mode_io__1_ccff_tail; wire [0:0] logical_tile_io_mode_io__2_ccff_tail; -wire [0:0] logical_tile_io_mode_io__3_ccff_tail; -wire [0:0] logical_tile_io_mode_io__4_ccff_tail; -wire [0:0] logical_tile_io_mode_io__5_ccff_tail; -wire [0:0] logical_tile_io_mode_io__6_ccff_tail; // ----- BEGIN Local short connections ----- // ----- END Local short connections ----- @@ -153,54 +124,6 @@ wire [0:0] logical_tile_io_mode_io__6_ccff_tail; .io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_), .ccff_head(logical_tile_io_mode_io__2_ccff_tail), .io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_), - .ccff_tail(logical_tile_io_mode_io__3_ccff_tail)); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__4 ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4]), - .io_outpad(bottom_width_0_height_0_subtile_4__pin_outpad_0_), - .ccff_head(logical_tile_io_mode_io__3_ccff_tail), - .io_inpad(bottom_width_0_height_0_subtile_4__pin_inpad_0_), - .ccff_tail(logical_tile_io_mode_io__4_ccff_tail)); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5]), - .io_outpad(bottom_width_0_height_0_subtile_5__pin_outpad_0_), - .ccff_head(logical_tile_io_mode_io__4_ccff_tail), - .io_inpad(bottom_width_0_height_0_subtile_5__pin_inpad_0_), - .ccff_tail(logical_tile_io_mode_io__5_ccff_tail)); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__6 ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6]), - .io_outpad(bottom_width_0_height_0_subtile_6__pin_outpad_0_), - .ccff_head(logical_tile_io_mode_io__5_ccff_tail), - .io_inpad(bottom_width_0_height_0_subtile_6__pin_inpad_0_), - .ccff_tail(logical_tile_io_mode_io__6_ccff_tail)); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__7 ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7]), - .io_outpad(bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(logical_tile_io_mode_io__6_ccff_tail), - .io_inpad(bottom_width_0_height_0_subtile_7__pin_inpad_0_), .ccff_tail(ccff_tail)); endmodule diff --git a/SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_clb_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_clb_.v similarity index 99% rename from SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_clb_.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_clb_.v index 877a47d..83679b0 100644 --- a/SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_clb_.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_clb_.v @@ -3,7 +3,6 @@ // Description: Verilog modules for pb_type: clb // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle.v similarity index 99% rename from SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle.v index 4ce80cd..cba4e41 100644 --- a/SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle.v @@ -3,7 +3,6 @@ // Description: Verilog modules for pb_type: fle // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v similarity index 99% rename from SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v index 0b4ad40..c66b8ca 100644 --- a/SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v @@ -3,7 +3,6 @@ // Description: Verilog modules for pb_type: fabric // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v similarity index 98% rename from SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v index ab1ee5e..d6186fb 100644 --- a/SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v @@ -3,7 +3,6 @@ // Description: Verilog modules for primitive pb_type: ff // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v similarity index 99% rename from SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v index 79f3ddd..8ad3aa4 100644 --- a/SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v @@ -3,7 +3,6 @@ // Description: Verilog modules for pb_type: frac_logic // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v similarity index 98% rename from SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v index fc583fd..7d9d578 100644 --- a/SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v @@ -3,7 +3,6 @@ // Description: Verilog modules for primitive pb_type: carry_follower // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v similarity index 98% rename from SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v index f3ad46f..e90f948 100644 --- a/SOFA_A/SOFA_A_verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v @@ -3,7 +3,6 @@ // Description: Verilog modules for primitive pb_type: frac_lut4 // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/lb/logical_tile_io_mode_io_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_io_mode_io_.v similarity index 98% rename from SOFA_A/SOFA_A_verilog/lb/logical_tile_io_mode_io_.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_io_mode_io_.v index 6636837..a2d5d55 100644 --- a/SOFA_A/SOFA_A_verilog/lb/logical_tile_io_mode_io_.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_io_mode_io_.v @@ -3,7 +3,6 @@ // Description: Verilog modules for pb_type: io // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/lb/logical_tile_io_mode_physical__iopad.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_io_mode_physical__iopad.v similarity index 98% rename from SOFA_A/SOFA_A_verilog/lb/logical_tile_io_mode_physical__iopad.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_io_mode_physical__iopad.v index 493cdc4..400532e 100644 --- a/SOFA_A/SOFA_A_verilog/lb/logical_tile_io_mode_physical__iopad.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_io_mode_physical__iopad.v @@ -3,7 +3,6 @@ // Description: Verilog modules for primitive pb_type: iopad // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__0_.v new file mode 100644 index 0000000..7b1b6b7 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__0_.v @@ -0,0 +1,376 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Connection Blocks[1][0] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for cbx_1__0_ ----- +module cbx_1__0_(pReset, + prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:29] chanx_left_in; +//----- INPUT PORTS ----- +input [0:29] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:29] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:29] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:3] mux_top_ipin_0_undriven_sram_inv; +wire [0:3] mux_top_ipin_1_undriven_sram_inv; +wire [0:3] mux_top_ipin_2_undriven_sram_inv; +wire [0:3] mux_top_ipin_3_undriven_sram_inv; +wire [0:3] mux_tree_tapbuf_size12_0_sram; +wire [0:3] mux_tree_tapbuf_size12_1_sram; +wire [0:3] mux_tree_tapbuf_size12_2_sram; +wire [0:3] mux_tree_tapbuf_size12_3_sram; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[0] = chanx_left_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[1] = chanx_left_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[2] = chanx_left_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[3] = chanx_left_in[3]; +// ----- Local connection due to Wire 4 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[4] = chanx_left_in[4]; +// ----- Local connection due to Wire 5 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[5] = chanx_left_in[5]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[6] = chanx_left_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[7] = chanx_left_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[8] = chanx_left_in[8]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[9] = chanx_left_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[10] = chanx_left_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[11] = chanx_left_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[12] = chanx_left_in[12]; +// ----- Local connection due to Wire 13 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[13] = chanx_left_in[13]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[14] = chanx_left_in[14]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[15] = chanx_left_in[15]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[16] = chanx_left_in[16]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[17] = chanx_left_in[17]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[18] = chanx_left_in[18]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[19] = chanx_left_in[19]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[20] = chanx_left_in[20]; +// ----- Local connection due to Wire 21 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[21] = chanx_left_in[21]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[22] = chanx_left_in[22]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[23] = chanx_left_in[23]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[24] = chanx_left_in[24]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[25] = chanx_left_in[25]; +// ----- Local connection due to Wire 26 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[26] = chanx_left_in[26]; +// ----- Local connection due to Wire 27 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[27] = chanx_left_in[27]; +// ----- Local connection due to Wire 28 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[28] = chanx_left_in[28]; +// ----- Local connection due to Wire 29 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[29] = chanx_left_in[29]; +// ----- Local connection due to Wire 30 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[0] = chanx_right_in[0]; +// ----- Local connection due to Wire 31 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[1] = chanx_right_in[1]; +// ----- Local connection due to Wire 32 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[2] = chanx_right_in[2]; +// ----- Local connection due to Wire 33 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[3] = chanx_right_in[3]; +// ----- Local connection due to Wire 34 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[4] = chanx_right_in[4]; +// ----- Local connection due to Wire 35 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[5] = chanx_right_in[5]; +// ----- Local connection due to Wire 36 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[6] = chanx_right_in[6]; +// ----- Local connection due to Wire 37 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[7] = chanx_right_in[7]; +// ----- Local connection due to Wire 38 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[8] = chanx_right_in[8]; +// ----- Local connection due to Wire 39 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[9] = chanx_right_in[9]; +// ----- Local connection due to Wire 40 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[10] = chanx_right_in[10]; +// ----- Local connection due to Wire 41 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[11] = chanx_right_in[11]; +// ----- Local connection due to Wire 42 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[12] = chanx_right_in[12]; +// ----- Local connection due to Wire 43 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[13] = chanx_right_in[13]; +// ----- Local connection due to Wire 44 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[14] = chanx_right_in[14]; +// ----- Local connection due to Wire 45 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[15] = chanx_right_in[15]; +// ----- Local connection due to Wire 46 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[16] = chanx_right_in[16]; +// ----- Local connection due to Wire 47 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[17] = chanx_right_in[17]; +// ----- Local connection due to Wire 48 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[18] = chanx_right_in[18]; +// ----- Local connection due to Wire 49 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[19] = chanx_right_in[19]; +// ----- Local connection due to Wire 50 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[20] = chanx_right_in[20]; +// ----- Local connection due to Wire 51 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[21] = chanx_right_in[21]; +// ----- Local connection due to Wire 52 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[22] = chanx_right_in[22]; +// ----- Local connection due to Wire 53 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[23] = chanx_right_in[23]; +// ----- Local connection due to Wire 54 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[24] = chanx_right_in[24]; +// ----- Local connection due to Wire 55 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[25] = chanx_right_in[25]; +// ----- Local connection due to Wire 56 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[26] = chanx_right_in[26]; +// ----- Local connection due to Wire 57 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[27] = chanx_right_in[27]; +// ----- Local connection due to Wire 58 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[28] = chanx_right_in[28]; +// ----- Local connection due to Wire 59 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[29] = chanx_right_in[29]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size12 mux_top_ipin_0 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram[0:3]), + .sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_1 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram[0:3]), + .sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_2 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram[0:3]), + .sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_3 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21], chanx_left_in[27], chanx_right_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram[0:3]), + .sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_)); + + mux_tree_tapbuf_size12_mem mem_top_ipin_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram[0:3])); + +endmodule +// ----- END Verilog module for cbx_1__0_ ----- + +//----- Default net type ----- +`default_nettype none + + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__1_.v new file mode 100644 index 0000000..f72e28e --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__1_.v @@ -0,0 +1,604 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Connection Blocks[1][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for cbx_1__1_ ----- +module cbx_1__1_(pReset, + prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:29] chanx_left_in; +//----- INPUT PORTS ----- +input [0:29] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:29] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:29] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:3] mux_top_ipin_0_undriven_sram_inv; +wire [0:3] mux_top_ipin_10_undriven_sram_inv; +wire [0:3] mux_top_ipin_11_undriven_sram_inv; +wire [0:3] mux_top_ipin_12_undriven_sram_inv; +wire [0:3] mux_top_ipin_13_undriven_sram_inv; +wire [0:3] mux_top_ipin_14_undriven_sram_inv; +wire [0:3] mux_top_ipin_15_undriven_sram_inv; +wire [0:3] mux_top_ipin_1_undriven_sram_inv; +wire [0:3] mux_top_ipin_2_undriven_sram_inv; +wire [0:3] mux_top_ipin_3_undriven_sram_inv; +wire [0:3] mux_top_ipin_4_undriven_sram_inv; +wire [0:3] mux_top_ipin_5_undriven_sram_inv; +wire [0:3] mux_top_ipin_6_undriven_sram_inv; +wire [0:3] mux_top_ipin_7_undriven_sram_inv; +wire [0:3] mux_top_ipin_8_undriven_sram_inv; +wire [0:3] mux_top_ipin_9_undriven_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_0_sram; +wire [0:3] mux_tree_tapbuf_size10_1_sram; +wire [0:3] mux_tree_tapbuf_size10_2_sram; +wire [0:3] mux_tree_tapbuf_size10_3_sram; +wire [0:3] mux_tree_tapbuf_size10_4_sram; +wire [0:3] mux_tree_tapbuf_size10_5_sram; +wire [0:3] mux_tree_tapbuf_size10_6_sram; +wire [0:3] mux_tree_tapbuf_size10_7_sram; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; +wire [0:3] mux_tree_tapbuf_size12_0_sram; +wire [0:3] mux_tree_tapbuf_size12_1_sram; +wire [0:3] mux_tree_tapbuf_size12_2_sram; +wire [0:3] mux_tree_tapbuf_size12_3_sram; +wire [0:3] mux_tree_tapbuf_size12_4_sram; +wire [0:3] mux_tree_tapbuf_size12_5_sram; +wire [0:3] mux_tree_tapbuf_size12_6_sram; +wire [0:3] mux_tree_tapbuf_size12_7_sram; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[0] = chanx_left_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[1] = chanx_left_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[2] = chanx_left_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[3] = chanx_left_in[3]; +// ----- Local connection due to Wire 4 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[4] = chanx_left_in[4]; +// ----- Local connection due to Wire 5 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[5] = chanx_left_in[5]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[6] = chanx_left_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[7] = chanx_left_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[8] = chanx_left_in[8]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[9] = chanx_left_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[10] = chanx_left_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[11] = chanx_left_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[12] = chanx_left_in[12]; +// ----- Local connection due to Wire 13 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[13] = chanx_left_in[13]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[14] = chanx_left_in[14]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[15] = chanx_left_in[15]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[16] = chanx_left_in[16]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[17] = chanx_left_in[17]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[18] = chanx_left_in[18]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[19] = chanx_left_in[19]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[20] = chanx_left_in[20]; +// ----- Local connection due to Wire 21 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[21] = chanx_left_in[21]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[22] = chanx_left_in[22]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[23] = chanx_left_in[23]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[24] = chanx_left_in[24]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[25] = chanx_left_in[25]; +// ----- Local connection due to Wire 26 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[26] = chanx_left_in[26]; +// ----- Local connection due to Wire 27 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[27] = chanx_left_in[27]; +// ----- Local connection due to Wire 28 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[28] = chanx_left_in[28]; +// ----- Local connection due to Wire 29 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[29] = chanx_left_in[29]; +// ----- Local connection due to Wire 30 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[0] = chanx_right_in[0]; +// ----- Local connection due to Wire 31 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[1] = chanx_right_in[1]; +// ----- Local connection due to Wire 32 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[2] = chanx_right_in[2]; +// ----- Local connection due to Wire 33 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[3] = chanx_right_in[3]; +// ----- Local connection due to Wire 34 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[4] = chanx_right_in[4]; +// ----- Local connection due to Wire 35 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[5] = chanx_right_in[5]; +// ----- Local connection due to Wire 36 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[6] = chanx_right_in[6]; +// ----- Local connection due to Wire 37 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[7] = chanx_right_in[7]; +// ----- Local connection due to Wire 38 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[8] = chanx_right_in[8]; +// ----- Local connection due to Wire 39 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[9] = chanx_right_in[9]; +// ----- Local connection due to Wire 40 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[10] = chanx_right_in[10]; +// ----- Local connection due to Wire 41 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[11] = chanx_right_in[11]; +// ----- Local connection due to Wire 42 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[12] = chanx_right_in[12]; +// ----- Local connection due to Wire 43 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[13] = chanx_right_in[13]; +// ----- Local connection due to Wire 44 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[14] = chanx_right_in[14]; +// ----- Local connection due to Wire 45 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[15] = chanx_right_in[15]; +// ----- Local connection due to Wire 46 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[16] = chanx_right_in[16]; +// ----- Local connection due to Wire 47 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[17] = chanx_right_in[17]; +// ----- Local connection due to Wire 48 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[18] = chanx_right_in[18]; +// ----- Local connection due to Wire 49 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[19] = chanx_right_in[19]; +// ----- Local connection due to Wire 50 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[20] = chanx_right_in[20]; +// ----- Local connection due to Wire 51 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[21] = chanx_right_in[21]; +// ----- Local connection due to Wire 52 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[22] = chanx_right_in[22]; +// ----- Local connection due to Wire 53 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[23] = chanx_right_in[23]; +// ----- Local connection due to Wire 54 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[24] = chanx_right_in[24]; +// ----- Local connection due to Wire 55 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[25] = chanx_right_in[25]; +// ----- Local connection due to Wire 56 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[26] = chanx_right_in[26]; +// ----- Local connection due to Wire 57 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[27] = chanx_right_in[27]; +// ----- Local connection due to Wire 58 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[28] = chanx_right_in[28]; +// ----- Local connection due to Wire 59 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[29] = chanx_right_in[29]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size12 mux_top_ipin_0 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram[0:3]), + .sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_2 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_1_sram[0:3]), + .sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_4 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_2_sram[0:3]), + .sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_6 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_3_sram[0:3]), + .sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_8 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_4_sram[0:3]), + .sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_10 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_5_sram[0:3]), + .sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_12 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_6_sram[0:3]), + .sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_7_sram[0:3]), + .sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_)); + + mux_tree_tapbuf_size12_mem mem_top_ipin_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_8 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram[0:3])); + + mux_tree_tapbuf_size10 mux_top_ipin_1 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[16], chanx_right_in[16], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_)); + + mux_tree_tapbuf_size10 mux_top_ipin_3 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[18], chanx_right_in[18], chanx_left_in[27], chanx_right_in[27]}), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_)); + + mux_tree_tapbuf_size10 mux_top_ipin_5 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[20], chanx_right_in[20], chanx_left_in[29], chanx_right_in[29]}), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_)); + + mux_tree_tapbuf_size10 mux_top_ipin_7 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[22], chanx_right_in[22]}), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_)); + + mux_tree_tapbuf_size10 mux_top_ipin_9 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_)); + + mux_tree_tapbuf_size10 mux_top_ipin_11 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_)); + + mux_tree_tapbuf_size10 mux_top_ipin_13 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_)); + + mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21]}), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_)); + + mux_tree_tapbuf_size10_mem mem_top_ipin_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_ipin_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_ipin_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_ipin_9 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_ipin_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_ipin_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3])); + +endmodule +// ----- END Verilog module for cbx_1__1_ ----- + +//----- Default net type ----- +`default_nettype none + + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__8_.v new file mode 100644 index 0000000..5dd04ca --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__8_.v @@ -0,0 +1,680 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Connection Blocks[1][8] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for cbx_1__8_ ----- +module cbx_1__8_(pReset, + prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:29] chanx_left_in; +//----- INPUT PORTS ----- +input [0:29] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:29] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:29] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:3] mux_bottom_ipin_0_undriven_sram_inv; +wire [0:3] mux_bottom_ipin_1_undriven_sram_inv; +wire [0:3] mux_bottom_ipin_2_undriven_sram_inv; +wire [0:3] mux_bottom_ipin_3_undriven_sram_inv; +wire [0:3] mux_top_ipin_0_undriven_sram_inv; +wire [0:3] mux_top_ipin_10_undriven_sram_inv; +wire [0:3] mux_top_ipin_11_undriven_sram_inv; +wire [0:3] mux_top_ipin_12_undriven_sram_inv; +wire [0:3] mux_top_ipin_13_undriven_sram_inv; +wire [0:3] mux_top_ipin_14_undriven_sram_inv; +wire [0:3] mux_top_ipin_15_undriven_sram_inv; +wire [0:3] mux_top_ipin_1_undriven_sram_inv; +wire [0:3] mux_top_ipin_2_undriven_sram_inv; +wire [0:3] mux_top_ipin_3_undriven_sram_inv; +wire [0:3] mux_top_ipin_4_undriven_sram_inv; +wire [0:3] mux_top_ipin_5_undriven_sram_inv; +wire [0:3] mux_top_ipin_6_undriven_sram_inv; +wire [0:3] mux_top_ipin_7_undriven_sram_inv; +wire [0:3] mux_top_ipin_8_undriven_sram_inv; +wire [0:3] mux_top_ipin_9_undriven_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_0_sram; +wire [0:3] mux_tree_tapbuf_size10_1_sram; +wire [0:3] mux_tree_tapbuf_size10_2_sram; +wire [0:3] mux_tree_tapbuf_size10_3_sram; +wire [0:3] mux_tree_tapbuf_size10_4_sram; +wire [0:3] mux_tree_tapbuf_size10_5_sram; +wire [0:3] mux_tree_tapbuf_size10_6_sram; +wire [0:3] mux_tree_tapbuf_size10_7_sram; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; +wire [0:3] mux_tree_tapbuf_size12_0_sram; +wire [0:3] mux_tree_tapbuf_size12_10_sram; +wire [0:3] mux_tree_tapbuf_size12_11_sram; +wire [0:3] mux_tree_tapbuf_size12_1_sram; +wire [0:3] mux_tree_tapbuf_size12_2_sram; +wire [0:3] mux_tree_tapbuf_size12_3_sram; +wire [0:3] mux_tree_tapbuf_size12_4_sram; +wire [0:3] mux_tree_tapbuf_size12_5_sram; +wire [0:3] mux_tree_tapbuf_size12_6_sram; +wire [0:3] mux_tree_tapbuf_size12_7_sram; +wire [0:3] mux_tree_tapbuf_size12_8_sram; +wire [0:3] mux_tree_tapbuf_size12_9_sram; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_9_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[0] = chanx_left_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[1] = chanx_left_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[2] = chanx_left_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[3] = chanx_left_in[3]; +// ----- Local connection due to Wire 4 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[4] = chanx_left_in[4]; +// ----- Local connection due to Wire 5 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[5] = chanx_left_in[5]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[6] = chanx_left_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[7] = chanx_left_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[8] = chanx_left_in[8]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[9] = chanx_left_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[10] = chanx_left_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[11] = chanx_left_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[12] = chanx_left_in[12]; +// ----- Local connection due to Wire 13 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[13] = chanx_left_in[13]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[14] = chanx_left_in[14]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[15] = chanx_left_in[15]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[16] = chanx_left_in[16]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[17] = chanx_left_in[17]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[18] = chanx_left_in[18]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[19] = chanx_left_in[19]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[20] = chanx_left_in[20]; +// ----- Local connection due to Wire 21 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[21] = chanx_left_in[21]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[22] = chanx_left_in[22]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[23] = chanx_left_in[23]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[24] = chanx_left_in[24]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[25] = chanx_left_in[25]; +// ----- Local connection due to Wire 26 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[26] = chanx_left_in[26]; +// ----- Local connection due to Wire 27 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[27] = chanx_left_in[27]; +// ----- Local connection due to Wire 28 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[28] = chanx_left_in[28]; +// ----- Local connection due to Wire 29 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[29] = chanx_left_in[29]; +// ----- Local connection due to Wire 30 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[0] = chanx_right_in[0]; +// ----- Local connection due to Wire 31 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[1] = chanx_right_in[1]; +// ----- Local connection due to Wire 32 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[2] = chanx_right_in[2]; +// ----- Local connection due to Wire 33 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[3] = chanx_right_in[3]; +// ----- Local connection due to Wire 34 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[4] = chanx_right_in[4]; +// ----- Local connection due to Wire 35 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[5] = chanx_right_in[5]; +// ----- Local connection due to Wire 36 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[6] = chanx_right_in[6]; +// ----- Local connection due to Wire 37 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[7] = chanx_right_in[7]; +// ----- Local connection due to Wire 38 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[8] = chanx_right_in[8]; +// ----- Local connection due to Wire 39 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[9] = chanx_right_in[9]; +// ----- Local connection due to Wire 40 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[10] = chanx_right_in[10]; +// ----- Local connection due to Wire 41 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[11] = chanx_right_in[11]; +// ----- Local connection due to Wire 42 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[12] = chanx_right_in[12]; +// ----- Local connection due to Wire 43 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[13] = chanx_right_in[13]; +// ----- Local connection due to Wire 44 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[14] = chanx_right_in[14]; +// ----- Local connection due to Wire 45 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[15] = chanx_right_in[15]; +// ----- Local connection due to Wire 46 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[16] = chanx_right_in[16]; +// ----- Local connection due to Wire 47 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[17] = chanx_right_in[17]; +// ----- Local connection due to Wire 48 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[18] = chanx_right_in[18]; +// ----- Local connection due to Wire 49 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[19] = chanx_right_in[19]; +// ----- Local connection due to Wire 50 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[20] = chanx_right_in[20]; +// ----- Local connection due to Wire 51 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[21] = chanx_right_in[21]; +// ----- Local connection due to Wire 52 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[22] = chanx_right_in[22]; +// ----- Local connection due to Wire 53 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[23] = chanx_right_in[23]; +// ----- Local connection due to Wire 54 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[24] = chanx_right_in[24]; +// ----- Local connection due to Wire 55 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[25] = chanx_right_in[25]; +// ----- Local connection due to Wire 56 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[26] = chanx_right_in[26]; +// ----- Local connection due to Wire 57 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[27] = chanx_right_in[27]; +// ----- Local connection due to Wire 58 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[28] = chanx_right_in[28]; +// ----- Local connection due to Wire 59 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[29] = chanx_right_in[29]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size12 mux_bottom_ipin_0 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram[0:3]), + .sram_inv(mux_bottom_ipin_0_undriven_sram_inv[0:3]), + .out(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_)); + + mux_tree_tapbuf_size12 mux_bottom_ipin_1 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram[0:3]), + .sram_inv(mux_bottom_ipin_1_undriven_sram_inv[0:3]), + .out(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_)); + + mux_tree_tapbuf_size12 mux_bottom_ipin_2 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram[0:3]), + .sram_inv(mux_bottom_ipin_2_undriven_sram_inv[0:3]), + .out(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_)); + + mux_tree_tapbuf_size12 mux_bottom_ipin_3 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21], chanx_left_in[27], chanx_right_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram[0:3]), + .sram_inv(mux_bottom_ipin_3_undriven_sram_inv[0:3]), + .out(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_0 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_4_sram[0:3]), + .sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_2 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_5_sram[0:3]), + .sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_4 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_6_sram[0:3]), + .sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_6 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_7_sram[0:3]), + .sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_8 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_8_sram[0:3]), + .sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_10 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_9_sram[0:3]), + .sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_12 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_10_sram[0:3]), + .sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_)); + + mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_11_sram[0:3]), + .sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_)); + + mux_tree_tapbuf_size12_mem mem_bottom_ipin_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_bottom_ipin_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_bottom_ipin_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_bottom_ipin_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_8 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_8_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_9_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_10_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_11_sram[0:3])); + + mux_tree_tapbuf_size10 mux_top_ipin_1 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[20], chanx_right_in[20], chanx_left_in[29], chanx_right_in[29]}), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_)); + + mux_tree_tapbuf_size10 mux_top_ipin_3 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[22], chanx_right_in[22]}), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_)); + + mux_tree_tapbuf_size10 mux_top_ipin_5 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_)); + + mux_tree_tapbuf_size10 mux_top_ipin_7 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_)); + + mux_tree_tapbuf_size10 mux_top_ipin_9 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_)); + + mux_tree_tapbuf_size10 mux_top_ipin_11 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21]}), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_)); + + mux_tree_tapbuf_size10 mux_top_ipin_13 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[17], chanx_right_in[17], chanx_left_in[23], chanx_right_in[23]}), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_)); + + mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_)); + + mux_tree_tapbuf_size10_mem mem_top_ipin_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_ipin_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_ipin_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_ipin_9 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_ipin_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_ipin_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3])); + +endmodule +// ----- END Verilog module for cbx_1__8_ ----- + +//----- Default net type ----- +`default_nettype none + + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_0__1_.v new file mode 100644 index 0000000..676a6aa --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_0__1_.v @@ -0,0 +1,376 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Connection Blocks[0][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for cby_0__1_ ----- +module cby_0__1_(pReset, + prog_clk, + chany_bottom_in, + chany_top_in, + ccff_head, + chany_bottom_out, + chany_top_out, + left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:29] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:29] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:29] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:29] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:3] mux_right_ipin_0_undriven_sram_inv; +wire [0:3] mux_right_ipin_1_undriven_sram_inv; +wire [0:3] mux_right_ipin_2_undriven_sram_inv; +wire [0:3] mux_right_ipin_3_undriven_sram_inv; +wire [0:3] mux_tree_tapbuf_size12_0_sram; +wire [0:3] mux_tree_tapbuf_size12_1_sram; +wire [0:3] mux_tree_tapbuf_size12_2_sram; +wire [0:3] mux_tree_tapbuf_size12_3_sram; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[0] = chany_bottom_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[1] = chany_bottom_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[2] = chany_bottom_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[3] = chany_bottom_in[3]; +// ----- Local connection due to Wire 4 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[4] = chany_bottom_in[4]; +// ----- Local connection due to Wire 5 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[5] = chany_bottom_in[5]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[6] = chany_bottom_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[7] = chany_bottom_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[8] = chany_bottom_in[8]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[9] = chany_bottom_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[10] = chany_bottom_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[11] = chany_bottom_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[12] = chany_bottom_in[12]; +// ----- Local connection due to Wire 13 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[13] = chany_bottom_in[13]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[14] = chany_bottom_in[14]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[15] = chany_bottom_in[15]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[16] = chany_bottom_in[16]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[17] = chany_bottom_in[17]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[18] = chany_bottom_in[18]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[19] = chany_bottom_in[19]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[20] = chany_bottom_in[20]; +// ----- Local connection due to Wire 21 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[21] = chany_bottom_in[21]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[22] = chany_bottom_in[22]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[23] = chany_bottom_in[23]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[24] = chany_bottom_in[24]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[25] = chany_bottom_in[25]; +// ----- Local connection due to Wire 26 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[26] = chany_bottom_in[26]; +// ----- Local connection due to Wire 27 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[27] = chany_bottom_in[27]; +// ----- Local connection due to Wire 28 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[28] = chany_bottom_in[28]; +// ----- Local connection due to Wire 29 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[29] = chany_bottom_in[29]; +// ----- Local connection due to Wire 30 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[0] = chany_top_in[0]; +// ----- Local connection due to Wire 31 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[1] = chany_top_in[1]; +// ----- Local connection due to Wire 32 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[2] = chany_top_in[2]; +// ----- Local connection due to Wire 33 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[3] = chany_top_in[3]; +// ----- Local connection due to Wire 34 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[4] = chany_top_in[4]; +// ----- Local connection due to Wire 35 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[5] = chany_top_in[5]; +// ----- Local connection due to Wire 36 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[6] = chany_top_in[6]; +// ----- Local connection due to Wire 37 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[7] = chany_top_in[7]; +// ----- Local connection due to Wire 38 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[8] = chany_top_in[8]; +// ----- Local connection due to Wire 39 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[9] = chany_top_in[9]; +// ----- Local connection due to Wire 40 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[10] = chany_top_in[10]; +// ----- Local connection due to Wire 41 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[11] = chany_top_in[11]; +// ----- Local connection due to Wire 42 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[12] = chany_top_in[12]; +// ----- Local connection due to Wire 43 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[13] = chany_top_in[13]; +// ----- Local connection due to Wire 44 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[14] = chany_top_in[14]; +// ----- Local connection due to Wire 45 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[15] = chany_top_in[15]; +// ----- Local connection due to Wire 46 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[16] = chany_top_in[16]; +// ----- Local connection due to Wire 47 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[17] = chany_top_in[17]; +// ----- Local connection due to Wire 48 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[18] = chany_top_in[18]; +// ----- Local connection due to Wire 49 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[19] = chany_top_in[19]; +// ----- Local connection due to Wire 50 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[20] = chany_top_in[20]; +// ----- Local connection due to Wire 51 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[21] = chany_top_in[21]; +// ----- Local connection due to Wire 52 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[22] = chany_top_in[22]; +// ----- Local connection due to Wire 53 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[23] = chany_top_in[23]; +// ----- Local connection due to Wire 54 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[24] = chany_top_in[24]; +// ----- Local connection due to Wire 55 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[25] = chany_top_in[25]; +// ----- Local connection due to Wire 56 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[26] = chany_top_in[26]; +// ----- Local connection due to Wire 57 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[27] = chany_top_in[27]; +// ----- Local connection due to Wire 58 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[28] = chany_top_in[28]; +// ----- Local connection due to Wire 59 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[29] = chany_top_in[29]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size12 mux_right_ipin_0 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram[0:3]), + .sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_1 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram[0:3]), + .sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_2 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram[0:3]), + .sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_3 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21], chany_bottom_in[27], chany_top_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram[0:3]), + .sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_)); + + mux_tree_tapbuf_size12_mem mem_right_ipin_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram[0:3])); + +endmodule +// ----- END Verilog module for cby_0__1_ ----- + +//----- Default net type ----- +`default_nettype none + + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_1__1_.v new file mode 100644 index 0000000..1e53e9e --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_1__1_.v @@ -0,0 +1,604 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Connection Blocks[1][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for cby_1__1_ ----- +module cby_1__1_(pReset, + prog_clk, + chany_bottom_in, + chany_top_in, + ccff_head, + chany_bottom_out, + chany_top_out, + left_grid_right_width_0_height_0_subtile_0__pin_I4_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:29] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:29] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:29] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:29] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:3] mux_right_ipin_0_undriven_sram_inv; +wire [0:3] mux_right_ipin_10_undriven_sram_inv; +wire [0:3] mux_right_ipin_11_undriven_sram_inv; +wire [0:3] mux_right_ipin_12_undriven_sram_inv; +wire [0:3] mux_right_ipin_13_undriven_sram_inv; +wire [0:3] mux_right_ipin_14_undriven_sram_inv; +wire [0:3] mux_right_ipin_15_undriven_sram_inv; +wire [0:3] mux_right_ipin_1_undriven_sram_inv; +wire [0:3] mux_right_ipin_2_undriven_sram_inv; +wire [0:3] mux_right_ipin_3_undriven_sram_inv; +wire [0:3] mux_right_ipin_4_undriven_sram_inv; +wire [0:3] mux_right_ipin_5_undriven_sram_inv; +wire [0:3] mux_right_ipin_6_undriven_sram_inv; +wire [0:3] mux_right_ipin_7_undriven_sram_inv; +wire [0:3] mux_right_ipin_8_undriven_sram_inv; +wire [0:3] mux_right_ipin_9_undriven_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_0_sram; +wire [0:3] mux_tree_tapbuf_size10_1_sram; +wire [0:3] mux_tree_tapbuf_size10_2_sram; +wire [0:3] mux_tree_tapbuf_size10_3_sram; +wire [0:3] mux_tree_tapbuf_size10_4_sram; +wire [0:3] mux_tree_tapbuf_size10_5_sram; +wire [0:3] mux_tree_tapbuf_size10_6_sram; +wire [0:3] mux_tree_tapbuf_size10_7_sram; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; +wire [0:3] mux_tree_tapbuf_size12_0_sram; +wire [0:3] mux_tree_tapbuf_size12_1_sram; +wire [0:3] mux_tree_tapbuf_size12_2_sram; +wire [0:3] mux_tree_tapbuf_size12_3_sram; +wire [0:3] mux_tree_tapbuf_size12_4_sram; +wire [0:3] mux_tree_tapbuf_size12_5_sram; +wire [0:3] mux_tree_tapbuf_size12_6_sram; +wire [0:3] mux_tree_tapbuf_size12_7_sram; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[0] = chany_bottom_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[1] = chany_bottom_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[2] = chany_bottom_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[3] = chany_bottom_in[3]; +// ----- Local connection due to Wire 4 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[4] = chany_bottom_in[4]; +// ----- Local connection due to Wire 5 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[5] = chany_bottom_in[5]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[6] = chany_bottom_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[7] = chany_bottom_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[8] = chany_bottom_in[8]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[9] = chany_bottom_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[10] = chany_bottom_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[11] = chany_bottom_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[12] = chany_bottom_in[12]; +// ----- Local connection due to Wire 13 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[13] = chany_bottom_in[13]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[14] = chany_bottom_in[14]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[15] = chany_bottom_in[15]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[16] = chany_bottom_in[16]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[17] = chany_bottom_in[17]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[18] = chany_bottom_in[18]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[19] = chany_bottom_in[19]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[20] = chany_bottom_in[20]; +// ----- Local connection due to Wire 21 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[21] = chany_bottom_in[21]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[22] = chany_bottom_in[22]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[23] = chany_bottom_in[23]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[24] = chany_bottom_in[24]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[25] = chany_bottom_in[25]; +// ----- Local connection due to Wire 26 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[26] = chany_bottom_in[26]; +// ----- Local connection due to Wire 27 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[27] = chany_bottom_in[27]; +// ----- Local connection due to Wire 28 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[28] = chany_bottom_in[28]; +// ----- Local connection due to Wire 29 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[29] = chany_bottom_in[29]; +// ----- Local connection due to Wire 30 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[0] = chany_top_in[0]; +// ----- Local connection due to Wire 31 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[1] = chany_top_in[1]; +// ----- Local connection due to Wire 32 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[2] = chany_top_in[2]; +// ----- Local connection due to Wire 33 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[3] = chany_top_in[3]; +// ----- Local connection due to Wire 34 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[4] = chany_top_in[4]; +// ----- Local connection due to Wire 35 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[5] = chany_top_in[5]; +// ----- Local connection due to Wire 36 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[6] = chany_top_in[6]; +// ----- Local connection due to Wire 37 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[7] = chany_top_in[7]; +// ----- Local connection due to Wire 38 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[8] = chany_top_in[8]; +// ----- Local connection due to Wire 39 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[9] = chany_top_in[9]; +// ----- Local connection due to Wire 40 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[10] = chany_top_in[10]; +// ----- Local connection due to Wire 41 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[11] = chany_top_in[11]; +// ----- Local connection due to Wire 42 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[12] = chany_top_in[12]; +// ----- Local connection due to Wire 43 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[13] = chany_top_in[13]; +// ----- Local connection due to Wire 44 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[14] = chany_top_in[14]; +// ----- Local connection due to Wire 45 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[15] = chany_top_in[15]; +// ----- Local connection due to Wire 46 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[16] = chany_top_in[16]; +// ----- Local connection due to Wire 47 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[17] = chany_top_in[17]; +// ----- Local connection due to Wire 48 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[18] = chany_top_in[18]; +// ----- Local connection due to Wire 49 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[19] = chany_top_in[19]; +// ----- Local connection due to Wire 50 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[20] = chany_top_in[20]; +// ----- Local connection due to Wire 51 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[21] = chany_top_in[21]; +// ----- Local connection due to Wire 52 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[22] = chany_top_in[22]; +// ----- Local connection due to Wire 53 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[23] = chany_top_in[23]; +// ----- Local connection due to Wire 54 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[24] = chany_top_in[24]; +// ----- Local connection due to Wire 55 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[25] = chany_top_in[25]; +// ----- Local connection due to Wire 56 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[26] = chany_top_in[26]; +// ----- Local connection due to Wire 57 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[27] = chany_top_in[27]; +// ----- Local connection due to Wire 58 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[28] = chany_top_in[28]; +// ----- Local connection due to Wire 59 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[29] = chany_top_in[29]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size12 mux_right_ipin_0 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram[0:3]), + .sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_2 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_1_sram[0:3]), + .sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_4 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_2_sram[0:3]), + .sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_6 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_3_sram[0:3]), + .sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_8 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_4_sram[0:3]), + .sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_10 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_5_sram[0:3]), + .sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_12 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_6_sram[0:3]), + .sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_7_sram[0:3]), + .sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_)); + + mux_tree_tapbuf_size12_mem mem_right_ipin_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_8 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram[0:3])); + + mux_tree_tapbuf_size10 mux_right_ipin_1 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_)); + + mux_tree_tapbuf_size10 mux_right_ipin_3 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[27], chany_top_in[27]}), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_)); + + mux_tree_tapbuf_size10 mux_right_ipin_5 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[29], chany_top_in[29]}), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_)); + + mux_tree_tapbuf_size10 mux_right_ipin_7 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[22], chany_top_in[22]}), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_)); + + mux_tree_tapbuf_size10 mux_right_ipin_9 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_)); + + mux_tree_tapbuf_size10 mux_right_ipin_11 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_)); + + mux_tree_tapbuf_size10 mux_right_ipin_13 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_)); + + mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21]}), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_)); + + mux_tree_tapbuf_size10_mem mem_right_ipin_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_9 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3])); + +endmodule +// ----- END Verilog module for cby_1__1_ ----- + +//----- Default net type ----- +`default_nettype none + + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_8__1_.v new file mode 100644 index 0000000..2f01006 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_8__1_.v @@ -0,0 +1,680 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Connection Blocks[8][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for cby_8__1_ ----- +module cby_8__1_(pReset, + prog_clk, + chany_bottom_in, + chany_top_in, + ccff_head, + chany_bottom_out, + chany_top_out, + right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:29] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:29] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:29] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:29] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:3] mux_left_ipin_0_undriven_sram_inv; +wire [0:3] mux_left_ipin_1_undriven_sram_inv; +wire [0:3] mux_left_ipin_2_undriven_sram_inv; +wire [0:3] mux_left_ipin_3_undriven_sram_inv; +wire [0:3] mux_right_ipin_0_undriven_sram_inv; +wire [0:3] mux_right_ipin_10_undriven_sram_inv; +wire [0:3] mux_right_ipin_11_undriven_sram_inv; +wire [0:3] mux_right_ipin_12_undriven_sram_inv; +wire [0:3] mux_right_ipin_13_undriven_sram_inv; +wire [0:3] mux_right_ipin_14_undriven_sram_inv; +wire [0:3] mux_right_ipin_15_undriven_sram_inv; +wire [0:3] mux_right_ipin_1_undriven_sram_inv; +wire [0:3] mux_right_ipin_2_undriven_sram_inv; +wire [0:3] mux_right_ipin_3_undriven_sram_inv; +wire [0:3] mux_right_ipin_4_undriven_sram_inv; +wire [0:3] mux_right_ipin_5_undriven_sram_inv; +wire [0:3] mux_right_ipin_6_undriven_sram_inv; +wire [0:3] mux_right_ipin_7_undriven_sram_inv; +wire [0:3] mux_right_ipin_8_undriven_sram_inv; +wire [0:3] mux_right_ipin_9_undriven_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_0_sram; +wire [0:3] mux_tree_tapbuf_size10_1_sram; +wire [0:3] mux_tree_tapbuf_size10_2_sram; +wire [0:3] mux_tree_tapbuf_size10_3_sram; +wire [0:3] mux_tree_tapbuf_size10_4_sram; +wire [0:3] mux_tree_tapbuf_size10_5_sram; +wire [0:3] mux_tree_tapbuf_size10_6_sram; +wire [0:3] mux_tree_tapbuf_size10_7_sram; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; +wire [0:3] mux_tree_tapbuf_size12_0_sram; +wire [0:3] mux_tree_tapbuf_size12_10_sram; +wire [0:3] mux_tree_tapbuf_size12_11_sram; +wire [0:3] mux_tree_tapbuf_size12_1_sram; +wire [0:3] mux_tree_tapbuf_size12_2_sram; +wire [0:3] mux_tree_tapbuf_size12_3_sram; +wire [0:3] mux_tree_tapbuf_size12_4_sram; +wire [0:3] mux_tree_tapbuf_size12_5_sram; +wire [0:3] mux_tree_tapbuf_size12_6_sram; +wire [0:3] mux_tree_tapbuf_size12_7_sram; +wire [0:3] mux_tree_tapbuf_size12_8_sram; +wire [0:3] mux_tree_tapbuf_size12_9_sram; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_9_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[0] = chany_bottom_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[1] = chany_bottom_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[2] = chany_bottom_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[3] = chany_bottom_in[3]; +// ----- Local connection due to Wire 4 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[4] = chany_bottom_in[4]; +// ----- Local connection due to Wire 5 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[5] = chany_bottom_in[5]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[6] = chany_bottom_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[7] = chany_bottom_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[8] = chany_bottom_in[8]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[9] = chany_bottom_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[10] = chany_bottom_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[11] = chany_bottom_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[12] = chany_bottom_in[12]; +// ----- Local connection due to Wire 13 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[13] = chany_bottom_in[13]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[14] = chany_bottom_in[14]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[15] = chany_bottom_in[15]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[16] = chany_bottom_in[16]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[17] = chany_bottom_in[17]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[18] = chany_bottom_in[18]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[19] = chany_bottom_in[19]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[20] = chany_bottom_in[20]; +// ----- Local connection due to Wire 21 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[21] = chany_bottom_in[21]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[22] = chany_bottom_in[22]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[23] = chany_bottom_in[23]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[24] = chany_bottom_in[24]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[25] = chany_bottom_in[25]; +// ----- Local connection due to Wire 26 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[26] = chany_bottom_in[26]; +// ----- Local connection due to Wire 27 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[27] = chany_bottom_in[27]; +// ----- Local connection due to Wire 28 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[28] = chany_bottom_in[28]; +// ----- Local connection due to Wire 29 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[29] = chany_bottom_in[29]; +// ----- Local connection due to Wire 30 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[0] = chany_top_in[0]; +// ----- Local connection due to Wire 31 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[1] = chany_top_in[1]; +// ----- Local connection due to Wire 32 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[2] = chany_top_in[2]; +// ----- Local connection due to Wire 33 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[3] = chany_top_in[3]; +// ----- Local connection due to Wire 34 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[4] = chany_top_in[4]; +// ----- Local connection due to Wire 35 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[5] = chany_top_in[5]; +// ----- Local connection due to Wire 36 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[6] = chany_top_in[6]; +// ----- Local connection due to Wire 37 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[7] = chany_top_in[7]; +// ----- Local connection due to Wire 38 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[8] = chany_top_in[8]; +// ----- Local connection due to Wire 39 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[9] = chany_top_in[9]; +// ----- Local connection due to Wire 40 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[10] = chany_top_in[10]; +// ----- Local connection due to Wire 41 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[11] = chany_top_in[11]; +// ----- Local connection due to Wire 42 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[12] = chany_top_in[12]; +// ----- Local connection due to Wire 43 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[13] = chany_top_in[13]; +// ----- Local connection due to Wire 44 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[14] = chany_top_in[14]; +// ----- Local connection due to Wire 45 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[15] = chany_top_in[15]; +// ----- Local connection due to Wire 46 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[16] = chany_top_in[16]; +// ----- Local connection due to Wire 47 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[17] = chany_top_in[17]; +// ----- Local connection due to Wire 48 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[18] = chany_top_in[18]; +// ----- Local connection due to Wire 49 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[19] = chany_top_in[19]; +// ----- Local connection due to Wire 50 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[20] = chany_top_in[20]; +// ----- Local connection due to Wire 51 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[21] = chany_top_in[21]; +// ----- Local connection due to Wire 52 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[22] = chany_top_in[22]; +// ----- Local connection due to Wire 53 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[23] = chany_top_in[23]; +// ----- Local connection due to Wire 54 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[24] = chany_top_in[24]; +// ----- Local connection due to Wire 55 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[25] = chany_top_in[25]; +// ----- Local connection due to Wire 56 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[26] = chany_top_in[26]; +// ----- Local connection due to Wire 57 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[27] = chany_top_in[27]; +// ----- Local connection due to Wire 58 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[28] = chany_top_in[28]; +// ----- Local connection due to Wire 59 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[29] = chany_top_in[29]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size12 mux_left_ipin_0 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram[0:3]), + .sram_inv(mux_left_ipin_0_undriven_sram_inv[0:3]), + .out(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_)); + + mux_tree_tapbuf_size12 mux_left_ipin_1 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram[0:3]), + .sram_inv(mux_left_ipin_1_undriven_sram_inv[0:3]), + .out(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_)); + + mux_tree_tapbuf_size12 mux_left_ipin_2 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram[0:3]), + .sram_inv(mux_left_ipin_2_undriven_sram_inv[0:3]), + .out(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_)); + + mux_tree_tapbuf_size12 mux_left_ipin_3 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21], chany_bottom_in[27], chany_top_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram[0:3]), + .sram_inv(mux_left_ipin_3_undriven_sram_inv[0:3]), + .out(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_0 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_4_sram[0:3]), + .sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_2 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_5_sram[0:3]), + .sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_4 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_6_sram[0:3]), + .sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_6 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_7_sram[0:3]), + .sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_8 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_8_sram[0:3]), + .sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_10 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_9_sram[0:3]), + .sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_12 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_10_sram[0:3]), + .sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_)); + + mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_11_sram[0:3]), + .sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_)); + + mux_tree_tapbuf_size12_mem mem_left_ipin_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_left_ipin_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_left_ipin_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_left_ipin_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_8 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_8_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_9_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_10_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_11_sram[0:3])); + + mux_tree_tapbuf_size10 mux_right_ipin_1 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[29], chany_top_in[29]}), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_)); + + mux_tree_tapbuf_size10 mux_right_ipin_3 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[22], chany_top_in[22]}), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_)); + + mux_tree_tapbuf_size10 mux_right_ipin_5 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_)); + + mux_tree_tapbuf_size10 mux_right_ipin_7 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_)); + + mux_tree_tapbuf_size10 mux_right_ipin_9 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_)); + + mux_tree_tapbuf_size10 mux_right_ipin_11 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21]}), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_)); + + mux_tree_tapbuf_size10 mux_right_ipin_13 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[23], chany_top_in[23]}), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_)); + + mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_)); + + mux_tree_tapbuf_size10_mem mem_right_ipin_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_9 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3])); + +endmodule +// ----- END Verilog module for cby_8__1_ ----- + +//----- Default net type ----- +`default_nettype none + + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__0_.v new file mode 100644 index 0000000..6b894fa --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__0_.v @@ -0,0 +1,755 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[0][0] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_0__0_ ----- +module sb_0__0_(pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + chanx_right_in, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_right_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:29] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:29] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:29] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:29] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:1] mux_right_track_0_undriven_sram_inv; +wire [0:1] mux_right_track_10_undriven_sram_inv; +wire [0:1] mux_right_track_12_undriven_sram_inv; +wire [0:1] mux_right_track_14_undriven_sram_inv; +wire [0:1] mux_right_track_16_undriven_sram_inv; +wire [0:1] mux_right_track_18_undriven_sram_inv; +wire [0:1] mux_right_track_28_undriven_sram_inv; +wire [0:1] mux_right_track_2_undriven_sram_inv; +wire [0:1] mux_right_track_30_undriven_sram_inv; +wire [0:1] mux_right_track_32_undriven_sram_inv; +wire [0:1] mux_right_track_34_undriven_sram_inv; +wire [0:1] mux_right_track_44_undriven_sram_inv; +wire [0:1] mux_right_track_46_undriven_sram_inv; +wire [0:1] mux_right_track_48_undriven_sram_inv; +wire [0:1] mux_right_track_4_undriven_sram_inv; +wire [0:1] mux_right_track_50_undriven_sram_inv; +wire [0:1] mux_right_track_6_undriven_sram_inv; +wire [0:1] mux_right_track_8_undriven_sram_inv; +wire [0:1] mux_top_track_0_undriven_sram_inv; +wire [0:1] mux_top_track_10_undriven_sram_inv; +wire [0:1] mux_top_track_12_undriven_sram_inv; +wire [0:1] mux_top_track_14_undriven_sram_inv; +wire [0:1] mux_top_track_16_undriven_sram_inv; +wire [0:1] mux_top_track_18_undriven_sram_inv; +wire [0:1] mux_top_track_28_undriven_sram_inv; +wire [0:1] mux_top_track_2_undriven_sram_inv; +wire [0:1] mux_top_track_30_undriven_sram_inv; +wire [0:1] mux_top_track_32_undriven_sram_inv; +wire [0:1] mux_top_track_34_undriven_sram_inv; +wire [0:1] mux_top_track_44_undriven_sram_inv; +wire [0:1] mux_top_track_46_undriven_sram_inv; +wire [0:1] mux_top_track_48_undriven_sram_inv; +wire [0:1] mux_top_track_4_undriven_sram_inv; +wire [0:1] mux_top_track_50_undriven_sram_inv; +wire [0:1] mux_top_track_6_undriven_sram_inv; +wire [0:1] mux_top_track_8_undriven_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_10_sram; +wire [0:1] mux_tree_tapbuf_size2_11_sram; +wire [0:1] mux_tree_tapbuf_size2_12_sram; +wire [0:1] mux_tree_tapbuf_size2_13_sram; +wire [0:1] mux_tree_tapbuf_size2_14_sram; +wire [0:1] mux_tree_tapbuf_size2_15_sram; +wire [0:1] mux_tree_tapbuf_size2_16_sram; +wire [0:1] mux_tree_tapbuf_size2_17_sram; +wire [0:1] mux_tree_tapbuf_size2_18_sram; +wire [0:1] mux_tree_tapbuf_size2_19_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_20_sram; +wire [0:1] mux_tree_tapbuf_size2_21_sram; +wire [0:1] mux_tree_tapbuf_size2_22_sram; +wire [0:1] mux_tree_tapbuf_size2_23_sram; +wire [0:1] mux_tree_tapbuf_size2_24_sram; +wire [0:1] mux_tree_tapbuf_size2_25_sram; +wire [0:1] mux_tree_tapbuf_size2_26_sram; +wire [0:1] mux_tree_tapbuf_size2_27_sram; +wire [0:1] mux_tree_tapbuf_size2_28_sram; +wire [0:1] mux_tree_tapbuf_size2_29_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_30_sram; +wire [0:1] mux_tree_tapbuf_size2_31_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_7_sram; +wire [0:1] mux_tree_tapbuf_size2_8_sram; +wire [0:1] mux_tree_tapbuf_size2_9_sram; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[10] = chany_top_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[11] = chany_top_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[12] = chany_top_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[13] = chany_top_in[12]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[18] = chany_top_in[17]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[19] = chany_top_in[18]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[20] = chany_top_in[19]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[21] = chany_top_in[20]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[26] = chany_top_in[25]; +// ----- Local connection due to Wire 26 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[27] = chany_top_in[26]; +// ----- Local connection due to Wire 27 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[28] = chany_top_in[27]; +// ----- Local connection due to Wire 28 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[29] = chany_top_in[28]; +// ----- Local connection due to Wire 34 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[29] = chanx_right_in[0]; +// ----- Local connection due to Wire 45 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[10] = chanx_right_in[11]; +// ----- Local connection due to Wire 46 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[11] = chanx_right_in[12]; +// ----- Local connection due to Wire 47 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[12] = chanx_right_in[13]; +// ----- Local connection due to Wire 48 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[13] = chanx_right_in[14]; +// ----- Local connection due to Wire 53 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[18] = chanx_right_in[19]; +// ----- Local connection due to Wire 54 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[19] = chanx_right_in[20]; +// ----- Local connection due to Wire 55 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[20] = chanx_right_in[21]; +// ----- Local connection due to Wire 56 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[21] = chanx_right_in[22]; +// ----- Local connection due to Wire 61 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[26] = chanx_right_in[27]; +// ----- Local connection due to Wire 62 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[27] = chanx_right_in[28]; +// ----- Local connection due to Wire 63 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[28] = chanx_right_in[29]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size3 mux_top_track_0 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[1]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_top_track_0_undriven_sram_inv[0:1]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size3 mux_top_track_6 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[4]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_top_track_6_undriven_sram_inv[0:1]), + .out(chany_top_out[3])); + + mux_tree_tapbuf_size3 mux_right_track_0 ( + .in({chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_right_track_0_undriven_sram_inv[0:1]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size3 mux_right_track_6 ( + .in({chany_top_in[2], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_right_track_6_undriven_sram_inv[0:1]), + .out(chanx_right_out[3])); + + mux_tree_tapbuf_size3_mem mem_top_track_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1])); + + mux_tree_tapbuf_size2 mux_top_track_2 ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[2]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_top_track_2_undriven_sram_inv[0:1]), + .out(chany_top_out[1])); + + mux_tree_tapbuf_size2 mux_top_track_4 ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[3]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_top_track_4_undriven_sram_inv[0:1]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size2 mux_top_track_8 ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[5]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_top_track_8_undriven_sram_inv[0:1]), + .out(chany_top_out[4])); + + mux_tree_tapbuf_size2 mux_top_track_10 ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[6]}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_top_track_10_undriven_sram_inv[0:1]), + .out(chany_top_out[5])); + + mux_tree_tapbuf_size2 mux_top_track_12 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[7]}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_top_track_12_undriven_sram_inv[0:1]), + .out(chany_top_out[6])); + + mux_tree_tapbuf_size2 mux_top_track_14 ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[8]}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_top_track_14_undriven_sram_inv[0:1]), + .out(chany_top_out[7])); + + mux_tree_tapbuf_size2 mux_top_track_16 ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[9]}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_top_track_16_undriven_sram_inv[0:1]), + .out(chany_top_out[8])); + + mux_tree_tapbuf_size2 mux_top_track_18 ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[10]}), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_top_track_18_undriven_sram_inv[0:1]), + .out(chany_top_out[9])); + + mux_tree_tapbuf_size2 mux_top_track_28 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[15]}), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_top_track_28_undriven_sram_inv[0:1]), + .out(chany_top_out[14])); + + mux_tree_tapbuf_size2 mux_top_track_30 ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[16]}), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_top_track_30_undriven_sram_inv[0:1]), + .out(chany_top_out[15])); + + mux_tree_tapbuf_size2 mux_top_track_32 ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[17]}), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_top_track_32_undriven_sram_inv[0:1]), + .out(chany_top_out[16])); + + mux_tree_tapbuf_size2 mux_top_track_34 ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[18]}), + .sram(mux_tree_tapbuf_size2_11_sram[0:1]), + .sram_inv(mux_top_track_34_undriven_sram_inv[0:1]), + .out(chany_top_out[17])); + + mux_tree_tapbuf_size2 mux_top_track_44 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[23]}), + .sram(mux_tree_tapbuf_size2_12_sram[0:1]), + .sram_inv(mux_top_track_44_undriven_sram_inv[0:1]), + .out(chany_top_out[22])); + + mux_tree_tapbuf_size2 mux_top_track_46 ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size2_13_sram[0:1]), + .sram_inv(mux_top_track_46_undriven_sram_inv[0:1]), + .out(chany_top_out[23])); + + mux_tree_tapbuf_size2 mux_top_track_48 ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size2_14_sram[0:1]), + .sram_inv(mux_top_track_48_undriven_sram_inv[0:1]), + .out(chany_top_out[24])); + + mux_tree_tapbuf_size2 mux_top_track_50 ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size2_15_sram[0:1]), + .sram_inv(mux_top_track_50_undriven_sram_inv[0:1]), + .out(chany_top_out[25])); + + mux_tree_tapbuf_size2 mux_right_track_2 ( + .in({chany_top_in[0], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_16_sram[0:1]), + .sram_inv(mux_right_track_2_undriven_sram_inv[0:1]), + .out(chanx_right_out[1])); + + mux_tree_tapbuf_size2 mux_right_track_4 ( + .in({chany_top_in[1], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_17_sram[0:1]), + .sram_inv(mux_right_track_4_undriven_sram_inv[0:1]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size2 mux_right_track_8 ( + .in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_18_sram[0:1]), + .sram_inv(mux_right_track_8_undriven_sram_inv[0:1]), + .out(chanx_right_out[4])); + + mux_tree_tapbuf_size2 mux_right_track_10 ( + .in({chany_top_in[4], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_19_sram[0:1]), + .sram_inv(mux_right_track_10_undriven_sram_inv[0:1]), + .out(chanx_right_out[5])); + + mux_tree_tapbuf_size2 mux_right_track_12 ( + .in({chany_top_in[5], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_20_sram[0:1]), + .sram_inv(mux_right_track_12_undriven_sram_inv[0:1]), + .out(chanx_right_out[6])); + + mux_tree_tapbuf_size2 mux_right_track_14 ( + .in({chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram[0:1]), + .sram_inv(mux_right_track_14_undriven_sram_inv[0:1]), + .out(chanx_right_out[7])); + + mux_tree_tapbuf_size2 mux_right_track_16 ( + .in({chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_22_sram[0:1]), + .sram_inv(mux_right_track_16_undriven_sram_inv[0:1]), + .out(chanx_right_out[8])); + + mux_tree_tapbuf_size2 mux_right_track_18 ( + .in({chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_23_sram[0:1]), + .sram_inv(mux_right_track_18_undriven_sram_inv[0:1]), + .out(chanx_right_out[9])); + + mux_tree_tapbuf_size2 mux_right_track_28 ( + .in({chany_top_in[13], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_24_sram[0:1]), + .sram_inv(mux_right_track_28_undriven_sram_inv[0:1]), + .out(chanx_right_out[14])); + + mux_tree_tapbuf_size2 mux_right_track_30 ( + .in({chany_top_in[14], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_25_sram[0:1]), + .sram_inv(mux_right_track_30_undriven_sram_inv[0:1]), + .out(chanx_right_out[15])); + + mux_tree_tapbuf_size2 mux_right_track_32 ( + .in({chany_top_in[15], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_26_sram[0:1]), + .sram_inv(mux_right_track_32_undriven_sram_inv[0:1]), + .out(chanx_right_out[16])); + + mux_tree_tapbuf_size2 mux_right_track_34 ( + .in({chany_top_in[16], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_27_sram[0:1]), + .sram_inv(mux_right_track_34_undriven_sram_inv[0:1]), + .out(chanx_right_out[17])); + + mux_tree_tapbuf_size2 mux_right_track_44 ( + .in({chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_28_sram[0:1]), + .sram_inv(mux_right_track_44_undriven_sram_inv[0:1]), + .out(chanx_right_out[22])); + + mux_tree_tapbuf_size2 mux_right_track_46 ( + .in({chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_29_sram[0:1]), + .sram_inv(mux_right_track_46_undriven_sram_inv[0:1]), + .out(chanx_right_out[23])); + + mux_tree_tapbuf_size2 mux_right_track_48 ( + .in({chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_30_sram[0:1]), + .sram_inv(mux_right_track_48_undriven_sram_inv[0:1]), + .out(chanx_right_out[24])); + + mux_tree_tapbuf_size2 mux_right_track_50 ( + .in({chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_31_sram[0:1]), + .sram_inv(mux_right_track_50_undriven_sram_inv[0:1]), + .out(chanx_right_out[25])); + + mux_tree_tapbuf_size2_mem mem_top_track_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_8 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_14 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_16 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_18 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_28 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_30 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_32 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_34 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_44 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_46 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_48 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_50 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_8 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_14 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_16 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_18 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_28 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_30 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_25_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_32 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_26_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_34 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_27_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_44 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_28_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_28_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_46 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_28_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_29_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_29_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_48 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_29_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_30_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_30_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_50 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_30_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_31_sram[0:1])); + +endmodule +// ----- END Verilog module for sb_0__0_ ----- + +//----- Default net type ----- +`default_nettype none + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__1_.v new file mode 100644 index 0000000..22f060a --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__1_.v @@ -0,0 +1,1069 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[0][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_0__1_ ----- +module sb_0__1_(pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + chanx_right_in, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + chany_bottom_in, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_right_out, + chany_bottom_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:29] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:29] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; +//----- INPUT PORTS ----- +input [0:29] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:29] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:29] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:29] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:2] mux_bottom_track_11_undriven_sram_inv; +wire [0:2] mux_bottom_track_13_undriven_sram_inv; +wire [0:2] mux_bottom_track_1_undriven_sram_inv; +wire [0:2] mux_bottom_track_21_undriven_sram_inv; +wire [0:2] mux_bottom_track_29_undriven_sram_inv; +wire [0:2] mux_bottom_track_37_undriven_sram_inv; +wire [0:2] mux_bottom_track_3_undriven_sram_inv; +wire [0:2] mux_bottom_track_45_undriven_sram_inv; +wire [0:1] mux_bottom_track_53_undriven_sram_inv; +wire [0:2] mux_bottom_track_5_undriven_sram_inv; +wire [0:2] mux_bottom_track_7_undriven_sram_inv; +wire [0:2] mux_right_track_0_undriven_sram_inv; +wire [0:2] mux_right_track_10_undriven_sram_inv; +wire [0:2] mux_right_track_12_undriven_sram_inv; +wire [0:2] mux_right_track_14_undriven_sram_inv; +wire [0:2] mux_right_track_16_undriven_sram_inv; +wire [0:2] mux_right_track_18_undriven_sram_inv; +wire [0:2] mux_right_track_20_undriven_sram_inv; +wire [0:2] mux_right_track_22_undriven_sram_inv; +wire [0:1] mux_right_track_24_undriven_sram_inv; +wire [0:1] mux_right_track_26_undriven_sram_inv; +wire [0:1] mux_right_track_28_undriven_sram_inv; +wire [0:2] mux_right_track_2_undriven_sram_inv; +wire [0:1] mux_right_track_30_undriven_sram_inv; +wire [0:1] mux_right_track_32_undriven_sram_inv; +wire [0:1] mux_right_track_34_undriven_sram_inv; +wire [0:2] mux_right_track_36_undriven_sram_inv; +wire [0:1] mux_right_track_38_undriven_sram_inv; +wire [0:1] mux_right_track_40_undriven_sram_inv; +wire [0:1] mux_right_track_44_undriven_sram_inv; +wire [0:1] mux_right_track_46_undriven_sram_inv; +wire [0:1] mux_right_track_48_undriven_sram_inv; +wire [0:2] mux_right_track_4_undriven_sram_inv; +wire [0:1] mux_right_track_50_undriven_sram_inv; +wire [0:1] mux_right_track_52_undriven_sram_inv; +wire [0:1] mux_right_track_54_undriven_sram_inv; +wire [0:1] mux_right_track_56_undriven_sram_inv; +wire [0:2] mux_right_track_6_undriven_sram_inv; +wire [0:2] mux_right_track_8_undriven_sram_inv; +wire [0:2] mux_top_track_0_undriven_sram_inv; +wire [0:2] mux_top_track_10_undriven_sram_inv; +wire [0:2] mux_top_track_12_undriven_sram_inv; +wire [0:2] mux_top_track_20_undriven_sram_inv; +wire [0:2] mux_top_track_28_undriven_sram_inv; +wire [0:2] mux_top_track_2_undriven_sram_inv; +wire [0:2] mux_top_track_36_undriven_sram_inv; +wire [0:1] mux_top_track_44_undriven_sram_inv; +wire [0:2] mux_top_track_4_undriven_sram_inv; +wire [0:2] mux_top_track_52_undriven_sram_inv; +wire [0:2] mux_top_track_6_undriven_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_7_sram; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:1] mux_tree_tapbuf_size3_7_sram; +wire [0:1] mux_tree_tapbuf_size3_8_sram; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_2_sram; +wire [0:2] mux_tree_tapbuf_size4_3_sram; +wire [0:2] mux_tree_tapbuf_size4_4_sram; +wire [0:2] mux_tree_tapbuf_size4_5_sram; +wire [0:2] mux_tree_tapbuf_size4_6_sram; +wire [0:2] mux_tree_tapbuf_size4_7_sram; +wire [0:2] mux_tree_tapbuf_size4_8_sram; +wire [0:2] mux_tree_tapbuf_size4_9_sram; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail; +wire [0:2] mux_tree_tapbuf_size5_0_sram; +wire [0:2] mux_tree_tapbuf_size5_1_sram; +wire [0:2] mux_tree_tapbuf_size5_2_sram; +wire [0:2] mux_tree_tapbuf_size5_3_sram; +wire [0:2] mux_tree_tapbuf_size5_4_sram; +wire [0:2] mux_tree_tapbuf_size5_5_sram; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail; +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_10_sram; +wire [0:2] mux_tree_tapbuf_size6_11_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_4_sram; +wire [0:2] mux_tree_tapbuf_size6_5_sram; +wire [0:2] mux_tree_tapbuf_size6_6_sram; +wire [0:2] mux_tree_tapbuf_size6_7_sram; +wire [0:2] mux_tree_tapbuf_size6_8_sram; +wire [0:2] mux_tree_tapbuf_size6_9_sram; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail; +wire [0:2] mux_tree_tapbuf_size7_0_sram; +wire [0:2] mux_tree_tapbuf_size7_1_sram; +wire [0:2] mux_tree_tapbuf_size7_2_sram; +wire [0:2] mux_tree_tapbuf_size7_3_sram; +wire [0:2] mux_tree_tapbuf_size7_4_sram; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[4] = chany_top_in[3]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[7] = chany_top_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[8] = chany_top_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[9] = chany_top_in[8]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[11] = chany_top_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[12] = chany_top_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[13] = chany_top_in[12]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[15] = chany_top_in[14]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[16] = chany_top_in[15]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[17] = chany_top_in[16]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[19] = chany_top_in[18]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[20] = chany_top_in[19]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[21] = chany_top_in[20]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[23] = chany_top_in[22]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[24] = chany_top_in[23]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[25] = chany_top_in[24]; +// ----- Local connection due to Wire 26 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[27] = chany_top_in[26]; +// ----- Local connection due to Wire 27 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[28] = chany_top_in[27]; +// ----- Local connection due to Wire 28 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[29] = chany_top_in[28]; +// ----- Local connection due to Wire 75 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[4] = chany_bottom_in[3]; +// ----- Local connection due to Wire 78 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[7] = chany_bottom_in[6]; +// ----- Local connection due to Wire 79 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[8] = chany_bottom_in[7]; +// ----- Local connection due to Wire 80 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[9] = chany_bottom_in[8]; +// ----- Local connection due to Wire 82 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[11] = chany_bottom_in[10]; +// ----- Local connection due to Wire 83 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[12] = chany_bottom_in[11]; +// ----- Local connection due to Wire 84 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[13] = chany_bottom_in[12]; +// ----- Local connection due to Wire 86 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[15] = chany_bottom_in[14]; +// ----- Local connection due to Wire 87 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[16] = chany_bottom_in[15]; +// ----- Local connection due to Wire 88 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[17] = chany_bottom_in[16]; +// ----- Local connection due to Wire 89 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[21] = chany_bottom_in[17]; +// ----- Local connection due to Wire 90 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[19] = chany_bottom_in[18]; +// ----- Local connection due to Wire 91 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[20] = chany_bottom_in[19]; +// ----- Local connection due to Wire 92 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[21] = chany_bottom_in[20]; +// ----- Local connection due to Wire 94 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[23] = chany_bottom_in[22]; +// ----- Local connection due to Wire 95 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[24] = chany_bottom_in[23]; +// ----- Local connection due to Wire 96 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[25] = chany_bottom_in[24]; +// ----- Local connection due to Wire 98 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[27] = chany_bottom_in[26]; +// ----- Local connection due to Wire 99 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[28] = chany_bottom_in[27]; +// ----- Local connection due to Wire 100 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[29] = chany_bottom_in[28]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size7 mux_top_track_0 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[1], chanx_right_in[12], chanx_right_in[23], chany_bottom_in[3], chany_bottom_in[19]}), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_top_track_0_undriven_sram_inv[0:2]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size7 mux_top_track_6 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[4], chanx_right_in[15], chanx_right_in[26], chany_bottom_in[8], chany_bottom_in[23]}), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_top_track_6_undriven_sram_inv[0:2]), + .out(chany_top_out[3])); + + mux_tree_tapbuf_size7 mux_top_track_10 ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[5], chanx_right_in[16], chanx_right_in[27], chany_bottom_in[10], chany_bottom_in[24]}), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_top_track_10_undriven_sram_inv[0:2]), + .out(chany_top_out[5])); + + mux_tree_tapbuf_size7 mux_bottom_track_7 ( + .in({chany_top_in[8], chany_top_in[23], chanx_right_in[6], chanx_right_in[17], chanx_right_in[28], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_bottom_track_7_undriven_sram_inv[0:2]), + .out(chany_bottom_out[3])); + + mux_tree_tapbuf_size7 mux_bottom_track_11 ( + .in({chany_top_in[10], chany_top_in[24], chanx_right_in[5], chanx_right_in[16], chanx_right_in[27], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_4_sram[0:2]), + .sram_inv(mux_bottom_track_11_undriven_sram_inv[0:2]), + .out(chany_bottom_out[5])); + + mux_tree_tapbuf_size7_mem mem_top_track_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_top_track_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_top_track_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_bottom_track_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_bottom_track_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram[0:2])); + + mux_tree_tapbuf_size6 mux_top_track_2 ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[2], chanx_right_in[13], chanx_right_in[24], chany_bottom_in[6], chany_bottom_in[20]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_top_track_2_undriven_sram_inv[0:2]), + .out(chany_top_out[1])); + + mux_tree_tapbuf_size6 mux_top_track_4 ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[3], chanx_right_in[14], chanx_right_in[25], chany_bottom_in[7], chany_bottom_in[22]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_top_track_4_undriven_sram_inv[0:2]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size6 mux_top_track_12 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[6], chanx_right_in[17], chanx_right_in[28], chany_bottom_in[11], chany_bottom_in[26]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_top_track_12_undriven_sram_inv[0:2]), + .out(chany_top_out[6])); + + mux_tree_tapbuf_size6 mux_top_track_20 ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[7], chanx_right_in[18], chanx_right_in[29], chany_bottom_in[12], chany_bottom_in[27]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_top_track_20_undriven_sram_inv[0:2]), + .out(chany_top_out[10])); + + mux_tree_tapbuf_size6 mux_right_track_2 ( + .in({chany_top_in[0], chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[6]}), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_right_track_2_undriven_sram_inv[0:2]), + .out(chanx_right_out[1])); + + mux_tree_tapbuf_size6 mux_right_track_6 ( + .in({chany_top_in[2], chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[8]}), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_right_track_6_undriven_sram_inv[0:2]), + .out(chanx_right_out[3])); + + mux_tree_tapbuf_size6 mux_right_track_8 ( + .in({chany_top_in[4], chany_top_in[10], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[10]}), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_right_track_8_undriven_sram_inv[0:2]), + .out(chanx_right_out[4])); + + mux_tree_tapbuf_size6 mux_bottom_track_1 ( + .in({chany_top_in[3], chany_top_in[19], chanx_right_in[9], chanx_right_in[20], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_7_sram[0:2]), + .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size6 mux_bottom_track_5 ( + .in({chany_top_in[7], chany_top_in[22], chanx_right_in[7], chanx_right_in[18], chanx_right_in[29], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_8_sram[0:2]), + .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size6 mux_bottom_track_13 ( + .in({chany_top_in[11], chany_top_in[26], chanx_right_in[4], chanx_right_in[15], chanx_right_in[26], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_9_sram[0:2]), + .sram_inv(mux_bottom_track_13_undriven_sram_inv[0:2]), + .out(chany_bottom_out[6])); + + mux_tree_tapbuf_size6 mux_bottom_track_21 ( + .in({chany_top_in[12], chany_top_in[27], chanx_right_in[3], chanx_right_in[14], chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_10_sram[0:2]), + .sram_inv(mux_bottom_track_21_undriven_sram_inv[0:2]), + .out(chany_bottom_out[10])); + + mux_tree_tapbuf_size6 mux_bottom_track_29 ( + .in({chany_top_in[14], chany_top_in[28], chanx_right_in[2], chanx_right_in[13], chanx_right_in[24], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_11_sram[0:2]), + .sram_inv(mux_bottom_track_29_undriven_sram_inv[0:2]), + .out(chany_bottom_out[14])); + + mux_tree_tapbuf_size6_mem mem_top_track_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_track_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_track_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_track_20 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_8 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_21 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_29 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_11_sram[0:2])); + + mux_tree_tapbuf_size5 mux_top_track_28 ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[8], chanx_right_in[19], chany_bottom_in[14], chany_bottom_in[28]}), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_top_track_28_undriven_sram_inv[0:2]), + .out(chany_top_out[14])); + + mux_tree_tapbuf_size5 mux_right_track_0 ( + .in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[3]}), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_right_track_0_undriven_sram_inv[0:2]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size5 mux_right_track_4 ( + .in({chany_top_in[1], chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[7]}), + .sram(mux_tree_tapbuf_size5_2_sram[0:2]), + .sram_inv(mux_right_track_4_undriven_sram_inv[0:2]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size5 mux_right_track_10 ( + .in({chany_top_in[5], chany_top_in[11], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[11]}), + .sram(mux_tree_tapbuf_size5_3_sram[0:2]), + .sram_inv(mux_right_track_10_undriven_sram_inv[0:2]), + .out(chanx_right_out[5])); + + mux_tree_tapbuf_size5 mux_bottom_track_3 ( + .in({chany_top_in[6], chany_top_in[20], chanx_right_in[8], chanx_right_in[19], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_4_sram[0:2]), + .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]), + .out(chany_bottom_out[1])); + + mux_tree_tapbuf_size5 mux_bottom_track_37 ( + .in({chany_top_in[15], chanx_right_in[1], chanx_right_in[12], chanx_right_in[23], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_5_sram[0:2]), + .sram_inv(mux_bottom_track_37_undriven_sram_inv[0:2]), + .out(chany_bottom_out[18])); + + mux_tree_tapbuf_size5_mem mem_top_track_28 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_right_track_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_right_track_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_right_track_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_37 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram[0:2])); + + mux_tree_tapbuf_size4 mux_top_track_36 ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[9], chanx_right_in[20], chany_bottom_in[15]}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_top_track_36_undriven_sram_inv[0:2]), + .out(chany_top_out[18])); + + mux_tree_tapbuf_size4 mux_top_track_52 ( + .in({chanx_right_in[0], chanx_right_in[11], chanx_right_in[22], chany_bottom_in[18]}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_top_track_52_undriven_sram_inv[0:2]), + .out(chany_top_out[26])); + + mux_tree_tapbuf_size4 mux_right_track_12 ( + .in({chany_top_in[9], chany_top_in[12], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[12]}), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_right_track_12_undriven_sram_inv[0:2]), + .out(chanx_right_out[6])); + + mux_tree_tapbuf_size4 mux_right_track_14 ( + .in({chany_top_in[13:14], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[14]}), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_right_track_14_undriven_sram_inv[0:2]), + .out(chanx_right_out[7])); + + mux_tree_tapbuf_size4 mux_right_track_16 ( + .in({chany_top_in[15], chany_top_in[17], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[15]}), + .sram(mux_tree_tapbuf_size4_4_sram[0:2]), + .sram_inv(mux_right_track_16_undriven_sram_inv[0:2]), + .out(chanx_right_out[8])); + + mux_tree_tapbuf_size4 mux_right_track_18 ( + .in({chany_top_in[16], chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[16]}), + .sram(mux_tree_tapbuf_size4_5_sram[0:2]), + .sram_inv(mux_right_track_18_undriven_sram_inv[0:2]), + .out(chanx_right_out[9])); + + mux_tree_tapbuf_size4 mux_right_track_20 ( + .in({chany_top_in[18], chany_top_in[25], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[18]}), + .sram(mux_tree_tapbuf_size4_6_sram[0:2]), + .sram_inv(mux_right_track_20_undriven_sram_inv[0:2]), + .out(chanx_right_out[10])); + + mux_tree_tapbuf_size4 mux_right_track_22 ( + .in({chany_top_in[19], chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[19]}), + .sram(mux_tree_tapbuf_size4_7_sram[0:2]), + .sram_inv(mux_right_track_22_undriven_sram_inv[0:2]), + .out(chanx_right_out[11])); + + mux_tree_tapbuf_size4 mux_right_track_36 ( + .in({chany_top_in[28], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[28:29]}), + .sram(mux_tree_tapbuf_size4_8_sram[0:2]), + .sram_inv(mux_right_track_36_undriven_sram_inv[0:2]), + .out(chanx_right_out[18])); + + mux_tree_tapbuf_size4 mux_bottom_track_45 ( + .in({chany_top_in[16], chanx_right_in[0], chanx_right_in[11], chanx_right_in[22]}), + .sram(mux_tree_tapbuf_size4_9_sram[0:2]), + .sram_inv(mux_bottom_track_45_undriven_sram_inv[0:2]), + .out(chany_bottom_out[22])); + + mux_tree_tapbuf_size4_mem mem_top_track_36 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_top_track_52 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_14 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_16 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_18 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_20 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_6_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_22 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_7_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_36 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_8_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_45 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_9_sram[0:2])); + + mux_tree_tapbuf_size3 mux_top_track_44 ( + .in({chanx_right_in[10], chanx_right_in[21], chany_bottom_in[16]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_top_track_44_undriven_sram_inv[0:1]), + .out(chany_top_out[22])); + + mux_tree_tapbuf_size3 mux_right_track_24 ( + .in({chany_top_in[20], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[20]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_right_track_24_undriven_sram_inv[0:1]), + .out(chanx_right_out[12])); + + mux_tree_tapbuf_size3 mux_right_track_26 ( + .in({chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[22]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_right_track_26_undriven_sram_inv[0:1]), + .out(chanx_right_out[13])); + + mux_tree_tapbuf_size3 mux_right_track_28 ( + .in({chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[23]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_right_track_28_undriven_sram_inv[0:1]), + .out(chanx_right_out[14])); + + mux_tree_tapbuf_size3 mux_right_track_30 ( + .in({chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[24]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_right_track_30_undriven_sram_inv[0:1]), + .out(chanx_right_out[15])); + + mux_tree_tapbuf_size3 mux_right_track_32 ( + .in({chany_top_in[26], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[26]}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_right_track_32_undriven_sram_inv[0:1]), + .out(chanx_right_out[16])); + + mux_tree_tapbuf_size3 mux_right_track_34 ( + .in({chany_top_in[27], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[27]}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_right_track_34_undriven_sram_inv[0:1]), + .out(chanx_right_out[17])); + + mux_tree_tapbuf_size3 mux_right_track_50 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[4]}), + .sram(mux_tree_tapbuf_size3_7_sram[0:1]), + .sram_inv(mux_right_track_50_undriven_sram_inv[0:1]), + .out(chanx_right_out[25])); + + mux_tree_tapbuf_size3 mux_bottom_track_53 ( + .in({chany_top_in[18], chanx_right_in[10], chanx_right_in[21]}), + .sram(mux_tree_tapbuf_size3_8_sram[0:1]), + .sram_inv(mux_bottom_track_53_undriven_sram_inv[0:1]), + .out(chany_bottom_out[26])); + + mux_tree_tapbuf_size3_mem mem_top_track_44 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_24 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_26 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_28 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_30 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_32 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_34 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_50 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_53 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_9_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram[0:1])); + + mux_tree_tapbuf_size2 mux_right_track_38 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[25]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_right_track_38_undriven_sram_inv[0:1]), + .out(chanx_right_out[19])); + + mux_tree_tapbuf_size2 mux_right_track_40 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[21]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_right_track_40_undriven_sram_inv[0:1]), + .out(chanx_right_out[20])); + + mux_tree_tapbuf_size2 mux_right_track_44 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[13]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_right_track_44_undriven_sram_inv[0:1]), + .out(chanx_right_out[22])); + + mux_tree_tapbuf_size2 mux_right_track_46 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[9]}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_right_track_46_undriven_sram_inv[0:1]), + .out(chanx_right_out[23])); + + mux_tree_tapbuf_size2 mux_right_track_48 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[5]}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_right_track_48_undriven_sram_inv[0:1]), + .out(chanx_right_out[24])); + + mux_tree_tapbuf_size2 mux_right_track_52 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[2]}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_right_track_52_undriven_sram_inv[0:1]), + .out(chanx_right_out[26])); + + mux_tree_tapbuf_size2 mux_right_track_54 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[1]}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_right_track_54_undriven_sram_inv[0:1]), + .out(chanx_right_out[27])); + + mux_tree_tapbuf_size2 mux_right_track_56 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[0]}), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_right_track_56_undriven_sram_inv[0:1]), + .out(chanx_right_out[28])); + + mux_tree_tapbuf_size2_mem mem_right_track_38 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_40 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_44 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_46 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_48 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_52 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_54 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_56 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1])); + +endmodule +// ----- END Verilog module for sb_0__1_ ----- + +//----- Default net type ----- +`default_nettype none + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__8_.v new file mode 100644 index 0000000..3002d9f --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__8_.v @@ -0,0 +1,923 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[0][8] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_0__8_ ----- +module sb_0__8_(pReset, + prog_clk, + chanx_right_in, + right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + chany_bottom_in, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chanx_right_out, + chany_bottom_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:29] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; +//----- INPUT PORTS ----- +input [0:29] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:29] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:29] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:1] mux_bottom_track_11_undriven_sram_inv; +wire [0:1] mux_bottom_track_13_undriven_sram_inv; +wire [0:1] mux_bottom_track_15_undriven_sram_inv; +wire [0:1] mux_bottom_track_17_undriven_sram_inv; +wire [0:1] mux_bottom_track_19_undriven_sram_inv; +wire [0:1] mux_bottom_track_1_undriven_sram_inv; +wire [0:1] mux_bottom_track_29_undriven_sram_inv; +wire [0:1] mux_bottom_track_31_undriven_sram_inv; +wire [0:1] mux_bottom_track_33_undriven_sram_inv; +wire [0:1] mux_bottom_track_35_undriven_sram_inv; +wire [0:1] mux_bottom_track_3_undriven_sram_inv; +wire [0:1] mux_bottom_track_45_undriven_sram_inv; +wire [0:1] mux_bottom_track_47_undriven_sram_inv; +wire [0:1] mux_bottom_track_49_undriven_sram_inv; +wire [0:1] mux_bottom_track_51_undriven_sram_inv; +wire [0:1] mux_bottom_track_5_undriven_sram_inv; +wire [0:1] mux_bottom_track_7_undriven_sram_inv; +wire [0:1] mux_bottom_track_9_undriven_sram_inv; +wire [0:2] mux_right_track_0_undriven_sram_inv; +wire [0:2] mux_right_track_10_undriven_sram_inv; +wire [0:1] mux_right_track_12_undriven_sram_inv; +wire [0:1] mux_right_track_14_undriven_sram_inv; +wire [0:1] mux_right_track_16_undriven_sram_inv; +wire [0:1] mux_right_track_18_undriven_sram_inv; +wire [0:1] mux_right_track_20_undriven_sram_inv; +wire [0:1] mux_right_track_22_undriven_sram_inv; +wire [0:1] mux_right_track_24_undriven_sram_inv; +wire [0:1] mux_right_track_26_undriven_sram_inv; +wire [0:1] mux_right_track_28_undriven_sram_inv; +wire [0:2] mux_right_track_2_undriven_sram_inv; +wire [0:1] mux_right_track_30_undriven_sram_inv; +wire [0:1] mux_right_track_32_undriven_sram_inv; +wire [0:1] mux_right_track_34_undriven_sram_inv; +wire [0:1] mux_right_track_36_undriven_sram_inv; +wire [0:1] mux_right_track_38_undriven_sram_inv; +wire [0:1] mux_right_track_40_undriven_sram_inv; +wire [0:1] mux_right_track_42_undriven_sram_inv; +wire [0:1] mux_right_track_44_undriven_sram_inv; +wire [0:1] mux_right_track_46_undriven_sram_inv; +wire [0:1] mux_right_track_48_undriven_sram_inv; +wire [0:2] mux_right_track_4_undriven_sram_inv; +wire [0:1] mux_right_track_50_undriven_sram_inv; +wire [0:1] mux_right_track_52_undriven_sram_inv; +wire [0:1] mux_right_track_54_undriven_sram_inv; +wire [0:1] mux_right_track_56_undriven_sram_inv; +wire [0:1] mux_right_track_58_undriven_sram_inv; +wire [0:2] mux_right_track_6_undriven_sram_inv; +wire [0:2] mux_right_track_8_undriven_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_10_sram; +wire [0:1] mux_tree_tapbuf_size2_11_sram; +wire [0:1] mux_tree_tapbuf_size2_12_sram; +wire [0:1] mux_tree_tapbuf_size2_13_sram; +wire [0:1] mux_tree_tapbuf_size2_14_sram; +wire [0:1] mux_tree_tapbuf_size2_15_sram; +wire [0:1] mux_tree_tapbuf_size2_16_sram; +wire [0:1] mux_tree_tapbuf_size2_17_sram; +wire [0:1] mux_tree_tapbuf_size2_18_sram; +wire [0:1] mux_tree_tapbuf_size2_19_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_20_sram; +wire [0:1] mux_tree_tapbuf_size2_21_sram; +wire [0:1] mux_tree_tapbuf_size2_22_sram; +wire [0:1] mux_tree_tapbuf_size2_23_sram; +wire [0:1] mux_tree_tapbuf_size2_24_sram; +wire [0:1] mux_tree_tapbuf_size2_25_sram; +wire [0:1] mux_tree_tapbuf_size2_26_sram; +wire [0:1] mux_tree_tapbuf_size2_27_sram; +wire [0:1] mux_tree_tapbuf_size2_28_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_7_sram; +wire [0:1] mux_tree_tapbuf_size2_8_sram; +wire [0:1] mux_tree_tapbuf_size2_9_sram; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_10_sram; +wire [0:1] mux_tree_tapbuf_size3_11_sram; +wire [0:1] mux_tree_tapbuf_size3_12_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:1] mux_tree_tapbuf_size3_7_sram; +wire [0:1] mux_tree_tapbuf_size3_8_sram; +wire [0:1] mux_tree_tapbuf_size3_9_sram; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail; +wire [0:2] mux_tree_tapbuf_size5_0_sram; +wire [0:2] mux_tree_tapbuf_size5_1_sram; +wire [0:2] mux_tree_tapbuf_size5_2_sram; +wire [0:2] mux_tree_tapbuf_size5_3_sram; +wire [0:2] mux_tree_tapbuf_size5_4_sram; +wire [0:2] mux_tree_tapbuf_size5_5_sram; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[28] = chanx_right_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[27] = chanx_right_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[26] = chanx_right_in[2]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[21] = chanx_right_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[20] = chanx_right_in[8]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[19] = chanx_right_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[18] = chanx_right_in[10]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[13] = chanx_right_in[15]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[12] = chanx_right_in[16]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[11] = chanx_right_in[17]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[10] = chanx_right_in[18]; +// ----- Local connection due to Wire 29 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[29] = chanx_right_in[29]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size5 mux_right_track_0 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[28]}), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_right_track_0_undriven_sram_inv[0:2]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size5 mux_right_track_2 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[27]}), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_right_track_2_undriven_sram_inv[0:2]), + .out(chanx_right_out[1])); + + mux_tree_tapbuf_size5 mux_right_track_4 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[26]}), + .sram(mux_tree_tapbuf_size5_2_sram[0:2]), + .sram_inv(mux_right_track_4_undriven_sram_inv[0:2]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size5 mux_right_track_6 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[25]}), + .sram(mux_tree_tapbuf_size5_3_sram[0:2]), + .sram_inv(mux_right_track_6_undriven_sram_inv[0:2]), + .out(chanx_right_out[3])); + + mux_tree_tapbuf_size5 mux_right_track_8 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[24]}), + .sram(mux_tree_tapbuf_size5_4_sram[0:2]), + .sram_inv(mux_right_track_8_undriven_sram_inv[0:2]), + .out(chanx_right_out[4])); + + mux_tree_tapbuf_size5 mux_right_track_10 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[23]}), + .sram(mux_tree_tapbuf_size5_5_sram[0:2]), + .sram_inv(mux_right_track_10_undriven_sram_inv[0:2]), + .out(chanx_right_out[5])); + + mux_tree_tapbuf_size5_mem mem_right_track_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_right_track_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_right_track_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_right_track_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_right_track_8 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_right_track_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram[0:2])); + + mux_tree_tapbuf_size3 mux_right_track_12 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[22]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_right_track_12_undriven_sram_inv[0:1]), + .out(chanx_right_out[6])); + + mux_tree_tapbuf_size3 mux_right_track_14 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[21]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_right_track_14_undriven_sram_inv[0:1]), + .out(chanx_right_out[7])); + + mux_tree_tapbuf_size3 mux_right_track_16 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[20]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_right_track_16_undriven_sram_inv[0:1]), + .out(chanx_right_out[8])); + + mux_tree_tapbuf_size3 mux_right_track_28 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[14]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_right_track_28_undriven_sram_inv[0:1]), + .out(chanx_right_out[14])); + + mux_tree_tapbuf_size3 mux_right_track_30 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[13]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_right_track_30_undriven_sram_inv[0:1]), + .out(chanx_right_out[15])); + + mux_tree_tapbuf_size3 mux_right_track_32 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[12]}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_right_track_32_undriven_sram_inv[0:1]), + .out(chanx_right_out[16])); + + mux_tree_tapbuf_size3 mux_right_track_34 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[11]}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_right_track_34_undriven_sram_inv[0:1]), + .out(chanx_right_out[17])); + + mux_tree_tapbuf_size3 mux_right_track_44 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[6]}), + .sram(mux_tree_tapbuf_size3_7_sram[0:1]), + .sram_inv(mux_right_track_44_undriven_sram_inv[0:1]), + .out(chanx_right_out[22])); + + mux_tree_tapbuf_size3 mux_right_track_46 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[5]}), + .sram(mux_tree_tapbuf_size3_8_sram[0:1]), + .sram_inv(mux_right_track_46_undriven_sram_inv[0:1]), + .out(chanx_right_out[23])); + + mux_tree_tapbuf_size3 mux_right_track_48 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[4]}), + .sram(mux_tree_tapbuf_size3_9_sram[0:1]), + .sram_inv(mux_right_track_48_undriven_sram_inv[0:1]), + .out(chanx_right_out[24])); + + mux_tree_tapbuf_size3 mux_right_track_58 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[29]}), + .sram(mux_tree_tapbuf_size3_10_sram[0:1]), + .sram_inv(mux_right_track_58_undriven_sram_inv[0:1]), + .out(chanx_right_out[29])); + + mux_tree_tapbuf_size3 mux_bottom_track_1 ( + .in({chanx_right_in[28], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_11_sram[0:1]), + .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:1]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size3 mux_bottom_track_7 ( + .in({chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_12_sram[0:1]), + .sram_inv(mux_bottom_track_7_undriven_sram_inv[0:1]), + .out(chany_bottom_out[3])); + + mux_tree_tapbuf_size3_mem mem_right_track_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_14 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_16 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_28 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_30 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_32 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_34 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_44 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_46 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_48 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_58 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_12_sram[0:1])); + + mux_tree_tapbuf_size2 mux_right_track_18 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[19]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_right_track_18_undriven_sram_inv[0:1]), + .out(chanx_right_out[9])); + + mux_tree_tapbuf_size2 mux_right_track_20 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[18]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_right_track_20_undriven_sram_inv[0:1]), + .out(chanx_right_out[10])); + + mux_tree_tapbuf_size2 mux_right_track_22 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[17]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_right_track_22_undriven_sram_inv[0:1]), + .out(chanx_right_out[11])); + + mux_tree_tapbuf_size2 mux_right_track_24 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[16]}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_right_track_24_undriven_sram_inv[0:1]), + .out(chanx_right_out[12])); + + mux_tree_tapbuf_size2 mux_right_track_26 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[15]}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_right_track_26_undriven_sram_inv[0:1]), + .out(chanx_right_out[13])); + + mux_tree_tapbuf_size2 mux_right_track_36 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[10]}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_right_track_36_undriven_sram_inv[0:1]), + .out(chanx_right_out[18])); + + mux_tree_tapbuf_size2 mux_right_track_38 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[9]}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_right_track_38_undriven_sram_inv[0:1]), + .out(chanx_right_out[19])); + + mux_tree_tapbuf_size2 mux_right_track_40 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[8]}), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_right_track_40_undriven_sram_inv[0:1]), + .out(chanx_right_out[20])); + + mux_tree_tapbuf_size2 mux_right_track_42 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[7]}), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_right_track_42_undriven_sram_inv[0:1]), + .out(chanx_right_out[21])); + + mux_tree_tapbuf_size2 mux_right_track_50 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[3]}), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_right_track_50_undriven_sram_inv[0:1]), + .out(chanx_right_out[25])); + + mux_tree_tapbuf_size2 mux_right_track_52 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[2]}), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_right_track_52_undriven_sram_inv[0:1]), + .out(chanx_right_out[26])); + + mux_tree_tapbuf_size2 mux_right_track_54 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[1]}), + .sram(mux_tree_tapbuf_size2_11_sram[0:1]), + .sram_inv(mux_right_track_54_undriven_sram_inv[0:1]), + .out(chanx_right_out[27])); + + mux_tree_tapbuf_size2 mux_right_track_56 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[0]}), + .sram(mux_tree_tapbuf_size2_12_sram[0:1]), + .sram_inv(mux_right_track_56_undriven_sram_inv[0:1]), + .out(chanx_right_out[28])); + + mux_tree_tapbuf_size2 mux_bottom_track_3 ( + .in({chanx_right_in[27], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_13_sram[0:1]), + .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:1]), + .out(chany_bottom_out[1])); + + mux_tree_tapbuf_size2 mux_bottom_track_5 ( + .in({chanx_right_in[26], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_14_sram[0:1]), + .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:1]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size2 mux_bottom_track_9 ( + .in({chanx_right_in[24], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_15_sram[0:1]), + .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:1]), + .out(chany_bottom_out[4])); + + mux_tree_tapbuf_size2 mux_bottom_track_11 ( + .in({chanx_right_in[23], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_16_sram[0:1]), + .sram_inv(mux_bottom_track_11_undriven_sram_inv[0:1]), + .out(chany_bottom_out[5])); + + mux_tree_tapbuf_size2 mux_bottom_track_13 ( + .in({chanx_right_in[22], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_17_sram[0:1]), + .sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]), + .out(chany_bottom_out[6])); + + mux_tree_tapbuf_size2 mux_bottom_track_15 ( + .in({chanx_right_in[21], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_18_sram[0:1]), + .sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]), + .out(chany_bottom_out[7])); + + mux_tree_tapbuf_size2 mux_bottom_track_17 ( + .in({chanx_right_in[20], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_19_sram[0:1]), + .sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]), + .out(chany_bottom_out[8])); + + mux_tree_tapbuf_size2 mux_bottom_track_19 ( + .in({chanx_right_in[19], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_20_sram[0:1]), + .sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]), + .out(chany_bottom_out[9])); + + mux_tree_tapbuf_size2 mux_bottom_track_29 ( + .in({chanx_right_in[14], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram[0:1]), + .sram_inv(mux_bottom_track_29_undriven_sram_inv[0:1]), + .out(chany_bottom_out[14])); + + mux_tree_tapbuf_size2 mux_bottom_track_31 ( + .in({chanx_right_in[13], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_22_sram[0:1]), + .sram_inv(mux_bottom_track_31_undriven_sram_inv[0:1]), + .out(chany_bottom_out[15])); + + mux_tree_tapbuf_size2 mux_bottom_track_33 ( + .in({chanx_right_in[12], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_23_sram[0:1]), + .sram_inv(mux_bottom_track_33_undriven_sram_inv[0:1]), + .out(chany_bottom_out[16])); + + mux_tree_tapbuf_size2 mux_bottom_track_35 ( + .in({chanx_right_in[11], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_24_sram[0:1]), + .sram_inv(mux_bottom_track_35_undriven_sram_inv[0:1]), + .out(chany_bottom_out[17])); + + mux_tree_tapbuf_size2 mux_bottom_track_45 ( + .in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_25_sram[0:1]), + .sram_inv(mux_bottom_track_45_undriven_sram_inv[0:1]), + .out(chany_bottom_out[22])); + + mux_tree_tapbuf_size2 mux_bottom_track_47 ( + .in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_26_sram[0:1]), + .sram_inv(mux_bottom_track_47_undriven_sram_inv[0:1]), + .out(chany_bottom_out[23])); + + mux_tree_tapbuf_size2 mux_bottom_track_49 ( + .in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_27_sram[0:1]), + .sram_inv(mux_bottom_track_49_undriven_sram_inv[0:1]), + .out(chany_bottom_out[24])); + + mux_tree_tapbuf_size2 mux_bottom_track_51 ( + .in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_28_sram[0:1]), + .sram_inv(mux_bottom_track_51_undriven_sram_inv[0:1]), + .out(chany_bottom_out[25])); + + mux_tree_tapbuf_size2_mem mem_right_track_18 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_20 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_22 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_24 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_26 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_36 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_38 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_40 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_42 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_50 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_52 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_54 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_56 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_9 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_15 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_17 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_19 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_29 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_31 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_33 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_35 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_45 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_25_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_47 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_26_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_49 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_27_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_51 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_28_sram[0:1])); + +endmodule +// ----- END Verilog module for sb_0__8_ ----- + +//----- Default net type ----- +`default_nettype none + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__0_.v new file mode 100644 index 0000000..12f412b --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__0_.v @@ -0,0 +1,1049 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[1][0] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_1__0_ ----- +module sb_1__0_(pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_right_in, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + chanx_left_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_right_out, + chanx_left_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:29] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; +//----- INPUT PORTS ----- +input [0:29] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:29] chanx_left_in; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:29] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:29] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:29] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:2] mux_left_track_11_undriven_sram_inv; +wire [0:2] mux_left_track_13_undriven_sram_inv; +wire [0:2] mux_left_track_1_undriven_sram_inv; +wire [0:2] mux_left_track_21_undriven_sram_inv; +wire [0:2] mux_left_track_29_undriven_sram_inv; +wire [0:2] mux_left_track_37_undriven_sram_inv; +wire [0:2] mux_left_track_3_undriven_sram_inv; +wire [0:2] mux_left_track_45_undriven_sram_inv; +wire [0:2] mux_left_track_53_undriven_sram_inv; +wire [0:2] mux_left_track_5_undriven_sram_inv; +wire [0:2] mux_left_track_7_undriven_sram_inv; +wire [0:2] mux_right_track_0_undriven_sram_inv; +wire [0:2] mux_right_track_10_undriven_sram_inv; +wire [0:2] mux_right_track_12_undriven_sram_inv; +wire [0:2] mux_right_track_20_undriven_sram_inv; +wire [0:2] mux_right_track_28_undriven_sram_inv; +wire [0:2] mux_right_track_2_undriven_sram_inv; +wire [0:2] mux_right_track_36_undriven_sram_inv; +wire [0:1] mux_right_track_44_undriven_sram_inv; +wire [0:2] mux_right_track_4_undriven_sram_inv; +wire [0:1] mux_right_track_52_undriven_sram_inv; +wire [0:2] mux_right_track_6_undriven_sram_inv; +wire [0:2] mux_top_track_0_undriven_sram_inv; +wire [0:2] mux_top_track_10_undriven_sram_inv; +wire [0:2] mux_top_track_12_undriven_sram_inv; +wire [0:2] mux_top_track_14_undriven_sram_inv; +wire [0:2] mux_top_track_16_undriven_sram_inv; +wire [0:2] mux_top_track_18_undriven_sram_inv; +wire [0:1] mux_top_track_20_undriven_sram_inv; +wire [0:1] mux_top_track_22_undriven_sram_inv; +wire [0:1] mux_top_track_24_undriven_sram_inv; +wire [0:1] mux_top_track_26_undriven_sram_inv; +wire [0:1] mux_top_track_28_undriven_sram_inv; +wire [0:2] mux_top_track_2_undriven_sram_inv; +wire [0:1] mux_top_track_30_undriven_sram_inv; +wire [0:1] mux_top_track_32_undriven_sram_inv; +wire [0:1] mux_top_track_34_undriven_sram_inv; +wire [0:1] mux_top_track_36_undriven_sram_inv; +wire [0:1] mux_top_track_40_undriven_sram_inv; +wire [0:1] mux_top_track_42_undriven_sram_inv; +wire [0:1] mux_top_track_44_undriven_sram_inv; +wire [0:1] mux_top_track_46_undriven_sram_inv; +wire [0:1] mux_top_track_48_undriven_sram_inv; +wire [0:2] mux_top_track_4_undriven_sram_inv; +wire [0:1] mux_top_track_50_undriven_sram_inv; +wire [0:1] mux_top_track_58_undriven_sram_inv; +wire [0:2] mux_top_track_6_undriven_sram_inv; +wire [0:2] mux_top_track_8_undriven_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_10_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_7_sram; +wire [0:1] mux_tree_tapbuf_size2_8_sram; +wire [0:1] mux_tree_tapbuf_size2_9_sram; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_2_sram; +wire [0:2] mux_tree_tapbuf_size4_3_sram; +wire [0:2] mux_tree_tapbuf_size4_4_sram; +wire [0:2] mux_tree_tapbuf_size4_5_sram; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; +wire [0:2] mux_tree_tapbuf_size5_0_sram; +wire [0:2] mux_tree_tapbuf_size5_1_sram; +wire [0:2] mux_tree_tapbuf_size5_2_sram; +wire [0:2] mux_tree_tapbuf_size5_3_sram; +wire [0:2] mux_tree_tapbuf_size5_4_sram; +wire [0:2] mux_tree_tapbuf_size5_5_sram; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail; +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_10_sram; +wire [0:2] mux_tree_tapbuf_size6_11_sram; +wire [0:2] mux_tree_tapbuf_size6_12_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_4_sram; +wire [0:2] mux_tree_tapbuf_size6_5_sram; +wire [0:2] mux_tree_tapbuf_size6_6_sram; +wire [0:2] mux_tree_tapbuf_size6_7_sram; +wire [0:2] mux_tree_tapbuf_size6_8_sram; +wire [0:2] mux_tree_tapbuf_size6_9_sram; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_12_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail; +wire [0:2] mux_tree_tapbuf_size7_0_sram; +wire [0:2] mux_tree_tapbuf_size7_1_sram; +wire [0:2] mux_tree_tapbuf_size7_2_sram; +wire [0:2] mux_tree_tapbuf_size7_3_sram; +wire [0:2] mux_tree_tapbuf_size7_4_sram; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 31 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chany_top_out[19] = top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_[0]; +// ----- Local connection due to Wire 41 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[4] = chanx_right_in[3]; +// ----- Local connection due to Wire 44 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[7] = chanx_right_in[6]; +// ----- Local connection due to Wire 45 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[8] = chanx_right_in[7]; +// ----- Local connection due to Wire 46 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[9] = chanx_right_in[8]; +// ----- Local connection due to Wire 48 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[11] = chanx_right_in[10]; +// ----- Local connection due to Wire 49 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[12] = chanx_right_in[11]; +// ----- Local connection due to Wire 50 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[13] = chanx_right_in[12]; +// ----- Local connection due to Wire 52 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[15] = chanx_right_in[14]; +// ----- Local connection due to Wire 53 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_left_out[16] = chanx_right_in[15]; +// ----- Local connection due to Wire 54 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_left_out[17] = chanx_right_in[16]; +// ----- Local connection due to Wire 56 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_left_out[19] = chanx_right_in[18]; +// ----- Local connection due to Wire 57 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[20] = chanx_right_in[19]; +// ----- Local connection due to Wire 58 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[21] = chanx_right_in[20]; +// ----- Local connection due to Wire 60 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[23] = chanx_right_in[22]; +// ----- Local connection due to Wire 61 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[24] = chanx_right_in[23]; +// ----- Local connection due to Wire 62 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[25] = chanx_right_in[24]; +// ----- Local connection due to Wire 64 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[27] = chanx_right_in[26]; +// ----- Local connection due to Wire 65 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[28] = chanx_right_in[27]; +// ----- Local connection due to Wire 66 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[29] = chanx_right_in[28]; +// ----- Local connection due to Wire 74 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[28] = chanx_left_in[2]; +// ----- Local connection due to Wire 75 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[4] = chanx_left_in[3]; +// ----- Local connection due to Wire 76 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[27] = chanx_left_in[4]; +// ----- Local connection due to Wire 77 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[26] = chanx_left_in[5]; +// ----- Local connection due to Wire 78 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[7] = chanx_left_in[6]; +// ----- Local connection due to Wire 79 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[8] = chanx_left_in[7]; +// ----- Local connection due to Wire 80 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[9] = chanx_left_in[8]; +// ----- Local connection due to Wire 82 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[11] = chanx_left_in[10]; +// ----- Local connection due to Wire 83 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[12] = chanx_left_in[11]; +// ----- Local connection due to Wire 84 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[13] = chanx_left_in[12]; +// ----- Local connection due to Wire 86 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[15] = chanx_left_in[14]; +// ----- Local connection due to Wire 87 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[16] = chanx_left_in[15]; +// ----- Local connection due to Wire 88 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[17] = chanx_left_in[16]; +// ----- Local connection due to Wire 90 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[19] = chanx_left_in[18]; +// ----- Local connection due to Wire 91 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[20] = chanx_left_in[19]; +// ----- Local connection due to Wire 92 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[21] = chanx_left_in[20]; +// ----- Local connection due to Wire 94 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[23] = chanx_left_in[22]; +// ----- Local connection due to Wire 95 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[24] = chanx_left_in[23]; +// ----- Local connection due to Wire 96 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[25] = chanx_left_in[24]; +// ----- Local connection due to Wire 98 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[27] = chanx_left_in[26]; +// ----- Local connection due to Wire 99 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[28] = chanx_left_in[27]; +// ----- Local connection due to Wire 100 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[29] = chanx_left_in[28]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size7 mux_top_track_0 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[1], chanx_right_in[3], chanx_left_in[0], chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_top_track_0_undriven_sram_inv[0:2]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size7 mux_right_track_6 ( + .in({chany_top_in[2], chany_top_in[13], chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_right_track_6_undriven_sram_inv[0:2]), + .out(chanx_right_out[3])); + + mux_tree_tapbuf_size7 mux_right_track_10 ( + .in({chany_top_in[3], chany_top_in[14], chany_top_in[25], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_right_track_10_undriven_sram_inv[0:2]), + .out(chanx_right_out[5])); + + mux_tree_tapbuf_size7 mux_left_track_1 ( + .in({chany_top_in[0], chany_top_in[11], chany_top_in[22], chanx_right_in[3], chanx_right_in[19], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_left_track_1_undriven_sram_inv[0:2]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size7 mux_left_track_11 ( + .in({chany_top_in[7], chany_top_in[18], chany_top_in[29], chanx_right_in[10], chanx_right_in[24], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_4_sram[0:2]), + .sram_inv(mux_left_track_11_undriven_sram_inv[0:2]), + .out(chanx_left_out[5])); + + mux_tree_tapbuf_size7_mem mem_top_track_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_right_track_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_right_track_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_left_track_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_left_track_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram[0:2])); + + mux_tree_tapbuf_size6 mux_top_track_2 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[2], chanx_right_in[6], chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_top_track_2_undriven_sram_inv[0:2]), + .out(chany_top_out[1])); + + mux_tree_tapbuf_size6 mux_top_track_6 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[5], chanx_right_in[8], chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_top_track_6_undriven_sram_inv[0:2]), + .out(chany_top_out[3])); + + mux_tree_tapbuf_size6 mux_top_track_8 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[9:10], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_top_track_8_undriven_sram_inv[0:2]), + .out(chany_top_out[4])); + + mux_tree_tapbuf_size6 mux_right_track_0 ( + .in({chany_top_in[10], chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_right_track_0_undriven_sram_inv[0:2]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size6 mux_right_track_2 ( + .in({chany_top_in[0], chany_top_in[11], chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_right_track_2_undriven_sram_inv[0:2]), + .out(chanx_right_out[1])); + + mux_tree_tapbuf_size6 mux_right_track_4 ( + .in({chany_top_in[1], chany_top_in[12], chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_right_track_4_undriven_sram_inv[0:2]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size6 mux_right_track_12 ( + .in({chany_top_in[4], chany_top_in[15], chany_top_in[26], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[11], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_right_track_12_undriven_sram_inv[0:2]), + .out(chanx_right_out[6])); + + mux_tree_tapbuf_size6 mux_right_track_20 ( + .in({chany_top_in[5], chany_top_in[16], chany_top_in[27], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size6_7_sram[0:2]), + .sram_inv(mux_right_track_20_undriven_sram_inv[0:2]), + .out(chanx_right_out[10])); + + mux_tree_tapbuf_size6 mux_right_track_28 ( + .in({chany_top_in[6], chany_top_in[17], chany_top_in[28], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size6_8_sram[0:2]), + .sram_inv(mux_right_track_28_undriven_sram_inv[0:2]), + .out(chanx_right_out[14])); + + mux_tree_tapbuf_size6 mux_left_track_7 ( + .in({chany_top_in[8], chany_top_in[19], chanx_right_in[8], chanx_right_in[23], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_9_sram[0:2]), + .sram_inv(mux_left_track_7_undriven_sram_inv[0:2]), + .out(chanx_left_out[3])); + + mux_tree_tapbuf_size6 mux_left_track_13 ( + .in({chany_top_in[6], chany_top_in[17], chany_top_in[28], chanx_right_in[11], chanx_right_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_10_sram[0:2]), + .sram_inv(mux_left_track_13_undriven_sram_inv[0:2]), + .out(chanx_left_out[6])); + + mux_tree_tapbuf_size6 mux_left_track_21 ( + .in({chany_top_in[5], chany_top_in[16], chany_top_in[27], chanx_right_in[12], chanx_right_in[27], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_11_sram[0:2]), + .sram_inv(mux_left_track_21_undriven_sram_inv[0:2]), + .out(chanx_left_out[10])); + + mux_tree_tapbuf_size6 mux_left_track_29 ( + .in({chany_top_in[4], chany_top_in[15], chany_top_in[26], chanx_right_in[14], chanx_right_in[28], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_12_sram[0:2]), + .sram_inv(mux_left_track_29_undriven_sram_inv[0:2]), + .out(chanx_left_out[14])); + + mux_tree_tapbuf_size6_mem mem_top_track_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_track_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_track_8 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_20 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_28 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_21 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_11_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_29 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_12_sram[0:2])); + + mux_tree_tapbuf_size5 mux_top_track_4 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[4], chanx_right_in[7], chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_top_track_4_undriven_sram_inv[0:2]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size5 mux_top_track_10 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[11], chanx_right_in[13], chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_top_track_10_undriven_sram_inv[0:2]), + .out(chany_top_out[5])); + + mux_tree_tapbuf_size5 mux_right_track_36 ( + .in({chany_top_in[7], chany_top_in[18], chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size5_2_sram[0:2]), + .sram_inv(mux_right_track_36_undriven_sram_inv[0:2]), + .out(chanx_right_out[18])); + + mux_tree_tapbuf_size5 mux_left_track_3 ( + .in({chany_top_in[10], chany_top_in[21], chanx_right_in[6], chanx_right_in[20], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_3_sram[0:2]), + .sram_inv(mux_left_track_3_undriven_sram_inv[0:2]), + .out(chanx_left_out[1])); + + mux_tree_tapbuf_size5 mux_left_track_5 ( + .in({chany_top_in[9], chany_top_in[20], chanx_right_in[7], chanx_right_in[22], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_4_sram[0:2]), + .sram_inv(mux_left_track_5_undriven_sram_inv[0:2]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size5 mux_left_track_37 ( + .in({chany_top_in[3], chany_top_in[14], chany_top_in[25], chanx_right_in[15], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_5_sram[0:2]), + .sram_inv(mux_left_track_37_undriven_sram_inv[0:2]), + .out(chanx_left_out[18])); + + mux_tree_tapbuf_size5_mem mem_top_track_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_top_track_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_right_track_36 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_37 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram[0:2])); + + mux_tree_tapbuf_size4 mux_top_track_12 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_right_in[12], chanx_right_in[17], chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_top_track_12_undriven_sram_inv[0:2]), + .out(chany_top_out[6])); + + mux_tree_tapbuf_size4 mux_top_track_14 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_right_in[14], chanx_right_in[21], chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_top_track_14_undriven_sram_inv[0:2]), + .out(chany_top_out[7])); + + mux_tree_tapbuf_size4 mux_top_track_16 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_right_in[15], chanx_right_in[25], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_top_track_16_undriven_sram_inv[0:2]), + .out(chany_top_out[8])); + + mux_tree_tapbuf_size4 mux_top_track_18 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_right_in[16], chanx_right_in[29], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_top_track_18_undriven_sram_inv[0:2]), + .out(chany_top_out[9])); + + mux_tree_tapbuf_size4 mux_left_track_45 ( + .in({chany_top_in[2], chany_top_in[13], chany_top_in[24], chanx_right_in[16]}), + .sram(mux_tree_tapbuf_size4_4_sram[0:2]), + .sram_inv(mux_left_track_45_undriven_sram_inv[0:2]), + .out(chanx_left_out[22])); + + mux_tree_tapbuf_size4 mux_left_track_53 ( + .in({chany_top_in[1], chany_top_in[12], chany_top_in[23], chanx_right_in[18]}), + .sram(mux_tree_tapbuf_size4_5_sram[0:2]), + .sram_inv(mux_left_track_53_undriven_sram_inv[0:2]), + .out(chanx_left_out[26])); + + mux_tree_tapbuf_size4_mem mem_top_track_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_top_track_14 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_top_track_16 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_top_track_18 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_45 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_53 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram[0:2])); + + mux_tree_tapbuf_size3 mux_top_track_20 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_right_in[18], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_top_track_20_undriven_sram_inv[0:1]), + .out(chany_top_out[10])); + + mux_tree_tapbuf_size3 mux_top_track_22 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[19], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_top_track_22_undriven_sram_inv[0:1]), + .out(chany_top_out[11])); + + mux_tree_tapbuf_size3 mux_top_track_24 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[20], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_top_track_24_undriven_sram_inv[0:1]), + .out(chany_top_out[12])); + + mux_tree_tapbuf_size3 mux_top_track_26 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[22], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_top_track_26_undriven_sram_inv[0:1]), + .out(chany_top_out[13])); + + mux_tree_tapbuf_size3 mux_top_track_36 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_right_in[28], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_top_track_36_undriven_sram_inv[0:1]), + .out(chany_top_out[18])); + + mux_tree_tapbuf_size3 mux_right_track_44 ( + .in({chany_top_in[8], chany_top_in[19], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_right_track_44_undriven_sram_inv[0:1]), + .out(chanx_right_out[22])); + + mux_tree_tapbuf_size3 mux_right_track_52 ( + .in({chany_top_in[9], chany_top_in[20], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_right_track_52_undriven_sram_inv[0:1]), + .out(chanx_right_out[26])); + + mux_tree_tapbuf_size3_mem mem_top_track_20 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_22 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_24 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_26 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_36 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_44 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_52 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1])); + + mux_tree_tapbuf_size2 mux_top_track_28 ( + .in({chanx_right_in[23], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_top_track_28_undriven_sram_inv[0:1]), + .out(chany_top_out[14])); + + mux_tree_tapbuf_size2 mux_top_track_30 ( + .in({chanx_right_in[24], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_top_track_30_undriven_sram_inv[0:1]), + .out(chany_top_out[15])); + + mux_tree_tapbuf_size2 mux_top_track_32 ( + .in({chanx_right_in[26], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_top_track_32_undriven_sram_inv[0:1]), + .out(chany_top_out[16])); + + mux_tree_tapbuf_size2 mux_top_track_34 ( + .in({chanx_right_in[27], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_top_track_34_undriven_sram_inv[0:1]), + .out(chany_top_out[17])); + + mux_tree_tapbuf_size2 mux_top_track_40 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_top_track_40_undriven_sram_inv[0:1]), + .out(chany_top_out[20])); + + mux_tree_tapbuf_size2 mux_top_track_42 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_top_track_42_undriven_sram_inv[0:1]), + .out(chany_top_out[21])); + + mux_tree_tapbuf_size2 mux_top_track_44 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_top_track_44_undriven_sram_inv[0:1]), + .out(chany_top_out[22])); + + mux_tree_tapbuf_size2 mux_top_track_46 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_top_track_46_undriven_sram_inv[0:1]), + .out(chany_top_out[23])); + + mux_tree_tapbuf_size2 mux_top_track_48 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_top_track_48_undriven_sram_inv[0:1]), + .out(chany_top_out[24])); + + mux_tree_tapbuf_size2 mux_top_track_50 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_top_track_50_undriven_sram_inv[0:1]), + .out(chany_top_out[25])); + + mux_tree_tapbuf_size2 mux_top_track_58 ( + .in({chanx_right_in[0], chanx_left_in[1]}), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_top_track_58_undriven_sram_inv[0:1]), + .out(chany_top_out[29])); + + mux_tree_tapbuf_size2_mem mem_top_track_28 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_30 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_32 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_34 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_40 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_42 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_44 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_46 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_48 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_50 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_58 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1])); + +endmodule +// ----- END Verilog module for sb_1__0_ ----- + +//----- Default net type ----- +`default_nettype none + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__1_.v new file mode 100644 index 0000000..f4c49c6 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__1_.v @@ -0,0 +1,1175 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[1][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_1__1_ ----- +module sb_1__1_(pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_right_in, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + chany_bottom_in, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_left_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + ccff_head, + chany_top_out, + chanx_right_out, + chany_bottom_out, + chanx_left_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:29] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; +//----- INPUT PORTS ----- +input [0:29] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; +//----- INPUT PORTS ----- +input [0:29] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; +//----- INPUT PORTS ----- +input [0:29] chanx_left_in; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:29] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:29] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:29] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:29] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:3] mux_bottom_track_11_undriven_sram_inv; +wire [0:3] mux_bottom_track_13_undriven_sram_inv; +wire [0:3] mux_bottom_track_1_undriven_sram_inv; +wire [0:3] mux_bottom_track_21_undriven_sram_inv; +wire [0:3] mux_bottom_track_29_undriven_sram_inv; +wire [0:2] mux_bottom_track_37_undriven_sram_inv; +wire [0:3] mux_bottom_track_3_undriven_sram_inv; +wire [0:2] mux_bottom_track_45_undriven_sram_inv; +wire [0:2] mux_bottom_track_53_undriven_sram_inv; +wire [0:3] mux_bottom_track_5_undriven_sram_inv; +wire [0:3] mux_bottom_track_7_undriven_sram_inv; +wire [0:3] mux_left_track_11_undriven_sram_inv; +wire [0:3] mux_left_track_13_undriven_sram_inv; +wire [0:3] mux_left_track_1_undriven_sram_inv; +wire [0:3] mux_left_track_21_undriven_sram_inv; +wire [0:3] mux_left_track_29_undriven_sram_inv; +wire [0:2] mux_left_track_37_undriven_sram_inv; +wire [0:3] mux_left_track_3_undriven_sram_inv; +wire [0:2] mux_left_track_45_undriven_sram_inv; +wire [0:2] mux_left_track_53_undriven_sram_inv; +wire [0:3] mux_left_track_5_undriven_sram_inv; +wire [0:3] mux_left_track_7_undriven_sram_inv; +wire [0:3] mux_right_track_0_undriven_sram_inv; +wire [0:3] mux_right_track_10_undriven_sram_inv; +wire [0:3] mux_right_track_12_undriven_sram_inv; +wire [0:3] mux_right_track_20_undriven_sram_inv; +wire [0:3] mux_right_track_28_undriven_sram_inv; +wire [0:3] mux_right_track_2_undriven_sram_inv; +wire [0:2] mux_right_track_36_undriven_sram_inv; +wire [0:2] mux_right_track_44_undriven_sram_inv; +wire [0:3] mux_right_track_4_undriven_sram_inv; +wire [0:2] mux_right_track_52_undriven_sram_inv; +wire [0:3] mux_right_track_6_undriven_sram_inv; +wire [0:3] mux_top_track_0_undriven_sram_inv; +wire [0:3] mux_top_track_10_undriven_sram_inv; +wire [0:3] mux_top_track_12_undriven_sram_inv; +wire [0:3] mux_top_track_20_undriven_sram_inv; +wire [0:3] mux_top_track_28_undriven_sram_inv; +wire [0:3] mux_top_track_2_undriven_sram_inv; +wire [0:2] mux_top_track_36_undriven_sram_inv; +wire [0:2] mux_top_track_44_undriven_sram_inv; +wire [0:3] mux_top_track_4_undriven_sram_inv; +wire [0:2] mux_top_track_52_undriven_sram_inv; +wire [0:3] mux_top_track_6_undriven_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_0_sram; +wire [0:3] mux_tree_tapbuf_size10_10_sram; +wire [0:3] mux_tree_tapbuf_size10_11_sram; +wire [0:3] mux_tree_tapbuf_size10_1_sram; +wire [0:3] mux_tree_tapbuf_size10_2_sram; +wire [0:3] mux_tree_tapbuf_size10_3_sram; +wire [0:3] mux_tree_tapbuf_size10_4_sram; +wire [0:3] mux_tree_tapbuf_size10_5_sram; +wire [0:3] mux_tree_tapbuf_size10_6_sram; +wire [0:3] mux_tree_tapbuf_size10_7_sram; +wire [0:3] mux_tree_tapbuf_size10_8_sram; +wire [0:3] mux_tree_tapbuf_size10_9_sram; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail; +wire [0:3] mux_tree_tapbuf_size11_0_sram; +wire [0:3] mux_tree_tapbuf_size11_1_sram; +wire [0:3] mux_tree_tapbuf_size11_2_sram; +wire [0:3] mux_tree_tapbuf_size11_3_sram; +wire [0:3] mux_tree_tapbuf_size11_4_sram; +wire [0:3] mux_tree_tapbuf_size11_5_sram; +wire [0:3] mux_tree_tapbuf_size11_6_sram; +wire [0:3] mux_tree_tapbuf_size11_7_sram; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size11_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size11_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size11_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size11_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size11_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size11_mem_7_ccff_tail; +wire [0:3] mux_tree_tapbuf_size12_0_sram; +wire [0:3] mux_tree_tapbuf_size12_1_sram; +wire [0:3] mux_tree_tapbuf_size12_2_sram; +wire [0:3] mux_tree_tapbuf_size12_3_sram; +wire [0:3] mux_tree_tapbuf_size12_4_sram; +wire [0:3] mux_tree_tapbuf_size12_5_sram; +wire [0:3] mux_tree_tapbuf_size12_6_sram; +wire [0:3] mux_tree_tapbuf_size12_7_sram; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail; +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_10_sram; +wire [0:2] mux_tree_tapbuf_size6_11_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_4_sram; +wire [0:2] mux_tree_tapbuf_size6_5_sram; +wire [0:2] mux_tree_tapbuf_size6_6_sram; +wire [0:2] mux_tree_tapbuf_size6_7_sram; +wire [0:2] mux_tree_tapbuf_size6_8_sram; +wire [0:2] mux_tree_tapbuf_size6_9_sram; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail; +wire [0:3] mux_tree_tapbuf_size9_0_sram; +wire [0:3] mux_tree_tapbuf_size9_1_sram; +wire [0:3] mux_tree_tapbuf_size9_2_sram; +wire [0:3] mux_tree_tapbuf_size9_3_sram; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[4] = chany_top_in[3]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[7] = chany_top_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[8] = chany_top_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[9] = chany_top_in[8]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[11] = chany_top_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[12] = chany_top_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[13] = chany_top_in[12]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[15] = chany_top_in[14]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[16] = chany_top_in[15]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[17] = chany_top_in[16]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[19] = chany_top_in[18]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[20] = chany_top_in[19]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[21] = chany_top_in[20]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[23] = chany_top_in[22]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[24] = chany_top_in[23]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[25] = chany_top_in[24]; +// ----- Local connection due to Wire 26 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[27] = chany_top_in[26]; +// ----- Local connection due to Wire 27 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[28] = chany_top_in[27]; +// ----- Local connection due to Wire 28 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chany_bottom_out[29] = chany_top_in[28]; +// ----- Local connection due to Wire 41 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[4] = chanx_right_in[3]; +// ----- Local connection due to Wire 44 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[7] = chanx_right_in[6]; +// ----- Local connection due to Wire 45 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[8] = chanx_right_in[7]; +// ----- Local connection due to Wire 46 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[9] = chanx_right_in[8]; +// ----- Local connection due to Wire 48 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[11] = chanx_right_in[10]; +// ----- Local connection due to Wire 49 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[12] = chanx_right_in[11]; +// ----- Local connection due to Wire 50 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[13] = chanx_right_in[12]; +// ----- Local connection due to Wire 52 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[15] = chanx_right_in[14]; +// ----- Local connection due to Wire 53 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[16] = chanx_right_in[15]; +// ----- Local connection due to Wire 54 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[17] = chanx_right_in[16]; +// ----- Local connection due to Wire 56 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[19] = chanx_right_in[18]; +// ----- Local connection due to Wire 57 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[20] = chanx_right_in[19]; +// ----- Local connection due to Wire 58 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[21] = chanx_right_in[20]; +// ----- Local connection due to Wire 60 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[23] = chanx_right_in[22]; +// ----- Local connection due to Wire 61 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[24] = chanx_right_in[23]; +// ----- Local connection due to Wire 62 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[25] = chanx_right_in[24]; +// ----- Local connection due to Wire 64 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[27] = chanx_right_in[26]; +// ----- Local connection due to Wire 65 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[28] = chanx_right_in[27]; +// ----- Local connection due to Wire 66 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[29] = chanx_right_in[28]; +// ----- Local connection due to Wire 79 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[4] = chany_bottom_in[3]; +// ----- Local connection due to Wire 82 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[7] = chany_bottom_in[6]; +// ----- Local connection due to Wire 83 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[8] = chany_bottom_in[7]; +// ----- Local connection due to Wire 84 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[9] = chany_bottom_in[8]; +// ----- Local connection due to Wire 86 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[11] = chany_bottom_in[10]; +// ----- Local connection due to Wire 87 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[12] = chany_bottom_in[11]; +// ----- Local connection due to Wire 88 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[13] = chany_bottom_in[12]; +// ----- Local connection due to Wire 90 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[15] = chany_bottom_in[14]; +// ----- Local connection due to Wire 91 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[16] = chany_bottom_in[15]; +// ----- Local connection due to Wire 92 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[17] = chany_bottom_in[16]; +// ----- Local connection due to Wire 94 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[19] = chany_bottom_in[18]; +// ----- Local connection due to Wire 95 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[20] = chany_bottom_in[19]; +// ----- Local connection due to Wire 96 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[21] = chany_bottom_in[20]; +// ----- Local connection due to Wire 98 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[23] = chany_bottom_in[22]; +// ----- Local connection due to Wire 99 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[24] = chany_bottom_in[23]; +// ----- Local connection due to Wire 100 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[25] = chany_bottom_in[24]; +// ----- Local connection due to Wire 102 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[27] = chany_bottom_in[26]; +// ----- Local connection due to Wire 103 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[28] = chany_bottom_in[27]; +// ----- Local connection due to Wire 104 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[29] = chany_bottom_in[28]; +// ----- Local connection due to Wire 117 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[4] = chanx_left_in[3]; +// ----- Local connection due to Wire 120 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[7] = chanx_left_in[6]; +// ----- Local connection due to Wire 121 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[8] = chanx_left_in[7]; +// ----- Local connection due to Wire 122 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[9] = chanx_left_in[8]; +// ----- Local connection due to Wire 124 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[11] = chanx_left_in[10]; +// ----- Local connection due to Wire 125 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[12] = chanx_left_in[11]; +// ----- Local connection due to Wire 126 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[13] = chanx_left_in[12]; +// ----- Local connection due to Wire 128 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[15] = chanx_left_in[14]; +// ----- Local connection due to Wire 129 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[16] = chanx_left_in[15]; +// ----- Local connection due to Wire 130 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[17] = chanx_left_in[16]; +// ----- Local connection due to Wire 132 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[19] = chanx_left_in[18]; +// ----- Local connection due to Wire 133 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[20] = chanx_left_in[19]; +// ----- Local connection due to Wire 134 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[21] = chanx_left_in[20]; +// ----- Local connection due to Wire 136 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[23] = chanx_left_in[22]; +// ----- Local connection due to Wire 137 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[24] = chanx_left_in[23]; +// ----- Local connection due to Wire 138 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[25] = chanx_left_in[24]; +// ----- Local connection due to Wire 140 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[27] = chanx_left_in[26]; +// ----- Local connection due to Wire 141 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[28] = chanx_left_in[27]; +// ----- Local connection due to Wire 142 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_right_out[29] = chanx_left_in[28]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size11 mux_top_track_0 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[1], chanx_right_in[3], chanx_right_in[19], chany_bottom_in[3], chany_bottom_in[19], chanx_left_in[0], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size11_0_sram[0:3]), + .sram_inv(mux_top_track_0_undriven_sram_inv[0:3]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size11 mux_top_track_2 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[2], chanx_right_in[6], chanx_right_in[20], chany_bottom_in[6], chany_bottom_in[20], chanx_left_in[6], chanx_left_in[20], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size11_1_sram[0:3]), + .sram_inv(mux_top_track_2_undriven_sram_inv[0:3]), + .out(chany_top_out[1])); + + mux_tree_tapbuf_size11 mux_right_track_0 ( + .in({chany_top_in[3], chany_top_in[19], chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[3], chany_bottom_in[19], chany_bottom_in[25], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size11_2_sram[0:3]), + .sram_inv(mux_right_track_0_undriven_sram_inv[0:3]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size11 mux_right_track_2 ( + .in({chany_top_in[0], chany_top_in[6], chany_top_in[20], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[6], chany_bottom_in[20:21], chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size11_3_sram[0:3]), + .sram_inv(mux_right_track_2_undriven_sram_inv[0:3]), + .out(chanx_right_out[1])); + + mux_tree_tapbuf_size11 mux_bottom_track_1 ( + .in({chany_top_in[3], chany_top_in[19], chanx_right_in[3], chanx_right_in[19], chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[1], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size11_4_sram[0:3]), + .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:3]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size11 mux_bottom_track_3 ( + .in({chany_top_in[6], chany_top_in[20], chanx_right_in[6], chanx_right_in[20:21], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[2], chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size11_5_sram[0:3]), + .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:3]), + .out(chany_bottom_out[1])); + + mux_tree_tapbuf_size11 mux_left_track_1 ( + .in({chany_top_in[0], chany_top_in[3], chany_top_in[19], chanx_right_in[3], chanx_right_in[19], chany_bottom_in[3], chany_bottom_in[19], chany_bottom_in[29], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size11_6_sram[0:3]), + .sram_inv(mux_left_track_1_undriven_sram_inv[0:3]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size11 mux_left_track_3 ( + .in({chany_top_in[6], chany_top_in[20], chany_top_in[29], chanx_right_in[6], chanx_right_in[20], chany_bottom_in[0], chany_bottom_in[6], chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size11_7_sram[0:3]), + .sram_inv(mux_left_track_3_undriven_sram_inv[0:3]), + .out(chanx_left_out[1])); + + mux_tree_tapbuf_size11_mem mem_top_track_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_0_sram[0:3])); + + mux_tree_tapbuf_size11_mem mem_top_track_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_1_sram[0:3])); + + mux_tree_tapbuf_size11_mem mem_right_track_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_2_sram[0:3])); + + mux_tree_tapbuf_size11_mem mem_right_track_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_3_sram[0:3])); + + mux_tree_tapbuf_size11_mem mem_bottom_track_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_4_sram[0:3])); + + mux_tree_tapbuf_size11_mem mem_bottom_track_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_5_sram[0:3])); + + mux_tree_tapbuf_size11_mem mem_left_track_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_6_sram[0:3])); + + mux_tree_tapbuf_size11_mem mem_left_track_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_7_sram[0:3])); + + mux_tree_tapbuf_size10 mux_top_track_4 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[4], chanx_right_in[7], chanx_right_in[22], chany_bottom_in[7], chany_bottom_in[22], chanx_left_in[7], chanx_left_in[22], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_top_track_4_undriven_sram_inv[0:3]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size10 mux_top_track_12 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[11], chanx_right_in[13], chanx_right_in[26], chany_bottom_in[11], chany_bottom_in[26], chanx_left_in[11], chanx_left_in[13], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_top_track_12_undriven_sram_inv[0:3]), + .out(chany_top_out[6])); + + mux_tree_tapbuf_size10 mux_top_track_20 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[12], chanx_right_in[17], chanx_right_in[27], chany_bottom_in[12], chany_bottom_in[27], chanx_left_in[9], chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_top_track_20_undriven_sram_inv[0:3]), + .out(chany_top_out[10])); + + mux_tree_tapbuf_size10 mux_right_track_4 ( + .in({chany_top_in[1], chany_top_in[7], chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[7], chany_bottom_in[17], chany_bottom_in[22], chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_right_track_4_undriven_sram_inv[0:3]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size10 mux_right_track_12 ( + .in({chany_top_in[5], chany_top_in[11], chany_top_in[26], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[5], chany_bottom_in[11], chany_bottom_in[26], chanx_left_in[11], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_right_track_12_undriven_sram_inv[0:3]), + .out(chanx_right_out[6])); + + mux_tree_tapbuf_size10 mux_right_track_20 ( + .in({chany_top_in[9], chany_top_in[12], chany_top_in[27], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[4], chany_bottom_in[12], chany_bottom_in[27], chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_right_track_20_undriven_sram_inv[0:3]), + .out(chanx_right_out[10])); + + mux_tree_tapbuf_size10 mux_bottom_track_5 ( + .in({chany_top_in[7], chany_top_in[22], chanx_right_in[7], chanx_right_in[17], chanx_right_in[22], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[4], chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:3]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size10 mux_bottom_track_13 ( + .in({chany_top_in[11], chany_top_in[26], chanx_right_in[5], chanx_right_in[11], chanx_right_in[26], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[11], chanx_left_in[13], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_bottom_track_13_undriven_sram_inv[0:3]), + .out(chany_bottom_out[6])); + + mux_tree_tapbuf_size10 mux_bottom_track_21 ( + .in({chany_top_in[12], chany_top_in[27], chanx_right_in[4], chanx_right_in[12], chanx_right_in[27], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[12], chanx_left_in[17], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size10_8_sram[0:3]), + .sram_inv(mux_bottom_track_21_undriven_sram_inv[0:3]), + .out(chany_bottom_out[10])); + + mux_tree_tapbuf_size10 mux_left_track_5 ( + .in({chany_top_in[7], chany_top_in[22], chany_top_in[25], chanx_right_in[7], chanx_right_in[22], chany_bottom_in[1], chany_bottom_in[7], chany_bottom_in[22], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size10_9_sram[0:3]), + .sram_inv(mux_left_track_5_undriven_sram_inv[0:3]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size10 mux_left_track_13 ( + .in({chany_top_in[11], chany_top_in[13], chany_top_in[26], chanx_right_in[11], chanx_right_in[26], chany_bottom_in[5], chany_bottom_in[11], chany_bottom_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size10_10_sram[0:3]), + .sram_inv(mux_left_track_13_undriven_sram_inv[0:3]), + .out(chanx_left_out[6])); + + mux_tree_tapbuf_size10 mux_left_track_21 ( + .in({chany_top_in[9], chany_top_in[12], chany_top_in[27], chanx_right_in[12], chanx_right_in[27], chany_bottom_in[9], chany_bottom_in[12], chany_bottom_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size10_11_sram[0:3]), + .sram_inv(mux_left_track_21_undriven_sram_inv[0:3]), + .out(chanx_left_out[10])); + + mux_tree_tapbuf_size10_mem mem_top_track_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_track_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_track_20 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_track_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_track_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_track_20 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_track_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_track_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_track_21 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_8_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_left_track_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_9_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_left_track_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_10_sram[0:3])); + + mux_tree_tapbuf_size10_mem mem_left_track_21 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_11_sram[0:3])); + + mux_tree_tapbuf_size12 mux_top_track_6 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[5], chanx_right_in[8], chanx_right_in[23], chany_bottom_in[8], chany_bottom_in[23], chanx_left_in[8], chanx_left_in[21], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size12_0_sram[0:3]), + .sram_inv(mux_top_track_6_undriven_sram_inv[0:3]), + .out(chany_top_out[3])); + + mux_tree_tapbuf_size12 mux_top_track_10 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[9:10], chanx_right_in[24], chany_bottom_in[10], chany_bottom_in[24], chanx_left_in[10], chanx_left_in[17], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size12_1_sram[0:3]), + .sram_inv(mux_top_track_10_undriven_sram_inv[0:3]), + .out(chany_top_out[5])); + + mux_tree_tapbuf_size12 mux_right_track_6 ( + .in({chany_top_in[2], chany_top_in[8], chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[8], chany_bottom_in[13], chany_bottom_in[23], chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size12_2_sram[0:3]), + .sram_inv(mux_right_track_6_undriven_sram_inv[0:3]), + .out(chanx_right_out[3])); + + mux_tree_tapbuf_size12 mux_right_track_10 ( + .in({chany_top_in[4], chany_top_in[10], chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[9:10], chany_bottom_in[24], chanx_left_in[10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size12_3_sram[0:3]), + .sram_inv(mux_right_track_10_undriven_sram_inv[0:3]), + .out(chanx_right_out[5])); + + mux_tree_tapbuf_size12 mux_bottom_track_7 ( + .in({chany_top_in[8], chany_top_in[23], chanx_right_in[8], chanx_right_in[13], chanx_right_in[23], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[5], chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size12_4_sram[0:3]), + .sram_inv(mux_bottom_track_7_undriven_sram_inv[0:3]), + .out(chany_bottom_out[3])); + + mux_tree_tapbuf_size12 mux_bottom_track_11 ( + .in({chany_top_in[10], chany_top_in[24], chanx_right_in[9:10], chanx_right_in[24], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[9:10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size12_5_sram[0:3]), + .sram_inv(mux_bottom_track_11_undriven_sram_inv[0:3]), + .out(chany_bottom_out[5])); + + mux_tree_tapbuf_size12 mux_left_track_7 ( + .in({chany_top_in[8], chany_top_in[21], chany_top_in[23], chanx_right_in[8], chanx_right_in[23], chany_bottom_in[2], chany_bottom_in[8], chany_bottom_in[23], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size12_6_sram[0:3]), + .sram_inv(mux_left_track_7_undriven_sram_inv[0:3]), + .out(chanx_left_out[3])); + + mux_tree_tapbuf_size12 mux_left_track_11 ( + .in({chany_top_in[10], chany_top_in[17], chany_top_in[24], chanx_right_in[10], chanx_right_in[24], chany_bottom_in[4], chany_bottom_in[10], chany_bottom_in[24], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size12_7_sram[0:3]), + .sram_inv(mux_left_track_11_undriven_sram_inv[0:3]), + .out(chanx_left_out[5])); + + mux_tree_tapbuf_size12_mem mem_top_track_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_track_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_track_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_track_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_bottom_track_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_bottom_track_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_left_track_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram[0:3])); + + mux_tree_tapbuf_size12_mem mem_left_track_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram[0:3])); + + mux_tree_tapbuf_size9 mux_top_track_28 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_right_in[14], chanx_right_in[21], chanx_right_in[28], chany_bottom_in[14], chany_bottom_in[28], chanx_left_in[5], chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size9_0_sram[0:3]), + .sram_inv(mux_top_track_28_undriven_sram_inv[0:3]), + .out(chany_top_out[14])); + + mux_tree_tapbuf_size9 mux_right_track_28 ( + .in({chany_top_in[13:14], chany_top_in[28], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[2], chany_bottom_in[14], chany_bottom_in[28], chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size9_1_sram[0:3]), + .sram_inv(mux_right_track_28_undriven_sram_inv[0:3]), + .out(chanx_right_out[14])); + + mux_tree_tapbuf_size9 mux_bottom_track_29 ( + .in({chany_top_in[14], chany_top_in[28], chanx_right_in[2], chanx_right_in[14], chanx_right_in[28], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[14], chanx_left_in[21], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size9_2_sram[0:3]), + .sram_inv(mux_bottom_track_29_undriven_sram_inv[0:3]), + .out(chany_bottom_out[14])); + + mux_tree_tapbuf_size9 mux_left_track_29 ( + .in({chany_top_in[5], chany_top_in[14], chany_top_in[28], chanx_right_in[14], chanx_right_in[28], chany_bottom_in[13:14], chany_bottom_in[28], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size9_3_sram[0:3]), + .sram_inv(mux_left_track_29_undriven_sram_inv[0:3]), + .out(chanx_left_out[14])); + + mux_tree_tapbuf_size9_mem mem_top_track_28 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_0_sram[0:3])); + + mux_tree_tapbuf_size9_mem mem_right_track_28 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_1_sram[0:3])); + + mux_tree_tapbuf_size9_mem mem_bottom_track_29 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_2_sram[0:3])); + + mux_tree_tapbuf_size9_mem mem_left_track_29 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_3_sram[0:3])); + + mux_tree_tapbuf_size6 mux_top_track_36 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_right_in[15], chanx_right_in[25], chany_bottom_in[15], chanx_left_in[4], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_top_track_36_undriven_sram_inv[0:2]), + .out(chany_top_out[18])); + + mux_tree_tapbuf_size6 mux_top_track_44 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_right_in[16], chanx_right_in[29], chany_bottom_in[16], chanx_left_in[2], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_top_track_44_undriven_sram_inv[0:2]), + .out(chany_top_out[22])); + + mux_tree_tapbuf_size6 mux_top_track_52 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[0], chanx_right_in[18], chany_bottom_in[18], chanx_left_in[1], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_top_track_52_undriven_sram_inv[0:2]), + .out(chany_top_out[26])); + + mux_tree_tapbuf_size6 mux_right_track_36 ( + .in({chany_top_in[15], chany_top_in[17], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[1], chany_bottom_in[15], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_right_track_36_undriven_sram_inv[0:2]), + .out(chanx_right_out[18])); + + mux_tree_tapbuf_size6 mux_right_track_44 ( + .in({chany_top_in[16], chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[0], chany_bottom_in[16], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_right_track_44_undriven_sram_inv[0:2]), + .out(chanx_right_out[22])); + + mux_tree_tapbuf_size6 mux_right_track_52 ( + .in({chany_top_in[18], chany_top_in[25], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[18], chany_bottom_in[29], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_right_track_52_undriven_sram_inv[0:2]), + .out(chanx_right_out[26])); + + mux_tree_tapbuf_size6 mux_bottom_track_37 ( + .in({chany_top_in[15], chanx_right_in[1], chanx_right_in[15], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[15], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_bottom_track_37_undriven_sram_inv[0:2]), + .out(chany_bottom_out[18])); + + mux_tree_tapbuf_size6 mux_bottom_track_45 ( + .in({chany_top_in[16], chanx_right_in[0], chanx_right_in[16], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[16], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size6_7_sram[0:2]), + .sram_inv(mux_bottom_track_45_undriven_sram_inv[0:2]), + .out(chany_bottom_out[22])); + + mux_tree_tapbuf_size6 mux_bottom_track_53 ( + .in({chany_top_in[18], chanx_right_in[18], chanx_right_in[29], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[0], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size6_8_sram[0:2]), + .sram_inv(mux_bottom_track_53_undriven_sram_inv[0:2]), + .out(chany_bottom_out[26])); + + mux_tree_tapbuf_size6 mux_left_track_37 ( + .in({chany_top_in[4], chany_top_in[15], chanx_right_in[15], chany_bottom_in[15], chany_bottom_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size6_9_sram[0:2]), + .sram_inv(mux_left_track_37_undriven_sram_inv[0:2]), + .out(chanx_left_out[18])); + + mux_tree_tapbuf_size6 mux_left_track_45 ( + .in({chany_top_in[2], chany_top_in[16], chanx_right_in[16], chany_bottom_in[16], chany_bottom_in[21], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size6_10_sram[0:2]), + .sram_inv(mux_left_track_45_undriven_sram_inv[0:2]), + .out(chanx_left_out[22])); + + mux_tree_tapbuf_size6 mux_left_track_53 ( + .in({chany_top_in[1], chany_top_in[18], chanx_right_in[18], chany_bottom_in[18], chany_bottom_in[25], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size6_11_sram[0:2]), + .sram_inv(mux_left_track_53_undriven_sram_inv[0:2]), + .out(chanx_left_out[26])); + + mux_tree_tapbuf_size6_mem mem_top_track_36 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_track_44 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_track_52 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_36 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_44 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_52 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_37 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_45 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_53 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_37 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_45 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_53 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size6_11_sram[0:2])); + +endmodule +// ----- END Verilog module for sb_1__1_ ----- + +//----- Default net type ----- +`default_nettype none + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__8_.v new file mode 100644 index 0000000..507ecfe --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__8_.v @@ -0,0 +1,1097 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[1][8] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_1__8_ ----- +module sb_1__8_(pReset, + prog_clk, + chanx_right_in, + right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + chany_bottom_in, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_left_in, + left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + ccff_head, + chanx_right_out, + chany_bottom_out, + chanx_left_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:29] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; +//----- INPUT PORTS ----- +input [0:29] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; +//----- INPUT PORTS ----- +input [0:29] chanx_left_in; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:29] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:29] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:29] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:2] mux_bottom_track_11_undriven_sram_inv; +wire [0:2] mux_bottom_track_13_undriven_sram_inv; +wire [0:2] mux_bottom_track_15_undriven_sram_inv; +wire [0:2] mux_bottom_track_17_undriven_sram_inv; +wire [0:2] mux_bottom_track_19_undriven_sram_inv; +wire [0:2] mux_bottom_track_1_undriven_sram_inv; +wire [0:1] mux_bottom_track_21_undriven_sram_inv; +wire [0:1] mux_bottom_track_23_undriven_sram_inv; +wire [0:1] mux_bottom_track_25_undriven_sram_inv; +wire [0:1] mux_bottom_track_27_undriven_sram_inv; +wire [0:1] mux_bottom_track_29_undriven_sram_inv; +wire [0:1] mux_bottom_track_31_undriven_sram_inv; +wire [0:1] mux_bottom_track_33_undriven_sram_inv; +wire [0:1] mux_bottom_track_35_undriven_sram_inv; +wire [0:2] mux_bottom_track_37_undriven_sram_inv; +wire [0:1] mux_bottom_track_39_undriven_sram_inv; +wire [0:2] mux_bottom_track_3_undriven_sram_inv; +wire [0:1] mux_bottom_track_41_undriven_sram_inv; +wire [0:1] mux_bottom_track_43_undriven_sram_inv; +wire [0:1] mux_bottom_track_45_undriven_sram_inv; +wire [0:1] mux_bottom_track_47_undriven_sram_inv; +wire [0:1] mux_bottom_track_49_undriven_sram_inv; +wire [0:1] mux_bottom_track_51_undriven_sram_inv; +wire [0:2] mux_bottom_track_5_undriven_sram_inv; +wire [0:2] mux_bottom_track_7_undriven_sram_inv; +wire [0:2] mux_bottom_track_9_undriven_sram_inv; +wire [0:3] mux_left_track_11_undriven_sram_inv; +wire [0:2] mux_left_track_13_undriven_sram_inv; +wire [0:3] mux_left_track_1_undriven_sram_inv; +wire [0:2] mux_left_track_21_undriven_sram_inv; +wire [0:2] mux_left_track_29_undriven_sram_inv; +wire [0:2] mux_left_track_37_undriven_sram_inv; +wire [0:3] mux_left_track_3_undriven_sram_inv; +wire [0:2] mux_left_track_45_undriven_sram_inv; +wire [0:2] mux_left_track_53_undriven_sram_inv; +wire [0:3] mux_left_track_5_undriven_sram_inv; +wire [0:3] mux_left_track_7_undriven_sram_inv; +wire [0:3] mux_right_track_0_undriven_sram_inv; +wire [0:3] mux_right_track_10_undriven_sram_inv; +wire [0:2] mux_right_track_12_undriven_sram_inv; +wire [0:2] mux_right_track_20_undriven_sram_inv; +wire [0:2] mux_right_track_28_undriven_sram_inv; +wire [0:3] mux_right_track_2_undriven_sram_inv; +wire [0:2] mux_right_track_36_undriven_sram_inv; +wire [0:2] mux_right_track_44_undriven_sram_inv; +wire [0:3] mux_right_track_4_undriven_sram_inv; +wire [0:2] mux_right_track_52_undriven_sram_inv; +wire [0:3] mux_right_track_6_undriven_sram_inv; +wire [0:3] mux_tree_tapbuf_size11_0_sram; +wire [0:3] mux_tree_tapbuf_size11_1_sram; +wire [0:3] mux_tree_tapbuf_size11_2_sram; +wire [0:3] mux_tree_tapbuf_size11_3_sram; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size11_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size11_mem_3_ccff_tail; +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_10_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_7_sram; +wire [0:1] mux_tree_tapbuf_size2_8_sram; +wire [0:1] mux_tree_tapbuf_size2_9_sram; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_2_sram; +wire [0:2] mux_tree_tapbuf_size4_3_sram; +wire [0:2] mux_tree_tapbuf_size4_4_sram; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; +wire [0:2] mux_tree_tapbuf_size5_0_sram; +wire [0:2] mux_tree_tapbuf_size5_1_sram; +wire [0:2] mux_tree_tapbuf_size5_2_sram; +wire [0:2] mux_tree_tapbuf_size5_3_sram; +wire [0:2] mux_tree_tapbuf_size5_4_sram; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_4_sram; +wire [0:2] mux_tree_tapbuf_size6_5_sram; +wire [0:2] mux_tree_tapbuf_size6_6_sram; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; +wire [0:2] mux_tree_tapbuf_size7_0_sram; +wire [0:2] mux_tree_tapbuf_size7_1_sram; +wire [0:2] mux_tree_tapbuf_size7_2_sram; +wire [0:2] mux_tree_tapbuf_size7_3_sram; +wire [0:2] mux_tree_tapbuf_size7_4_sram; +wire [0:2] mux_tree_tapbuf_size7_5_sram; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; +wire [0:3] mux_tree_tapbuf_size8_0_sram; +wire [0:3] mux_tree_tapbuf_size8_1_sram; +wire [0:3] mux_tree_tapbuf_size8_2_sram; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; +wire [0:3] mux_tree_tapbuf_size9_0_sram; +wire [0:3] mux_tree_tapbuf_size9_1_sram; +wire [0:3] mux_tree_tapbuf_size9_2_sram; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[28] = chanx_right_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[27] = chanx_right_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[26] = chanx_right_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[4] = chanx_right_in[3]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[7] = chanx_right_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[8] = chanx_right_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[9] = chanx_right_in[8]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[11] = chanx_right_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[12] = chanx_right_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[13] = chanx_right_in[12]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[15] = chanx_right_in[14]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_left_out[16] = chanx_right_in[15]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_left_out[17] = chanx_right_in[16]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_left_out[19] = chanx_right_in[18]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[20] = chanx_right_in[19]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[21] = chanx_right_in[20]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[23] = chanx_right_in[22]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[24] = chanx_right_in[23]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[25] = chanx_right_in[24]; +// ----- Local connection due to Wire 26 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[27] = chanx_right_in[26]; +// ----- Local connection due to Wire 27 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[28] = chanx_right_in[27]; +// ----- Local connection due to Wire 28 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 2 ----- + assign chanx_left_out[29] = chanx_right_in[28]; +// ----- Local connection due to Wire 80 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[29] = chanx_left_in[0]; +// ----- Local connection due to Wire 83 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[4] = chanx_left_in[3]; +// ----- Local connection due to Wire 86 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[7] = chanx_left_in[6]; +// ----- Local connection due to Wire 87 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[8] = chanx_left_in[7]; +// ----- Local connection due to Wire 88 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[9] = chanx_left_in[8]; +// ----- Local connection due to Wire 90 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[11] = chanx_left_in[10]; +// ----- Local connection due to Wire 91 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[12] = chanx_left_in[11]; +// ----- Local connection due to Wire 92 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[13] = chanx_left_in[12]; +// ----- Local connection due to Wire 94 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[15] = chanx_left_in[14]; +// ----- Local connection due to Wire 95 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[16] = chanx_left_in[15]; +// ----- Local connection due to Wire 96 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[17] = chanx_left_in[16]; +// ----- Local connection due to Wire 98 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[19] = chanx_left_in[18]; +// ----- Local connection due to Wire 99 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[20] = chanx_left_in[19]; +// ----- Local connection due to Wire 100 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[21] = chanx_left_in[20]; +// ----- Local connection due to Wire 102 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[23] = chanx_left_in[22]; +// ----- Local connection due to Wire 103 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[24] = chanx_left_in[23]; +// ----- Local connection due to Wire 104 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[25] = chanx_left_in[24]; +// ----- Local connection due to Wire 106 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[27] = chanx_left_in[26]; +// ----- Local connection due to Wire 107 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[28] = chanx_left_in[27]; +// ----- Local connection due to Wire 108 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chanx_right_out[29] = chanx_left_in[28]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size8 mux_right_track_0 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[9], chany_bottom_in[20], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_right_track_0_undriven_sram_inv[0:3]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size8 mux_right_track_2 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[8], chany_bottom_in[19], chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_right_track_2_undriven_sram_inv[0:3]), + .out(chanx_right_out[1])); + + mux_tree_tapbuf_size8 mux_left_track_1 ( + .in({chanx_right_in[3], chanx_right_in[19], chany_bottom_in[10], chany_bottom_in[21], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_left_track_1_undriven_sram_inv[0:3]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size8_mem mem_right_track_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3])); + + mux_tree_tapbuf_size8_mem mem_right_track_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3])); + + mux_tree_tapbuf_size8_mem mem_left_track_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3])); + + mux_tree_tapbuf_size9 mux_right_track_4 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[7], chany_bottom_in[18], chany_bottom_in[29], chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size9_0_sram[0:3]), + .sram_inv(mux_right_track_4_undriven_sram_inv[0:3]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size9 mux_left_track_3 ( + .in({chanx_right_in[6], chanx_right_in[20], chany_bottom_in[0], chany_bottom_in[11], chany_bottom_in[22], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size9_1_sram[0:3]), + .sram_inv(mux_left_track_3_undriven_sram_inv[0:3]), + .out(chanx_left_out[1])); + + mux_tree_tapbuf_size9 mux_left_track_5 ( + .in({chanx_right_in[7], chanx_right_in[22], chany_bottom_in[1], chany_bottom_in[12], chany_bottom_in[23], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size9_2_sram[0:3]), + .sram_inv(mux_left_track_5_undriven_sram_inv[0:3]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size9_mem mem_right_track_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_0_sram[0:3])); + + mux_tree_tapbuf_size9_mem mem_left_track_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_1_sram[0:3])); + + mux_tree_tapbuf_size9_mem mem_left_track_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_2_sram[0:3])); + + mux_tree_tapbuf_size11 mux_right_track_6 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[6], chany_bottom_in[17], chany_bottom_in[28], chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size11_0_sram[0:3]), + .sram_inv(mux_right_track_6_undriven_sram_inv[0:3]), + .out(chanx_right_out[3])); + + mux_tree_tapbuf_size11 mux_right_track_10 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[5], chany_bottom_in[16], chany_bottom_in[27], chanx_left_in[10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size11_1_sram[0:3]), + .sram_inv(mux_right_track_10_undriven_sram_inv[0:3]), + .out(chanx_right_out[5])); + + mux_tree_tapbuf_size11 mux_left_track_7 ( + .in({chanx_right_in[8], chanx_right_in[23], chany_bottom_in[2], chany_bottom_in[13], chany_bottom_in[24], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size11_2_sram[0:3]), + .sram_inv(mux_left_track_7_undriven_sram_inv[0:3]), + .out(chanx_left_out[3])); + + mux_tree_tapbuf_size11 mux_left_track_11 ( + .in({chanx_right_in[10], chanx_right_in[24], chany_bottom_in[3], chany_bottom_in[14], chany_bottom_in[25], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size11_3_sram[0:3]), + .sram_inv(mux_left_track_11_undriven_sram_inv[0:3]), + .out(chanx_left_out[5])); + + mux_tree_tapbuf_size11_mem mem_right_track_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_0_sram[0:3])); + + mux_tree_tapbuf_size11_mem mem_right_track_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_1_sram[0:3])); + + mux_tree_tapbuf_size11_mem mem_left_track_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_2_sram[0:3])); + + mux_tree_tapbuf_size11_mem mem_left_track_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_3_sram[0:3])); + + mux_tree_tapbuf_size7 mux_right_track_12 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[4], chany_bottom_in[15], chany_bottom_in[26], chanx_left_in[11], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_right_track_12_undriven_sram_inv[0:2]), + .out(chanx_right_out[6])); + + mux_tree_tapbuf_size7 mux_right_track_20 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[3], chany_bottom_in[14], chany_bottom_in[25], chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_right_track_20_undriven_sram_inv[0:2]), + .out(chanx_right_out[10])); + + mux_tree_tapbuf_size7 mux_right_track_28 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[2], chany_bottom_in[13], chany_bottom_in[24], chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_right_track_28_undriven_sram_inv[0:2]), + .out(chanx_right_out[14])); + + mux_tree_tapbuf_size7 mux_left_track_13 ( + .in({chanx_right_in[11], chanx_right_in[26], chany_bottom_in[4], chany_bottom_in[15], chany_bottom_in[26], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_left_track_13_undriven_sram_inv[0:2]), + .out(chanx_left_out[6])); + + mux_tree_tapbuf_size7 mux_left_track_21 ( + .in({chanx_right_in[12], chanx_right_in[27], chany_bottom_in[5], chany_bottom_in[16], chany_bottom_in[27], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size7_4_sram[0:2]), + .sram_inv(mux_left_track_21_undriven_sram_inv[0:2]), + .out(chanx_left_out[10])); + + mux_tree_tapbuf_size7 mux_left_track_29 ( + .in({chanx_right_in[14], chanx_right_in[28], chany_bottom_in[6], chany_bottom_in[17], chany_bottom_in[28], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size7_5_sram[0:2]), + .sram_inv(mux_left_track_29_undriven_sram_inv[0:2]), + .out(chanx_left_out[14])); + + mux_tree_tapbuf_size7_mem mem_right_track_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_right_track_20 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_right_track_28 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_left_track_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_left_track_21 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_left_track_29 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_5_sram[0:2])); + + mux_tree_tapbuf_size6 mux_right_track_36 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[1], chany_bottom_in[12], chany_bottom_in[23], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_right_track_36_undriven_sram_inv[0:2]), + .out(chanx_right_out[18])); + + mux_tree_tapbuf_size6 mux_right_track_44 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[0], chany_bottom_in[11], chany_bottom_in[22], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_right_track_44_undriven_sram_inv[0:2]), + .out(chanx_right_out[22])); + + mux_tree_tapbuf_size6 mux_bottom_track_1 ( + .in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[1], chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size6 mux_bottom_track_3 ( + .in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[2], chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]), + .out(chany_bottom_out[1])); + + mux_tree_tapbuf_size6 mux_bottom_track_7 ( + .in({chanx_right_in[8], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[5], chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_bottom_track_7_undriven_sram_inv[0:2]), + .out(chany_bottom_out[3])); + + mux_tree_tapbuf_size6 mux_bottom_track_9 ( + .in({chanx_right_in[10], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[9:10]}), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:2]), + .out(chany_bottom_out[4])); + + mux_tree_tapbuf_size6 mux_left_track_37 ( + .in({chanx_right_in[15], chany_bottom_in[7], chany_bottom_in[18], chany_bottom_in[29], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_left_track_37_undriven_sram_inv[0:2]), + .out(chanx_left_out[18])); + + mux_tree_tapbuf_size6_mem mem_right_track_36 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_44 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_37 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2])); + + mux_tree_tapbuf_size5 mux_right_track_52 ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[10], chany_bottom_in[21], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_right_track_52_undriven_sram_inv[0:2]), + .out(chanx_right_out[26])); + + mux_tree_tapbuf_size5 mux_bottom_track_5 ( + .in({chanx_right_in[7], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[4], chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size5 mux_bottom_track_11 ( + .in({chanx_right_in[11], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[11], chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size5_2_sram[0:2]), + .sram_inv(mux_bottom_track_11_undriven_sram_inv[0:2]), + .out(chany_bottom_out[5])); + + mux_tree_tapbuf_size5 mux_left_track_45 ( + .in({chanx_right_in[16], chany_bottom_in[8], chany_bottom_in[19], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size5_3_sram[0:2]), + .sram_inv(mux_left_track_45_undriven_sram_inv[0:2]), + .out(chanx_left_out[22])); + + mux_tree_tapbuf_size5 mux_left_track_53 ( + .in({chanx_right_in[18], chany_bottom_in[9], chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size5_4_sram[0:2]), + .sram_inv(mux_left_track_53_undriven_sram_inv[0:2]), + .out(chanx_left_out[26])); + + mux_tree_tapbuf_size5_mem mem_right_track_52 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_45 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_53 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram[0:2])); + + mux_tree_tapbuf_size4 mux_bottom_track_13 ( + .in({chanx_right_in[12], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[12], chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_bottom_track_13_undriven_sram_inv[0:2]), + .out(chany_bottom_out[6])); + + mux_tree_tapbuf_size4 mux_bottom_track_15 ( + .in({chanx_right_in[14], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[14], chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_bottom_track_15_undriven_sram_inv[0:2]), + .out(chany_bottom_out[7])); + + mux_tree_tapbuf_size4 mux_bottom_track_17 ( + .in({chanx_right_in[15], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[15], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_bottom_track_17_undriven_sram_inv[0:2]), + .out(chany_bottom_out[8])); + + mux_tree_tapbuf_size4 mux_bottom_track_19 ( + .in({chanx_right_in[16], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[16], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_bottom_track_19_undriven_sram_inv[0:2]), + .out(chany_bottom_out[9])); + + mux_tree_tapbuf_size4 mux_bottom_track_37 ( + .in({chanx_right_in[28:29], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size4_4_sram[0:2]), + .sram_inv(mux_bottom_track_37_undriven_sram_inv[0:2]), + .out(chany_bottom_out[18])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_15 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_17 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_19 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_37 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram[0:2])); + + mux_tree_tapbuf_size3 mux_bottom_track_21 ( + .in({chanx_right_in[18], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]), + .out(chany_bottom_out[10])); + + mux_tree_tapbuf_size3 mux_bottom_track_23 ( + .in({chanx_right_in[19], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_bottom_track_23_undriven_sram_inv[0:1]), + .out(chany_bottom_out[11])); + + mux_tree_tapbuf_size3 mux_bottom_track_25 ( + .in({chanx_right_in[20], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_bottom_track_25_undriven_sram_inv[0:1]), + .out(chany_bottom_out[12])); + + mux_tree_tapbuf_size3 mux_bottom_track_27 ( + .in({chanx_right_in[22], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_bottom_track_27_undriven_sram_inv[0:1]), + .out(chany_bottom_out[13])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_21 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_25 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_27 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1])); + + mux_tree_tapbuf_size2 mux_bottom_track_29 ( + .in({chanx_right_in[23], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_bottom_track_29_undriven_sram_inv[0:1]), + .out(chany_bottom_out[14])); + + mux_tree_tapbuf_size2 mux_bottom_track_31 ( + .in({chanx_right_in[24], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_bottom_track_31_undriven_sram_inv[0:1]), + .out(chany_bottom_out[15])); + + mux_tree_tapbuf_size2 mux_bottom_track_33 ( + .in({chanx_right_in[26], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_bottom_track_33_undriven_sram_inv[0:1]), + .out(chany_bottom_out[16])); + + mux_tree_tapbuf_size2 mux_bottom_track_35 ( + .in({chanx_right_in[27], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_bottom_track_35_undriven_sram_inv[0:1]), + .out(chany_bottom_out[17])); + + mux_tree_tapbuf_size2 mux_bottom_track_39 ( + .in({chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_bottom_track_39_undriven_sram_inv[0:1]), + .out(chany_bottom_out[19])); + + mux_tree_tapbuf_size2 mux_bottom_track_41 ( + .in({chanx_right_in[21], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_bottom_track_41_undriven_sram_inv[0:1]), + .out(chany_bottom_out[20])); + + mux_tree_tapbuf_size2 mux_bottom_track_43 ( + .in({chanx_right_in[17], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_bottom_track_43_undriven_sram_inv[0:1]), + .out(chany_bottom_out[21])); + + mux_tree_tapbuf_size2 mux_bottom_track_45 ( + .in({chanx_right_in[13], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_}), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_bottom_track_45_undriven_sram_inv[0:1]), + .out(chany_bottom_out[22])); + + mux_tree_tapbuf_size2 mux_bottom_track_47 ( + .in({chanx_right_in[9], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_}), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_bottom_track_47_undriven_sram_inv[0:1]), + .out(chany_bottom_out[23])); + + mux_tree_tapbuf_size2 mux_bottom_track_49 ( + .in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_}), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_bottom_track_49_undriven_sram_inv[0:1]), + .out(chany_bottom_out[24])); + + mux_tree_tapbuf_size2 mux_bottom_track_51 ( + .in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_}), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_bottom_track_51_undriven_sram_inv[0:1]), + .out(chany_bottom_out[25])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_29 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_31 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_33 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_35 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_39 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_41 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_43 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_45 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_47 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_49 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_51 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1])); + +endmodule +// ----- END Verilog module for sb_1__8_ ----- + +//----- Default net type ----- +`default_nettype none + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__0_.v new file mode 100644 index 0000000..928bfd5 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__0_.v @@ -0,0 +1,875 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[8][0] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_8__0_ ----- +module sb_8__0_(pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + chanx_left_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_left_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:29] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:29] chanx_left_in; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:29] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:29] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:1] mux_left_track_11_undriven_sram_inv; +wire [0:1] mux_left_track_13_undriven_sram_inv; +wire [0:1] mux_left_track_15_undriven_sram_inv; +wire [0:1] mux_left_track_17_undriven_sram_inv; +wire [0:1] mux_left_track_19_undriven_sram_inv; +wire [0:1] mux_left_track_1_undriven_sram_inv; +wire [0:1] mux_left_track_29_undriven_sram_inv; +wire [0:1] mux_left_track_31_undriven_sram_inv; +wire [0:1] mux_left_track_33_undriven_sram_inv; +wire [0:1] mux_left_track_35_undriven_sram_inv; +wire [0:1] mux_left_track_3_undriven_sram_inv; +wire [0:1] mux_left_track_45_undriven_sram_inv; +wire [0:1] mux_left_track_47_undriven_sram_inv; +wire [0:1] mux_left_track_49_undriven_sram_inv; +wire [0:1] mux_left_track_51_undriven_sram_inv; +wire [0:1] mux_left_track_5_undriven_sram_inv; +wire [0:1] mux_left_track_7_undriven_sram_inv; +wire [0:1] mux_left_track_9_undriven_sram_inv; +wire [0:2] mux_top_track_0_undriven_sram_inv; +wire [0:2] mux_top_track_10_undriven_sram_inv; +wire [0:1] mux_top_track_12_undriven_sram_inv; +wire [0:1] mux_top_track_14_undriven_sram_inv; +wire [0:1] mux_top_track_16_undriven_sram_inv; +wire [0:1] mux_top_track_18_undriven_sram_inv; +wire [0:1] mux_top_track_20_undriven_sram_inv; +wire [0:1] mux_top_track_22_undriven_sram_inv; +wire [0:1] mux_top_track_24_undriven_sram_inv; +wire [0:1] mux_top_track_26_undriven_sram_inv; +wire [0:1] mux_top_track_28_undriven_sram_inv; +wire [0:2] mux_top_track_2_undriven_sram_inv; +wire [0:1] mux_top_track_30_undriven_sram_inv; +wire [0:1] mux_top_track_32_undriven_sram_inv; +wire [0:1] mux_top_track_34_undriven_sram_inv; +wire [0:1] mux_top_track_36_undriven_sram_inv; +wire [0:1] mux_top_track_38_undriven_sram_inv; +wire [0:1] mux_top_track_40_undriven_sram_inv; +wire [0:1] mux_top_track_42_undriven_sram_inv; +wire [0:1] mux_top_track_44_undriven_sram_inv; +wire [0:1] mux_top_track_46_undriven_sram_inv; +wire [0:1] mux_top_track_48_undriven_sram_inv; +wire [0:2] mux_top_track_4_undriven_sram_inv; +wire [0:1] mux_top_track_50_undriven_sram_inv; +wire [0:2] mux_top_track_6_undriven_sram_inv; +wire [0:2] mux_top_track_8_undriven_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_10_sram; +wire [0:1] mux_tree_tapbuf_size2_11_sram; +wire [0:1] mux_tree_tapbuf_size2_12_sram; +wire [0:1] mux_tree_tapbuf_size2_13_sram; +wire [0:1] mux_tree_tapbuf_size2_14_sram; +wire [0:1] mux_tree_tapbuf_size2_15_sram; +wire [0:1] mux_tree_tapbuf_size2_16_sram; +wire [0:1] mux_tree_tapbuf_size2_17_sram; +wire [0:1] mux_tree_tapbuf_size2_18_sram; +wire [0:1] mux_tree_tapbuf_size2_19_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_20_sram; +wire [0:1] mux_tree_tapbuf_size2_21_sram; +wire [0:1] mux_tree_tapbuf_size2_22_sram; +wire [0:1] mux_tree_tapbuf_size2_23_sram; +wire [0:1] mux_tree_tapbuf_size2_24_sram; +wire [0:1] mux_tree_tapbuf_size2_25_sram; +wire [0:1] mux_tree_tapbuf_size2_26_sram; +wire [0:1] mux_tree_tapbuf_size2_27_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_7_sram; +wire [0:1] mux_tree_tapbuf_size2_8_sram; +wire [0:1] mux_tree_tapbuf_size2_9_sram; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:1] mux_tree_tapbuf_size3_7_sram; +wire [0:1] mux_tree_tapbuf_size3_8_sram; +wire [0:1] mux_tree_tapbuf_size3_9_sram; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail; +wire [0:2] mux_tree_tapbuf_size5_0_sram; +wire [0:2] mux_tree_tapbuf_size5_1_sram; +wire [0:2] mux_tree_tapbuf_size5_2_sram; +wire [0:2] mux_tree_tapbuf_size5_3_sram; +wire [0:2] mux_tree_tapbuf_size5_4_sram; +wire [0:2] mux_tree_tapbuf_size5_5_sram; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[29] = chany_top_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[28] = chany_top_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[27] = chany_top_in[3]; +// ----- Local connection due to Wire 4 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[26] = chany_top_in[4]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[21] = chany_top_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[20] = chany_top_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[19] = chany_top_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[18] = chany_top_in[12]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[13] = chany_top_in[17]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[12] = chany_top_in[18]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[11] = chany_top_in[19]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[10] = chany_top_in[20]; +// ----- Local connection due to Wire 43 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[29] = chanx_left_in[1]; +// ----- Local connection due to Wire 44 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[28] = chanx_left_in[2]; +// ----- Local connection due to Wire 45 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[27] = chanx_left_in[3]; +// ----- Local connection due to Wire 46 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[26] = chanx_left_in[4]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size5 mux_top_track_0 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[0]}), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_top_track_0_undriven_sram_inv[0:2]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size5 mux_top_track_2 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_top_track_2_undriven_sram_inv[0:2]), + .out(chany_top_out[1])); + + mux_tree_tapbuf_size5 mux_top_track_4 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size5_2_sram[0:2]), + .sram_inv(mux_top_track_4_undriven_sram_inv[0:2]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size5 mux_top_track_6 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size5_3_sram[0:2]), + .sram_inv(mux_top_track_6_undriven_sram_inv[0:2]), + .out(chany_top_out[3])); + + mux_tree_tapbuf_size5 mux_top_track_8 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size5_4_sram[0:2]), + .sram_inv(mux_top_track_8_undriven_sram_inv[0:2]), + .out(chany_top_out[4])); + + mux_tree_tapbuf_size5 mux_top_track_10 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size5_5_sram[0:2]), + .sram_inv(mux_top_track_10_undriven_sram_inv[0:2]), + .out(chany_top_out[5])); + + mux_tree_tapbuf_size5_mem mem_top_track_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_top_track_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_top_track_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_top_track_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_top_track_8 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_top_track_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram[0:2])); + + mux_tree_tapbuf_size3 mux_top_track_12 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_top_track_12_undriven_sram_inv[0:1]), + .out(chany_top_out[6])); + + mux_tree_tapbuf_size3 mux_top_track_14 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_top_track_14_undriven_sram_inv[0:1]), + .out(chany_top_out[7])); + + mux_tree_tapbuf_size3 mux_top_track_16 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_top_track_16_undriven_sram_inv[0:1]), + .out(chany_top_out[8])); + + mux_tree_tapbuf_size3 mux_top_track_18 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_top_track_18_undriven_sram_inv[0:1]), + .out(chany_top_out[9])); + + mux_tree_tapbuf_size3 mux_top_track_44 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_top_track_44_undriven_sram_inv[0:1]), + .out(chany_top_out[22])); + + mux_tree_tapbuf_size3 mux_top_track_46 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_top_track_46_undriven_sram_inv[0:1]), + .out(chany_top_out[23])); + + mux_tree_tapbuf_size3 mux_top_track_48 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_top_track_48_undriven_sram_inv[0:1]), + .out(chany_top_out[24])); + + mux_tree_tapbuf_size3 mux_top_track_50 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[5]}), + .sram(mux_tree_tapbuf_size3_7_sram[0:1]), + .sram_inv(mux_top_track_50_undriven_sram_inv[0:1]), + .out(chany_top_out[25])); + + mux_tree_tapbuf_size3 mux_left_track_1 ( + .in({chany_top_in[0], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_8_sram[0:1]), + .sram_inv(mux_left_track_1_undriven_sram_inv[0:1]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size3 mux_left_track_7 ( + .in({chany_top_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_9_sram[0:1]), + .sram_inv(mux_left_track_7_undriven_sram_inv[0:1]), + .out(chanx_left_out[3])); + + mux_tree_tapbuf_size3_mem mem_top_track_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_14 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_16 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_18 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_44 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_46 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_48 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_50 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram[0:1])); + + mux_tree_tapbuf_size2 mux_top_track_20 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_top_track_20_undriven_sram_inv[0:1]), + .out(chany_top_out[10])); + + mux_tree_tapbuf_size2 mux_top_track_22 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_top_track_22_undriven_sram_inv[0:1]), + .out(chany_top_out[11])); + + mux_tree_tapbuf_size2 mux_top_track_24 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_top_track_24_undriven_sram_inv[0:1]), + .out(chany_top_out[12])); + + mux_tree_tapbuf_size2 mux_top_track_26 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_top_track_26_undriven_sram_inv[0:1]), + .out(chany_top_out[13])); + + mux_tree_tapbuf_size2 mux_top_track_28 ( + .in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_top_track_28_undriven_sram_inv[0:1]), + .out(chany_top_out[14])); + + mux_tree_tapbuf_size2 mux_top_track_30 ( + .in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_top_track_30_undriven_sram_inv[0:1]), + .out(chany_top_out[15])); + + mux_tree_tapbuf_size2 mux_top_track_32 ( + .in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_top_track_32_undriven_sram_inv[0:1]), + .out(chany_top_out[16])); + + mux_tree_tapbuf_size2 mux_top_track_34 ( + .in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_top_track_34_undriven_sram_inv[0:1]), + .out(chany_top_out[17])); + + mux_tree_tapbuf_size2 mux_top_track_36 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_top_track_36_undriven_sram_inv[0:1]), + .out(chany_top_out[18])); + + mux_tree_tapbuf_size2 mux_top_track_38 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_top_track_38_undriven_sram_inv[0:1]), + .out(chany_top_out[19])); + + mux_tree_tapbuf_size2 mux_top_track_40 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_top_track_40_undriven_sram_inv[0:1]), + .out(chany_top_out[20])); + + mux_tree_tapbuf_size2 mux_top_track_42 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size2_11_sram[0:1]), + .sram_inv(mux_top_track_42_undriven_sram_inv[0:1]), + .out(chany_top_out[21])); + + mux_tree_tapbuf_size2 mux_left_track_3 ( + .in({chany_top_in[29], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_12_sram[0:1]), + .sram_inv(mux_left_track_3_undriven_sram_inv[0:1]), + .out(chanx_left_out[1])); + + mux_tree_tapbuf_size2 mux_left_track_5 ( + .in({chany_top_in[28], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_13_sram[0:1]), + .sram_inv(mux_left_track_5_undriven_sram_inv[0:1]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size2 mux_left_track_9 ( + .in({chany_top_in[26], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_14_sram[0:1]), + .sram_inv(mux_left_track_9_undriven_sram_inv[0:1]), + .out(chanx_left_out[4])); + + mux_tree_tapbuf_size2 mux_left_track_11 ( + .in({chany_top_in[25], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_15_sram[0:1]), + .sram_inv(mux_left_track_11_undriven_sram_inv[0:1]), + .out(chanx_left_out[5])); + + mux_tree_tapbuf_size2 mux_left_track_13 ( + .in({chany_top_in[24], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_16_sram[0:1]), + .sram_inv(mux_left_track_13_undriven_sram_inv[0:1]), + .out(chanx_left_out[6])); + + mux_tree_tapbuf_size2 mux_left_track_15 ( + .in({chany_top_in[23], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_17_sram[0:1]), + .sram_inv(mux_left_track_15_undriven_sram_inv[0:1]), + .out(chanx_left_out[7])); + + mux_tree_tapbuf_size2 mux_left_track_17 ( + .in({chany_top_in[22], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_18_sram[0:1]), + .sram_inv(mux_left_track_17_undriven_sram_inv[0:1]), + .out(chanx_left_out[8])); + + mux_tree_tapbuf_size2 mux_left_track_19 ( + .in({chany_top_in[21], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_19_sram[0:1]), + .sram_inv(mux_left_track_19_undriven_sram_inv[0:1]), + .out(chanx_left_out[9])); + + mux_tree_tapbuf_size2 mux_left_track_29 ( + .in({chany_top_in[16], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_20_sram[0:1]), + .sram_inv(mux_left_track_29_undriven_sram_inv[0:1]), + .out(chanx_left_out[14])); + + mux_tree_tapbuf_size2 mux_left_track_31 ( + .in({chany_top_in[15], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram[0:1]), + .sram_inv(mux_left_track_31_undriven_sram_inv[0:1]), + .out(chanx_left_out[15])); + + mux_tree_tapbuf_size2 mux_left_track_33 ( + .in({chany_top_in[14], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_22_sram[0:1]), + .sram_inv(mux_left_track_33_undriven_sram_inv[0:1]), + .out(chanx_left_out[16])); + + mux_tree_tapbuf_size2 mux_left_track_35 ( + .in({chany_top_in[13], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_23_sram[0:1]), + .sram_inv(mux_left_track_35_undriven_sram_inv[0:1]), + .out(chanx_left_out[17])); + + mux_tree_tapbuf_size2 mux_left_track_45 ( + .in({chany_top_in[8], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_24_sram[0:1]), + .sram_inv(mux_left_track_45_undriven_sram_inv[0:1]), + .out(chanx_left_out[22])); + + mux_tree_tapbuf_size2 mux_left_track_47 ( + .in({chany_top_in[7], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_25_sram[0:1]), + .sram_inv(mux_left_track_47_undriven_sram_inv[0:1]), + .out(chanx_left_out[23])); + + mux_tree_tapbuf_size2 mux_left_track_49 ( + .in({chany_top_in[6], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_26_sram[0:1]), + .sram_inv(mux_left_track_49_undriven_sram_inv[0:1]), + .out(chanx_left_out[24])); + + mux_tree_tapbuf_size2 mux_left_track_51 ( + .in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_27_sram[0:1]), + .sram_inv(mux_left_track_51_undriven_sram_inv[0:1]), + .out(chanx_left_out[25])); + + mux_tree_tapbuf_size2_mem mem_top_track_20 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_22 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_24 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_26 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_28 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_30 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_32 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_34 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_36 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_38 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_40 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_42 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_9 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_15 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_17 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_19 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_29 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_31 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_33 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_35 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_45 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_47 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_25_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_49 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_26_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_51 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_27_sram[0:1])); + +endmodule +// ----- END Verilog module for sb_8__0_ ----- + +//----- Default net type ----- +`default_nettype none + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__1_.v new file mode 100644 index 0000000..cd19ad3 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__1_.v @@ -0,0 +1,1109 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[8][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_8__1_ ----- +module sb_8__1_(pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + chany_bottom_in, + bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_left_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + ccff_head, + chany_top_out, + chany_bottom_out, + chanx_left_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:29] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:29] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; +//----- INPUT PORTS ----- +input [0:29] chanx_left_in; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:29] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:29] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:29] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:3] mux_bottom_track_11_undriven_sram_inv; +wire [0:2] mux_bottom_track_13_undriven_sram_inv; +wire [0:3] mux_bottom_track_1_undriven_sram_inv; +wire [0:2] mux_bottom_track_21_undriven_sram_inv; +wire [0:2] mux_bottom_track_29_undriven_sram_inv; +wire [0:2] mux_bottom_track_37_undriven_sram_inv; +wire [0:3] mux_bottom_track_3_undriven_sram_inv; +wire [0:2] mux_bottom_track_45_undriven_sram_inv; +wire [0:2] mux_bottom_track_53_undriven_sram_inv; +wire [0:3] mux_bottom_track_5_undriven_sram_inv; +wire [0:3] mux_bottom_track_7_undriven_sram_inv; +wire [0:2] mux_left_track_11_undriven_sram_inv; +wire [0:2] mux_left_track_13_undriven_sram_inv; +wire [0:2] mux_left_track_15_undriven_sram_inv; +wire [0:2] mux_left_track_17_undriven_sram_inv; +wire [0:2] mux_left_track_19_undriven_sram_inv; +wire [0:2] mux_left_track_1_undriven_sram_inv; +wire [0:2] mux_left_track_21_undriven_sram_inv; +wire [0:2] mux_left_track_23_undriven_sram_inv; +wire [0:1] mux_left_track_25_undriven_sram_inv; +wire [0:1] mux_left_track_27_undriven_sram_inv; +wire [0:1] mux_left_track_29_undriven_sram_inv; +wire [0:1] mux_left_track_31_undriven_sram_inv; +wire [0:1] mux_left_track_33_undriven_sram_inv; +wire [0:1] mux_left_track_35_undriven_sram_inv; +wire [0:1] mux_left_track_37_undriven_sram_inv; +wire [0:2] mux_left_track_3_undriven_sram_inv; +wire [0:1] mux_left_track_41_undriven_sram_inv; +wire [0:1] mux_left_track_45_undriven_sram_inv; +wire [0:1] mux_left_track_47_undriven_sram_inv; +wire [0:1] mux_left_track_49_undriven_sram_inv; +wire [0:1] mux_left_track_51_undriven_sram_inv; +wire [0:1] mux_left_track_53_undriven_sram_inv; +wire [0:1] mux_left_track_55_undriven_sram_inv; +wire [0:1] mux_left_track_57_undriven_sram_inv; +wire [0:2] mux_left_track_5_undriven_sram_inv; +wire [0:2] mux_left_track_7_undriven_sram_inv; +wire [0:2] mux_left_track_9_undriven_sram_inv; +wire [0:3] mux_top_track_0_undriven_sram_inv; +wire [0:3] mux_top_track_10_undriven_sram_inv; +wire [0:2] mux_top_track_12_undriven_sram_inv; +wire [0:2] mux_top_track_20_undriven_sram_inv; +wire [0:2] mux_top_track_28_undriven_sram_inv; +wire [0:3] mux_top_track_2_undriven_sram_inv; +wire [0:2] mux_top_track_36_undriven_sram_inv; +wire [0:2] mux_top_track_44_undriven_sram_inv; +wire [0:3] mux_top_track_4_undriven_sram_inv; +wire [0:2] mux_top_track_52_undriven_sram_inv; +wire [0:3] mux_top_track_6_undriven_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_0_sram; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; +wire [0:3] mux_tree_tapbuf_size11_0_sram; +wire [0:3] mux_tree_tapbuf_size11_1_sram; +wire [0:3] mux_tree_tapbuf_size11_2_sram; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size11_mem_2_ccff_tail; +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:1] mux_tree_tapbuf_size3_7_sram; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_2_sram; +wire [0:2] mux_tree_tapbuf_size4_3_sram; +wire [0:2] mux_tree_tapbuf_size4_4_sram; +wire [0:2] mux_tree_tapbuf_size4_5_sram; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail; +wire [0:2] mux_tree_tapbuf_size5_0_sram; +wire [0:2] mux_tree_tapbuf_size5_1_sram; +wire [0:2] mux_tree_tapbuf_size5_2_sram; +wire [0:2] mux_tree_tapbuf_size5_3_sram; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_4_sram; +wire [0:2] mux_tree_tapbuf_size6_5_sram; +wire [0:2] mux_tree_tapbuf_size6_6_sram; +wire [0:2] mux_tree_tapbuf_size6_7_sram; +wire [0:2] mux_tree_tapbuf_size6_8_sram; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail; +wire [0:2] mux_tree_tapbuf_size7_0_sram; +wire [0:2] mux_tree_tapbuf_size7_1_sram; +wire [0:2] mux_tree_tapbuf_size7_2_sram; +wire [0:2] mux_tree_tapbuf_size7_3_sram; +wire [0:2] mux_tree_tapbuf_size7_4_sram; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; +wire [0:3] mux_tree_tapbuf_size8_0_sram; +wire [0:3] mux_tree_tapbuf_size8_1_sram; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; +wire [0:3] mux_tree_tapbuf_size9_0_sram; +wire [0:3] mux_tree_tapbuf_size9_1_sram; +wire [0:3] mux_tree_tapbuf_size9_2_sram; +wire [0:3] mux_tree_tapbuf_size9_3_sram; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[29] = chany_top_in[1]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[4] = chany_top_in[3]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[7] = chany_top_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[8] = chany_top_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[9] = chany_top_in[8]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[11] = chany_top_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[12] = chany_top_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[13] = chany_top_in[12]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[15] = chany_top_in[14]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[16] = chany_top_in[15]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[17] = chany_top_in[16]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[19] = chany_top_in[18]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[20] = chany_top_in[19]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[21] = chany_top_in[20]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[23] = chany_top_in[22]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[24] = chany_top_in[23]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[25] = chany_top_in[24]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[21] = chany_top_in[25]; +// ----- Local connection due to Wire 26 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[27] = chany_top_in[26]; +// ----- Local connection due to Wire 27 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[28] = chany_top_in[27]; +// ----- Local connection due to Wire 28 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_bottom_out[29] = chany_top_in[28]; +// ----- Local connection due to Wire 45 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[4] = chany_bottom_in[3]; +// ----- Local connection due to Wire 48 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[7] = chany_bottom_in[6]; +// ----- Local connection due to Wire 49 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[8] = chany_bottom_in[7]; +// ----- Local connection due to Wire 50 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[9] = chany_bottom_in[8]; +// ----- Local connection due to Wire 52 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[11] = chany_bottom_in[10]; +// ----- Local connection due to Wire 53 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[12] = chany_bottom_in[11]; +// ----- Local connection due to Wire 54 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[13] = chany_bottom_in[12]; +// ----- Local connection due to Wire 56 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[15] = chany_bottom_in[14]; +// ----- Local connection due to Wire 57 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[16] = chany_bottom_in[15]; +// ----- Local connection due to Wire 58 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[17] = chany_bottom_in[16]; +// ----- Local connection due to Wire 60 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[19] = chany_bottom_in[18]; +// ----- Local connection due to Wire 61 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[20] = chany_bottom_in[19]; +// ----- Local connection due to Wire 62 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[21] = chany_bottom_in[20]; +// ----- Local connection due to Wire 64 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[23] = chany_bottom_in[22]; +// ----- Local connection due to Wire 65 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[24] = chany_bottom_in[23]; +// ----- Local connection due to Wire 66 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[25] = chany_bottom_in[24]; +// ----- Local connection due to Wire 68 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[27] = chany_bottom_in[26]; +// ----- Local connection due to Wire 69 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[28] = chany_bottom_in[27]; +// ----- Local connection due to Wire 70 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 1 ----- + assign chany_top_out[29] = chany_bottom_in[28]; +// ----- Local connection due to Wire 119 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 3 ----- + assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_[0]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size9 mux_top_track_0 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chany_bottom_in[3], chany_bottom_in[19], chanx_left_in[0], chanx_left_in[11], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size9_0_sram[0:3]), + .sram_inv(mux_top_track_0_undriven_sram_inv[0:3]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size9 mux_bottom_track_1 ( + .in({chany_top_in[3], chany_top_in[19], bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[1], chanx_left_in[12], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size9_1_sram[0:3]), + .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:3]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size9 mux_bottom_track_3 ( + .in({chany_top_in[6], chany_top_in[20], bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[2], chanx_left_in[13], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size9_2_sram[0:3]), + .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:3]), + .out(chany_bottom_out[1])); + + mux_tree_tapbuf_size9 mux_bottom_track_5 ( + .in({chany_top_in[7], chany_top_in[22], bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[3], chanx_left_in[14], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size9_3_sram[0:3]), + .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:3]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size9_mem mem_top_track_0 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_0_sram[0:3])); + + mux_tree_tapbuf_size9_mem mem_bottom_track_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_1_sram[0:3])); + + mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_2_sram[0:3])); + + mux_tree_tapbuf_size9_mem mem_bottom_track_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_3_sram[0:3])); + + mux_tree_tapbuf_size8 mux_top_track_2 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[6], chany_bottom_in[20], chanx_left_in[10], chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_top_track_2_undriven_sram_inv[0:3]), + .out(chany_top_out[1])); + + mux_tree_tapbuf_size8 mux_top_track_4 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[7], chany_bottom_in[22], chanx_left_in[9], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_top_track_4_undriven_sram_inv[0:3]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size8_mem mem_top_track_2 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3])); + + mux_tree_tapbuf_size8_mem mem_top_track_4 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3])); + + mux_tree_tapbuf_size10 mux_top_track_6 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[8], chany_bottom_in[23], chanx_left_in[8], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_top_track_6_undriven_sram_inv[0:3]), + .out(chany_top_out[3])); + + mux_tree_tapbuf_size10_mem mem_top_track_6 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3])); + + mux_tree_tapbuf_size11 mux_top_track_10 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[10], chany_bottom_in[24], chanx_left_in[7], chanx_left_in[18], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size11_0_sram[0:3]), + .sram_inv(mux_top_track_10_undriven_sram_inv[0:3]), + .out(chany_top_out[5])); + + mux_tree_tapbuf_size11 mux_bottom_track_7 ( + .in({chany_top_in[8], chany_top_in[23], bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[4], chanx_left_in[15], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size11_1_sram[0:3]), + .sram_inv(mux_bottom_track_7_undriven_sram_inv[0:3]), + .out(chany_bottom_out[3])); + + mux_tree_tapbuf_size11 mux_bottom_track_11 ( + .in({chany_top_in[10], chany_top_in[24], bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[5], chanx_left_in[16], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size11_2_sram[0:3]), + .sram_inv(mux_bottom_track_11_undriven_sram_inv[0:3]), + .out(chany_bottom_out[5])); + + mux_tree_tapbuf_size11_mem mem_top_track_10 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_0_sram[0:3])); + + mux_tree_tapbuf_size11_mem mem_bottom_track_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_1_sram[0:3])); + + mux_tree_tapbuf_size11_mem mem_bottom_track_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_2_sram[0:3])); + + mux_tree_tapbuf_size7 mux_top_track_12 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chany_bottom_in[11], chany_bottom_in[26], chanx_left_in[6], chanx_left_in[17], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_top_track_12_undriven_sram_inv[0:2]), + .out(chany_top_out[6])); + + mux_tree_tapbuf_size7 mux_top_track_20 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chany_bottom_in[12], chany_bottom_in[27], chanx_left_in[5], chanx_left_in[16], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_top_track_20_undriven_sram_inv[0:2]), + .out(chany_top_out[10])); + + mux_tree_tapbuf_size7 mux_top_track_28 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chany_bottom_in[14], chany_bottom_in[28], chanx_left_in[4], chanx_left_in[15], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_top_track_28_undriven_sram_inv[0:2]), + .out(chany_top_out[14])); + + mux_tree_tapbuf_size7 mux_bottom_track_13 ( + .in({chany_top_in[11], chany_top_in[26], bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[6], chanx_left_in[17], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_bottom_track_13_undriven_sram_inv[0:2]), + .out(chany_bottom_out[6])); + + mux_tree_tapbuf_size7 mux_bottom_track_21 ( + .in({chany_top_in[12], chany_top_in[27], bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[7], chanx_left_in[18], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size7_4_sram[0:2]), + .sram_inv(mux_bottom_track_21_undriven_sram_inv[0:2]), + .out(chany_bottom_out[10])); + + mux_tree_tapbuf_size7_mem mem_top_track_12 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_top_track_20 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_top_track_28 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_bottom_track_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2])); + + mux_tree_tapbuf_size7_mem mem_bottom_track_21 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram[0:2])); + + mux_tree_tapbuf_size6 mux_top_track_36 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chany_bottom_in[15], chanx_left_in[3], chanx_left_in[14], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_top_track_36_undriven_sram_inv[0:2]), + .out(chany_top_out[18])); + + mux_tree_tapbuf_size6 mux_top_track_44 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[16], chanx_left_in[2], chanx_left_in[13], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_top_track_44_undriven_sram_inv[0:2]), + .out(chany_top_out[22])); + + mux_tree_tapbuf_size6 mux_top_track_52 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[18], chanx_left_in[1], chanx_left_in[12], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_top_track_52_undriven_sram_inv[0:2]), + .out(chany_top_out[26])); + + mux_tree_tapbuf_size6 mux_bottom_track_29 ( + .in({chany_top_in[14], chany_top_in[28], bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[8], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_bottom_track_29_undriven_sram_inv[0:2]), + .out(chany_bottom_out[14])); + + mux_tree_tapbuf_size6 mux_bottom_track_53 ( + .in({chany_top_in[18], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[0], chanx_left_in[11], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_bottom_track_53_undriven_sram_inv[0:2]), + .out(chany_bottom_out[26])); + + mux_tree_tapbuf_size6 mux_left_track_1 ( + .in({chany_top_in[0], chany_top_in[3], chany_bottom_in[3], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_left_track_1_undriven_sram_inv[0:2]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size6 mux_left_track_3 ( + .in({chany_top_in[6], chany_bottom_in[0], chany_bottom_in[6], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_left_track_3_undriven_sram_inv[0:2]), + .out(chanx_left_out[1])); + + mux_tree_tapbuf_size6 mux_left_track_7 ( + .in({chany_top_in[8], chany_bottom_in[2], chany_bottom_in[8], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size6_7_sram[0:2]), + .sram_inv(mux_left_track_7_undriven_sram_inv[0:2]), + .out(chanx_left_out[3])); + + mux_tree_tapbuf_size6 mux_left_track_9 ( + .in({chany_top_in[10], chany_bottom_in[4], chany_bottom_in[10], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size6_8_sram[0:2]), + .sram_inv(mux_left_track_9_undriven_sram_inv[0:2]), + .out(chanx_left_out[4])); + + mux_tree_tapbuf_size6_mem mem_top_track_36 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_track_44 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_track_52 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_29 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_53 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_9 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram[0:2])); + + mux_tree_tapbuf_size5 mux_bottom_track_37 ( + .in({chany_top_in[15], bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[9], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_bottom_track_37_undriven_sram_inv[0:2]), + .out(chany_bottom_out[18])); + + mux_tree_tapbuf_size5 mux_bottom_track_45 ( + .in({chany_top_in[16], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[10], chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_bottom_track_45_undriven_sram_inv[0:2]), + .out(chany_bottom_out[22])); + + mux_tree_tapbuf_size5 mux_left_track_5 ( + .in({chany_top_in[7], chany_bottom_in[1], chany_bottom_in[7], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_2_sram[0:2]), + .sram_inv(mux_left_track_5_undriven_sram_inv[0:2]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size5 mux_left_track_11 ( + .in({chany_top_in[11], chany_bottom_in[5], chany_bottom_in[11], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_3_sram[0:2]), + .sram_inv(mux_left_track_11_undriven_sram_inv[0:2]), + .out(chanx_left_out[5])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_37 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_45 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2])); + + mux_tree_tapbuf_size4 mux_left_track_13 ( + .in({chany_top_in[12], chany_bottom_in[9], chany_bottom_in[12], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_left_track_13_undriven_sram_inv[0:2]), + .out(chanx_left_out[6])); + + mux_tree_tapbuf_size4 mux_left_track_15 ( + .in({chany_top_in[14], chany_bottom_in[13:14], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_left_track_15_undriven_sram_inv[0:2]), + .out(chanx_left_out[7])); + + mux_tree_tapbuf_size4 mux_left_track_17 ( + .in({chany_top_in[15], chany_bottom_in[15], chany_bottom_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_left_track_17_undriven_sram_inv[0:2]), + .out(chanx_left_out[8])); + + mux_tree_tapbuf_size4 mux_left_track_19 ( + .in({chany_top_in[16], chany_bottom_in[16], chany_bottom_in[21], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_left_track_19_undriven_sram_inv[0:2]), + .out(chanx_left_out[9])); + + mux_tree_tapbuf_size4 mux_left_track_21 ( + .in({chany_top_in[18], chany_bottom_in[18], chany_bottom_in[25], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size4_4_sram[0:2]), + .sram_inv(mux_left_track_21_undriven_sram_inv[0:2]), + .out(chanx_left_out[10])); + + mux_tree_tapbuf_size4 mux_left_track_23 ( + .in({chany_top_in[19], chany_bottom_in[19], chany_bottom_in[29], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size4_5_sram[0:2]), + .sram_inv(mux_left_track_23_undriven_sram_inv[0:2]), + .out(chanx_left_out[11])); + + mux_tree_tapbuf_size4_mem mem_left_track_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_15 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_17 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_19 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_21 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_23 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram[0:2])); + + mux_tree_tapbuf_size3 mux_left_track_25 ( + .in({chany_top_in[20], chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_left_track_25_undriven_sram_inv[0:1]), + .out(chanx_left_out[12])); + + mux_tree_tapbuf_size3 mux_left_track_27 ( + .in({chany_top_in[22], chany_bottom_in[22], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_left_track_27_undriven_sram_inv[0:1]), + .out(chanx_left_out[13])); + + mux_tree_tapbuf_size3 mux_left_track_29 ( + .in({chany_top_in[23], chany_bottom_in[23], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_left_track_29_undriven_sram_inv[0:1]), + .out(chanx_left_out[14])); + + mux_tree_tapbuf_size3 mux_left_track_31 ( + .in({chany_top_in[24], chany_bottom_in[24], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_left_track_31_undriven_sram_inv[0:1]), + .out(chanx_left_out[15])); + + mux_tree_tapbuf_size3 mux_left_track_33 ( + .in({chany_top_in[26], chany_bottom_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_left_track_33_undriven_sram_inv[0:1]), + .out(chanx_left_out[16])); + + mux_tree_tapbuf_size3 mux_left_track_35 ( + .in({chany_top_in[27], chany_bottom_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_left_track_35_undriven_sram_inv[0:1]), + .out(chanx_left_out[17])); + + mux_tree_tapbuf_size3 mux_left_track_37 ( + .in({chany_top_in[28], chany_bottom_in[28], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_left_track_37_undriven_sram_inv[0:1]), + .out(chanx_left_out[18])); + + mux_tree_tapbuf_size3 mux_left_track_51 ( + .in({chany_top_in[9], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_7_sram[0:1]), + .sram_inv(mux_left_track_51_undriven_sram_inv[0:1]), + .out(chanx_left_out[25])); + + mux_tree_tapbuf_size3_mem mem_left_track_25 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_27 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_29 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_31 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_33 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_35 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_37 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_51 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram[0:1])); + + mux_tree_tapbuf_size2 mux_left_track_41 ( + .in({chany_top_in[29], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_left_track_41_undriven_sram_inv[0:1]), + .out(chanx_left_out[20])); + + mux_tree_tapbuf_size2 mux_left_track_45 ( + .in({chany_top_in[21], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_left_track_45_undriven_sram_inv[0:1]), + .out(chanx_left_out[22])); + + mux_tree_tapbuf_size2 mux_left_track_47 ( + .in({chany_top_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_left_track_47_undriven_sram_inv[0:1]), + .out(chanx_left_out[23])); + + mux_tree_tapbuf_size2 mux_left_track_49 ( + .in({chany_top_in[13], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_left_track_49_undriven_sram_inv[0:1]), + .out(chanx_left_out[24])); + + mux_tree_tapbuf_size2 mux_left_track_53 ( + .in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_left_track_53_undriven_sram_inv[0:1]), + .out(chanx_left_out[26])); + + mux_tree_tapbuf_size2 mux_left_track_55 ( + .in({chany_top_in[4], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_left_track_55_undriven_sram_inv[0:1]), + .out(chanx_left_out[27])); + + mux_tree_tapbuf_size2 mux_left_track_57 ( + .in({chany_top_in[2], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_left_track_57_undriven_sram_inv[0:1]), + .out(chanx_left_out[28])); + + mux_tree_tapbuf_size2_mem mem_left_track_41 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_45 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_47 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_49 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_53 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_55 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_57 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1])); + +endmodule +// ----- END Verilog module for sb_8__1_ ----- + +//----- Default net type ----- +`default_nettype none + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__8_.v new file mode 100644 index 0000000..a29805d --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__8_.v @@ -0,0 +1,1043 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[8][8] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_8__8_ ----- +module sb_8__8_(pReset, + prog_clk, + chany_bottom_in, + bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_left_in, + left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + ccff_head, + chany_bottom_out, + chanx_left_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:29] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; +//----- INPUT PORTS ----- +input [0:29] chanx_left_in; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:29] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:29] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:2] mux_bottom_track_11_undriven_sram_inv; +wire [0:1] mux_bottom_track_13_undriven_sram_inv; +wire [0:1] mux_bottom_track_15_undriven_sram_inv; +wire [0:1] mux_bottom_track_17_undriven_sram_inv; +wire [0:1] mux_bottom_track_19_undriven_sram_inv; +wire [0:2] mux_bottom_track_1_undriven_sram_inv; +wire [0:1] mux_bottom_track_21_undriven_sram_inv; +wire [0:1] mux_bottom_track_23_undriven_sram_inv; +wire [0:1] mux_bottom_track_25_undriven_sram_inv; +wire [0:1] mux_bottom_track_27_undriven_sram_inv; +wire [0:1] mux_bottom_track_29_undriven_sram_inv; +wire [0:1] mux_bottom_track_31_undriven_sram_inv; +wire [0:1] mux_bottom_track_33_undriven_sram_inv; +wire [0:1] mux_bottom_track_35_undriven_sram_inv; +wire [0:2] mux_bottom_track_3_undriven_sram_inv; +wire [0:1] mux_bottom_track_45_undriven_sram_inv; +wire [0:1] mux_bottom_track_47_undriven_sram_inv; +wire [0:1] mux_bottom_track_49_undriven_sram_inv; +wire [0:1] mux_bottom_track_51_undriven_sram_inv; +wire [0:1] mux_bottom_track_53_undriven_sram_inv; +wire [0:1] mux_bottom_track_55_undriven_sram_inv; +wire [0:1] mux_bottom_track_57_undriven_sram_inv; +wire [0:1] mux_bottom_track_59_undriven_sram_inv; +wire [0:2] mux_bottom_track_5_undriven_sram_inv; +wire [0:2] mux_bottom_track_7_undriven_sram_inv; +wire [0:2] mux_bottom_track_9_undriven_sram_inv; +wire [0:2] mux_left_track_11_undriven_sram_inv; +wire [0:1] mux_left_track_13_undriven_sram_inv; +wire [0:1] mux_left_track_15_undriven_sram_inv; +wire [0:1] mux_left_track_17_undriven_sram_inv; +wire [0:1] mux_left_track_19_undriven_sram_inv; +wire [0:2] mux_left_track_1_undriven_sram_inv; +wire [0:1] mux_left_track_21_undriven_sram_inv; +wire [0:1] mux_left_track_23_undriven_sram_inv; +wire [0:1] mux_left_track_25_undriven_sram_inv; +wire [0:1] mux_left_track_27_undriven_sram_inv; +wire [0:1] mux_left_track_29_undriven_sram_inv; +wire [0:1] mux_left_track_31_undriven_sram_inv; +wire [0:1] mux_left_track_33_undriven_sram_inv; +wire [0:1] mux_left_track_35_undriven_sram_inv; +wire [0:1] mux_left_track_37_undriven_sram_inv; +wire [0:1] mux_left_track_39_undriven_sram_inv; +wire [0:2] mux_left_track_3_undriven_sram_inv; +wire [0:1] mux_left_track_41_undriven_sram_inv; +wire [0:1] mux_left_track_43_undriven_sram_inv; +wire [0:1] mux_left_track_45_undriven_sram_inv; +wire [0:1] mux_left_track_47_undriven_sram_inv; +wire [0:1] mux_left_track_49_undriven_sram_inv; +wire [0:1] mux_left_track_51_undriven_sram_inv; +wire [0:1] mux_left_track_53_undriven_sram_inv; +wire [0:1] mux_left_track_55_undriven_sram_inv; +wire [0:1] mux_left_track_57_undriven_sram_inv; +wire [0:1] mux_left_track_59_undriven_sram_inv; +wire [0:2] mux_left_track_5_undriven_sram_inv; +wire [0:2] mux_left_track_7_undriven_sram_inv; +wire [0:2] mux_left_track_9_undriven_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_10_sram; +wire [0:1] mux_tree_tapbuf_size2_11_sram; +wire [0:1] mux_tree_tapbuf_size2_12_sram; +wire [0:1] mux_tree_tapbuf_size2_13_sram; +wire [0:1] mux_tree_tapbuf_size2_14_sram; +wire [0:1] mux_tree_tapbuf_size2_15_sram; +wire [0:1] mux_tree_tapbuf_size2_16_sram; +wire [0:1] mux_tree_tapbuf_size2_17_sram; +wire [0:1] mux_tree_tapbuf_size2_18_sram; +wire [0:1] mux_tree_tapbuf_size2_19_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_20_sram; +wire [0:1] mux_tree_tapbuf_size2_21_sram; +wire [0:1] mux_tree_tapbuf_size2_22_sram; +wire [0:1] mux_tree_tapbuf_size2_23_sram; +wire [0:1] mux_tree_tapbuf_size2_24_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_7_sram; +wire [0:1] mux_tree_tapbuf_size2_8_sram; +wire [0:1] mux_tree_tapbuf_size2_9_sram; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_10_sram; +wire [0:1] mux_tree_tapbuf_size3_11_sram; +wire [0:1] mux_tree_tapbuf_size3_12_sram; +wire [0:1] mux_tree_tapbuf_size3_13_sram; +wire [0:1] mux_tree_tapbuf_size3_14_sram; +wire [0:1] mux_tree_tapbuf_size3_15_sram; +wire [0:1] mux_tree_tapbuf_size3_16_sram; +wire [0:1] mux_tree_tapbuf_size3_17_sram; +wire [0:1] mux_tree_tapbuf_size3_18_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:1] mux_tree_tapbuf_size3_7_sram; +wire [0:1] mux_tree_tapbuf_size3_8_sram; +wire [0:1] mux_tree_tapbuf_size3_9_sram; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_13_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_14_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_15_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_16_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_17_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail; +wire [0:2] mux_tree_tapbuf_size5_0_sram; +wire [0:2] mux_tree_tapbuf_size5_10_sram; +wire [0:2] mux_tree_tapbuf_size5_11_sram; +wire [0:2] mux_tree_tapbuf_size5_1_sram; +wire [0:2] mux_tree_tapbuf_size5_2_sram; +wire [0:2] mux_tree_tapbuf_size5_3_sram; +wire [0:2] mux_tree_tapbuf_size5_4_sram; +wire [0:2] mux_tree_tapbuf_size5_5_sram; +wire [0:2] mux_tree_tapbuf_size5_6_sram; +wire [0:2] mux_tree_tapbuf_size5_7_sram; +wire [0:2] mux_tree_tapbuf_size5_8_sram; +wire [0:2] mux_tree_tapbuf_size5_9_sram; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_9_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 61 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[18] = chanx_left_in[19]; +// ----- Local connection due to Wire 62 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[19] = chanx_left_in[20]; +// ----- Local connection due to Wire 63 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[20] = chanx_left_in[21]; +// ----- Local connection due to Wire 64 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[21] = chanx_left_in[22]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size5 mux_bottom_track_1 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[1]}), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size5 mux_bottom_track_3 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[2]}), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]), + .out(chany_bottom_out[1])); + + mux_tree_tapbuf_size5 mux_bottom_track_5 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size5_2_sram[0:2]), + .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size5 mux_bottom_track_7 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[4]}), + .sram(mux_tree_tapbuf_size5_3_sram[0:2]), + .sram_inv(mux_bottom_track_7_undriven_sram_inv[0:2]), + .out(chany_bottom_out[3])); + + mux_tree_tapbuf_size5 mux_bottom_track_9 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[5]}), + .sram(mux_tree_tapbuf_size5_4_sram[0:2]), + .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:2]), + .out(chany_bottom_out[4])); + + mux_tree_tapbuf_size5 mux_bottom_track_11 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size5_5_sram[0:2]), + .sram_inv(mux_bottom_track_11_undriven_sram_inv[0:2]), + .out(chany_bottom_out[5])); + + mux_tree_tapbuf_size5 mux_left_track_1 ( + .in({chany_bottom_in[29], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_6_sram[0:2]), + .sram_inv(mux_left_track_1_undriven_sram_inv[0:2]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size5 mux_left_track_3 ( + .in({chany_bottom_in[0], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size5_7_sram[0:2]), + .sram_inv(mux_left_track_3_undriven_sram_inv[0:2]), + .out(chanx_left_out[1])); + + mux_tree_tapbuf_size5 mux_left_track_5 ( + .in({chany_bottom_in[1], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size5_8_sram[0:2]), + .sram_inv(mux_left_track_5_undriven_sram_inv[0:2]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size5 mux_left_track_7 ( + .in({chany_bottom_in[2], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_9_sram[0:2]), + .sram_inv(mux_left_track_7_undriven_sram_inv[0:2]), + .out(chanx_left_out[3])); + + mux_tree_tapbuf_size5 mux_left_track_9 ( + .in({chany_bottom_in[3], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size5_10_sram[0:2]), + .sram_inv(mux_left_track_9_undriven_sram_inv[0:2]), + .out(chanx_left_out[4])); + + mux_tree_tapbuf_size5 mux_left_track_11 ( + .in({chany_bottom_in[4], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size5_11_sram[0:2]), + .sram_inv(mux_left_track_11_undriven_sram_inv[0:2]), + .out(chanx_left_out[5])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_9 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_1 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_6_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_3 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_7_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_5 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_8_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_7 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_9_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_9 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_10_sram[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_11 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_11_sram[0:2])); + + mux_tree_tapbuf_size2 mux_bottom_track_13 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]), + .out(chany_bottom_out[6])); + + mux_tree_tapbuf_size2 mux_bottom_track_15 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]), + .out(chany_bottom_out[7])); + + mux_tree_tapbuf_size2 mux_bottom_track_17 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]), + .out(chany_bottom_out[8])); + + mux_tree_tapbuf_size2 mux_bottom_track_19 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]), + .out(chany_bottom_out[9])); + + mux_tree_tapbuf_size2 mux_bottom_track_21 ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]), + .out(chany_bottom_out[10])); + + mux_tree_tapbuf_size2 mux_bottom_track_23 ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_bottom_track_23_undriven_sram_inv[0:1]), + .out(chany_bottom_out[11])); + + mux_tree_tapbuf_size2 mux_bottom_track_25 ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_bottom_track_25_undriven_sram_inv[0:1]), + .out(chany_bottom_out[12])); + + mux_tree_tapbuf_size2 mux_bottom_track_27 ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_bottom_track_27_undriven_sram_inv[0:1]), + .out(chany_bottom_out[13])); + + mux_tree_tapbuf_size2 mux_bottom_track_53 ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_bottom_track_53_undriven_sram_inv[0:1]), + .out(chany_bottom_out[26])); + + mux_tree_tapbuf_size2 mux_bottom_track_55 ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_bottom_track_55_undriven_sram_inv[0:1]), + .out(chany_bottom_out[27])); + + mux_tree_tapbuf_size2 mux_bottom_track_57 ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_bottom_track_57_undriven_sram_inv[0:1]), + .out(chany_bottom_out[28])); + + mux_tree_tapbuf_size2 mux_bottom_track_59 ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[0]}), + .sram(mux_tree_tapbuf_size2_11_sram[0:1]), + .sram_inv(mux_bottom_track_59_undriven_sram_inv[0:1]), + .out(chany_bottom_out[29])); + + mux_tree_tapbuf_size2 mux_left_track_19 ( + .in({chany_bottom_in[8], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_12_sram[0:1]), + .sram_inv(mux_left_track_19_undriven_sram_inv[0:1]), + .out(chanx_left_out[9])); + + mux_tree_tapbuf_size2 mux_left_track_21 ( + .in({chany_bottom_in[9], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_13_sram[0:1]), + .sram_inv(mux_left_track_21_undriven_sram_inv[0:1]), + .out(chanx_left_out[10])); + + mux_tree_tapbuf_size2 mux_left_track_23 ( + .in({chany_bottom_in[10], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_14_sram[0:1]), + .sram_inv(mux_left_track_23_undriven_sram_inv[0:1]), + .out(chanx_left_out[11])); + + mux_tree_tapbuf_size2 mux_left_track_25 ( + .in({chany_bottom_in[11], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_15_sram[0:1]), + .sram_inv(mux_left_track_25_undriven_sram_inv[0:1]), + .out(chanx_left_out[12])); + + mux_tree_tapbuf_size2 mux_left_track_27 ( + .in({chany_bottom_in[12], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size2_16_sram[0:1]), + .sram_inv(mux_left_track_27_undriven_sram_inv[0:1]), + .out(chanx_left_out[13])); + + mux_tree_tapbuf_size2 mux_left_track_37 ( + .in({chany_bottom_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_17_sram[0:1]), + .sram_inv(mux_left_track_37_undriven_sram_inv[0:1]), + .out(chanx_left_out[18])); + + mux_tree_tapbuf_size2 mux_left_track_39 ( + .in({chany_bottom_in[18], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_18_sram[0:1]), + .sram_inv(mux_left_track_39_undriven_sram_inv[0:1]), + .out(chanx_left_out[19])); + + mux_tree_tapbuf_size2 mux_left_track_41 ( + .in({chany_bottom_in[19], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_19_sram[0:1]), + .sram_inv(mux_left_track_41_undriven_sram_inv[0:1]), + .out(chanx_left_out[20])); + + mux_tree_tapbuf_size2 mux_left_track_43 ( + .in({chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size2_20_sram[0:1]), + .sram_inv(mux_left_track_43_undriven_sram_inv[0:1]), + .out(chanx_left_out[21])); + + mux_tree_tapbuf_size2 mux_left_track_51 ( + .in({chany_bottom_in[24], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram[0:1]), + .sram_inv(mux_left_track_51_undriven_sram_inv[0:1]), + .out(chanx_left_out[25])); + + mux_tree_tapbuf_size2 mux_left_track_53 ( + .in({chany_bottom_in[25], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_22_sram[0:1]), + .sram_inv(mux_left_track_53_undriven_sram_inv[0:1]), + .out(chanx_left_out[26])); + + mux_tree_tapbuf_size2 mux_left_track_55 ( + .in({chany_bottom_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_23_sram[0:1]), + .sram_inv(mux_left_track_55_undriven_sram_inv[0:1]), + .out(chanx_left_out[27])); + + mux_tree_tapbuf_size2 mux_left_track_57 ( + .in({chany_bottom_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_24_sram[0:1]), + .sram_inv(mux_left_track_57_undriven_sram_inv[0:1]), + .out(chanx_left_out[28])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_15 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_17 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_19 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_21 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_23 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_25 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_53 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_55 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_57 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_59 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_19 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_21 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_23 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_25 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_27 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_37 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_39 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_41 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_43 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_51 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_17_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_53 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_55 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_57 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram[0:1])); + + mux_tree_tapbuf_size3 mux_bottom_track_29 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_bottom_track_29_undriven_sram_inv[0:1]), + .out(chany_bottom_out[14])); + + mux_tree_tapbuf_size3 mux_bottom_track_31 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_bottom_track_31_undriven_sram_inv[0:1]), + .out(chany_bottom_out[15])); + + mux_tree_tapbuf_size3 mux_bottom_track_33 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_bottom_track_33_undriven_sram_inv[0:1]), + .out(chany_bottom_out[16])); + + mux_tree_tapbuf_size3 mux_bottom_track_35 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_bottom_track_35_undriven_sram_inv[0:1]), + .out(chany_bottom_out[17])); + + mux_tree_tapbuf_size3 mux_bottom_track_45 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_bottom_track_45_undriven_sram_inv[0:1]), + .out(chany_bottom_out[22])); + + mux_tree_tapbuf_size3 mux_bottom_track_47 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_bottom_track_47_undriven_sram_inv[0:1]), + .out(chany_bottom_out[23])); + + mux_tree_tapbuf_size3 mux_bottom_track_49 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_bottom_track_49_undriven_sram_inv[0:1]), + .out(chany_bottom_out[24])); + + mux_tree_tapbuf_size3 mux_bottom_track_51 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size3_7_sram[0:1]), + .sram_inv(mux_bottom_track_51_undriven_sram_inv[0:1]), + .out(chany_bottom_out[25])); + + mux_tree_tapbuf_size3 mux_left_track_13 ( + .in({chany_bottom_in[5], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_8_sram[0:1]), + .sram_inv(mux_left_track_13_undriven_sram_inv[0:1]), + .out(chanx_left_out[6])); + + mux_tree_tapbuf_size3 mux_left_track_15 ( + .in({chany_bottom_in[6], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size3_9_sram[0:1]), + .sram_inv(mux_left_track_15_undriven_sram_inv[0:1]), + .out(chanx_left_out[7])); + + mux_tree_tapbuf_size3 mux_left_track_17 ( + .in({chany_bottom_in[7], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_10_sram[0:1]), + .sram_inv(mux_left_track_17_undriven_sram_inv[0:1]), + .out(chanx_left_out[8])); + + mux_tree_tapbuf_size3 mux_left_track_29 ( + .in({chany_bottom_in[13], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_11_sram[0:1]), + .sram_inv(mux_left_track_29_undriven_sram_inv[0:1]), + .out(chanx_left_out[14])); + + mux_tree_tapbuf_size3 mux_left_track_31 ( + .in({chany_bottom_in[14], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size3_12_sram[0:1]), + .sram_inv(mux_left_track_31_undriven_sram_inv[0:1]), + .out(chanx_left_out[15])); + + mux_tree_tapbuf_size3 mux_left_track_33 ( + .in({chany_bottom_in[15], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_13_sram[0:1]), + .sram_inv(mux_left_track_33_undriven_sram_inv[0:1]), + .out(chanx_left_out[16])); + + mux_tree_tapbuf_size3 mux_left_track_35 ( + .in({chany_bottom_in[16], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_14_sram[0:1]), + .sram_inv(mux_left_track_35_undriven_sram_inv[0:1]), + .out(chanx_left_out[17])); + + mux_tree_tapbuf_size3 mux_left_track_45 ( + .in({chany_bottom_in[21], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_15_sram[0:1]), + .sram_inv(mux_left_track_45_undriven_sram_inv[0:1]), + .out(chanx_left_out[22])); + + mux_tree_tapbuf_size3 mux_left_track_47 ( + .in({chany_bottom_in[22], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size3_16_sram[0:1]), + .sram_inv(mux_left_track_47_undriven_sram_inv[0:1]), + .out(chanx_left_out[23])); + + mux_tree_tapbuf_size3 mux_left_track_49 ( + .in({chany_bottom_in[23], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_17_sram[0:1]), + .sram_inv(mux_left_track_49_undriven_sram_inv[0:1]), + .out(chanx_left_out[24])); + + mux_tree_tapbuf_size3 mux_left_track_59 ( + .in({chany_bottom_in[28], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_18_sram[0:1]), + .sram_inv(mux_left_track_59_undriven_sram_inv[0:1]), + .out(chanx_left_out[29])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_29 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_31 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_33 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_35 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_45 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_47 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_49 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_51 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_13 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_15 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_17 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_29 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_31 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_12_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_33 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_13_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_35 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_14_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_45 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_15_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_47 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_15_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_16_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_49 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_16_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_17_sram[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_59 ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size3_18_sram[0:1])); + +endmodule +// ----- END Verilog module for sb_8__8_ ----- + +//----- Default net type ----- +`default_nettype none + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sc_verilog/digital_io_hd.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sc_verilog/digital_io_hd.v new file mode 100644 index 0000000..46ac151 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sc_verilog/digital_io_hd.v @@ -0,0 +1,55 @@ +`timescale 1ns/1ps + +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +module EMBEDDED_IO_HD ( + input SOC_IN, // + output SOC_OUT, // + output SOC_DIR, // + output FPGA_IN, // + input FPGA_OUT, // + input FPGA_DIR, // + input IO_ISOL_N // +); + + wire SOC_DIR_N; + + // + sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE (.B_N(IO_ISOL_N), + .A(FPGA_DIR), + .X(SOC_DIR) + ); + + // + sky130_fd_sc_hd__inv_1 INV_SOC_DIR (.A(SOC_DIR), .Y(SOC_DIR_N)); + sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE (.TE_B(SOC_DIR_N), + .A(SOC_IN), + .Z(FPGA_IN) + ); + + // + sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE (.TE_B(SOC_DIR), + .A(FPGA_OUT), + .Z(SOC_OUT) + ); + +endmodule \ No newline at end of file diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sc_verilog/fpga_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sc_verilog/fpga_top.v new file mode 100644 index 0000000..6227391 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sc_verilog/fpga_top.v @@ -0,0 +1,483 @@ +/* + *------------------------------------------------------------- + * + * A wrapper for the FPGA IP to fit the I/O interface of Caravel SoC + * + * The wrapper is a technology mapped netlist where the mode-switch + * multiplexers are mapped to the Skywater 130nm + * High-Density (HD) standard cells + * + *------------------------------------------------------------- + */ + +module fpga_top ( + // + // + inout vdda1, // + inout vdda2, // + inout vssa1, // + inout vssa2, // + inout vccd1, // + inout vccd2, // + inout vssd1, // + inout vssd2, // + + // + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + output wbs_ack_o, + output [31:0] wbs_dat_o, + + // + input [127:0] la_data_in, + output [127:0] la_data_out, + input [127:0] la_oen, + + // + input [37:0] io_in, + output [37:0] io_out, + output [37:0] io_oeb +); + + // + // + // + // + // + // + // + + // + wire prog_clk; + wire Test_en; + wire IO_ISOL_N; + wire clk; + wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire ccff_head; + wire ccff_tail; + wire sc_head; + wire sc_tail; + wire pReset; + wire Reset; + + // + wire wb_la_switch; + wire wb_la_switch_b; + + // + // + // + sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV (.A(wb_la_switch), .Y(wb_la_switch_b)); + + // + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24]; + assign io_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]; + assign io_oeb[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = io_in[23]; + assign io_out[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]; + assign io_oeb[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = io_in[22]; + assign io_out[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]; + assign io_oeb[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = io_in[21]; + assign io_out[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]; + assign io_oeb[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = io_in[20]; + assign io_out[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4]; + assign io_oeb[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = io_in[19]; + assign io_out[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5]; + assign io_oeb[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = io_in[18]; + assign io_out[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6]; + assign io_oeb[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = io_in[17]; + assign io_out[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7]; + assign io_oeb[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = io_in[16]; + assign io_out[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8]; + assign io_oeb[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = io_in[15]; + assign io_out[15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9]; + assign io_oeb[15] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = io_in[14]; + assign io_out[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10]; + assign io_oeb[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = io_in[13]; + assign io_out[13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11]; + assign io_oeb[13] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11]; + assign ccff_head = io_in[12]; + assign io_out[12] = 1'b0; + assign io_oeb[12] = 1'b1; + assign io_out[11] = sc_tail; + assign io_oeb[11] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = io_in[10]; + assign io_out[10] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12]; + assign io_oeb[10] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = io_in[9]; + assign io_out[9] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13]; + assign io_oeb[9] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = io_in[8]; + assign io_out[8] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14]; + assign io_oeb[8] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = io_in[7]; + assign io_out[7] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15]; + assign io_oeb[7] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = io_in[6]; + assign io_out[6] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16]; + assign io_oeb[6] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = io_in[5]; + assign io_out[5] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17]; + assign io_oeb[5] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = io_in[4]; + assign io_out[4] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18]; + assign io_oeb[4] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18]; + assign pReset = io_in[3]; + assign io_out[3] = 1'b0; + assign io_oeb[3] = 1'b1; + assign Reset = io_in[2]; + assign io_out[2] = 1'b0; + assign io_oeb[2] = 1'b1; + assign IO_ISOL_N = io_in[1]; + assign io_out[1] = 1'b0; + assign io_oeb[1] = 1'b1; + assign Test_en = io_in[0]; + assign io_out[0] = 1'b0; + assign io_oeb[0] = 1'b1; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = la_data_in[127]; + assign la_data_out[127] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = la_data_in[126]; + assign la_data_out[126] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[125]; + assign la_data_out[125] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[124]; + assign la_data_out[124] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[123]; + assign la_data_out[123] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[122]; + assign la_data_out[122] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[121]; + assign la_data_out[121] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[120]; + assign la_data_out[120] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[119]; + assign la_data_out[119] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[118]; + assign la_data_out[118] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[117]; + assign la_data_out[117] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[116]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(wbs_dat_o[0])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(la_data_out[116])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[115]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(wbs_dat_o[1])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(la_data_out[115])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[114]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(wbs_dat_o[2])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(la_data_out[114])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[113]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(wbs_dat_o[3])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(la_data_out[113])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[112]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(wbs_dat_o[4])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(la_data_out[112])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[111]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(wbs_dat_o[5])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(la_data_out[111])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[110]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(wbs_dat_o[6])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(la_data_out[110])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[109]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(wbs_dat_o[7])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(la_data_out[109])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[108]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(wbs_dat_o[8])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(la_data_out[108])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[107]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(wbs_dat_o[9])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(la_data_out[107])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[106]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(wbs_dat_o[10])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(la_data_out[106])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[105]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(wbs_dat_o[11])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(la_data_out[105])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[104]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(wbs_dat_o[12])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(la_data_out[104])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[103]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(wbs_dat_o[13])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(la_data_out[103])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[102]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(wbs_dat_o[14])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(la_data_out[102])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[101]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(wbs_dat_o[15])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(la_data_out[101])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[100]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(wbs_dat_o[16])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(la_data_out[100])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[99]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(wbs_dat_o[17])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(la_data_out[99])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[98]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(wbs_dat_o[18])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(la_data_out[98])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[97]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(wbs_dat_o[19])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(la_data_out[97])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[96]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(wbs_dat_o[20])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(la_data_out[96])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[95]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(wbs_dat_o[21])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(la_data_out[95])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[94]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(wbs_dat_o[22])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(la_data_out[94])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[93]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(wbs_dat_o[23])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(la_data_out[93])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[92]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(wbs_dat_o[24])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(la_data_out[92])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[91]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(wbs_dat_o[25])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(la_data_out[91])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[90]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(wbs_dat_o[26])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(la_data_out[90])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[89]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(wbs_dat_o[27])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(la_data_out[89])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[88]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(wbs_dat_o[28])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(la_data_out[88])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[87]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(wbs_dat_o[29])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(la_data_out[87])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[86]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(wbs_dat_o[30])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(la_data_out[86])); + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[85]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(wbs_dat_o[31])); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(la_data_out[85])); + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX (.S(wb_la_switch), .A1(wbs_dat_i[0]), .A0(la_data_in[84]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62])); + assign la_data_out[84] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX (.S(wb_la_switch), .A1(wbs_dat_i[1]), .A0(la_data_in[83]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63])); + assign la_data_out[83] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX (.S(wb_la_switch), .A1(wbs_dat_i[2]), .A0(la_data_in[82]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64])); + assign la_data_out[82] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX (.S(wb_la_switch), .A1(wbs_dat_i[3]), .A0(la_data_in[81]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65])); + assign la_data_out[81] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX (.S(wb_la_switch), .A1(wbs_dat_i[4]), .A0(la_data_in[80]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66])); + assign la_data_out[80] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX (.S(wb_la_switch), .A1(wbs_dat_i[5]), .A0(la_data_in[79]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67])); + assign la_data_out[79] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX (.S(wb_la_switch), .A1(wbs_dat_i[6]), .A0(la_data_in[78]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68])); + assign la_data_out[78] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX (.S(wb_la_switch), .A1(wbs_dat_i[7]), .A0(la_data_in[77]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69])); + assign la_data_out[77] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX (.S(wb_la_switch), .A1(wbs_dat_i[8]), .A0(la_data_in[76]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70])); + assign la_data_out[76] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX (.S(wb_la_switch), .A1(wbs_dat_i[9]), .A0(la_data_in[75]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71])); + assign la_data_out[75] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX (.S(wb_la_switch), .A1(wbs_dat_i[10]), .A0(la_data_in[74]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72])); + assign la_data_out[74] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX (.S(wb_la_switch), .A1(wbs_dat_i[11]), .A0(la_data_in[73]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73])); + assign la_data_out[73] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX (.S(wb_la_switch), .A1(wbs_dat_i[12]), .A0(la_data_in[72]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74])); + assign la_data_out[72] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX (.S(wb_la_switch), .A1(wbs_dat_i[13]), .A0(la_data_in[71]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75])); + assign la_data_out[71] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX (.S(wb_la_switch), .A1(wbs_dat_i[14]), .A0(la_data_in[70]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76])); + assign la_data_out[70] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX (.S(wb_la_switch), .A1(wbs_dat_i[15]), .A0(la_data_in[69]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77])); + assign la_data_out[69] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX (.S(wb_la_switch), .A1(wbs_dat_i[16]), .A0(la_data_in[68]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78])); + assign la_data_out[68] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX (.S(wb_la_switch), .A1(wbs_dat_i[17]), .A0(la_data_in[67]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79])); + assign la_data_out[67] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX (.S(wb_la_switch), .A1(wbs_dat_i[18]), .A0(la_data_in[66]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80])); + assign la_data_out[66] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX (.S(wb_la_switch), .A1(wbs_dat_i[19]), .A0(la_data_in[65]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81])); + assign la_data_out[65] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX (.S(wb_la_switch), .A1(wbs_dat_i[20]), .A0(la_data_in[64]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82])); + assign la_data_out[64] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX (.S(wb_la_switch), .A1(wbs_dat_i[21]), .A0(la_data_in[63]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83])); + assign la_data_out[63] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX (.S(wb_la_switch), .A1(wbs_dat_i[22]), .A0(la_data_in[62]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84])); + assign la_data_out[62] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX (.S(wb_la_switch), .A1(wbs_dat_i[23]), .A0(la_data_in[61]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85])); + assign la_data_out[61] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX (.S(wb_la_switch), .A1(wbs_dat_i[24]), .A0(la_data_in[60]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86])); + assign la_data_out[60] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX (.S(wb_la_switch), .A1(wbs_dat_i[25]), .A0(la_data_in[59]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87])); + assign la_data_out[59] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX (.S(wb_la_switch), .A1(wbs_dat_i[26]), .A0(la_data_in[58]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88])); + assign la_data_out[58] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX (.S(wb_la_switch), .A1(wbs_dat_i[27]), .A0(la_data_in[57]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89])); + assign la_data_out[57] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX (.S(wb_la_switch), .A1(wbs_dat_i[28]), .A0(la_data_in[56]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90])); + assign la_data_out[56] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX (.S(wb_la_switch), .A1(wbs_dat_i[29]), .A0(la_data_in[55]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91])); + assign la_data_out[55] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX (.S(wb_la_switch), .A1(wbs_dat_i[30]), .A0(la_data_in[54]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92])); + assign la_data_out[54] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX (.S(wb_la_switch), .A1(wbs_dat_i[31]), .A0(la_data_in[53]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93])); + assign la_data_out[53] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX (.S(wb_la_switch), .A1(wbs_adr_i[0]), .A0(la_data_in[52]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94])); + assign la_data_out[52] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX (.S(wb_la_switch), .A1(wbs_adr_i[1]), .A0(la_data_in[51]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95])); + assign la_data_out[51] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX (.S(wb_la_switch), .A1(wbs_adr_i[2]), .A0(la_data_in[50]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96])); + assign la_data_out[50] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX (.S(wb_la_switch), .A1(wbs_adr_i[3]), .A0(la_data_in[49]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97])); + assign la_data_out[49] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX (.S(wb_la_switch), .A1(wbs_adr_i[4]), .A0(la_data_in[48]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98])); + assign la_data_out[48] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX (.S(wb_la_switch), .A1(wbs_adr_i[5]), .A0(la_data_in[47]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99])); + assign la_data_out[47] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX (.S(wb_la_switch), .A1(wbs_adr_i[6]), .A0(la_data_in[46]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100])); + assign la_data_out[46] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX (.S(wb_la_switch), .A1(wbs_adr_i[7]), .A0(la_data_in[45]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101])); + assign la_data_out[45] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX (.S(wb_la_switch), .A1(wbs_adr_i[8]), .A0(la_data_in[44]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102])); + assign la_data_out[44] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX (.S(wb_la_switch), .A1(wbs_adr_i[9]), .A0(la_data_in[43]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103])); + assign la_data_out[43] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX (.S(wb_la_switch), .A1(wbs_adr_i[10]), .A0(la_data_in[42]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104])); + assign la_data_out[42] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX (.S(wb_la_switch), .A1(wbs_adr_i[11]), .A0(la_data_in[41]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105])); + assign la_data_out[41] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX (.S(wb_la_switch), .A1(wbs_adr_i[12]), .A0(la_data_in[40]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106])); + assign la_data_out[40] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX (.S(wb_la_switch), .A1(wbs_adr_i[13]), .A0(la_data_in[39]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107])); + assign la_data_out[39] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX (.S(wb_la_switch), .A1(wbs_adr_i[14]), .A0(la_data_in[38]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108])); + assign la_data_out[38] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX (.S(wb_la_switch), .A1(wbs_adr_i[15]), .A0(la_data_in[37]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109])); + assign la_data_out[37] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX (.S(wb_la_switch), .A1(wbs_adr_i[16]), .A0(la_data_in[36]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110])); + assign la_data_out[36] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX (.S(wb_la_switch), .A1(wbs_adr_i[17]), .A0(la_data_in[35]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111])); + assign la_data_out[35] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX (.S(wb_la_switch), .A1(wbs_adr_i[18]), .A0(la_data_in[34]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112])); + assign la_data_out[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX (.S(wb_la_switch), .A1(wbs_adr_i[19]), .A0(la_data_in[33]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113])); + assign la_data_out[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX (.S(wb_la_switch), .A1(wbs_adr_i[20]), .A0(la_data_in[32]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114])); + assign la_data_out[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX (.S(wb_la_switch), .A1(wbs_adr_i[21]), .A0(la_data_in[31]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115])); + assign la_data_out[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX (.S(wb_la_switch), .A1(wbs_adr_i[22]), .A0(la_data_in[30]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116])); + assign la_data_out[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX (.S(wb_la_switch), .A1(wbs_adr_i[23]), .A0(la_data_in[29]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117])); + assign la_data_out[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX (.S(wb_la_switch), .A1(wbs_adr_i[24]), .A0(la_data_in[28]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118])); + assign la_data_out[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX (.S(wb_la_switch), .A1(wbs_adr_i[25]), .A0(la_data_in[27]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119])); + assign la_data_out[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX (.S(wb_la_switch), .A1(wbs_adr_i[26]), .A0(la_data_in[26]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120])); + assign la_data_out[26] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX (.S(wb_la_switch), .A1(wbs_adr_i[27]), .A0(la_data_in[25]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121])); + assign la_data_out[25] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX (.S(wb_la_switch), .A1(wbs_adr_i[28]), .A0(la_data_in[24]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122])); + assign la_data_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX (.S(wb_la_switch), .A1(wbs_adr_i[29]), .A0(la_data_in[23]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123])); + assign la_data_out[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX (.S(wb_la_switch), .A1(wbs_adr_i[30]), .A0(la_data_in[22]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124])); + assign la_data_out[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX (.S(wb_la_switch), .A1(wbs_adr_i[31]), .A0(la_data_in[21]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125])); + assign la_data_out[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX (.S(wb_la_switch), .A1(wbs_sel_i[0]), .A0(la_data_in[20]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126])); + assign la_data_out[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX (.S(wb_la_switch), .A1(wbs_sel_i[1]), .A0(la_data_in[19]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127])); + assign la_data_out[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX (.S(wb_la_switch), .A1(wbs_sel_i[2]), .A0(la_data_in[18]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128])); + assign la_data_out[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX (.S(wb_la_switch), .A1(wbs_sel_i[3]), .A0(la_data_in[17]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129])); + assign la_data_out[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX (.S(wb_la_switch), .A1(wbs_we_i), .A0(la_data_in[16]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130])); + assign la_data_out[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX (.S(wb_la_switch), .A1(wbs_stb_i), .A0(la_data_in[15]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131])); + assign la_data_out[15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX (.S(wb_la_switch), .A1(wbs_cyc_i), .A0(la_data_in[14]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132])); + assign la_data_out[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[13]; + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(wbs_ack_o)); + sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(la_data_out[13])); + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX (.S(wb_la_switch), .A1(wb_rst_i), .A0(la_data_in[12]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134])); + assign la_data_out[12] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134]; + sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX (.S(wb_la_switch), .A1(wb_clk_i), .A0(la_data_in[11]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135])); + assign la_data_out[11] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135]; + assign prog_clk = io_in[37]; + assign io_out[37] = 1'b0; + assign io_oeb[37] = 1'b1; + assign clk = io_in[36]; + assign io_out[36] = 1'b0; + assign io_oeb[36] = 1'b1; + assign io_out[35] = ccff_tail; + assign io_oeb[35] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = io_in[34]; + assign io_out[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136]; + assign io_oeb[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = io_in[33]; + assign io_out[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137]; + assign io_oeb[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = io_in[32]; + assign io_out[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138]; + assign io_oeb[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = io_in[31]; + assign io_out[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139]; + assign io_oeb[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = io_in[30]; + assign io_out[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140]; + assign io_oeb[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = io_in[29]; + assign io_out[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141]; + assign io_oeb[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = io_in[28]; + assign io_out[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142]; + assign io_oeb[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142]; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = io_in[27]; + assign io_out[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143]; + assign io_oeb[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143]; + assign sc_head = io_in[26]; + assign io_out[26] = 1'b0; + assign io_oeb[26] = 1'b1; + // + + // + // + assign wb_la_switch = io_in[25]; + assign io_out[25] = 1'b0; + assign io_oeb[25] = 1'b1; + + // + + fpga_core fpga_core_uut( + .prog_clk(prog_clk), + .Test_en(Test_en), + .clk(clk), + .IO_ISOL_N(IO_ISOL_N), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .ccff_head(ccff_head), + .ccff_tail(ccff_tail), + .sc_head(sc_head), + .sc_tail(sc_tail), + .pReset(pReset), + .Reset(Reset) + ); + +endmodule diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sc_verilog/sky130_fd_sc_hd_wrapper .v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sc_verilog/sky130_fd_sc_hd_wrapper .v new file mode 100644 index 0000000..1a884d1 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sc_verilog/sky130_fd_sc_hd_wrapper .v @@ -0,0 +1,20 @@ +`timescale 1ns/1ps + +// +// +// +module sky130_fd_sc_hd__mux2_1_wrapper ( + input A0, + input A1, + input S, + output X +); + + sky130_fd_sc_hd__mux2_1 MUX2 (.A0(A0), + .A1(A1), + .S(S), + .X(X) + ); + +endmodule + diff --git a/SOFA_A/SOFA_A_verilog/sub_module/arch_encoder.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/arch_encoder.v similarity index 89% rename from SOFA_A/SOFA_A_verilog/sub_module/arch_encoder.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/arch_encoder.v index 9d63aa9..6a7ec3e 100644 --- a/SOFA_A/SOFA_A_verilog/sub_module/arch_encoder.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/arch_encoder.v @@ -3,7 +3,6 @@ // Description: Decoders for fabric configuration protocol // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/sub_module/inv_buf_passgate.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/inv_buf_passgate.v similarity index 97% rename from SOFA_A/SOFA_A_verilog/sub_module/inv_buf_passgate.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/inv_buf_passgate.v index 745ccdf..9fb6253 100644 --- a/SOFA_A/SOFA_A_verilog/sub_module/inv_buf_passgate.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/inv_buf_passgate.v @@ -3,7 +3,6 @@ // Description: Essential gates // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/sub_module/local_encoder.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/local_encoder.v similarity index 89% rename from SOFA_A/SOFA_A_verilog/sub_module/local_encoder.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/local_encoder.v index 6ccd8e0..63dca3f 100644 --- a/SOFA_A/SOFA_A_verilog/sub_module/local_encoder.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/local_encoder.v @@ -3,7 +3,6 @@ // Description: Local Decoders for Multiplexers // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/sub_module/luts.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/luts.v similarity index 98% rename from SOFA_A/SOFA_A_verilog/sub_module/luts.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/luts.v index 5bd91cf..c49db26 100644 --- a/SOFA_A/SOFA_A_verilog/sub_module/luts.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/luts.v @@ -3,7 +3,6 @@ // Description: Look-Up Tables // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/sub_module/memories.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/memories.v similarity index 65% rename from SOFA_A/SOFA_A_verilog/sub_module/memories.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/memories.v index 25ab78f..06572de 100644 --- a/SOFA_A/SOFA_A_verilog/sub_module/memories.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/memories.v @@ -3,11 +3,78 @@ // Description: Memories used in FPGA // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size12_mem ----- +module mux_tree_tapbuf_size12_mem(pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:3] mem_out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[3]; +// ----- END Local output short connections ----- + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0])); + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1])); + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2])); + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3])); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size12_mem ----- + +//----- Default net type ----- +`default_nettype none + + + + //----- Default net type ----- `default_nettype none @@ -79,8 +146,64 @@ endmodule //----- Default net type ----- `default_nettype none -// ----- Verilog module for mux_tree_tapbuf_size6_mem ----- -module mux_tree_tapbuf_size6_mem(pReset, +// ----- Verilog module for mux_tree_tapbuf_size3_mem ----- +module mux_tree_tapbuf_size3_mem(pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:1] mem_out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[1]; +// ----- END Local output short connections ----- + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0])); + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1])); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size3_mem ----- + +//----- Default net type ----- +`default_nettype none + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size7_mem ----- +module mux_tree_tapbuf_size7_mem(pReset, prog_clk, ccff_head, ccff_tail, @@ -130,7 +253,7 @@ output [0:2] mem_out; .Q(mem_out[2])); endmodule -// ----- END Verilog module for mux_tree_tapbuf_size6_mem ----- +// ----- END Verilog module for mux_tree_tapbuf_size7_mem ----- //----- Default net type ----- `default_nettype none @@ -197,82 +320,8 @@ endmodule //----- Default net type ----- `default_nettype none -// ----- Verilog module for mux_tree_tapbuf_size17_mem ----- -module mux_tree_tapbuf_size17_mem(pReset, - prog_clk, - ccff_head, - ccff_tail, - mem_out); -//----- GLOBAL PORTS ----- -input [0:0] pReset; -//----- GLOBAL PORTS ----- -input [0:0] prog_clk; -//----- INPUT PORTS ----- -input [0:0] ccff_head; -//----- OUTPUT PORTS ----- -output [0:0] ccff_tail; -//----- OUTPUT PORTS ----- -output [0:4] mem_out; - -//----- BEGIN wire-connection ports ----- -//----- END wire-connection ports ----- - - -//----- BEGIN Registered ports ----- -//----- END Registered ports ----- - - - -// ----- BEGIN Local short connections ----- -// ----- END Local short connections ----- -// ----- BEGIN Local output short connections ----- - assign ccff_tail[0] = mem_out[4]; -// ----- END Local output short connections ----- - - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( - .RESET_B(pReset), - .CLK(prog_clk), - .D(ccff_head), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( - .RESET_B(pReset), - .CLK(prog_clk), - .D(mem_out[0]), - .Q(mem_out[1])); - - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( - .RESET_B(pReset), - .CLK(prog_clk), - .D(mem_out[1]), - .Q(mem_out[2])); - - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( - .RESET_B(pReset), - .CLK(prog_clk), - .D(mem_out[2]), - .Q(mem_out[3])); - - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( - .RESET_B(pReset), - .CLK(prog_clk), - .D(mem_out[3]), - .Q(mem_out[4])); - -endmodule -// ----- END Verilog module for mux_tree_tapbuf_size17_mem ----- - -//----- Default net type ----- -`default_nettype none - - - - -//----- Default net type ----- -`default_nettype none - -// ----- Verilog module for mux_tree_tapbuf_size3_mem ----- -module mux_tree_tapbuf_size3_mem(pReset, +// ----- Verilog module for mux_tree_tapbuf_size5_mem ----- +module mux_tree_tapbuf_size5_mem(pReset, prog_clk, ccff_head, ccff_tail, @@ -286,7 +335,7 @@ input [0:0] ccff_head; //----- OUTPUT PORTS ----- output [0:0] ccff_tail; //----- OUTPUT PORTS ----- -output [0:1] mem_out; +output [0:2] mem_out; //----- BEGIN wire-connection ports ----- //----- END wire-connection ports ----- @@ -300,7 +349,7 @@ output [0:1] mem_out; // ----- BEGIN Local short connections ----- // ----- END Local short connections ----- // ----- BEGIN Local output short connections ----- - assign ccff_tail[0] = mem_out[1]; + assign ccff_tail[0] = mem_out[2]; // ----- END Local output short connections ----- sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( @@ -315,8 +364,14 @@ output [0:1] mem_out; .D(mem_out[0]), .Q(mem_out[1])); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2])); + endmodule -// ----- END Verilog module for mux_tree_tapbuf_size3_mem ----- +// ----- END Verilog module for mux_tree_tapbuf_size5_mem ----- //----- Default net type ----- `default_nettype none @@ -327,12 +382,12 @@ endmodule //----- Default net type ----- `default_nettype none -// ----- Verilog module for mux_tree_tapbuf_size16_mem ----- -module mux_tree_tapbuf_size16_mem(pReset, - prog_clk, - ccff_head, - ccff_tail, - mem_out); +// ----- Verilog module for mux_tree_tapbuf_size6_mem ----- +module mux_tree_tapbuf_size6_mem(pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out); //----- GLOBAL PORTS ----- input [0:0] pReset; //----- GLOBAL PORTS ----- @@ -342,7 +397,7 @@ input [0:0] ccff_head; //----- OUTPUT PORTS ----- output [0:0] ccff_tail; //----- OUTPUT PORTS ----- -output [0:4] mem_out; +output [0:2] mem_out; //----- BEGIN wire-connection ports ----- //----- END wire-connection ports ----- @@ -356,7 +411,131 @@ output [0:4] mem_out; // ----- BEGIN Local short connections ----- // ----- END Local short connections ----- // ----- BEGIN Local output short connections ----- - assign ccff_tail[0] = mem_out[4]; + assign ccff_tail[0] = mem_out[2]; +// ----- END Local output short connections ----- + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0])); + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1])); + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2])); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size6_mem ----- + +//----- Default net type ----- +`default_nettype none + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size4_mem ----- +module mux_tree_tapbuf_size4_mem(pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:2] mem_out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[2]; +// ----- END Local output short connections ----- + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0])); + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1])); + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2])); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size4_mem ----- + +//----- Default net type ----- +`default_nettype none + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size11_mem ----- +module mux_tree_tapbuf_size11_mem(pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:3] mem_out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[3]; // ----- END Local output short connections ----- sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( @@ -383,14 +562,144 @@ output [0:4] mem_out; .D(mem_out[2]), .Q(mem_out[3])); - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size11_mem ----- + +//----- Default net type ----- +`default_nettype none + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size9_mem ----- +module mux_tree_tapbuf_size9_mem(pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:3] mem_out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[3]; +// ----- END Local output short connections ----- + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .RESET_B(pReset), .CLK(prog_clk), - .D(mem_out[3]), - .Q(mem_out[4])); + .D(ccff_head), + .Q(mem_out[0])); + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1])); + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2])); + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3])); endmodule -// ----- END Verilog module for mux_tree_tapbuf_size16_mem ----- +// ----- END Verilog module for mux_tree_tapbuf_size9_mem ----- + +//----- Default net type ----- +`default_nettype none + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size8_mem ----- +module mux_tree_tapbuf_size8_mem(pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out); +//----- GLOBAL PORTS ----- +input [0:0] pReset; +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:3] mem_out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[3]; +// ----- END Local output short connections ----- + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0])); + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1])); + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2])); + + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3])); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size8_mem ----- //----- Default net type ----- `default_nettype none diff --git a/SOFA_A/SOFA_A_verilog/sub_module/mux_primitives.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/mux_primitives.v similarity index 88% rename from SOFA_A/SOFA_A_verilog/sub_module/mux_primitives.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/mux_primitives.v index 554d4a6..2418841 100644 --- a/SOFA_A/SOFA_A_verilog/sub_module/mux_primitives.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/mux_primitives.v @@ -3,7 +3,6 @@ // Description: Multiplexer primitives // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/sub_module/muxes.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/muxes.v similarity index 62% rename from SOFA_A/SOFA_A_verilog/sub_module/muxes.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/muxes.v index c8c9b1e..ba2235f 100644 --- a/SOFA_A/SOFA_A_verilog/sub_module/muxes.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/muxes.v @@ -3,11 +3,142 @@ // Description: Multiplexers // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size12 ----- +module mux_tree_tapbuf_size12(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:11] in; +//----- INPUT PORTS ----- +input [0:3] sram; +//----- INPUT PORTS ----- +input [0:3] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + const1 const1_0_ ( + .const1(const1_0_const1)); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_11_X), + .X(out)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( + .A1(in[6]), + .A0(in[7]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( + .A1(in[8]), + .A0(in[9]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_4_X)); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X)); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X)); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .A0(in[10]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_7_X)); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A1(in[11]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_8_X)); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_5_X), + .A0(sky130_fd_sc_hd__mux2_1_6_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_9_X)); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_7_X), + .A0(sky130_fd_sc_hd__mux2_1_8_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_10_X)); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_9_X), + .A0(sky130_fd_sc_hd__mux2_1_10_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_11_X)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size12 ----- + +//----- Default net type ----- +`default_nettype none + + + + //----- Default net type ----- `default_nettype none @@ -126,6 +257,317 @@ endmodule +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size3 ----- +module mux_tree_tapbuf_size3(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:2] in; +//----- INPUT PORTS ----- +input [0:1] sram; +//----- INPUT PORTS ----- +input [0:1] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + const1 const1_0_ ( + .const1(const1_0_const1)); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_2_X), + .X(out)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(const1_0_const1), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X)); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size3 ----- + +//----- Default net type ----- +`default_nettype none + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size7 ----- +module mux_tree_tapbuf_size7(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:6] in; +//----- INPUT PORTS ----- +input [0:2] sram; +//----- INPUT PORTS ----- +input [0:2] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + const1 const1_0_ ( + .const1(const1_0_const1)); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_6_X), + .X(out)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( + .A1(in[6]), + .A0(const1_0_const1), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X)); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X)); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X)); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .A0(sky130_fd_sc_hd__mux2_1_5_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size7 ----- + +//----- Default net type ----- +`default_nettype none + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size2 ----- +module mux_tree_tapbuf_size2(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:1] in; +//----- INPUT PORTS ----- +input [0:1] sram; +//----- INPUT PORTS ----- +input [0:1] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + const1 const1_0_ ( + .const1(const1_0_const1)); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_1_X), + .X(out)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X)); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size2 ----- + +//----- Default net type ----- +`default_nettype none + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size5 ----- +module mux_tree_tapbuf_size5(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:4] in; +//----- INPUT PORTS ----- +input [0:2] sram; +//----- INPUT PORTS ----- +input [0:2] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + const1 const1_0_ ( + .const1(const1_0_const1)); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_4_X), + .X(out)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X)); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X)); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(in[4]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X)); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_4_X)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size5 ----- + +//----- Default net type ----- +`default_nettype none + + + + //----- Default net type ----- `default_nettype none @@ -219,17 +661,17 @@ endmodule //----- Default net type ----- `default_nettype none -// ----- Verilog module for mux_tree_tapbuf_size2 ----- -module mux_tree_tapbuf_size2(in, +// ----- Verilog module for mux_tree_tapbuf_size4 ----- +module mux_tree_tapbuf_size4(in, sram, sram_inv, out); //----- INPUT PORTS ----- -input [0:1] in; +input [0:3] in; //----- INPUT PORTS ----- -input [0:1] sram; +input [0:2] sram; //----- INPUT PORTS ----- -input [0:1] sram_inv; +input [0:2] sram_inv; //----- OUTPUT PORTS ----- output [0:0] out; @@ -244,6 +686,8 @@ output [0:0] out; wire [0:0] const1_0_const1; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; // ----- BEGIN Local short connections ----- // ----- END Local short connections ----- @@ -254,7 +698,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; .const1(const1_0_const1)); sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_1_X), + .A(sky130_fd_sc_hd__mux2_1_3_X), .X(out)); sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( @@ -265,12 +709,24 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A1(sky130_fd_sc_hd__mux2_1_0_X), - .A0(const1_0_const1), + .A0(in[2]), .S(sram[1]), .X(sky130_fd_sc_hd__mux2_1_1_X)); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(in[3]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X)); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_1_X), + .A0(sky130_fd_sc_hd__mux2_1_2_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_3_X)); + endmodule -// ----- END Verilog module for mux_tree_tapbuf_size2 ----- +// ----- END Verilog module for mux_tree_tapbuf_size4 ----- //----- Default net type ----- `default_nettype none @@ -281,17 +737,17 @@ endmodule //----- Default net type ----- `default_nettype none -// ----- Verilog module for mux_tree_tapbuf_size17 ----- -module mux_tree_tapbuf_size17(in, +// ----- Verilog module for mux_tree_tapbuf_size11 ----- +module mux_tree_tapbuf_size11(in, sram, sram_inv, out); //----- INPUT PORTS ----- -input [0:16] in; +input [0:10] in; //----- INPUT PORTS ----- -input [0:4] sram; +input [0:3] sram; //----- INPUT PORTS ----- -input [0:4] sram_inv; +input [0:3] sram_inv; //----- OUTPUT PORTS ----- output [0:0] out; @@ -306,12 +762,6 @@ output [0:0] out; wire [0:0] const1_0_const1; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_16_X; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; @@ -331,7 +781,130 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; .const1(const1_0_const1)); sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_16_X), + .A(sky130_fd_sc_hd__mux2_1_10_X), + .X(out)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X)); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( + .A1(in[6]), + .A0(in[7]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X)); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X)); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X)); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A1(in[8]), + .A0(in[9]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X)); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A1(in[10]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_7_X)); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .A0(sky130_fd_sc_hd__mux2_1_5_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_8_X)); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_6_X), + .A0(sky130_fd_sc_hd__mux2_1_7_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_9_X)); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_8_X), + .A0(sky130_fd_sc_hd__mux2_1_9_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_10_X)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size11 ----- + +//----- Default net type ----- +`default_nettype none + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size9 ----- +module mux_tree_tapbuf_size9(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:8] in; +//----- INPUT PORTS ----- +input [0:3] sram; +//----- INPUT PORTS ----- +input [0:3] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + const1 const1_0_ ( + .const1(const1_0_const1)); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_8_X), .X(out)); sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( @@ -366,78 +939,30 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A1(in[8]), - .A0(in[9]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_5_X)); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( - .A1(in[10]), - .A0(in[11]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_6_X)); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( - .A1(in[12]), - .A0(in[13]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_7_X)); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( - .A1(in[14]), - .A0(in[15]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_8_X)); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( - .A1(in[16]), .A0(const1_0_const1), .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_9_X)); + .X(sky130_fd_sc_hd__mux2_1_5_X)); sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A1(sky130_fd_sc_hd__mux2_1_2_X), .A0(sky130_fd_sc_hd__mux2_1_3_X), .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_10_X)); + .X(sky130_fd_sc_hd__mux2_1_6_X)); sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A1(sky130_fd_sc_hd__mux2_1_4_X), .A0(sky130_fd_sc_hd__mux2_1_5_X), .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_11_X)); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A1(sky130_fd_sc_hd__mux2_1_6_X), - .A0(sky130_fd_sc_hd__mux2_1_7_X), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_12_X)); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A1(sky130_fd_sc_hd__mux2_1_8_X), - .A0(sky130_fd_sc_hd__mux2_1_9_X), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_13_X)); + .X(sky130_fd_sc_hd__mux2_1_7_X)); sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_10_X), - .A0(sky130_fd_sc_hd__mux2_1_11_X), + .A1(sky130_fd_sc_hd__mux2_1_6_X), + .A0(sky130_fd_sc_hd__mux2_1_7_X), .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_14_X)); - - sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_12_X), - .A0(sky130_fd_sc_hd__mux2_1_13_X), - .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_15_X)); - - sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_14_X), - .A0(sky130_fd_sc_hd__mux2_1_15_X), - .S(sram[4]), - .X(sky130_fd_sc_hd__mux2_1_16_X)); + .X(sky130_fd_sc_hd__mux2_1_8_X)); endmodule -// ----- END Verilog module for mux_tree_tapbuf_size17 ----- +// ----- END Verilog module for mux_tree_tapbuf_size9 ----- //----- Default net type ----- `default_nettype none @@ -448,17 +973,17 @@ endmodule //----- Default net type ----- `default_nettype none -// ----- Verilog module for mux_tree_tapbuf_size3 ----- -module mux_tree_tapbuf_size3(in, +// ----- Verilog module for mux_tree_tapbuf_size8 ----- +module mux_tree_tapbuf_size8(in, sram, sram_inv, out); //----- INPUT PORTS ----- -input [0:2] in; +input [0:7] in; //----- INPUT PORTS ----- -input [0:1] sram; +input [0:3] sram; //----- INPUT PORTS ----- -input [0:1] sram_inv; +input [0:3] sram_inv; //----- OUTPUT PORTS ----- output [0:0] out; @@ -474,88 +999,11 @@ wire [0:0] const1_0_const1; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; - -// ----- BEGIN Local short connections ----- -// ----- END Local short connections ----- -// ----- BEGIN Local output short connections ----- -// ----- END Local output short connections ----- - - const1 const1_0_ ( - .const1(const1_0_const1)); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_2_X), - .X(out)); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X)); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(const1_0_const1), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X)); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X), - .A0(sky130_fd_sc_hd__mux2_1_1_X), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_2_X)); - -endmodule -// ----- END Verilog module for mux_tree_tapbuf_size3 ----- - -//----- Default net type ----- -`default_nettype none - - - - -//----- Default net type ----- -`default_nettype none - -// ----- Verilog module for mux_tree_tapbuf_size16 ----- -module mux_tree_tapbuf_size16(in, - sram, - sram_inv, - out); -//----- INPUT PORTS ----- -input [0:15] in; -//----- INPUT PORTS ----- -input [0:4] sram; -//----- INPUT PORTS ----- -input [0:4] sram_inv; -//----- OUTPUT PORTS ----- -output [0:0] out; - -//----- BEGIN wire-connection ports ----- -//----- END wire-connection ports ----- - - -//----- BEGIN Registered ports ----- -//----- END Registered ports ----- - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; // ----- BEGIN Local short connections ----- // ----- END Local short connections ----- @@ -566,7 +1014,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; .const1(const1_0_const1)); sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_15_X), + .A(sky130_fd_sc_hd__mux2_1_7_X), .X(out)); sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( @@ -595,78 +1043,30 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A1(in[7]), - .A0(in[8]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_4_X)); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( - .A1(in[9]), - .A0(in[10]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_5_X)); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( - .A1(in[11]), - .A0(in[12]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_6_X)); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( - .A1(in[13]), - .A0(in[14]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_7_X)); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( - .A1(in[15]), .A0(const1_0_const1), .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_8_X)); + .X(sky130_fd_sc_hd__mux2_1_4_X)); sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A1(sky130_fd_sc_hd__mux2_1_1_X), .A0(sky130_fd_sc_hd__mux2_1_2_X), .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_9_X)); + .X(sky130_fd_sc_hd__mux2_1_5_X)); sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A1(sky130_fd_sc_hd__mux2_1_3_X), .A0(sky130_fd_sc_hd__mux2_1_4_X), .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_10_X)); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A1(sky130_fd_sc_hd__mux2_1_5_X), - .A0(sky130_fd_sc_hd__mux2_1_6_X), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_11_X)); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A1(sky130_fd_sc_hd__mux2_1_7_X), - .A0(sky130_fd_sc_hd__mux2_1_8_X), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_12_X)); + .X(sky130_fd_sc_hd__mux2_1_6_X)); sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_9_X), - .A0(sky130_fd_sc_hd__mux2_1_10_X), + .A1(sky130_fd_sc_hd__mux2_1_5_X), + .A0(sky130_fd_sc_hd__mux2_1_6_X), .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_13_X)); - - sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_11_X), - .A0(sky130_fd_sc_hd__mux2_1_12_X), - .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_14_X)); - - sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_13_X), - .A0(sky130_fd_sc_hd__mux2_1_14_X), - .S(sram[4]), - .X(sky130_fd_sc_hd__mux2_1_15_X)); + .X(sky130_fd_sc_hd__mux2_1_7_X)); endmodule -// ----- END Verilog module for mux_tree_tapbuf_size16 ----- +// ----- END Verilog module for mux_tree_tapbuf_size8 ----- //----- Default net type ----- `default_nettype none diff --git a/SOFA_A/SOFA_A_verilog/sub_module/shift_register_banks.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/shift_register_banks.v similarity index 89% rename from SOFA_A/SOFA_A_verilog/sub_module/shift_register_banks.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/shift_register_banks.v index a5e1c7f..877cae3 100644 --- a/SOFA_A/SOFA_A_verilog/sub_module/shift_register_banks.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/shift_register_banks.v @@ -3,7 +3,6 @@ // Description: Shift register banks used in FPGA // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/sub_module/user_defined_templates.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/user_defined_templates.v similarity index 99% rename from SOFA_A/SOFA_A_verilog/sub_module/user_defined_templates.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/user_defined_templates.v index 3d0c382..452ff30 100644 --- a/SOFA_A/SOFA_A_verilog/sub_module/user_defined_templates.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/user_defined_templates.v @@ -3,7 +3,6 @@ // Description: Template for user-defined Verilog modules // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/SOFA_A_verilog/sub_module/wires.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/wires.v similarity index 96% rename from SOFA_A/SOFA_A_verilog/sub_module/wires.v rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/wires.v index 9b0d08e..e8d10f4 100644 --- a/SOFA_A/SOFA_A_verilog/sub_module/wires.v +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/wires.v @@ -3,7 +3,6 @@ // Description: Wires // Author: Xifan TANG // Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 //------------------------------------------- //----- Time scale ----- `timescale 1ns / 1ps diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/CustomModules/custom_module.txt b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/CustomModules/custom_module.txt new file mode 100644 index 0000000..3834131 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/CustomModules/custom_module.txt @@ -0,0 +1 @@ +# Dummy file to list all custom modules used in this project \ No newline at end of file diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/fpga_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/fpga_top.v new file mode 100644 index 0000000..54050e1 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/fpga_top.v @@ -0,0 +1,17437 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module fpga_top +( + clk, + Reset, + IO_ISOL_N, + pReset, + prog_clk, + Test_en, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + ccff_head, + ccff_tail +); + + input clk; + input Reset; + input IO_ISOL_N; + input pReset; + input prog_clk; + input Test_en; + input [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + output [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + input ccff_head; + output ccff_tail; + + wire clk; + wire Reset; + wire IO_ISOL_N; + wire pReset; + wire prog_clk; + wire Test_en; + wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire ccff_head; + wire ccff_tail; + wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__0_ccff_tail; + wire [0:29]cbx_1__0__0_chanx_left_out; + wire [0:29]cbx_1__0__0_chanx_right_out; + wire cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__1_ccff_tail; + wire [0:29]cbx_1__0__1_chanx_left_out; + wire [0:29]cbx_1__0__1_chanx_right_out; + wire cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__2_ccff_tail; + wire [0:29]cbx_1__0__2_chanx_left_out; + wire [0:29]cbx_1__0__2_chanx_right_out; + wire cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__3_ccff_tail; + wire [0:29]cbx_1__0__3_chanx_left_out; + wire [0:29]cbx_1__0__3_chanx_right_out; + wire cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__4_ccff_tail; + wire [0:29]cbx_1__0__4_chanx_left_out; + wire [0:29]cbx_1__0__4_chanx_right_out; + wire cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__5_ccff_tail; + wire [0:29]cbx_1__0__5_chanx_left_out; + wire [0:29]cbx_1__0__5_chanx_right_out; + wire cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__6_ccff_tail; + wire [0:29]cbx_1__0__6_chanx_left_out; + wire [0:29]cbx_1__0__6_chanx_right_out; + wire cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__0__7_ccff_tail; + wire [0:29]cbx_1__0__7_chanx_left_out; + wire [0:29]cbx_1__0__7_chanx_right_out; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__0_ccff_tail; + wire [0:29]cbx_1__1__0_chanx_left_out; + wire [0:29]cbx_1__1__0_chanx_right_out; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__10_ccff_tail; + wire [0:29]cbx_1__1__10_chanx_left_out; + wire [0:29]cbx_1__1__10_chanx_right_out; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__11_ccff_tail; + wire [0:29]cbx_1__1__11_chanx_left_out; + wire [0:29]cbx_1__1__11_chanx_right_out; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__12_ccff_tail; + wire [0:29]cbx_1__1__12_chanx_left_out; + wire [0:29]cbx_1__1__12_chanx_right_out; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__13_ccff_tail; + wire [0:29]cbx_1__1__13_chanx_left_out; + wire [0:29]cbx_1__1__13_chanx_right_out; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__14_ccff_tail; + wire [0:29]cbx_1__1__14_chanx_left_out; + wire [0:29]cbx_1__1__14_chanx_right_out; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__15_ccff_tail; + wire [0:29]cbx_1__1__15_chanx_left_out; + wire [0:29]cbx_1__1__15_chanx_right_out; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__16_ccff_tail; + wire [0:29]cbx_1__1__16_chanx_left_out; + wire [0:29]cbx_1__1__16_chanx_right_out; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__17_ccff_tail; + wire [0:29]cbx_1__1__17_chanx_left_out; + wire [0:29]cbx_1__1__17_chanx_right_out; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__18_ccff_tail; + wire [0:29]cbx_1__1__18_chanx_left_out; + wire [0:29]cbx_1__1__18_chanx_right_out; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__19_ccff_tail; + wire [0:29]cbx_1__1__19_chanx_left_out; + wire [0:29]cbx_1__1__19_chanx_right_out; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__1_ccff_tail; + wire [0:29]cbx_1__1__1_chanx_left_out; + wire [0:29]cbx_1__1__1_chanx_right_out; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__20_ccff_tail; + wire [0:29]cbx_1__1__20_chanx_left_out; + wire [0:29]cbx_1__1__20_chanx_right_out; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__21_ccff_tail; + wire [0:29]cbx_1__1__21_chanx_left_out; + wire [0:29]cbx_1__1__21_chanx_right_out; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__22_ccff_tail; + wire [0:29]cbx_1__1__22_chanx_left_out; + wire [0:29]cbx_1__1__22_chanx_right_out; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__23_ccff_tail; + wire [0:29]cbx_1__1__23_chanx_left_out; + wire [0:29]cbx_1__1__23_chanx_right_out; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__24_ccff_tail; + wire [0:29]cbx_1__1__24_chanx_left_out; + wire [0:29]cbx_1__1__24_chanx_right_out; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__25_ccff_tail; + wire [0:29]cbx_1__1__25_chanx_left_out; + wire [0:29]cbx_1__1__25_chanx_right_out; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__26_ccff_tail; + wire [0:29]cbx_1__1__26_chanx_left_out; + wire [0:29]cbx_1__1__26_chanx_right_out; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__27_ccff_tail; + wire [0:29]cbx_1__1__27_chanx_left_out; + wire [0:29]cbx_1__1__27_chanx_right_out; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__28_ccff_tail; + wire [0:29]cbx_1__1__28_chanx_left_out; + wire [0:29]cbx_1__1__28_chanx_right_out; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__29_ccff_tail; + wire [0:29]cbx_1__1__29_chanx_left_out; + wire [0:29]cbx_1__1__29_chanx_right_out; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__2_ccff_tail; + wire [0:29]cbx_1__1__2_chanx_left_out; + wire [0:29]cbx_1__1__2_chanx_right_out; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__30_ccff_tail; + wire [0:29]cbx_1__1__30_chanx_left_out; + wire [0:29]cbx_1__1__30_chanx_right_out; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__31_ccff_tail; + wire [0:29]cbx_1__1__31_chanx_left_out; + wire [0:29]cbx_1__1__31_chanx_right_out; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__32_ccff_tail; + wire [0:29]cbx_1__1__32_chanx_left_out; + wire [0:29]cbx_1__1__32_chanx_right_out; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__33_ccff_tail; + wire [0:29]cbx_1__1__33_chanx_left_out; + wire [0:29]cbx_1__1__33_chanx_right_out; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__34_ccff_tail; + wire [0:29]cbx_1__1__34_chanx_left_out; + wire [0:29]cbx_1__1__34_chanx_right_out; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__35_ccff_tail; + wire [0:29]cbx_1__1__35_chanx_left_out; + wire [0:29]cbx_1__1__35_chanx_right_out; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__36_ccff_tail; + wire [0:29]cbx_1__1__36_chanx_left_out; + wire [0:29]cbx_1__1__36_chanx_right_out; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__37_ccff_tail; + wire [0:29]cbx_1__1__37_chanx_left_out; + wire [0:29]cbx_1__1__37_chanx_right_out; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__38_ccff_tail; + wire [0:29]cbx_1__1__38_chanx_left_out; + wire [0:29]cbx_1__1__38_chanx_right_out; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__39_ccff_tail; + wire [0:29]cbx_1__1__39_chanx_left_out; + wire [0:29]cbx_1__1__39_chanx_right_out; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__3_ccff_tail; + wire [0:29]cbx_1__1__3_chanx_left_out; + wire [0:29]cbx_1__1__3_chanx_right_out; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__40_ccff_tail; + wire [0:29]cbx_1__1__40_chanx_left_out; + wire [0:29]cbx_1__1__40_chanx_right_out; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__41_ccff_tail; + wire [0:29]cbx_1__1__41_chanx_left_out; + wire [0:29]cbx_1__1__41_chanx_right_out; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__42_ccff_tail; + wire [0:29]cbx_1__1__42_chanx_left_out; + wire [0:29]cbx_1__1__42_chanx_right_out; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__43_ccff_tail; + wire [0:29]cbx_1__1__43_chanx_left_out; + wire [0:29]cbx_1__1__43_chanx_right_out; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__44_ccff_tail; + wire [0:29]cbx_1__1__44_chanx_left_out; + wire [0:29]cbx_1__1__44_chanx_right_out; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__45_ccff_tail; + wire [0:29]cbx_1__1__45_chanx_left_out; + wire [0:29]cbx_1__1__45_chanx_right_out; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__46_ccff_tail; + wire [0:29]cbx_1__1__46_chanx_left_out; + wire [0:29]cbx_1__1__46_chanx_right_out; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__47_ccff_tail; + wire [0:29]cbx_1__1__47_chanx_left_out; + wire [0:29]cbx_1__1__47_chanx_right_out; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__48_ccff_tail; + wire [0:29]cbx_1__1__48_chanx_left_out; + wire [0:29]cbx_1__1__48_chanx_right_out; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__49_ccff_tail; + wire [0:29]cbx_1__1__49_chanx_left_out; + wire [0:29]cbx_1__1__49_chanx_right_out; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__4_ccff_tail; + wire [0:29]cbx_1__1__4_chanx_left_out; + wire [0:29]cbx_1__1__4_chanx_right_out; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__50_ccff_tail; + wire [0:29]cbx_1__1__50_chanx_left_out; + wire [0:29]cbx_1__1__50_chanx_right_out; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__51_ccff_tail; + wire [0:29]cbx_1__1__51_chanx_left_out; + wire [0:29]cbx_1__1__51_chanx_right_out; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__52_ccff_tail; + wire [0:29]cbx_1__1__52_chanx_left_out; + wire [0:29]cbx_1__1__52_chanx_right_out; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__53_ccff_tail; + wire [0:29]cbx_1__1__53_chanx_left_out; + wire [0:29]cbx_1__1__53_chanx_right_out; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__54_ccff_tail; + wire [0:29]cbx_1__1__54_chanx_left_out; + wire [0:29]cbx_1__1__54_chanx_right_out; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__55_ccff_tail; + wire [0:29]cbx_1__1__55_chanx_left_out; + wire [0:29]cbx_1__1__55_chanx_right_out; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__5_ccff_tail; + wire [0:29]cbx_1__1__5_chanx_left_out; + wire [0:29]cbx_1__1__5_chanx_right_out; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__6_ccff_tail; + wire [0:29]cbx_1__1__6_chanx_left_out; + wire [0:29]cbx_1__1__6_chanx_right_out; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__7_ccff_tail; + wire [0:29]cbx_1__1__7_chanx_left_out; + wire [0:29]cbx_1__1__7_chanx_right_out; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__8_ccff_tail; + wire [0:29]cbx_1__1__8_chanx_left_out; + wire [0:29]cbx_1__1__8_chanx_right_out; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__1__9_ccff_tail; + wire [0:29]cbx_1__1__9_chanx_left_out; + wire [0:29]cbx_1__1__9_chanx_right_out; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__0_ccff_tail; + wire [0:29]cbx_1__8__0_chanx_left_out; + wire [0:29]cbx_1__8__0_chanx_right_out; + wire cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__1_ccff_tail; + wire [0:29]cbx_1__8__1_chanx_left_out; + wire [0:29]cbx_1__8__1_chanx_right_out; + wire cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__2_ccff_tail; + wire [0:29]cbx_1__8__2_chanx_left_out; + wire [0:29]cbx_1__8__2_chanx_right_out; + wire cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__3_ccff_tail; + wire [0:29]cbx_1__8__3_chanx_left_out; + wire [0:29]cbx_1__8__3_chanx_right_out; + wire cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__4_ccff_tail; + wire [0:29]cbx_1__8__4_chanx_left_out; + wire [0:29]cbx_1__8__4_chanx_right_out; + wire cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__5_ccff_tail; + wire [0:29]cbx_1__8__5_chanx_left_out; + wire [0:29]cbx_1__8__5_chanx_right_out; + wire cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__6_ccff_tail; + wire [0:29]cbx_1__8__6_chanx_left_out; + wire [0:29]cbx_1__8__6_chanx_right_out; + wire cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire cbx_1__8__7_ccff_tail; + wire [0:29]cbx_1__8__7_chanx_left_out; + wire [0:29]cbx_1__8__7_chanx_right_out; + wire cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__0_ccff_tail; + wire [0:29]cby_0__1__0_chany_bottom_out; + wire [0:29]cby_0__1__0_chany_top_out; + wire cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__1_ccff_tail; + wire [0:29]cby_0__1__1_chany_bottom_out; + wire [0:29]cby_0__1__1_chany_top_out; + wire cby_0__1__1_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__1_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__1_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__1_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__2_ccff_tail; + wire [0:29]cby_0__1__2_chany_bottom_out; + wire [0:29]cby_0__1__2_chany_top_out; + wire cby_0__1__2_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__2_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__2_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__2_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__3_ccff_tail; + wire [0:29]cby_0__1__3_chany_bottom_out; + wire [0:29]cby_0__1__3_chany_top_out; + wire cby_0__1__3_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__3_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__3_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__3_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__4_ccff_tail; + wire [0:29]cby_0__1__4_chany_bottom_out; + wire [0:29]cby_0__1__4_chany_top_out; + wire cby_0__1__4_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__4_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__4_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__4_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__5_ccff_tail; + wire [0:29]cby_0__1__5_chany_bottom_out; + wire [0:29]cby_0__1__5_chany_top_out; + wire cby_0__1__5_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__5_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__5_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__5_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__6_ccff_tail; + wire [0:29]cby_0__1__6_chany_bottom_out; + wire [0:29]cby_0__1__6_chany_top_out; + wire cby_0__1__6_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__6_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__6_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__6_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_0__1__7_ccff_tail; + wire [0:29]cby_0__1__7_chany_bottom_out; + wire [0:29]cby_0__1__7_chany_top_out; + wire cby_0__1__7_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_0__1__7_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_0__1__7_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_0__1__7_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_1__1__0_ccff_tail; + wire [0:29]cby_1__1__0_chany_bottom_out; + wire [0:29]cby_1__1__0_chany_top_out; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__10_ccff_tail; + wire [0:29]cby_1__1__10_chany_bottom_out; + wire [0:29]cby_1__1__10_chany_top_out; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__11_ccff_tail; + wire [0:29]cby_1__1__11_chany_bottom_out; + wire [0:29]cby_1__1__11_chany_top_out; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__12_ccff_tail; + wire [0:29]cby_1__1__12_chany_bottom_out; + wire [0:29]cby_1__1__12_chany_top_out; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__13_ccff_tail; + wire [0:29]cby_1__1__13_chany_bottom_out; + wire [0:29]cby_1__1__13_chany_top_out; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__14_ccff_tail; + wire [0:29]cby_1__1__14_chany_bottom_out; + wire [0:29]cby_1__1__14_chany_top_out; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__15_ccff_tail; + wire [0:29]cby_1__1__15_chany_bottom_out; + wire [0:29]cby_1__1__15_chany_top_out; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__16_ccff_tail; + wire [0:29]cby_1__1__16_chany_bottom_out; + wire [0:29]cby_1__1__16_chany_top_out; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__17_ccff_tail; + wire [0:29]cby_1__1__17_chany_bottom_out; + wire [0:29]cby_1__1__17_chany_top_out; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__18_ccff_tail; + wire [0:29]cby_1__1__18_chany_bottom_out; + wire [0:29]cby_1__1__18_chany_top_out; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__19_ccff_tail; + wire [0:29]cby_1__1__19_chany_bottom_out; + wire [0:29]cby_1__1__19_chany_top_out; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__1_ccff_tail; + wire [0:29]cby_1__1__1_chany_bottom_out; + wire [0:29]cby_1__1__1_chany_top_out; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__20_ccff_tail; + wire [0:29]cby_1__1__20_chany_bottom_out; + wire [0:29]cby_1__1__20_chany_top_out; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__21_ccff_tail; + wire [0:29]cby_1__1__21_chany_bottom_out; + wire [0:29]cby_1__1__21_chany_top_out; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__22_ccff_tail; + wire [0:29]cby_1__1__22_chany_bottom_out; + wire [0:29]cby_1__1__22_chany_top_out; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__23_ccff_tail; + wire [0:29]cby_1__1__23_chany_bottom_out; + wire [0:29]cby_1__1__23_chany_top_out; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__24_ccff_tail; + wire [0:29]cby_1__1__24_chany_bottom_out; + wire [0:29]cby_1__1__24_chany_top_out; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__25_ccff_tail; + wire [0:29]cby_1__1__25_chany_bottom_out; + wire [0:29]cby_1__1__25_chany_top_out; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__26_ccff_tail; + wire [0:29]cby_1__1__26_chany_bottom_out; + wire [0:29]cby_1__1__26_chany_top_out; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__27_ccff_tail; + wire [0:29]cby_1__1__27_chany_bottom_out; + wire [0:29]cby_1__1__27_chany_top_out; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__28_ccff_tail; + wire [0:29]cby_1__1__28_chany_bottom_out; + wire [0:29]cby_1__1__28_chany_top_out; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__29_ccff_tail; + wire [0:29]cby_1__1__29_chany_bottom_out; + wire [0:29]cby_1__1__29_chany_top_out; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__2_ccff_tail; + wire [0:29]cby_1__1__2_chany_bottom_out; + wire [0:29]cby_1__1__2_chany_top_out; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__30_ccff_tail; + wire [0:29]cby_1__1__30_chany_bottom_out; + wire [0:29]cby_1__1__30_chany_top_out; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__31_ccff_tail; + wire [0:29]cby_1__1__31_chany_bottom_out; + wire [0:29]cby_1__1__31_chany_top_out; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__32_ccff_tail; + wire [0:29]cby_1__1__32_chany_bottom_out; + wire [0:29]cby_1__1__32_chany_top_out; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__33_ccff_tail; + wire [0:29]cby_1__1__33_chany_bottom_out; + wire [0:29]cby_1__1__33_chany_top_out; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__34_ccff_tail; + wire [0:29]cby_1__1__34_chany_bottom_out; + wire [0:29]cby_1__1__34_chany_top_out; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__35_ccff_tail; + wire [0:29]cby_1__1__35_chany_bottom_out; + wire [0:29]cby_1__1__35_chany_top_out; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__36_ccff_tail; + wire [0:29]cby_1__1__36_chany_bottom_out; + wire [0:29]cby_1__1__36_chany_top_out; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__37_ccff_tail; + wire [0:29]cby_1__1__37_chany_bottom_out; + wire [0:29]cby_1__1__37_chany_top_out; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__38_ccff_tail; + wire [0:29]cby_1__1__38_chany_bottom_out; + wire [0:29]cby_1__1__38_chany_top_out; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__39_ccff_tail; + wire [0:29]cby_1__1__39_chany_bottom_out; + wire [0:29]cby_1__1__39_chany_top_out; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__3_ccff_tail; + wire [0:29]cby_1__1__3_chany_bottom_out; + wire [0:29]cby_1__1__3_chany_top_out; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__40_ccff_tail; + wire [0:29]cby_1__1__40_chany_bottom_out; + wire [0:29]cby_1__1__40_chany_top_out; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__41_ccff_tail; + wire [0:29]cby_1__1__41_chany_bottom_out; + wire [0:29]cby_1__1__41_chany_top_out; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__42_ccff_tail; + wire [0:29]cby_1__1__42_chany_bottom_out; + wire [0:29]cby_1__1__42_chany_top_out; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__43_ccff_tail; + wire [0:29]cby_1__1__43_chany_bottom_out; + wire [0:29]cby_1__1__43_chany_top_out; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__44_ccff_tail; + wire [0:29]cby_1__1__44_chany_bottom_out; + wire [0:29]cby_1__1__44_chany_top_out; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__45_ccff_tail; + wire [0:29]cby_1__1__45_chany_bottom_out; + wire [0:29]cby_1__1__45_chany_top_out; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__46_ccff_tail; + wire [0:29]cby_1__1__46_chany_bottom_out; + wire [0:29]cby_1__1__46_chany_top_out; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__47_ccff_tail; + wire [0:29]cby_1__1__47_chany_bottom_out; + wire [0:29]cby_1__1__47_chany_top_out; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__48_ccff_tail; + wire [0:29]cby_1__1__48_chany_bottom_out; + wire [0:29]cby_1__1__48_chany_top_out; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__49_ccff_tail; + wire [0:29]cby_1__1__49_chany_bottom_out; + wire [0:29]cby_1__1__49_chany_top_out; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__4_ccff_tail; + wire [0:29]cby_1__1__4_chany_bottom_out; + wire [0:29]cby_1__1__4_chany_top_out; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__50_ccff_tail; + wire [0:29]cby_1__1__50_chany_bottom_out; + wire [0:29]cby_1__1__50_chany_top_out; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__51_ccff_tail; + wire [0:29]cby_1__1__51_chany_bottom_out; + wire [0:29]cby_1__1__51_chany_top_out; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__52_ccff_tail; + wire [0:29]cby_1__1__52_chany_bottom_out; + wire [0:29]cby_1__1__52_chany_top_out; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__53_ccff_tail; + wire [0:29]cby_1__1__53_chany_bottom_out; + wire [0:29]cby_1__1__53_chany_top_out; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__54_ccff_tail; + wire [0:29]cby_1__1__54_chany_bottom_out; + wire [0:29]cby_1__1__54_chany_top_out; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__55_ccff_tail; + wire [0:29]cby_1__1__55_chany_bottom_out; + wire [0:29]cby_1__1__55_chany_top_out; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__5_ccff_tail; + wire [0:29]cby_1__1__5_chany_bottom_out; + wire [0:29]cby_1__1__5_chany_top_out; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__6_ccff_tail; + wire [0:29]cby_1__1__6_chany_bottom_out; + wire [0:29]cby_1__1__6_chany_top_out; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__7_ccff_tail; + wire [0:29]cby_1__1__7_chany_bottom_out; + wire [0:29]cby_1__1__7_chany_top_out; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__8_ccff_tail; + wire [0:29]cby_1__1__8_chany_bottom_out; + wire [0:29]cby_1__1__8_chany_top_out; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_1__1__9_ccff_tail; + wire [0:29]cby_1__1__9_chany_bottom_out; + wire [0:29]cby_1__1__9_chany_top_out; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__0_ccff_tail; + wire [0:29]cby_8__1__0_chany_bottom_out; + wire [0:29]cby_8__1__0_chany_top_out; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__1_ccff_tail; + wire [0:29]cby_8__1__1_chany_bottom_out; + wire [0:29]cby_8__1__1_chany_top_out; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__1_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__1_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__1_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__2_ccff_tail; + wire [0:29]cby_8__1__2_chany_bottom_out; + wire [0:29]cby_8__1__2_chany_top_out; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__2_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__2_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__2_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__3_ccff_tail; + wire [0:29]cby_8__1__3_chany_bottom_out; + wire [0:29]cby_8__1__3_chany_top_out; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__3_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__3_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__3_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__4_ccff_tail; + wire [0:29]cby_8__1__4_chany_bottom_out; + wire [0:29]cby_8__1__4_chany_top_out; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__4_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__4_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__4_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__4_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__5_ccff_tail; + wire [0:29]cby_8__1__5_chany_bottom_out; + wire [0:29]cby_8__1__5_chany_top_out; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__5_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__5_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__5_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__5_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__6_ccff_tail; + wire [0:29]cby_8__1__6_chany_bottom_out; + wire [0:29]cby_8__1__6_chany_top_out; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__6_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__6_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__6_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__6_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire cby_8__1__7_ccff_tail; + wire [0:29]cby_8__1__7_chany_bottom_out; + wire [0:29]cby_8__1__7_chany_top_out; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire cby_8__1__7_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire cby_8__1__7_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire cby_8__1__7_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire cby_8__1__7_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire direct_interc_0_out; + wire direct_interc_100_out; + wire direct_interc_101_out; + wire direct_interc_102_out; + wire direct_interc_103_out; + wire direct_interc_104_out; + wire direct_interc_105_out; + wire direct_interc_106_out; + wire direct_interc_107_out; + wire direct_interc_108_out; + wire direct_interc_109_out; + wire direct_interc_10_out; + wire direct_interc_110_out; + wire direct_interc_111_out; + wire direct_interc_112_out; + wire direct_interc_113_out; + wire direct_interc_114_out; + wire direct_interc_115_out; + wire direct_interc_116_out; + wire direct_interc_117_out; + wire direct_interc_118_out; + wire direct_interc_119_out; + wire direct_interc_11_out; + wire direct_interc_120_out; + wire direct_interc_121_out; + wire direct_interc_122_out; + wire direct_interc_123_out; + wire direct_interc_124_out; + wire direct_interc_125_out; + wire direct_interc_126_out; + wire direct_interc_127_out; + wire direct_interc_128_out; + wire direct_interc_129_out; + wire direct_interc_12_out; + wire direct_interc_130_out; + wire direct_interc_131_out; + wire direct_interc_132_out; + wire direct_interc_133_out; + wire direct_interc_134_out; + wire direct_interc_135_out; + wire direct_interc_136_out; + wire direct_interc_137_out; + wire direct_interc_138_out; + wire direct_interc_139_out; + wire direct_interc_13_out; + wire direct_interc_140_out; + wire direct_interc_141_out; + wire direct_interc_142_out; + wire direct_interc_143_out; + wire direct_interc_144_out; + wire direct_interc_145_out; + wire direct_interc_146_out; + wire direct_interc_147_out; + wire direct_interc_148_out; + wire direct_interc_149_out; + wire direct_interc_14_out; + wire direct_interc_150_out; + wire direct_interc_151_out; + wire direct_interc_152_out; + wire direct_interc_153_out; + wire direct_interc_154_out; + wire direct_interc_155_out; + wire direct_interc_156_out; + wire direct_interc_157_out; + wire direct_interc_158_out; + wire direct_interc_159_out; + wire direct_interc_15_out; + wire direct_interc_160_out; + wire direct_interc_161_out; + wire direct_interc_162_out; + wire direct_interc_163_out; + wire direct_interc_164_out; + wire direct_interc_165_out; + wire direct_interc_166_out; + wire direct_interc_167_out; + wire direct_interc_168_out; + wire direct_interc_169_out; + wire direct_interc_16_out; + wire direct_interc_170_out; + wire direct_interc_171_out; + wire direct_interc_172_out; + wire direct_interc_173_out; + wire direct_interc_174_out; + wire direct_interc_17_out; + wire direct_interc_18_out; + wire direct_interc_19_out; + wire direct_interc_1_out; + wire direct_interc_20_out; + wire direct_interc_21_out; + wire direct_interc_22_out; + wire direct_interc_23_out; + wire direct_interc_24_out; + wire direct_interc_25_out; + wire direct_interc_26_out; + wire direct_interc_27_out; + wire direct_interc_28_out; + wire direct_interc_29_out; + wire direct_interc_2_out; + wire direct_interc_30_out; + wire direct_interc_31_out; + wire direct_interc_32_out; + wire direct_interc_33_out; + wire direct_interc_34_out; + wire direct_interc_35_out; + wire direct_interc_36_out; + wire direct_interc_37_out; + wire direct_interc_38_out; + wire direct_interc_39_out; + wire direct_interc_3_out; + wire direct_interc_40_out; + wire direct_interc_41_out; + wire direct_interc_42_out; + wire direct_interc_43_out; + wire direct_interc_44_out; + wire direct_interc_45_out; + wire direct_interc_46_out; + wire direct_interc_47_out; + wire direct_interc_48_out; + wire direct_interc_49_out; + wire direct_interc_4_out; + wire direct_interc_50_out; + wire direct_interc_51_out; + wire direct_interc_52_out; + wire direct_interc_53_out; + wire direct_interc_54_out; + wire direct_interc_55_out; + wire direct_interc_56_out; + wire direct_interc_57_out; + wire direct_interc_58_out; + wire direct_interc_59_out; + wire direct_interc_5_out; + wire direct_interc_60_out; + wire direct_interc_61_out; + wire direct_interc_62_out; + wire direct_interc_63_out; + wire direct_interc_64_out; + wire direct_interc_65_out; + wire direct_interc_66_out; + wire direct_interc_67_out; + wire direct_interc_68_out; + wire direct_interc_69_out; + wire direct_interc_6_out; + wire direct_interc_70_out; + wire direct_interc_71_out; + wire direct_interc_72_out; + wire direct_interc_73_out; + wire direct_interc_74_out; + wire direct_interc_75_out; + wire direct_interc_76_out; + wire direct_interc_77_out; + wire direct_interc_78_out; + wire direct_interc_79_out; + wire direct_interc_7_out; + wire direct_interc_80_out; + wire direct_interc_81_out; + wire direct_interc_82_out; + wire direct_interc_83_out; + wire direct_interc_84_out; + wire direct_interc_85_out; + wire direct_interc_86_out; + wire direct_interc_87_out; + wire direct_interc_88_out; + wire direct_interc_89_out; + wire direct_interc_8_out; + wire direct_interc_90_out; + wire direct_interc_91_out; + wire direct_interc_92_out; + wire direct_interc_93_out; + wire direct_interc_94_out; + wire direct_interc_95_out; + wire direct_interc_96_out; + wire direct_interc_97_out; + wire direct_interc_98_out; + wire direct_interc_99_out; + wire direct_interc_9_out; + wire grid_clb_0_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_0_ccff_tail; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_10_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_10_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_10_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_10_ccff_tail; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_10_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_11_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_11_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_11_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_11_ccff_tail; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_11_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_12_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_12_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_12_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_12_ccff_tail; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_12_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_13_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_13_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_13_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_13_ccff_tail; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_13_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_14_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_14_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_14_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_14_ccff_tail; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_14_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_15_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_15_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_15_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_15_ccff_tail; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_15_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_15_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_16_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_16_ccff_tail; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_16_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_17_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_17_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_17_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_17_ccff_tail; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_17_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_18_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_18_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_18_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_18_ccff_tail; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_18_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_19_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_19_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_19_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_19_ccff_tail; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_19_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_sc_in_0_; + wire grid_clb_1_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_1_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_1_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_1_ccff_tail; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_1_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_1_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_20_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_20_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_20_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_20_ccff_tail; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_20_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_21_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_21_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_21_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_21_ccff_tail; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_21_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_22_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_22_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_22_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_22_ccff_tail; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_22_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_23_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_23_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_23_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_23_ccff_tail; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_23_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_23_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_24_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_24_ccff_tail; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_24_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_25_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_25_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_25_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_25_ccff_tail; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_25_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_26_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_26_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_26_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_26_ccff_tail; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_26_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_27_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_27_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_27_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_27_ccff_tail; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_27_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_28_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_28_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_28_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_28_ccff_tail; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_28_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_29_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_29_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_29_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_29_ccff_tail; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_29_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_2_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_2_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_2_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_2_ccff_tail; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_2_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_2_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_30_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_30_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_30_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_30_ccff_tail; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_30_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_31_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_31_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_31_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_31_ccff_tail; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_31_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_31_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_32_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_32_ccff_tail; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_32_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_33_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_33_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_33_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_33_ccff_tail; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_33_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_34_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_34_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_34_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_34_ccff_tail; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_34_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_35_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_35_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_35_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_35_ccff_tail; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_35_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_36_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_36_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_36_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_36_ccff_tail; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_36_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_37_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_37_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_37_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_37_ccff_tail; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_37_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_38_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_38_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_38_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_38_ccff_tail; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_38_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_39_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_39_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_39_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_39_ccff_tail; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_39_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_39_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_3_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_3_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_3_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_3_ccff_tail; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_3_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_3_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_40_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_40_ccff_tail; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_40_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_41_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_41_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_41_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_41_ccff_tail; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_41_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_42_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_42_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_42_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_42_ccff_tail; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_42_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_43_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_43_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_43_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_43_ccff_tail; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_43_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_44_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_44_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_44_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_44_ccff_tail; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_44_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_45_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_45_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_45_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_45_ccff_tail; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_45_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_46_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_46_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_46_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_46_ccff_tail; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_46_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_47_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_47_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_47_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_47_ccff_tail; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_47_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_47_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_48_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_48_ccff_tail; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_48_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_49_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_49_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_49_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_49_ccff_tail; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_49_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_4_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_4_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_4_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_4_ccff_tail; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_4_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_4_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_50_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_50_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_50_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_50_ccff_tail; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_50_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_51_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_51_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_51_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_51_ccff_tail; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_51_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_52_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_52_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_52_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_52_ccff_tail; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_52_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_53_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_53_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_53_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_53_ccff_tail; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_53_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_54_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_54_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_54_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_54_ccff_tail; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_54_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_55_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_55_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_55_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_55_ccff_tail; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_55_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_55_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_56_ccff_tail; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_56_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_57_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_57_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_57_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_57_ccff_tail; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_57_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_58_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_58_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_58_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_58_ccff_tail; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_58_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_59_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_59_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_59_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_59_ccff_tail; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_59_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_5_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_5_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_5_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_5_ccff_tail; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_5_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_5_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_60_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_60_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_60_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_60_ccff_tail; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_60_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_61_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_61_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_61_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_61_ccff_tail; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_61_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_62_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_62_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_62_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_62_ccff_tail; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_62_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_63_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_63_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_63_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_63_ccff_tail; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_63_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_63_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_6_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_6_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_6_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_6_ccff_tail; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_6_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_6_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_7_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_7_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_7_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_7_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_7_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; + wire grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire grid_clb_8_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_8_ccff_tail; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_8_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_clb_9_bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire grid_clb_9_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire grid_clb_9_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire grid_clb_9_ccff_tail; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_13_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_14_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_15_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_; + wire grid_clb_9_right_width_0_height_0_subtile_0__pin_O_9_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_3_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_4_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_; + wire grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_; + wire grid_io_bottom_bottom_0_ccff_tail; + wire grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_1_ccff_tail; + wire grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_1_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_2_ccff_tail; + wire grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_2_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_3_ccff_tail; + wire grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_3_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_4_ccff_tail; + wire grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_4_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_5_ccff_tail; + wire grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_5_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_6_ccff_tail; + wire grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_6_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_bottom_bottom_7_ccff_tail; + wire grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_bottom_bottom_7_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_0_ccff_tail; + wire grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_1_ccff_tail; + wire grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_1_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_2_ccff_tail; + wire grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_2_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_3_ccff_tail; + wire grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_3_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_4_ccff_tail; + wire grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_4_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_5_ccff_tail; + wire grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_5_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_6_ccff_tail; + wire grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_6_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_left_left_7_ccff_tail; + wire grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_left_left_7_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_0_ccff_tail; + wire grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_1_ccff_tail; + wire grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_1_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_2_ccff_tail; + wire grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_2_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_3_ccff_tail; + wire grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_3_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_4_ccff_tail; + wire grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_4_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_5_ccff_tail; + wire grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_5_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_6_ccff_tail; + wire grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_6_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_right_right_7_ccff_tail; + wire grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_right_right_7_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_0_ccff_tail; + wire grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_1_ccff_tail; + wire grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_2_ccff_tail; + wire grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_3_ccff_tail; + wire grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_4_ccff_tail; + wire grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_5_ccff_tail; + wire grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_6_ccff_tail; + wire grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire grid_io_top_top_7_ccff_tail; + wire sb_0__0__0_ccff_tail; + wire [0:29]sb_0__0__0_chanx_right_out; + wire [0:29]sb_0__0__0_chany_top_out; + wire sb_0__1__0_ccff_tail; + wire [0:29]sb_0__1__0_chanx_right_out; + wire [0:29]sb_0__1__0_chany_bottom_out; + wire [0:29]sb_0__1__0_chany_top_out; + wire sb_0__1__1_ccff_tail; + wire [0:29]sb_0__1__1_chanx_right_out; + wire [0:29]sb_0__1__1_chany_bottom_out; + wire [0:29]sb_0__1__1_chany_top_out; + wire sb_0__1__2_ccff_tail; + wire [0:29]sb_0__1__2_chanx_right_out; + wire [0:29]sb_0__1__2_chany_bottom_out; + wire [0:29]sb_0__1__2_chany_top_out; + wire sb_0__1__3_ccff_tail; + wire [0:29]sb_0__1__3_chanx_right_out; + wire [0:29]sb_0__1__3_chany_bottom_out; + wire [0:29]sb_0__1__3_chany_top_out; + wire sb_0__1__4_ccff_tail; + wire [0:29]sb_0__1__4_chanx_right_out; + wire [0:29]sb_0__1__4_chany_bottom_out; + wire [0:29]sb_0__1__4_chany_top_out; + wire sb_0__1__5_ccff_tail; + wire [0:29]sb_0__1__5_chanx_right_out; + wire [0:29]sb_0__1__5_chany_bottom_out; + wire [0:29]sb_0__1__5_chany_top_out; + wire sb_0__1__6_ccff_tail; + wire [0:29]sb_0__1__6_chanx_right_out; + wire [0:29]sb_0__1__6_chany_bottom_out; + wire [0:29]sb_0__1__6_chany_top_out; + wire sb_0__8__0_ccff_tail; + wire [0:29]sb_0__8__0_chanx_right_out; + wire [0:29]sb_0__8__0_chany_bottom_out; + wire sb_1__0__0_ccff_tail; + wire [0:29]sb_1__0__0_chanx_left_out; + wire [0:29]sb_1__0__0_chanx_right_out; + wire [0:29]sb_1__0__0_chany_top_out; + wire sb_1__0__1_ccff_tail; + wire [0:29]sb_1__0__1_chanx_left_out; + wire [0:29]sb_1__0__1_chanx_right_out; + wire [0:29]sb_1__0__1_chany_top_out; + wire sb_1__0__2_ccff_tail; + wire [0:29]sb_1__0__2_chanx_left_out; + wire [0:29]sb_1__0__2_chanx_right_out; + wire [0:29]sb_1__0__2_chany_top_out; + wire sb_1__0__3_ccff_tail; + wire [0:29]sb_1__0__3_chanx_left_out; + wire [0:29]sb_1__0__3_chanx_right_out; + wire [0:29]sb_1__0__3_chany_top_out; + wire sb_1__0__4_ccff_tail; + wire [0:29]sb_1__0__4_chanx_left_out; + wire [0:29]sb_1__0__4_chanx_right_out; + wire [0:29]sb_1__0__4_chany_top_out; + wire sb_1__0__5_ccff_tail; + wire [0:29]sb_1__0__5_chanx_left_out; + wire [0:29]sb_1__0__5_chanx_right_out; + wire [0:29]sb_1__0__5_chany_top_out; + wire sb_1__0__6_ccff_tail; + wire [0:29]sb_1__0__6_chanx_left_out; + wire [0:29]sb_1__0__6_chanx_right_out; + wire [0:29]sb_1__0__6_chany_top_out; + wire sb_1__1__0_ccff_tail; + wire [0:29]sb_1__1__0_chanx_left_out; + wire [0:29]sb_1__1__0_chanx_right_out; + wire [0:29]sb_1__1__0_chany_bottom_out; + wire [0:29]sb_1__1__0_chany_top_out; + wire sb_1__1__10_ccff_tail; + wire [0:29]sb_1__1__10_chanx_left_out; + wire [0:29]sb_1__1__10_chanx_right_out; + wire [0:29]sb_1__1__10_chany_bottom_out; + wire [0:29]sb_1__1__10_chany_top_out; + wire sb_1__1__11_ccff_tail; + wire [0:29]sb_1__1__11_chanx_left_out; + wire [0:29]sb_1__1__11_chanx_right_out; + wire [0:29]sb_1__1__11_chany_bottom_out; + wire [0:29]sb_1__1__11_chany_top_out; + wire sb_1__1__12_ccff_tail; + wire [0:29]sb_1__1__12_chanx_left_out; + wire [0:29]sb_1__1__12_chanx_right_out; + wire [0:29]sb_1__1__12_chany_bottom_out; + wire [0:29]sb_1__1__12_chany_top_out; + wire sb_1__1__13_ccff_tail; + wire [0:29]sb_1__1__13_chanx_left_out; + wire [0:29]sb_1__1__13_chanx_right_out; + wire [0:29]sb_1__1__13_chany_bottom_out; + wire [0:29]sb_1__1__13_chany_top_out; + wire sb_1__1__14_ccff_tail; + wire [0:29]sb_1__1__14_chanx_left_out; + wire [0:29]sb_1__1__14_chanx_right_out; + wire [0:29]sb_1__1__14_chany_bottom_out; + wire [0:29]sb_1__1__14_chany_top_out; + wire sb_1__1__15_ccff_tail; + wire [0:29]sb_1__1__15_chanx_left_out; + wire [0:29]sb_1__1__15_chanx_right_out; + wire [0:29]sb_1__1__15_chany_bottom_out; + wire [0:29]sb_1__1__15_chany_top_out; + wire sb_1__1__16_ccff_tail; + wire [0:29]sb_1__1__16_chanx_left_out; + wire [0:29]sb_1__1__16_chanx_right_out; + wire [0:29]sb_1__1__16_chany_bottom_out; + wire [0:29]sb_1__1__16_chany_top_out; + wire sb_1__1__17_ccff_tail; + wire [0:29]sb_1__1__17_chanx_left_out; + wire [0:29]sb_1__1__17_chanx_right_out; + wire [0:29]sb_1__1__17_chany_bottom_out; + wire [0:29]sb_1__1__17_chany_top_out; + wire sb_1__1__18_ccff_tail; + wire [0:29]sb_1__1__18_chanx_left_out; + wire [0:29]sb_1__1__18_chanx_right_out; + wire [0:29]sb_1__1__18_chany_bottom_out; + wire [0:29]sb_1__1__18_chany_top_out; + wire sb_1__1__19_ccff_tail; + wire [0:29]sb_1__1__19_chanx_left_out; + wire [0:29]sb_1__1__19_chanx_right_out; + wire [0:29]sb_1__1__19_chany_bottom_out; + wire [0:29]sb_1__1__19_chany_top_out; + wire sb_1__1__1_ccff_tail; + wire [0:29]sb_1__1__1_chanx_left_out; + wire [0:29]sb_1__1__1_chanx_right_out; + wire [0:29]sb_1__1__1_chany_bottom_out; + wire [0:29]sb_1__1__1_chany_top_out; + wire sb_1__1__20_ccff_tail; + wire [0:29]sb_1__1__20_chanx_left_out; + wire [0:29]sb_1__1__20_chanx_right_out; + wire [0:29]sb_1__1__20_chany_bottom_out; + wire [0:29]sb_1__1__20_chany_top_out; + wire sb_1__1__21_ccff_tail; + wire [0:29]sb_1__1__21_chanx_left_out; + wire [0:29]sb_1__1__21_chanx_right_out; + wire [0:29]sb_1__1__21_chany_bottom_out; + wire [0:29]sb_1__1__21_chany_top_out; + wire sb_1__1__22_ccff_tail; + wire [0:29]sb_1__1__22_chanx_left_out; + wire [0:29]sb_1__1__22_chanx_right_out; + wire [0:29]sb_1__1__22_chany_bottom_out; + wire [0:29]sb_1__1__22_chany_top_out; + wire sb_1__1__23_ccff_tail; + wire [0:29]sb_1__1__23_chanx_left_out; + wire [0:29]sb_1__1__23_chanx_right_out; + wire [0:29]sb_1__1__23_chany_bottom_out; + wire [0:29]sb_1__1__23_chany_top_out; + wire sb_1__1__24_ccff_tail; + wire [0:29]sb_1__1__24_chanx_left_out; + wire [0:29]sb_1__1__24_chanx_right_out; + wire [0:29]sb_1__1__24_chany_bottom_out; + wire [0:29]sb_1__1__24_chany_top_out; + wire sb_1__1__25_ccff_tail; + wire [0:29]sb_1__1__25_chanx_left_out; + wire [0:29]sb_1__1__25_chanx_right_out; + wire [0:29]sb_1__1__25_chany_bottom_out; + wire [0:29]sb_1__1__25_chany_top_out; + wire sb_1__1__26_ccff_tail; + wire [0:29]sb_1__1__26_chanx_left_out; + wire [0:29]sb_1__1__26_chanx_right_out; + wire [0:29]sb_1__1__26_chany_bottom_out; + wire [0:29]sb_1__1__26_chany_top_out; + wire sb_1__1__27_ccff_tail; + wire [0:29]sb_1__1__27_chanx_left_out; + wire [0:29]sb_1__1__27_chanx_right_out; + wire [0:29]sb_1__1__27_chany_bottom_out; + wire [0:29]sb_1__1__27_chany_top_out; + wire sb_1__1__28_ccff_tail; + wire [0:29]sb_1__1__28_chanx_left_out; + wire [0:29]sb_1__1__28_chanx_right_out; + wire [0:29]sb_1__1__28_chany_bottom_out; + wire [0:29]sb_1__1__28_chany_top_out; + wire sb_1__1__29_ccff_tail; + wire [0:29]sb_1__1__29_chanx_left_out; + wire [0:29]sb_1__1__29_chanx_right_out; + wire [0:29]sb_1__1__29_chany_bottom_out; + wire [0:29]sb_1__1__29_chany_top_out; + wire sb_1__1__2_ccff_tail; + wire [0:29]sb_1__1__2_chanx_left_out; + wire [0:29]sb_1__1__2_chanx_right_out; + wire [0:29]sb_1__1__2_chany_bottom_out; + wire [0:29]sb_1__1__2_chany_top_out; + wire sb_1__1__30_ccff_tail; + wire [0:29]sb_1__1__30_chanx_left_out; + wire [0:29]sb_1__1__30_chanx_right_out; + wire [0:29]sb_1__1__30_chany_bottom_out; + wire [0:29]sb_1__1__30_chany_top_out; + wire sb_1__1__31_ccff_tail; + wire [0:29]sb_1__1__31_chanx_left_out; + wire [0:29]sb_1__1__31_chanx_right_out; + wire [0:29]sb_1__1__31_chany_bottom_out; + wire [0:29]sb_1__1__31_chany_top_out; + wire sb_1__1__32_ccff_tail; + wire [0:29]sb_1__1__32_chanx_left_out; + wire [0:29]sb_1__1__32_chanx_right_out; + wire [0:29]sb_1__1__32_chany_bottom_out; + wire [0:29]sb_1__1__32_chany_top_out; + wire sb_1__1__33_ccff_tail; + wire [0:29]sb_1__1__33_chanx_left_out; + wire [0:29]sb_1__1__33_chanx_right_out; + wire [0:29]sb_1__1__33_chany_bottom_out; + wire [0:29]sb_1__1__33_chany_top_out; + wire sb_1__1__34_ccff_tail; + wire [0:29]sb_1__1__34_chanx_left_out; + wire [0:29]sb_1__1__34_chanx_right_out; + wire [0:29]sb_1__1__34_chany_bottom_out; + wire [0:29]sb_1__1__34_chany_top_out; + wire sb_1__1__35_ccff_tail; + wire [0:29]sb_1__1__35_chanx_left_out; + wire [0:29]sb_1__1__35_chanx_right_out; + wire [0:29]sb_1__1__35_chany_bottom_out; + wire [0:29]sb_1__1__35_chany_top_out; + wire sb_1__1__36_ccff_tail; + wire [0:29]sb_1__1__36_chanx_left_out; + wire [0:29]sb_1__1__36_chanx_right_out; + wire [0:29]sb_1__1__36_chany_bottom_out; + wire [0:29]sb_1__1__36_chany_top_out; + wire sb_1__1__37_ccff_tail; + wire [0:29]sb_1__1__37_chanx_left_out; + wire [0:29]sb_1__1__37_chanx_right_out; + wire [0:29]sb_1__1__37_chany_bottom_out; + wire [0:29]sb_1__1__37_chany_top_out; + wire sb_1__1__38_ccff_tail; + wire [0:29]sb_1__1__38_chanx_left_out; + wire [0:29]sb_1__1__38_chanx_right_out; + wire [0:29]sb_1__1__38_chany_bottom_out; + wire [0:29]sb_1__1__38_chany_top_out; + wire sb_1__1__39_ccff_tail; + wire [0:29]sb_1__1__39_chanx_left_out; + wire [0:29]sb_1__1__39_chanx_right_out; + wire [0:29]sb_1__1__39_chany_bottom_out; + wire [0:29]sb_1__1__39_chany_top_out; + wire sb_1__1__3_ccff_tail; + wire [0:29]sb_1__1__3_chanx_left_out; + wire [0:29]sb_1__1__3_chanx_right_out; + wire [0:29]sb_1__1__3_chany_bottom_out; + wire [0:29]sb_1__1__3_chany_top_out; + wire sb_1__1__40_ccff_tail; + wire [0:29]sb_1__1__40_chanx_left_out; + wire [0:29]sb_1__1__40_chanx_right_out; + wire [0:29]sb_1__1__40_chany_bottom_out; + wire [0:29]sb_1__1__40_chany_top_out; + wire sb_1__1__41_ccff_tail; + wire [0:29]sb_1__1__41_chanx_left_out; + wire [0:29]sb_1__1__41_chanx_right_out; + wire [0:29]sb_1__1__41_chany_bottom_out; + wire [0:29]sb_1__1__41_chany_top_out; + wire sb_1__1__42_ccff_tail; + wire [0:29]sb_1__1__42_chanx_left_out; + wire [0:29]sb_1__1__42_chanx_right_out; + wire [0:29]sb_1__1__42_chany_bottom_out; + wire [0:29]sb_1__1__42_chany_top_out; + wire sb_1__1__43_ccff_tail; + wire [0:29]sb_1__1__43_chanx_left_out; + wire [0:29]sb_1__1__43_chanx_right_out; + wire [0:29]sb_1__1__43_chany_bottom_out; + wire [0:29]sb_1__1__43_chany_top_out; + wire sb_1__1__44_ccff_tail; + wire [0:29]sb_1__1__44_chanx_left_out; + wire [0:29]sb_1__1__44_chanx_right_out; + wire [0:29]sb_1__1__44_chany_bottom_out; + wire [0:29]sb_1__1__44_chany_top_out; + wire sb_1__1__45_ccff_tail; + wire [0:29]sb_1__1__45_chanx_left_out; + wire [0:29]sb_1__1__45_chanx_right_out; + wire [0:29]sb_1__1__45_chany_bottom_out; + wire [0:29]sb_1__1__45_chany_top_out; + wire sb_1__1__46_ccff_tail; + wire [0:29]sb_1__1__46_chanx_left_out; + wire [0:29]sb_1__1__46_chanx_right_out; + wire [0:29]sb_1__1__46_chany_bottom_out; + wire [0:29]sb_1__1__46_chany_top_out; + wire sb_1__1__47_ccff_tail; + wire [0:29]sb_1__1__47_chanx_left_out; + wire [0:29]sb_1__1__47_chanx_right_out; + wire [0:29]sb_1__1__47_chany_bottom_out; + wire [0:29]sb_1__1__47_chany_top_out; + wire sb_1__1__48_ccff_tail; + wire [0:29]sb_1__1__48_chanx_left_out; + wire [0:29]sb_1__1__48_chanx_right_out; + wire [0:29]sb_1__1__48_chany_bottom_out; + wire [0:29]sb_1__1__48_chany_top_out; + wire sb_1__1__4_ccff_tail; + wire [0:29]sb_1__1__4_chanx_left_out; + wire [0:29]sb_1__1__4_chanx_right_out; + wire [0:29]sb_1__1__4_chany_bottom_out; + wire [0:29]sb_1__1__4_chany_top_out; + wire sb_1__1__5_ccff_tail; + wire [0:29]sb_1__1__5_chanx_left_out; + wire [0:29]sb_1__1__5_chanx_right_out; + wire [0:29]sb_1__1__5_chany_bottom_out; + wire [0:29]sb_1__1__5_chany_top_out; + wire sb_1__1__6_ccff_tail; + wire [0:29]sb_1__1__6_chanx_left_out; + wire [0:29]sb_1__1__6_chanx_right_out; + wire [0:29]sb_1__1__6_chany_bottom_out; + wire [0:29]sb_1__1__6_chany_top_out; + wire sb_1__1__7_ccff_tail; + wire [0:29]sb_1__1__7_chanx_left_out; + wire [0:29]sb_1__1__7_chanx_right_out; + wire [0:29]sb_1__1__7_chany_bottom_out; + wire [0:29]sb_1__1__7_chany_top_out; + wire sb_1__1__8_ccff_tail; + wire [0:29]sb_1__1__8_chanx_left_out; + wire [0:29]sb_1__1__8_chanx_right_out; + wire [0:29]sb_1__1__8_chany_bottom_out; + wire [0:29]sb_1__1__8_chany_top_out; + wire sb_1__1__9_ccff_tail; + wire [0:29]sb_1__1__9_chanx_left_out; + wire [0:29]sb_1__1__9_chanx_right_out; + wire [0:29]sb_1__1__9_chany_bottom_out; + wire [0:29]sb_1__1__9_chany_top_out; + wire sb_1__8__0_ccff_tail; + wire [0:29]sb_1__8__0_chanx_left_out; + wire [0:29]sb_1__8__0_chanx_right_out; + wire [0:29]sb_1__8__0_chany_bottom_out; + wire sb_1__8__1_ccff_tail; + wire [0:29]sb_1__8__1_chanx_left_out; + wire [0:29]sb_1__8__1_chanx_right_out; + wire [0:29]sb_1__8__1_chany_bottom_out; + wire sb_1__8__2_ccff_tail; + wire [0:29]sb_1__8__2_chanx_left_out; + wire [0:29]sb_1__8__2_chanx_right_out; + wire [0:29]sb_1__8__2_chany_bottom_out; + wire sb_1__8__3_ccff_tail; + wire [0:29]sb_1__8__3_chanx_left_out; + wire [0:29]sb_1__8__3_chanx_right_out; + wire [0:29]sb_1__8__3_chany_bottom_out; + wire sb_1__8__4_ccff_tail; + wire [0:29]sb_1__8__4_chanx_left_out; + wire [0:29]sb_1__8__4_chanx_right_out; + wire [0:29]sb_1__8__4_chany_bottom_out; + wire sb_1__8__5_ccff_tail; + wire [0:29]sb_1__8__5_chanx_left_out; + wire [0:29]sb_1__8__5_chanx_right_out; + wire [0:29]sb_1__8__5_chany_bottom_out; + wire sb_1__8__6_ccff_tail; + wire [0:29]sb_1__8__6_chanx_left_out; + wire [0:29]sb_1__8__6_chanx_right_out; + wire [0:29]sb_1__8__6_chany_bottom_out; + wire sb_8__0__0_ccff_tail; + wire [0:29]sb_8__0__0_chanx_left_out; + wire [0:29]sb_8__0__0_chany_top_out; + wire sb_8__1__0_ccff_tail; + wire [0:29]sb_8__1__0_chanx_left_out; + wire [0:29]sb_8__1__0_chany_bottom_out; + wire [0:29]sb_8__1__0_chany_top_out; + wire sb_8__1__1_ccff_tail; + wire [0:29]sb_8__1__1_chanx_left_out; + wire [0:29]sb_8__1__1_chany_bottom_out; + wire [0:29]sb_8__1__1_chany_top_out; + wire sb_8__1__2_ccff_tail; + wire [0:29]sb_8__1__2_chanx_left_out; + wire [0:29]sb_8__1__2_chany_bottom_out; + wire [0:29]sb_8__1__2_chany_top_out; + wire sb_8__1__3_ccff_tail; + wire [0:29]sb_8__1__3_chanx_left_out; + wire [0:29]sb_8__1__3_chany_bottom_out; + wire [0:29]sb_8__1__3_chany_top_out; + wire sb_8__1__4_ccff_tail; + wire [0:29]sb_8__1__4_chanx_left_out; + wire [0:29]sb_8__1__4_chany_bottom_out; + wire [0:29]sb_8__1__4_chany_top_out; + wire sb_8__1__5_ccff_tail; + wire [0:29]sb_8__1__5_chanx_left_out; + wire [0:29]sb_8__1__5_chany_bottom_out; + wire [0:29]sb_8__1__5_chany_top_out; + wire sb_8__1__6_ccff_tail; + wire [0:29]sb_8__1__6_chanx_left_out; + wire [0:29]sb_8__1__6_chany_bottom_out; + wire [0:29]sb_8__1__6_chany_top_out; + wire sb_8__8__0_ccff_tail; + wire [0:29]sb_8__8__0_chanx_left_out; + wire [0:29]sb_8__8__0_chany_bottom_out; + + grid_io_top_top grid_io_top_top_1__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:3]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__0_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_0_ccff_tail) + ); + grid_io_top_top grid_io_top_top_2__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4:7]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4:7]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4:7]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__1_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_1_ccff_tail) + ); + grid_io_top_top grid_io_top_top_3__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8:11]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8:11]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8:11]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__2_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_2_ccff_tail) + ); + grid_io_top_top grid_io_top_top_4__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12:15]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12:15]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12:15]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__3_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_3_ccff_tail) + ); + grid_io_top_top grid_io_top_top_5__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16:19]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16:19]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16:19]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__4_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_4_ccff_tail) + ); + grid_io_top_top grid_io_top_top_6__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20:23]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20:23]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20:23]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__5_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_5_ccff_tail) + ); + grid_io_top_top grid_io_top_top_7__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24:27]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24:27]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24:27]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__6_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_6_ccff_tail) + ); + grid_io_top_top grid_io_top_top_8__9_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28:31]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28:31]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28:31]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cbx_1__8__7_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_top_top_7_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__8_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32:35]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32:35]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32:35]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_1_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_0_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__7_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36:39]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36:39]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36:39]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_2_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_1_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__6_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40:43]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40:43]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40:43]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_3_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_2_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__5_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44:47]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44:47]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44:47]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_4_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_3_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__4_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48:51]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48:51]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48:51]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_5_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_4_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__3_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52:55]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52:55]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52:55]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_6_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_5_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__2_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56:59]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56:59]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56:59]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_right_right_7_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_6_ccff_tail) + ); + grid_io_right_right grid_io_right_right_9__1_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60:63]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60:63]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60:63]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_0_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_right_right_7_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_8__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64:67]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64:67]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64:67]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_1_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_0_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_7__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68:71]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68:71]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68:71]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_2_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_1_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_6__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72:75]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72:75]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72:75]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_3_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_2_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_5__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76:79]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76:79]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76:79]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_4_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_3_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_4__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80:83]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80:83]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80:83]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_5_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_4_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_3__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84:87]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84:87]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84:87]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_6_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_5_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_2__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88:91]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88:91]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88:91]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(grid_io_bottom_bottom_7_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_6_ccff_tail) + ); + grid_io_bottom_bottom grid_io_bottom_bottom_1__0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92:95]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92:95]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92:95]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(ccff_head), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_bottom_bottom_7_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__1_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96:99]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96:99]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96:99]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__0_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_0_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__2_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100:103]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100:103]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100:103]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__1_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_1_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__3_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104:107]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104:107]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104:107]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__2_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_2_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__4_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108:111]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108:111]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108:111]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__3_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_3_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__5_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112:115]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112:115]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112:115]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__4_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_4_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__6_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116:119]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116:119]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116:119]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__5_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_5_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__7_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120:123]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120:123]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120:123]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__6_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_6_ccff_tail) + ); + grid_io_left_left grid_io_left_left_0__8_ + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124:127]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124:127]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124:127]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(cby_0__1__7_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(grid_io_left_left_7_ccff_tail) + ); + grid_clb grid_clb_1__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_56_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_112_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_0_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__0_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_0_ccff_tail) + ); + grid_clb grid_clb_1__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_57_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_113_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_1_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__1_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_1_ccff_tail) + ); + grid_clb grid_clb_1__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_58_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_114_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_2_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__2_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_2_ccff_tail) + ); + grid_clb grid_clb_1__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_59_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_115_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_3_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__3_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_3_ccff_tail) + ); + grid_clb grid_clb_1__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_60_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_116_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_4_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__4_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_4_ccff_tail) + ); + grid_clb grid_clb_1__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_61_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_117_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_5_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__5_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_5_ccff_tail) + ); + grid_clb grid_clb_1__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_62_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_118_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_6_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__6_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_6_ccff_tail) + ); + grid_clb grid_clb_1__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_sc_in_0_), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__7_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(ccff_tail) + ); + grid_clb grid_clb_2__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_63_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_119_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_7_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__8_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_8_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_2__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_8_ccff_tail) + ); + grid_clb grid_clb_2__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_64_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_120_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_8_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__9_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_9_ccff_tail) + ); + grid_clb grid_clb_2__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_65_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_121_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_9_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__10_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_10_ccff_tail) + ); + grid_clb grid_clb_2__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_66_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_122_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_10_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__11_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_11_ccff_tail) + ); + grid_clb grid_clb_2__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_67_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_123_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_11_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__12_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_12_ccff_tail) + ); + grid_clb grid_clb_2__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_68_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_124_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_12_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__13_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_13_ccff_tail) + ); + grid_clb grid_clb_2__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_69_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_125_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_13_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__14_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_14_ccff_tail) + ); + grid_clb grid_clb_2__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_168_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__15_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_15_ccff_tail) + ); + grid_clb grid_clb_3__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_70_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_126_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_14_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__16_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_16_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_3__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_16_ccff_tail) + ); + grid_clb grid_clb_3__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_71_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_127_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_15_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__17_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_17_ccff_tail) + ); + grid_clb grid_clb_3__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_72_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_128_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_16_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__18_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_18_ccff_tail) + ); + grid_clb grid_clb_3__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_73_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_129_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_17_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__19_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_19_ccff_tail) + ); + grid_clb grid_clb_3__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_74_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_130_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_18_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__20_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_20_ccff_tail) + ); + grid_clb grid_clb_3__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_75_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_131_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_19_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__21_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_21_ccff_tail) + ); + grid_clb grid_clb_3__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_76_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_132_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_20_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__22_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_22_ccff_tail) + ); + grid_clb grid_clb_3__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_169_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__23_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_23_ccff_tail) + ); + grid_clb grid_clb_4__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_77_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_133_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_21_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__24_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_24_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_4__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_24_ccff_tail) + ); + grid_clb grid_clb_4__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_78_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_134_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_22_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__25_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_25_ccff_tail) + ); + grid_clb grid_clb_4__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_79_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_135_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_23_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__26_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_26_ccff_tail) + ); + grid_clb grid_clb_4__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_80_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_136_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_24_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__27_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_27_ccff_tail) + ); + grid_clb grid_clb_4__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_81_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_137_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_25_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__28_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_28_ccff_tail) + ); + grid_clb grid_clb_4__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_82_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_138_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_26_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__29_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_29_ccff_tail) + ); + grid_clb grid_clb_4__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_83_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_139_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_27_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__30_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_30_ccff_tail) + ); + grid_clb grid_clb_4__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_170_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__31_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_31_ccff_tail) + ); + grid_clb grid_clb_5__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_84_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_140_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_28_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__32_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_32_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_5__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_32_ccff_tail) + ); + grid_clb grid_clb_5__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_85_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_141_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_29_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__33_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_33_ccff_tail) + ); + grid_clb grid_clb_5__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_86_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_142_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_30_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__34_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_34_ccff_tail) + ); + grid_clb grid_clb_5__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_87_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_143_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_31_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__35_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_35_ccff_tail) + ); + grid_clb grid_clb_5__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_88_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_144_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_32_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__36_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_36_ccff_tail) + ); + grid_clb grid_clb_5__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_89_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_145_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_33_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__37_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_37_ccff_tail) + ); + grid_clb grid_clb_5__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_90_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_146_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_34_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__38_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_38_ccff_tail) + ); + grid_clb grid_clb_5__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_171_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__39_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_39_ccff_tail) + ); + grid_clb grid_clb_6__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_91_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_147_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_35_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__40_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_40_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_6__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_40_ccff_tail) + ); + grid_clb grid_clb_6__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_92_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_148_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_36_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__41_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_41_ccff_tail) + ); + grid_clb grid_clb_6__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_93_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_149_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_37_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__42_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_42_ccff_tail) + ); + grid_clb grid_clb_6__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_94_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_150_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_38_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__43_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_43_ccff_tail) + ); + grid_clb grid_clb_6__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_95_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_151_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_39_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__44_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_44_ccff_tail) + ); + grid_clb grid_clb_6__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_96_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_152_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_40_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__45_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_45_ccff_tail) + ); + grid_clb grid_clb_6__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_97_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_153_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_41_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__46_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_46_ccff_tail) + ); + grid_clb grid_clb_6__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_172_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__47_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_47_ccff_tail) + ); + grid_clb grid_clb_7__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_98_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_154_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_42_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__48_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_48_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_7__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_48_ccff_tail) + ); + grid_clb grid_clb_7__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_99_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_155_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_43_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__49_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_49_ccff_tail) + ); + grid_clb grid_clb_7__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_100_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_156_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_44_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__50_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_50_ccff_tail) + ); + grid_clb grid_clb_7__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_101_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_157_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_45_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__51_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_51_ccff_tail) + ); + grid_clb grid_clb_7__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_102_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_158_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_46_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__52_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_52_ccff_tail) + ); + grid_clb grid_clb_7__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_103_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_159_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_47_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__53_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_53_ccff_tail) + ); + grid_clb grid_clb_7__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_104_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_160_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_48_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__54_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_54_ccff_tail) + ); + grid_clb grid_clb_7__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_173_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_1__1__55_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_55_ccff_tail) + ); + grid_clb grid_clb_8__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_105_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_161_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_49_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__0_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_8__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_56_ccff_tail) + ); + grid_clb grid_clb_8__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_106_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_162_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_50_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__1_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_57_ccff_tail) + ); + grid_clb grid_clb_8__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_107_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_163_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_51_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__2_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_58_ccff_tail) + ); + grid_clb grid_clb_8__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_108_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_164_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_52_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__3_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_59_ccff_tail) + ); + grid_clb grid_clb_8__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_109_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_165_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_53_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__4_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_60_ccff_tail) + ); + grid_clb grid_clb_8__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_110_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_166_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_54_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__5_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_61_ccff_tail) + ); + grid_clb grid_clb_8__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(direct_interc_111_out), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_167_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(direct_interc_55_out), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__6_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_62_ccff_tail) + ); + grid_clb grid_clb_8__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), + .top_width_0_height_0_subtile_0__pin_sc_in_0_(direct_interc_174_out), + .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), + .right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), + .left_width_0_height_0_subtile_0__pin_clk_0_(clk), + .ccff_head(cby_8__1__7_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_), + .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_), + .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_3_), + .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_4_), + .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_5_), + .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_6_), + .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_7_), + .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_), + .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_9_), + .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_), + .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_), + .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_), + .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_13_), + .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_14_), + .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_15_), + .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(grid_clb_63_ccff_tail) + ); + sb_0__0_ sb_0__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__0_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__0__0_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_1_ccff_tail), + .chany_top_out(sb_0__0__0_chany_top_out), + .chanx_right_out(sb_0__0__0_chanx_right_out), + .ccff_tail(sb_0__0__0_ccff_tail) + ); + sb_0__1_ sb_0__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__1_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__0_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__0_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_2_ccff_tail), + .chany_top_out(sb_0__1__0_chany_top_out), + .chanx_right_out(sb_0__1__0_chanx_right_out), + .chany_bottom_out(sb_0__1__0_chany_bottom_out), + .ccff_tail(sb_0__1__0_ccff_tail) + ); + sb_0__1_ sb_0__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__2_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__1_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__1_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_3_ccff_tail), + .chany_top_out(sb_0__1__1_chany_top_out), + .chanx_right_out(sb_0__1__1_chanx_right_out), + .chany_bottom_out(sb_0__1__1_chany_bottom_out), + .ccff_tail(sb_0__1__1_ccff_tail) + ); + sb_0__1_ sb_0__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__3_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__2_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__2_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_4_ccff_tail), + .chany_top_out(sb_0__1__2_chany_top_out), + .chanx_right_out(sb_0__1__2_chanx_right_out), + .chany_bottom_out(sb_0__1__2_chany_bottom_out), + .ccff_tail(sb_0__1__2_ccff_tail) + ); + sb_0__1_ sb_0__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__4_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__3_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__3_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_5_ccff_tail), + .chany_top_out(sb_0__1__3_chany_top_out), + .chanx_right_out(sb_0__1__3_chanx_right_out), + .chany_bottom_out(sb_0__1__3_chany_bottom_out), + .ccff_tail(sb_0__1__3_ccff_tail) + ); + sb_0__1_ sb_0__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__5_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__4_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__4_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_6_ccff_tail), + .chany_top_out(sb_0__1__4_chany_top_out), + .chanx_right_out(sb_0__1__4_chanx_right_out), + .chany_bottom_out(sb_0__1__4_chany_bottom_out), + .ccff_tail(sb_0__1__4_ccff_tail) + ); + sb_0__1_ sb_0__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__6_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__5_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__5_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_7_ccff_tail), + .chany_top_out(sb_0__1__5_chany_top_out), + .chanx_right_out(sb_0__1__5_chanx_right_out), + .chany_bottom_out(sb_0__1__5_chany_bottom_out), + .ccff_tail(sb_0__1__5_ccff_tail) + ); + sb_0__1_ sb_0__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__7_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_right_in(cbx_1__1__6_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__6_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(sb_0__8__0_ccff_tail), + .chany_top_out(sb_0__1__6_chany_top_out), + .chanx_right_out(sb_0__1__6_chanx_right_out), + .chany_bottom_out(sb_0__1__6_chany_bottom_out), + .ccff_tail(sb_0__1__6_ccff_tail) + ); + sb_0__8_ sb_0__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__0_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_0__1__7_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_top_top_0_ccff_tail), + .chanx_right_out(sb_0__8__0_chanx_right_out), + .chany_bottom_out(sb_0__8__0_chany_bottom_out), + .ccff_tail(sb_0__8__0_ccff_tail) + ); + sb_1__0_ sb_1__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__0_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__1_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__0_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_io_left_left_0_ccff_tail), + .chany_top_out(sb_1__0__0_chany_top_out), + .chanx_right_out(sb_1__0__0_chanx_right_out), + .chanx_left_out(sb_1__0__0_chanx_left_out), + .ccff_tail(sb_1__0__0_ccff_tail) + ); + sb_1__0_ sb_2__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__8_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__2_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__1_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_0_ccff_tail), + .chany_top_out(sb_1__0__1_chany_top_out), + .chanx_right_out(sb_1__0__1_chanx_right_out), + .chanx_left_out(sb_1__0__1_chanx_left_out), + .ccff_tail(sb_1__0__1_ccff_tail) + ); + sb_1__0_ sb_3__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__16_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__3_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__2_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_8_ccff_tail), + .chany_top_out(sb_1__0__2_chany_top_out), + .chanx_right_out(sb_1__0__2_chanx_right_out), + .chanx_left_out(sb_1__0__2_chanx_left_out), + .ccff_tail(sb_1__0__2_ccff_tail) + ); + sb_1__0_ sb_4__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__24_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__4_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__3_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_16_ccff_tail), + .chany_top_out(sb_1__0__3_chany_top_out), + .chanx_right_out(sb_1__0__3_chanx_right_out), + .chanx_left_out(sb_1__0__3_chanx_left_out), + .ccff_tail(sb_1__0__3_ccff_tail) + ); + sb_1__0_ sb_5__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__32_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__5_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__4_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_24_ccff_tail), + .chany_top_out(sb_1__0__4_chany_top_out), + .chanx_right_out(sb_1__0__4_chanx_right_out), + .chanx_left_out(sb_1__0__4_chanx_left_out), + .ccff_tail(sb_1__0__4_ccff_tail) + ); + sb_1__0_ sb_6__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__40_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__6_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__5_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_32_ccff_tail), + .chany_top_out(sb_1__0__5_chany_top_out), + .chanx_right_out(sb_1__0__5_chanx_right_out), + .chanx_left_out(sb_1__0__5_chanx_left_out), + .ccff_tail(sb_1__0__5_ccff_tail) + ); + sb_1__0_ sb_7__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__48_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__0__7_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__6_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_40_ccff_tail), + .chany_top_out(sb_1__0__6_chany_top_out), + .chanx_right_out(sb_1__0__6_chanx_right_out), + .chanx_left_out(sb_1__0__6_chanx_left_out), + .ccff_tail(sb_1__0__6_ccff_tail) + ); + sb_1__1_ sb_1__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__1_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__7_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__0_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__0_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_9_ccff_tail), + .chany_top_out(sb_1__1__0_chany_top_out), + .chanx_right_out(sb_1__1__0_chanx_right_out), + .chany_bottom_out(sb_1__1__0_chany_bottom_out), + .chanx_left_out(sb_1__1__0_chanx_left_out), + .ccff_tail(sb_1__1__0_ccff_tail) + ); + sb_1__1_ sb_1__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__2_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__8_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__1_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__1_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_1_ccff_tail), + .chany_top_out(sb_1__1__1_chany_top_out), + .chanx_right_out(sb_1__1__1_chanx_right_out), + .chany_bottom_out(sb_1__1__1_chany_bottom_out), + .chanx_left_out(sb_1__1__1_chanx_left_out), + .ccff_tail(sb_1__1__1_ccff_tail) + ); + sb_1__1_ sb_1__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__3_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__9_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__2_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__2_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_11_ccff_tail), + .chany_top_out(sb_1__1__2_chany_top_out), + .chanx_right_out(sb_1__1__2_chanx_right_out), + .chany_bottom_out(sb_1__1__2_chany_bottom_out), + .chanx_left_out(sb_1__1__2_chanx_left_out), + .ccff_tail(sb_1__1__2_ccff_tail) + ); + sb_1__1_ sb_1__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__4_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__10_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__3_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__3_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_3_ccff_tail), + .chany_top_out(sb_1__1__3_chany_top_out), + .chanx_right_out(sb_1__1__3_chanx_right_out), + .chany_bottom_out(sb_1__1__3_chany_bottom_out), + .chanx_left_out(sb_1__1__3_chanx_left_out), + .ccff_tail(sb_1__1__3_ccff_tail) + ); + sb_1__1_ sb_1__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__5_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__11_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__4_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__4_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_13_ccff_tail), + .chany_top_out(sb_1__1__4_chany_top_out), + .chanx_right_out(sb_1__1__4_chanx_right_out), + .chany_bottom_out(sb_1__1__4_chany_bottom_out), + .chanx_left_out(sb_1__1__4_chanx_left_out), + .ccff_tail(sb_1__1__4_ccff_tail) + ); + sb_1__1_ sb_1__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__6_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__12_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__5_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__5_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_5_ccff_tail), + .chany_top_out(sb_1__1__5_chany_top_out), + .chanx_right_out(sb_1__1__5_chanx_right_out), + .chany_bottom_out(sb_1__1__5_chany_bottom_out), + .chanx_left_out(sb_1__1__5_chanx_left_out), + .ccff_tail(sb_1__1__5_ccff_tail) + ); + sb_1__1_ sb_1__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__7_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__13_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__6_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__6_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_15_ccff_tail), + .chany_top_out(sb_1__1__6_chany_top_out), + .chanx_right_out(sb_1__1__6_chanx_right_out), + .chany_bottom_out(sb_1__1__6_chany_bottom_out), + .chanx_left_out(sb_1__1__6_chanx_left_out), + .ccff_tail(sb_1__1__6_ccff_tail) + ); + sb_1__1_ sb_2__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__9_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__14_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__8_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__7_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_17_ccff_tail), + .chany_top_out(sb_1__1__7_chany_top_out), + .chanx_right_out(sb_1__1__7_chanx_right_out), + .chany_bottom_out(sb_1__1__7_chany_bottom_out), + .chanx_left_out(sb_1__1__7_chanx_left_out), + .ccff_tail(sb_1__1__7_ccff_tail) + ); + sb_1__1_ sb_2__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__10_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__15_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__9_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__8_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_2_ccff_tail), + .chany_top_out(sb_1__1__8_chany_top_out), + .chanx_right_out(sb_1__1__8_chanx_right_out), + .chany_bottom_out(sb_1__1__8_chany_bottom_out), + .chanx_left_out(sb_1__1__8_chanx_left_out), + .ccff_tail(sb_1__1__8_ccff_tail) + ); + sb_1__1_ sb_2__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__11_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__16_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__10_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__9_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_19_ccff_tail), + .chany_top_out(sb_1__1__9_chany_top_out), + .chanx_right_out(sb_1__1__9_chanx_right_out), + .chany_bottom_out(sb_1__1__9_chany_bottom_out), + .chanx_left_out(sb_1__1__9_chanx_left_out), + .ccff_tail(sb_1__1__9_ccff_tail) + ); + sb_1__1_ sb_2__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__12_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__17_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__11_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__10_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_4_ccff_tail), + .chany_top_out(sb_1__1__10_chany_top_out), + .chanx_right_out(sb_1__1__10_chanx_right_out), + .chany_bottom_out(sb_1__1__10_chany_bottom_out), + .chanx_left_out(sb_1__1__10_chanx_left_out), + .ccff_tail(sb_1__1__10_ccff_tail) + ); + sb_1__1_ sb_2__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__13_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__18_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__12_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__11_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_21_ccff_tail), + .chany_top_out(sb_1__1__11_chany_top_out), + .chanx_right_out(sb_1__1__11_chanx_right_out), + .chany_bottom_out(sb_1__1__11_chany_bottom_out), + .chanx_left_out(sb_1__1__11_chanx_left_out), + .ccff_tail(sb_1__1__11_ccff_tail) + ); + sb_1__1_ sb_2__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__14_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__19_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__13_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__12_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_6_ccff_tail), + .chany_top_out(sb_1__1__12_chany_top_out), + .chanx_right_out(sb_1__1__12_chanx_right_out), + .chany_bottom_out(sb_1__1__12_chany_bottom_out), + .chanx_left_out(sb_1__1__12_chanx_left_out), + .ccff_tail(sb_1__1__12_ccff_tail) + ); + sb_1__1_ sb_2__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__15_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__20_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__14_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__13_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_23_ccff_tail), + .chany_top_out(sb_1__1__13_chany_top_out), + .chanx_right_out(sb_1__1__13_chanx_right_out), + .chany_bottom_out(sb_1__1__13_chany_bottom_out), + .chanx_left_out(sb_1__1__13_chanx_left_out), + .ccff_tail(sb_1__1__13_ccff_tail) + ); + sb_1__1_ sb_3__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__17_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__21_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__16_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__14_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_25_ccff_tail), + .chany_top_out(sb_1__1__14_chany_top_out), + .chanx_right_out(sb_1__1__14_chanx_right_out), + .chany_bottom_out(sb_1__1__14_chany_bottom_out), + .chanx_left_out(sb_1__1__14_chanx_left_out), + .ccff_tail(sb_1__1__14_ccff_tail) + ); + sb_1__1_ sb_3__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__18_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__22_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__17_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__15_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_10_ccff_tail), + .chany_top_out(sb_1__1__15_chany_top_out), + .chanx_right_out(sb_1__1__15_chanx_right_out), + .chany_bottom_out(sb_1__1__15_chany_bottom_out), + .chanx_left_out(sb_1__1__15_chanx_left_out), + .ccff_tail(sb_1__1__15_ccff_tail) + ); + sb_1__1_ sb_3__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__19_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__23_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__18_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__16_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_27_ccff_tail), + .chany_top_out(sb_1__1__16_chany_top_out), + .chanx_right_out(sb_1__1__16_chanx_right_out), + .chany_bottom_out(sb_1__1__16_chany_bottom_out), + .chanx_left_out(sb_1__1__16_chanx_left_out), + .ccff_tail(sb_1__1__16_ccff_tail) + ); + sb_1__1_ sb_3__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__20_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__24_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__19_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__17_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_12_ccff_tail), + .chany_top_out(sb_1__1__17_chany_top_out), + .chanx_right_out(sb_1__1__17_chanx_right_out), + .chany_bottom_out(sb_1__1__17_chany_bottom_out), + .chanx_left_out(sb_1__1__17_chanx_left_out), + .ccff_tail(sb_1__1__17_ccff_tail) + ); + sb_1__1_ sb_3__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__21_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__25_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__20_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__18_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_29_ccff_tail), + .chany_top_out(sb_1__1__18_chany_top_out), + .chanx_right_out(sb_1__1__18_chanx_right_out), + .chany_bottom_out(sb_1__1__18_chany_bottom_out), + .chanx_left_out(sb_1__1__18_chanx_left_out), + .ccff_tail(sb_1__1__18_ccff_tail) + ); + sb_1__1_ sb_3__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__22_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__26_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__21_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__19_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_14_ccff_tail), + .chany_top_out(sb_1__1__19_chany_top_out), + .chanx_right_out(sb_1__1__19_chanx_right_out), + .chany_bottom_out(sb_1__1__19_chany_bottom_out), + .chanx_left_out(sb_1__1__19_chanx_left_out), + .ccff_tail(sb_1__1__19_ccff_tail) + ); + sb_1__1_ sb_3__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__23_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__27_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__22_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__20_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_31_ccff_tail), + .chany_top_out(sb_1__1__20_chany_top_out), + .chanx_right_out(sb_1__1__20_chanx_right_out), + .chany_bottom_out(sb_1__1__20_chany_bottom_out), + .chanx_left_out(sb_1__1__20_chanx_left_out), + .ccff_tail(sb_1__1__20_ccff_tail) + ); + sb_1__1_ sb_4__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__25_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__28_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__24_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__21_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_33_ccff_tail), + .chany_top_out(sb_1__1__21_chany_top_out), + .chanx_right_out(sb_1__1__21_chanx_right_out), + .chany_bottom_out(sb_1__1__21_chany_bottom_out), + .chanx_left_out(sb_1__1__21_chanx_left_out), + .ccff_tail(sb_1__1__21_ccff_tail) + ); + sb_1__1_ sb_4__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__26_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__29_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__25_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__22_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_18_ccff_tail), + .chany_top_out(sb_1__1__22_chany_top_out), + .chanx_right_out(sb_1__1__22_chanx_right_out), + .chany_bottom_out(sb_1__1__22_chany_bottom_out), + .chanx_left_out(sb_1__1__22_chanx_left_out), + .ccff_tail(sb_1__1__22_ccff_tail) + ); + sb_1__1_ sb_4__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__27_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__30_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__26_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__23_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_35_ccff_tail), + .chany_top_out(sb_1__1__23_chany_top_out), + .chanx_right_out(sb_1__1__23_chanx_right_out), + .chany_bottom_out(sb_1__1__23_chany_bottom_out), + .chanx_left_out(sb_1__1__23_chanx_left_out), + .ccff_tail(sb_1__1__23_ccff_tail) + ); + sb_1__1_ sb_4__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__28_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__31_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__27_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__24_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_20_ccff_tail), + .chany_top_out(sb_1__1__24_chany_top_out), + .chanx_right_out(sb_1__1__24_chanx_right_out), + .chany_bottom_out(sb_1__1__24_chany_bottom_out), + .chanx_left_out(sb_1__1__24_chanx_left_out), + .ccff_tail(sb_1__1__24_ccff_tail) + ); + sb_1__1_ sb_4__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__29_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__32_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__28_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__25_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_37_ccff_tail), + .chany_top_out(sb_1__1__25_chany_top_out), + .chanx_right_out(sb_1__1__25_chanx_right_out), + .chany_bottom_out(sb_1__1__25_chany_bottom_out), + .chanx_left_out(sb_1__1__25_chanx_left_out), + .ccff_tail(sb_1__1__25_ccff_tail) + ); + sb_1__1_ sb_4__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__30_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__33_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__29_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__26_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_22_ccff_tail), + .chany_top_out(sb_1__1__26_chany_top_out), + .chanx_right_out(sb_1__1__26_chanx_right_out), + .chany_bottom_out(sb_1__1__26_chany_bottom_out), + .chanx_left_out(sb_1__1__26_chanx_left_out), + .ccff_tail(sb_1__1__26_ccff_tail) + ); + sb_1__1_ sb_4__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__31_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__34_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__30_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__27_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_39_ccff_tail), + .chany_top_out(sb_1__1__27_chany_top_out), + .chanx_right_out(sb_1__1__27_chanx_right_out), + .chany_bottom_out(sb_1__1__27_chany_bottom_out), + .chanx_left_out(sb_1__1__27_chanx_left_out), + .ccff_tail(sb_1__1__27_ccff_tail) + ); + sb_1__1_ sb_5__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__33_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__35_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__32_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__28_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_41_ccff_tail), + .chany_top_out(sb_1__1__28_chany_top_out), + .chanx_right_out(sb_1__1__28_chanx_right_out), + .chany_bottom_out(sb_1__1__28_chany_bottom_out), + .chanx_left_out(sb_1__1__28_chanx_left_out), + .ccff_tail(sb_1__1__28_ccff_tail) + ); + sb_1__1_ sb_5__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__34_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__36_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__33_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__29_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_26_ccff_tail), + .chany_top_out(sb_1__1__29_chany_top_out), + .chanx_right_out(sb_1__1__29_chanx_right_out), + .chany_bottom_out(sb_1__1__29_chany_bottom_out), + .chanx_left_out(sb_1__1__29_chanx_left_out), + .ccff_tail(sb_1__1__29_ccff_tail) + ); + sb_1__1_ sb_5__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__35_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__37_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__34_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__30_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_43_ccff_tail), + .chany_top_out(sb_1__1__30_chany_top_out), + .chanx_right_out(sb_1__1__30_chanx_right_out), + .chany_bottom_out(sb_1__1__30_chany_bottom_out), + .chanx_left_out(sb_1__1__30_chanx_left_out), + .ccff_tail(sb_1__1__30_ccff_tail) + ); + sb_1__1_ sb_5__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__36_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__38_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__35_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__31_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_28_ccff_tail), + .chany_top_out(sb_1__1__31_chany_top_out), + .chanx_right_out(sb_1__1__31_chanx_right_out), + .chany_bottom_out(sb_1__1__31_chany_bottom_out), + .chanx_left_out(sb_1__1__31_chanx_left_out), + .ccff_tail(sb_1__1__31_ccff_tail) + ); + sb_1__1_ sb_5__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__37_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__39_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__36_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__32_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_45_ccff_tail), + .chany_top_out(sb_1__1__32_chany_top_out), + .chanx_right_out(sb_1__1__32_chanx_right_out), + .chany_bottom_out(sb_1__1__32_chany_bottom_out), + .chanx_left_out(sb_1__1__32_chanx_left_out), + .ccff_tail(sb_1__1__32_ccff_tail) + ); + sb_1__1_ sb_5__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__38_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__40_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__37_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__33_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_30_ccff_tail), + .chany_top_out(sb_1__1__33_chany_top_out), + .chanx_right_out(sb_1__1__33_chanx_right_out), + .chany_bottom_out(sb_1__1__33_chany_bottom_out), + .chanx_left_out(sb_1__1__33_chanx_left_out), + .ccff_tail(sb_1__1__33_ccff_tail) + ); + sb_1__1_ sb_5__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__39_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__41_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__38_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__34_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_47_ccff_tail), + .chany_top_out(sb_1__1__34_chany_top_out), + .chanx_right_out(sb_1__1__34_chanx_right_out), + .chany_bottom_out(sb_1__1__34_chany_bottom_out), + .chanx_left_out(sb_1__1__34_chanx_left_out), + .ccff_tail(sb_1__1__34_ccff_tail) + ); + sb_1__1_ sb_6__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__41_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__42_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__40_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__35_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_49_ccff_tail), + .chany_top_out(sb_1__1__35_chany_top_out), + .chanx_right_out(sb_1__1__35_chanx_right_out), + .chany_bottom_out(sb_1__1__35_chany_bottom_out), + .chanx_left_out(sb_1__1__35_chanx_left_out), + .ccff_tail(sb_1__1__35_ccff_tail) + ); + sb_1__1_ sb_6__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__42_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__43_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__41_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__36_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_34_ccff_tail), + .chany_top_out(sb_1__1__36_chany_top_out), + .chanx_right_out(sb_1__1__36_chanx_right_out), + .chany_bottom_out(sb_1__1__36_chany_bottom_out), + .chanx_left_out(sb_1__1__36_chanx_left_out), + .ccff_tail(sb_1__1__36_ccff_tail) + ); + sb_1__1_ sb_6__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__43_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__44_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__42_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__37_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_51_ccff_tail), + .chany_top_out(sb_1__1__37_chany_top_out), + .chanx_right_out(sb_1__1__37_chanx_right_out), + .chany_bottom_out(sb_1__1__37_chany_bottom_out), + .chanx_left_out(sb_1__1__37_chanx_left_out), + .ccff_tail(sb_1__1__37_ccff_tail) + ); + sb_1__1_ sb_6__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__44_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__45_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__43_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__38_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_36_ccff_tail), + .chany_top_out(sb_1__1__38_chany_top_out), + .chanx_right_out(sb_1__1__38_chanx_right_out), + .chany_bottom_out(sb_1__1__38_chany_bottom_out), + .chanx_left_out(sb_1__1__38_chanx_left_out), + .ccff_tail(sb_1__1__38_ccff_tail) + ); + sb_1__1_ sb_6__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__45_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__46_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__44_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__39_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_53_ccff_tail), + .chany_top_out(sb_1__1__39_chany_top_out), + .chanx_right_out(sb_1__1__39_chanx_right_out), + .chany_bottom_out(sb_1__1__39_chany_bottom_out), + .chanx_left_out(sb_1__1__39_chanx_left_out), + .ccff_tail(sb_1__1__39_ccff_tail) + ); + sb_1__1_ sb_6__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__46_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__47_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__45_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__40_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_38_ccff_tail), + .chany_top_out(sb_1__1__40_chany_top_out), + .chanx_right_out(sb_1__1__40_chanx_right_out), + .chany_bottom_out(sb_1__1__40_chany_bottom_out), + .chanx_left_out(sb_1__1__40_chanx_left_out), + .ccff_tail(sb_1__1__40_ccff_tail) + ); + sb_1__1_ sb_6__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__47_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__48_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__46_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__41_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_55_ccff_tail), + .chany_top_out(sb_1__1__41_chany_top_out), + .chanx_right_out(sb_1__1__41_chanx_right_out), + .chany_bottom_out(sb_1__1__41_chany_bottom_out), + .chanx_left_out(sb_1__1__41_chanx_left_out), + .ccff_tail(sb_1__1__41_ccff_tail) + ); + sb_1__1_ sb_7__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__49_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__49_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__48_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__42_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_57_ccff_tail), + .chany_top_out(sb_1__1__42_chany_top_out), + .chanx_right_out(sb_1__1__42_chanx_right_out), + .chany_bottom_out(sb_1__1__42_chany_bottom_out), + .chanx_left_out(sb_1__1__42_chanx_left_out), + .ccff_tail(sb_1__1__42_ccff_tail) + ); + sb_1__1_ sb_7__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__50_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__50_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__49_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__43_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_42_ccff_tail), + .chany_top_out(sb_1__1__43_chany_top_out), + .chanx_right_out(sb_1__1__43_chanx_right_out), + .chany_bottom_out(sb_1__1__43_chany_bottom_out), + .chanx_left_out(sb_1__1__43_chanx_left_out), + .ccff_tail(sb_1__1__43_ccff_tail) + ); + sb_1__1_ sb_7__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__51_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__51_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__50_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__44_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_59_ccff_tail), + .chany_top_out(sb_1__1__44_chany_top_out), + .chanx_right_out(sb_1__1__44_chanx_right_out), + .chany_bottom_out(sb_1__1__44_chany_bottom_out), + .chanx_left_out(sb_1__1__44_chanx_left_out), + .ccff_tail(sb_1__1__44_ccff_tail) + ); + sb_1__1_ sb_7__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__52_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__52_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__51_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__45_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_44_ccff_tail), + .chany_top_out(sb_1__1__45_chany_top_out), + .chanx_right_out(sb_1__1__45_chanx_right_out), + .chany_bottom_out(sb_1__1__45_chany_bottom_out), + .chanx_left_out(sb_1__1__45_chanx_left_out), + .ccff_tail(sb_1__1__45_ccff_tail) + ); + sb_1__1_ sb_7__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__53_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__53_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__52_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__46_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_61_ccff_tail), + .chany_top_out(sb_1__1__46_chany_top_out), + .chanx_right_out(sb_1__1__46_chanx_right_out), + .chany_bottom_out(sb_1__1__46_chany_bottom_out), + .chanx_left_out(sb_1__1__46_chanx_left_out), + .ccff_tail(sb_1__1__46_ccff_tail) + ); + sb_1__1_ sb_7__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__54_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__54_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__53_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__47_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_46_ccff_tail), + .chany_top_out(sb_1__1__47_chany_top_out), + .chanx_right_out(sb_1__1__47_chanx_right_out), + .chany_bottom_out(sb_1__1__47_chany_bottom_out), + .chanx_left_out(sb_1__1__47_chanx_left_out), + .ccff_tail(sb_1__1__47_ccff_tail) + ); + sb_1__1_ sb_7__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__55_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_right_in(cbx_1__1__55_chanx_left_out), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__54_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__48_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_63_ccff_tail), + .chany_top_out(sb_1__1__48_chany_top_out), + .chanx_right_out(sb_1__1__48_chanx_right_out), + .chany_bottom_out(sb_1__1__48_chany_bottom_out), + .chanx_left_out(sb_1__1__48_chanx_left_out), + .ccff_tail(sb_1__1__48_ccff_tail) + ); + sb_1__8_ sb_1__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__1_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__7_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__0_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_1_ccff_tail), + .chanx_right_out(sb_1__8__0_chanx_right_out), + .chany_bottom_out(sb_1__8__0_chany_bottom_out), + .chanx_left_out(sb_1__8__0_chanx_left_out), + .ccff_tail(sb_1__8__0_ccff_tail) + ); + sb_1__8_ sb_2__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__2_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__15_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__1_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_2_ccff_tail), + .chanx_right_out(sb_1__8__1_chanx_right_out), + .chany_bottom_out(sb_1__8__1_chany_bottom_out), + .chanx_left_out(sb_1__8__1_chanx_left_out), + .ccff_tail(sb_1__8__1_ccff_tail) + ); + sb_1__8_ sb_3__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__3_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__23_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__2_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_3_ccff_tail), + .chanx_right_out(sb_1__8__2_chanx_right_out), + .chany_bottom_out(sb_1__8__2_chany_bottom_out), + .chanx_left_out(sb_1__8__2_chanx_left_out), + .ccff_tail(sb_1__8__2_ccff_tail) + ); + sb_1__8_ sb_4__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__4_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__31_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__3_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_4_ccff_tail), + .chanx_right_out(sb_1__8__3_chanx_right_out), + .chany_bottom_out(sb_1__8__3_chany_bottom_out), + .chanx_left_out(sb_1__8__3_chanx_left_out), + .ccff_tail(sb_1__8__3_ccff_tail) + ); + sb_1__8_ sb_5__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__5_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__39_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__4_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_5_ccff_tail), + .chanx_right_out(sb_1__8__4_chanx_right_out), + .chany_bottom_out(sb_1__8__4_chany_bottom_out), + .chanx_left_out(sb_1__8__4_chanx_left_out), + .ccff_tail(sb_1__8__4_ccff_tail) + ); + sb_1__8_ sb_6__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__6_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__47_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__5_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_6_ccff_tail), + .chanx_right_out(sb_1__8__5_chanx_right_out), + .chany_bottom_out(sb_1__8__5_chany_bottom_out), + .chanx_left_out(sb_1__8__5_chanx_left_out), + .ccff_tail(sb_1__8__5_ccff_tail) + ); + sb_1__8_ sb_7__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__8__7_chanx_left_out), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_3_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_4_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_5_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_6_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_7_), + .chany_bottom_in(cby_1__1__55_chany_top_out), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__6_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_top_top_7_ccff_tail), + .chanx_right_out(sb_1__8__6_chanx_right_out), + .chany_bottom_out(sb_1__8__6_chany_bottom_out), + .chanx_left_out(sb_1__8__6_chanx_left_out), + .ccff_tail(sb_1__8__6_ccff_tail) + ); + sb_8__0_ sb_8__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__0_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chanx_left_in(cbx_1__0__7_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_head(grid_clb_48_ccff_tail), + .chany_top_out(sb_8__0__0_chany_top_out), + .chanx_left_out(sb_8__0__0_chanx_left_out), + .ccff_tail(sb_8__0__0_ccff_tail) + ); + sb_8__1_ sb_8__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__1_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__0_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__49_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_56_ccff_tail), + .chany_top_out(sb_8__1__0_chany_top_out), + .chany_bottom_out(sb_8__1__0_chany_bottom_out), + .chanx_left_out(sb_8__1__0_chanx_left_out), + .ccff_tail(sb_8__1__0_ccff_tail) + ); + sb_8__1_ sb_8__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__2_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__1_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__50_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_50_ccff_tail), + .chany_top_out(sb_8__1__1_chany_top_out), + .chany_bottom_out(sb_8__1__1_chany_bottom_out), + .chanx_left_out(sb_8__1__1_chanx_left_out), + .ccff_tail(sb_8__1__1_ccff_tail) + ); + sb_8__1_ sb_8__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__3_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__2_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__51_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_58_ccff_tail), + .chany_top_out(sb_8__1__2_chany_top_out), + .chany_bottom_out(sb_8__1__2_chany_bottom_out), + .chanx_left_out(sb_8__1__2_chanx_left_out), + .ccff_tail(sb_8__1__2_ccff_tail) + ); + sb_8__1_ sb_8__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__4_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__3_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__52_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_52_ccff_tail), + .chany_top_out(sb_8__1__3_chany_top_out), + .chany_bottom_out(sb_8__1__3_chany_bottom_out), + .chanx_left_out(sb_8__1__3_chanx_left_out), + .ccff_tail(sb_8__1__3_ccff_tail) + ); + sb_8__1_ sb_8__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__5_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__4_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__53_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_60_ccff_tail), + .chany_top_out(sb_8__1__4_chany_top_out), + .chany_bottom_out(sb_8__1__4_chany_bottom_out), + .chanx_left_out(sb_8__1__4_chanx_left_out), + .ccff_tail(sb_8__1__4_ccff_tail) + ); + sb_8__1_ sb_8__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__6_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__5_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__54_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_54_ccff_tail), + .chany_top_out(sb_8__1__5_chany_top_out), + .chany_bottom_out(sb_8__1__5_chany_bottom_out), + .chanx_left_out(sb_8__1__5_chanx_left_out), + .ccff_tail(sb_8__1__5_ccff_tail) + ); + sb_8__1_ sb_8__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_top_in(cby_8__1__7_chany_bottom_out), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_9_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_13_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_14_), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_15_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .chany_bottom_in(cby_8__1__6_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__1__55_chanx_right_out), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_clb_62_ccff_tail), + .chany_top_out(sb_8__1__6_chany_top_out), + .chany_bottom_out(sb_8__1__6_chany_bottom_out), + .chanx_left_out(sb_8__1__6_chanx_left_out), + .ccff_tail(sb_8__1__6_ccff_tail) + ); + sb_8__8_ sb_8__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(cby_8__1__7_chany_top_out), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_9_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_13_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_14_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_15_), + .chanx_left_in(cbx_1__8__7_chanx_right_out), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_3_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_4_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_5_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_6_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_7_), + .ccff_head(grid_io_right_right_0_ccff_tail), + .chany_bottom_out(sb_8__8__0_chany_bottom_out), + .chanx_left_out(sb_8__8__0_chanx_left_out), + .ccff_tail(sb_8__8__0_ccff_tail) + ); + cbx_1__0_ cbx_1__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__0__0_chanx_right_out), + .chanx_right_in(sb_1__0__0_chanx_left_out), + .ccff_head(sb_1__0__0_ccff_tail), + .chanx_left_out(cbx_1__0__0_chanx_left_out), + .chanx_right_out(cbx_1__0__0_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__0_ccff_tail) + ); + cbx_1__0_ cbx_2__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__0_chanx_right_out), + .chanx_right_in(sb_1__0__1_chanx_left_out), + .ccff_head(sb_1__0__1_ccff_tail), + .chanx_left_out(cbx_1__0__1_chanx_left_out), + .chanx_right_out(cbx_1__0__1_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__1_ccff_tail) + ); + cbx_1__0_ cbx_3__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__1_chanx_right_out), + .chanx_right_in(sb_1__0__2_chanx_left_out), + .ccff_head(sb_1__0__2_ccff_tail), + .chanx_left_out(cbx_1__0__2_chanx_left_out), + .chanx_right_out(cbx_1__0__2_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__2_ccff_tail) + ); + cbx_1__0_ cbx_4__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__2_chanx_right_out), + .chanx_right_in(sb_1__0__3_chanx_left_out), + .ccff_head(sb_1__0__3_ccff_tail), + .chanx_left_out(cbx_1__0__3_chanx_left_out), + .chanx_right_out(cbx_1__0__3_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__3_ccff_tail) + ); + cbx_1__0_ cbx_5__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__3_chanx_right_out), + .chanx_right_in(sb_1__0__4_chanx_left_out), + .ccff_head(sb_1__0__4_ccff_tail), + .chanx_left_out(cbx_1__0__4_chanx_left_out), + .chanx_right_out(cbx_1__0__4_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__4_ccff_tail) + ); + cbx_1__0_ cbx_6__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__4_chanx_right_out), + .chanx_right_in(sb_1__0__5_chanx_left_out), + .ccff_head(sb_1__0__5_ccff_tail), + .chanx_left_out(cbx_1__0__5_chanx_left_out), + .chanx_right_out(cbx_1__0__5_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__5_ccff_tail) + ); + cbx_1__0_ cbx_7__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__5_chanx_right_out), + .chanx_right_in(sb_1__0__6_chanx_left_out), + .ccff_head(sb_1__0__6_ccff_tail), + .chanx_left_out(cbx_1__0__6_chanx_left_out), + .chanx_right_out(cbx_1__0__6_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__6_ccff_tail) + ); + cbx_1__0_ cbx_8__0_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__0__6_chanx_right_out), + .chanx_right_in(sb_8__0__0_chanx_left_out), + .ccff_head(sb_8__0__0_ccff_tail), + .chanx_left_out(cbx_1__0__7_chanx_left_out), + .chanx_right_out(cbx_1__0__7_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cbx_1__0__7_ccff_tail) + ); + cbx_1__1_ cbx_1__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__0_chanx_right_out), + .chanx_right_in(sb_1__1__0_chanx_left_out), + .ccff_head(sb_1__1__0_ccff_tail), + .chanx_left_out(cbx_1__1__0_chanx_left_out), + .chanx_right_out(cbx_1__1__0_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__0_ccff_tail) + ); + cbx_1__1_ cbx_1__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__1_chanx_right_out), + .chanx_right_in(sb_1__1__1_chanx_left_out), + .ccff_head(sb_1__1__1_ccff_tail), + .chanx_left_out(cbx_1__1__1_chanx_left_out), + .chanx_right_out(cbx_1__1__1_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__1_ccff_tail) + ); + cbx_1__1_ cbx_1__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__2_chanx_right_out), + .chanx_right_in(sb_1__1__2_chanx_left_out), + .ccff_head(sb_1__1__2_ccff_tail), + .chanx_left_out(cbx_1__1__2_chanx_left_out), + .chanx_right_out(cbx_1__1__2_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__2_ccff_tail) + ); + cbx_1__1_ cbx_1__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__3_chanx_right_out), + .chanx_right_in(sb_1__1__3_chanx_left_out), + .ccff_head(sb_1__1__3_ccff_tail), + .chanx_left_out(cbx_1__1__3_chanx_left_out), + .chanx_right_out(cbx_1__1__3_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__3_ccff_tail) + ); + cbx_1__1_ cbx_1__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__4_chanx_right_out), + .chanx_right_in(sb_1__1__4_chanx_left_out), + .ccff_head(sb_1__1__4_ccff_tail), + .chanx_left_out(cbx_1__1__4_chanx_left_out), + .chanx_right_out(cbx_1__1__4_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__4_ccff_tail) + ); + cbx_1__1_ cbx_1__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__5_chanx_right_out), + .chanx_right_in(sb_1__1__5_chanx_left_out), + .ccff_head(sb_1__1__5_ccff_tail), + .chanx_left_out(cbx_1__1__5_chanx_left_out), + .chanx_right_out(cbx_1__1__5_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__5_ccff_tail) + ); + cbx_1__1_ cbx_1__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__6_chanx_right_out), + .chanx_right_in(sb_1__1__6_chanx_left_out), + .ccff_head(sb_1__1__6_ccff_tail), + .chanx_left_out(cbx_1__1__6_chanx_left_out), + .chanx_right_out(cbx_1__1__6_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__6_ccff_tail) + ); + cbx_1__1_ cbx_2__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__0_chanx_right_out), + .chanx_right_in(sb_1__1__7_chanx_left_out), + .ccff_head(sb_1__1__7_ccff_tail), + .chanx_left_out(cbx_1__1__7_chanx_left_out), + .chanx_right_out(cbx_1__1__7_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__7_ccff_tail) + ); + cbx_1__1_ cbx_2__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__1_chanx_right_out), + .chanx_right_in(sb_1__1__8_chanx_left_out), + .ccff_head(sb_1__1__8_ccff_tail), + .chanx_left_out(cbx_1__1__8_chanx_left_out), + .chanx_right_out(cbx_1__1__8_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__8_ccff_tail) + ); + cbx_1__1_ cbx_2__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__2_chanx_right_out), + .chanx_right_in(sb_1__1__9_chanx_left_out), + .ccff_head(sb_1__1__9_ccff_tail), + .chanx_left_out(cbx_1__1__9_chanx_left_out), + .chanx_right_out(cbx_1__1__9_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__9_ccff_tail) + ); + cbx_1__1_ cbx_2__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__3_chanx_right_out), + .chanx_right_in(sb_1__1__10_chanx_left_out), + .ccff_head(sb_1__1__10_ccff_tail), + .chanx_left_out(cbx_1__1__10_chanx_left_out), + .chanx_right_out(cbx_1__1__10_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__10_ccff_tail) + ); + cbx_1__1_ cbx_2__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__4_chanx_right_out), + .chanx_right_in(sb_1__1__11_chanx_left_out), + .ccff_head(sb_1__1__11_ccff_tail), + .chanx_left_out(cbx_1__1__11_chanx_left_out), + .chanx_right_out(cbx_1__1__11_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__11_ccff_tail) + ); + cbx_1__1_ cbx_2__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__5_chanx_right_out), + .chanx_right_in(sb_1__1__12_chanx_left_out), + .ccff_head(sb_1__1__12_ccff_tail), + .chanx_left_out(cbx_1__1__12_chanx_left_out), + .chanx_right_out(cbx_1__1__12_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__12_ccff_tail) + ); + cbx_1__1_ cbx_2__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__6_chanx_right_out), + .chanx_right_in(sb_1__1__13_chanx_left_out), + .ccff_head(sb_1__1__13_ccff_tail), + .chanx_left_out(cbx_1__1__13_chanx_left_out), + .chanx_right_out(cbx_1__1__13_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__13_ccff_tail) + ); + cbx_1__1_ cbx_3__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__7_chanx_right_out), + .chanx_right_in(sb_1__1__14_chanx_left_out), + .ccff_head(sb_1__1__14_ccff_tail), + .chanx_left_out(cbx_1__1__14_chanx_left_out), + .chanx_right_out(cbx_1__1__14_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__14_ccff_tail) + ); + cbx_1__1_ cbx_3__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__8_chanx_right_out), + .chanx_right_in(sb_1__1__15_chanx_left_out), + .ccff_head(sb_1__1__15_ccff_tail), + .chanx_left_out(cbx_1__1__15_chanx_left_out), + .chanx_right_out(cbx_1__1__15_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__15_ccff_tail) + ); + cbx_1__1_ cbx_3__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__9_chanx_right_out), + .chanx_right_in(sb_1__1__16_chanx_left_out), + .ccff_head(sb_1__1__16_ccff_tail), + .chanx_left_out(cbx_1__1__16_chanx_left_out), + .chanx_right_out(cbx_1__1__16_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__16_ccff_tail) + ); + cbx_1__1_ cbx_3__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__10_chanx_right_out), + .chanx_right_in(sb_1__1__17_chanx_left_out), + .ccff_head(sb_1__1__17_ccff_tail), + .chanx_left_out(cbx_1__1__17_chanx_left_out), + .chanx_right_out(cbx_1__1__17_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__17_ccff_tail) + ); + cbx_1__1_ cbx_3__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__11_chanx_right_out), + .chanx_right_in(sb_1__1__18_chanx_left_out), + .ccff_head(sb_1__1__18_ccff_tail), + .chanx_left_out(cbx_1__1__18_chanx_left_out), + .chanx_right_out(cbx_1__1__18_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__18_ccff_tail) + ); + cbx_1__1_ cbx_3__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__12_chanx_right_out), + .chanx_right_in(sb_1__1__19_chanx_left_out), + .ccff_head(sb_1__1__19_ccff_tail), + .chanx_left_out(cbx_1__1__19_chanx_left_out), + .chanx_right_out(cbx_1__1__19_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__19_ccff_tail) + ); + cbx_1__1_ cbx_3__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__13_chanx_right_out), + .chanx_right_in(sb_1__1__20_chanx_left_out), + .ccff_head(sb_1__1__20_ccff_tail), + .chanx_left_out(cbx_1__1__20_chanx_left_out), + .chanx_right_out(cbx_1__1__20_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__20_ccff_tail) + ); + cbx_1__1_ cbx_4__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__14_chanx_right_out), + .chanx_right_in(sb_1__1__21_chanx_left_out), + .ccff_head(sb_1__1__21_ccff_tail), + .chanx_left_out(cbx_1__1__21_chanx_left_out), + .chanx_right_out(cbx_1__1__21_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__21_ccff_tail) + ); + cbx_1__1_ cbx_4__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__15_chanx_right_out), + .chanx_right_in(sb_1__1__22_chanx_left_out), + .ccff_head(sb_1__1__22_ccff_tail), + .chanx_left_out(cbx_1__1__22_chanx_left_out), + .chanx_right_out(cbx_1__1__22_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__22_ccff_tail) + ); + cbx_1__1_ cbx_4__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__16_chanx_right_out), + .chanx_right_in(sb_1__1__23_chanx_left_out), + .ccff_head(sb_1__1__23_ccff_tail), + .chanx_left_out(cbx_1__1__23_chanx_left_out), + .chanx_right_out(cbx_1__1__23_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__23_ccff_tail) + ); + cbx_1__1_ cbx_4__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__17_chanx_right_out), + .chanx_right_in(sb_1__1__24_chanx_left_out), + .ccff_head(sb_1__1__24_ccff_tail), + .chanx_left_out(cbx_1__1__24_chanx_left_out), + .chanx_right_out(cbx_1__1__24_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__24_ccff_tail) + ); + cbx_1__1_ cbx_4__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__18_chanx_right_out), + .chanx_right_in(sb_1__1__25_chanx_left_out), + .ccff_head(sb_1__1__25_ccff_tail), + .chanx_left_out(cbx_1__1__25_chanx_left_out), + .chanx_right_out(cbx_1__1__25_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__25_ccff_tail) + ); + cbx_1__1_ cbx_4__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__19_chanx_right_out), + .chanx_right_in(sb_1__1__26_chanx_left_out), + .ccff_head(sb_1__1__26_ccff_tail), + .chanx_left_out(cbx_1__1__26_chanx_left_out), + .chanx_right_out(cbx_1__1__26_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__26_ccff_tail) + ); + cbx_1__1_ cbx_4__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__20_chanx_right_out), + .chanx_right_in(sb_1__1__27_chanx_left_out), + .ccff_head(sb_1__1__27_ccff_tail), + .chanx_left_out(cbx_1__1__27_chanx_left_out), + .chanx_right_out(cbx_1__1__27_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__27_ccff_tail) + ); + cbx_1__1_ cbx_5__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__21_chanx_right_out), + .chanx_right_in(sb_1__1__28_chanx_left_out), + .ccff_head(sb_1__1__28_ccff_tail), + .chanx_left_out(cbx_1__1__28_chanx_left_out), + .chanx_right_out(cbx_1__1__28_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__28_ccff_tail) + ); + cbx_1__1_ cbx_5__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__22_chanx_right_out), + .chanx_right_in(sb_1__1__29_chanx_left_out), + .ccff_head(sb_1__1__29_ccff_tail), + .chanx_left_out(cbx_1__1__29_chanx_left_out), + .chanx_right_out(cbx_1__1__29_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__29_ccff_tail) + ); + cbx_1__1_ cbx_5__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__23_chanx_right_out), + .chanx_right_in(sb_1__1__30_chanx_left_out), + .ccff_head(sb_1__1__30_ccff_tail), + .chanx_left_out(cbx_1__1__30_chanx_left_out), + .chanx_right_out(cbx_1__1__30_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__30_ccff_tail) + ); + cbx_1__1_ cbx_5__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__24_chanx_right_out), + .chanx_right_in(sb_1__1__31_chanx_left_out), + .ccff_head(sb_1__1__31_ccff_tail), + .chanx_left_out(cbx_1__1__31_chanx_left_out), + .chanx_right_out(cbx_1__1__31_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__31_ccff_tail) + ); + cbx_1__1_ cbx_5__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__25_chanx_right_out), + .chanx_right_in(sb_1__1__32_chanx_left_out), + .ccff_head(sb_1__1__32_ccff_tail), + .chanx_left_out(cbx_1__1__32_chanx_left_out), + .chanx_right_out(cbx_1__1__32_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__32_ccff_tail) + ); + cbx_1__1_ cbx_5__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__26_chanx_right_out), + .chanx_right_in(sb_1__1__33_chanx_left_out), + .ccff_head(sb_1__1__33_ccff_tail), + .chanx_left_out(cbx_1__1__33_chanx_left_out), + .chanx_right_out(cbx_1__1__33_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__33_ccff_tail) + ); + cbx_1__1_ cbx_5__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__27_chanx_right_out), + .chanx_right_in(sb_1__1__34_chanx_left_out), + .ccff_head(sb_1__1__34_ccff_tail), + .chanx_left_out(cbx_1__1__34_chanx_left_out), + .chanx_right_out(cbx_1__1__34_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__34_ccff_tail) + ); + cbx_1__1_ cbx_6__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__28_chanx_right_out), + .chanx_right_in(sb_1__1__35_chanx_left_out), + .ccff_head(sb_1__1__35_ccff_tail), + .chanx_left_out(cbx_1__1__35_chanx_left_out), + .chanx_right_out(cbx_1__1__35_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__35_ccff_tail) + ); + cbx_1__1_ cbx_6__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__29_chanx_right_out), + .chanx_right_in(sb_1__1__36_chanx_left_out), + .ccff_head(sb_1__1__36_ccff_tail), + .chanx_left_out(cbx_1__1__36_chanx_left_out), + .chanx_right_out(cbx_1__1__36_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__36_ccff_tail) + ); + cbx_1__1_ cbx_6__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__30_chanx_right_out), + .chanx_right_in(sb_1__1__37_chanx_left_out), + .ccff_head(sb_1__1__37_ccff_tail), + .chanx_left_out(cbx_1__1__37_chanx_left_out), + .chanx_right_out(cbx_1__1__37_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__37_ccff_tail) + ); + cbx_1__1_ cbx_6__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__31_chanx_right_out), + .chanx_right_in(sb_1__1__38_chanx_left_out), + .ccff_head(sb_1__1__38_ccff_tail), + .chanx_left_out(cbx_1__1__38_chanx_left_out), + .chanx_right_out(cbx_1__1__38_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__38_ccff_tail) + ); + cbx_1__1_ cbx_6__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__32_chanx_right_out), + .chanx_right_in(sb_1__1__39_chanx_left_out), + .ccff_head(sb_1__1__39_ccff_tail), + .chanx_left_out(cbx_1__1__39_chanx_left_out), + .chanx_right_out(cbx_1__1__39_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__39_ccff_tail) + ); + cbx_1__1_ cbx_6__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__33_chanx_right_out), + .chanx_right_in(sb_1__1__40_chanx_left_out), + .ccff_head(sb_1__1__40_ccff_tail), + .chanx_left_out(cbx_1__1__40_chanx_left_out), + .chanx_right_out(cbx_1__1__40_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__40_ccff_tail) + ); + cbx_1__1_ cbx_6__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__34_chanx_right_out), + .chanx_right_in(sb_1__1__41_chanx_left_out), + .ccff_head(sb_1__1__41_ccff_tail), + .chanx_left_out(cbx_1__1__41_chanx_left_out), + .chanx_right_out(cbx_1__1__41_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__41_ccff_tail) + ); + cbx_1__1_ cbx_7__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__35_chanx_right_out), + .chanx_right_in(sb_1__1__42_chanx_left_out), + .ccff_head(sb_1__1__42_ccff_tail), + .chanx_left_out(cbx_1__1__42_chanx_left_out), + .chanx_right_out(cbx_1__1__42_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__42_ccff_tail) + ); + cbx_1__1_ cbx_7__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__36_chanx_right_out), + .chanx_right_in(sb_1__1__43_chanx_left_out), + .ccff_head(sb_1__1__43_ccff_tail), + .chanx_left_out(cbx_1__1__43_chanx_left_out), + .chanx_right_out(cbx_1__1__43_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__43_ccff_tail) + ); + cbx_1__1_ cbx_7__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__37_chanx_right_out), + .chanx_right_in(sb_1__1__44_chanx_left_out), + .ccff_head(sb_1__1__44_ccff_tail), + .chanx_left_out(cbx_1__1__44_chanx_left_out), + .chanx_right_out(cbx_1__1__44_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__44_ccff_tail) + ); + cbx_1__1_ cbx_7__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__38_chanx_right_out), + .chanx_right_in(sb_1__1__45_chanx_left_out), + .ccff_head(sb_1__1__45_ccff_tail), + .chanx_left_out(cbx_1__1__45_chanx_left_out), + .chanx_right_out(cbx_1__1__45_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__45_ccff_tail) + ); + cbx_1__1_ cbx_7__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__39_chanx_right_out), + .chanx_right_in(sb_1__1__46_chanx_left_out), + .ccff_head(sb_1__1__46_ccff_tail), + .chanx_left_out(cbx_1__1__46_chanx_left_out), + .chanx_right_out(cbx_1__1__46_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__46_ccff_tail) + ); + cbx_1__1_ cbx_7__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__40_chanx_right_out), + .chanx_right_in(sb_1__1__47_chanx_left_out), + .ccff_head(sb_1__1__47_ccff_tail), + .chanx_left_out(cbx_1__1__47_chanx_left_out), + .chanx_right_out(cbx_1__1__47_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__47_ccff_tail) + ); + cbx_1__1_ cbx_7__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__41_chanx_right_out), + .chanx_right_in(sb_1__1__48_chanx_left_out), + .ccff_head(sb_1__1__48_ccff_tail), + .chanx_left_out(cbx_1__1__48_chanx_left_out), + .chanx_right_out(cbx_1__1__48_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__48_ccff_tail) + ); + cbx_1__1_ cbx_8__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__42_chanx_right_out), + .chanx_right_in(sb_8__1__0_chanx_left_out), + .ccff_head(sb_8__1__0_ccff_tail), + .chanx_left_out(cbx_1__1__49_chanx_left_out), + .chanx_right_out(cbx_1__1__49_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__49_ccff_tail) + ); + cbx_1__1_ cbx_8__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__43_chanx_right_out), + .chanx_right_in(sb_8__1__1_chanx_left_out), + .ccff_head(sb_8__1__1_ccff_tail), + .chanx_left_out(cbx_1__1__50_chanx_left_out), + .chanx_right_out(cbx_1__1__50_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__50_ccff_tail) + ); + cbx_1__1_ cbx_8__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__44_chanx_right_out), + .chanx_right_in(sb_8__1__2_chanx_left_out), + .ccff_head(sb_8__1__2_ccff_tail), + .chanx_left_out(cbx_1__1__51_chanx_left_out), + .chanx_right_out(cbx_1__1__51_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__51_ccff_tail) + ); + cbx_1__1_ cbx_8__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__45_chanx_right_out), + .chanx_right_in(sb_8__1__3_chanx_left_out), + .ccff_head(sb_8__1__3_ccff_tail), + .chanx_left_out(cbx_1__1__52_chanx_left_out), + .chanx_right_out(cbx_1__1__52_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__52_ccff_tail) + ); + cbx_1__1_ cbx_8__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__46_chanx_right_out), + .chanx_right_in(sb_8__1__4_chanx_left_out), + .ccff_head(sb_8__1__4_ccff_tail), + .chanx_left_out(cbx_1__1__53_chanx_left_out), + .chanx_right_out(cbx_1__1__53_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__53_ccff_tail) + ); + cbx_1__1_ cbx_8__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__47_chanx_right_out), + .chanx_right_in(sb_8__1__5_chanx_left_out), + .ccff_head(sb_8__1__5_ccff_tail), + .chanx_left_out(cbx_1__1__54_chanx_left_out), + .chanx_right_out(cbx_1__1__54_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__54_ccff_tail) + ); + cbx_1__1_ cbx_8__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__1__48_chanx_right_out), + .chanx_right_in(sb_8__1__6_chanx_left_out), + .ccff_head(sb_8__1__6_ccff_tail), + .chanx_left_out(cbx_1__1__55_chanx_left_out), + .chanx_right_out(cbx_1__1__55_chanx_right_out), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__1__55_ccff_tail) + ); + cbx_1__8_ cbx_1__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_0__8__0_chanx_right_out), + .chanx_right_in(sb_1__8__0_chanx_left_out), + .ccff_head(sb_1__8__0_ccff_tail), + .chanx_left_out(cbx_1__8__0_chanx_left_out), + .chanx_right_out(cbx_1__8__0_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__0_ccff_tail) + ); + cbx_1__8_ cbx_2__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__0_chanx_right_out), + .chanx_right_in(sb_1__8__1_chanx_left_out), + .ccff_head(sb_1__8__1_ccff_tail), + .chanx_left_out(cbx_1__8__1_chanx_left_out), + .chanx_right_out(cbx_1__8__1_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__1_ccff_tail) + ); + cbx_1__8_ cbx_3__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__1_chanx_right_out), + .chanx_right_in(sb_1__8__2_chanx_left_out), + .ccff_head(sb_1__8__2_ccff_tail), + .chanx_left_out(cbx_1__8__2_chanx_left_out), + .chanx_right_out(cbx_1__8__2_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__2_ccff_tail) + ); + cbx_1__8_ cbx_4__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__2_chanx_right_out), + .chanx_right_in(sb_1__8__3_chanx_left_out), + .ccff_head(sb_1__8__3_ccff_tail), + .chanx_left_out(cbx_1__8__3_chanx_left_out), + .chanx_right_out(cbx_1__8__3_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__3_ccff_tail) + ); + cbx_1__8_ cbx_5__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__3_chanx_right_out), + .chanx_right_in(sb_1__8__4_chanx_left_out), + .ccff_head(sb_1__8__4_ccff_tail), + .chanx_left_out(cbx_1__8__4_chanx_left_out), + .chanx_right_out(cbx_1__8__4_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__4_ccff_tail) + ); + cbx_1__8_ cbx_6__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__4_chanx_right_out), + .chanx_right_in(sb_1__8__5_chanx_left_out), + .ccff_head(sb_1__8__5_ccff_tail), + .chanx_left_out(cbx_1__8__5_chanx_left_out), + .chanx_right_out(cbx_1__8__5_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__5_ccff_tail) + ); + cbx_1__8_ cbx_7__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__5_chanx_right_out), + .chanx_right_in(sb_1__8__6_chanx_left_out), + .ccff_head(sb_1__8__6_ccff_tail), + .chanx_left_out(cbx_1__8__6_chanx_left_out), + .chanx_right_out(cbx_1__8__6_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__6_ccff_tail) + ); + cbx_1__8_ cbx_8__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chanx_left_in(sb_1__8__6_chanx_right_out), + .chanx_right_in(sb_8__8__0_chanx_left_out), + .ccff_head(sb_8__8__0_ccff_tail), + .chanx_left_out(cbx_1__8__7_chanx_left_out), + .chanx_right_out(cbx_1__8__7_chanx_right_out), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), + .ccff_tail(cbx_1__8__7_ccff_tail) + ); + cby_0__1_ cby_0__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__0__0_chany_top_out), + .chany_top_in(sb_0__1__0_chany_bottom_out), + .ccff_head(sb_0__0__0_ccff_tail), + .chany_bottom_out(cby_0__1__0_chany_bottom_out), + .chany_top_out(cby_0__1__0_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__0_ccff_tail) + ); + cby_0__1_ cby_0__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__0_chany_top_out), + .chany_top_in(sb_0__1__1_chany_bottom_out), + .ccff_head(sb_0__1__0_ccff_tail), + .chany_bottom_out(cby_0__1__1_chany_bottom_out), + .chany_top_out(cby_0__1__1_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__1_ccff_tail) + ); + cby_0__1_ cby_0__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__1_chany_top_out), + .chany_top_in(sb_0__1__2_chany_bottom_out), + .ccff_head(sb_0__1__1_ccff_tail), + .chany_bottom_out(cby_0__1__2_chany_bottom_out), + .chany_top_out(cby_0__1__2_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__2_ccff_tail) + ); + cby_0__1_ cby_0__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__2_chany_top_out), + .chany_top_in(sb_0__1__3_chany_bottom_out), + .ccff_head(sb_0__1__2_ccff_tail), + .chany_bottom_out(cby_0__1__3_chany_bottom_out), + .chany_top_out(cby_0__1__3_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__3_ccff_tail) + ); + cby_0__1_ cby_0__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__3_chany_top_out), + .chany_top_in(sb_0__1__4_chany_bottom_out), + .ccff_head(sb_0__1__3_ccff_tail), + .chany_bottom_out(cby_0__1__4_chany_bottom_out), + .chany_top_out(cby_0__1__4_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__4_ccff_tail) + ); + cby_0__1_ cby_0__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__4_chany_top_out), + .chany_top_in(sb_0__1__5_chany_bottom_out), + .ccff_head(sb_0__1__4_ccff_tail), + .chany_bottom_out(cby_0__1__5_chany_bottom_out), + .chany_top_out(cby_0__1__5_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__5_ccff_tail) + ); + cby_0__1_ cby_0__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__5_chany_top_out), + .chany_top_in(sb_0__1__6_chany_bottom_out), + .ccff_head(sb_0__1__5_ccff_tail), + .chany_bottom_out(cby_0__1__6_chany_bottom_out), + .chany_top_out(cby_0__1__6_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__6_ccff_tail) + ); + cby_0__1_ cby_0__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__1__6_chany_top_out), + .chany_top_in(sb_0__8__0_chany_bottom_out), + .ccff_head(sb_0__1__6_ccff_tail), + .chany_bottom_out(cby_0__1__7_chany_bottom_out), + .chany_top_out(cby_0__1__7_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_tail(cby_0__1__7_ccff_tail) + ); + cby_1__1_ cby_1__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__0_chany_top_out), + .chany_top_in(sb_1__1__0_chany_bottom_out), + .ccff_head(cbx_1__0__0_ccff_tail), + .chany_bottom_out(cby_1__1__0_chany_bottom_out), + .chany_top_out(cby_1__1__0_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__0_ccff_tail) + ); + cby_1__1_ cby_1__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__0_chany_top_out), + .chany_top_in(sb_1__1__1_chany_bottom_out), + .ccff_head(cbx_1__1__0_ccff_tail), + .chany_bottom_out(cby_1__1__1_chany_bottom_out), + .chany_top_out(cby_1__1__1_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__1_ccff_tail) + ); + cby_1__1_ cby_1__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__1_chany_top_out), + .chany_top_in(sb_1__1__2_chany_bottom_out), + .ccff_head(cbx_1__1__1_ccff_tail), + .chany_bottom_out(cby_1__1__2_chany_bottom_out), + .chany_top_out(cby_1__1__2_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__2_ccff_tail) + ); + cby_1__1_ cby_1__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__2_chany_top_out), + .chany_top_in(sb_1__1__3_chany_bottom_out), + .ccff_head(cbx_1__1__2_ccff_tail), + .chany_bottom_out(cby_1__1__3_chany_bottom_out), + .chany_top_out(cby_1__1__3_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__3_ccff_tail) + ); + cby_1__1_ cby_1__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__3_chany_top_out), + .chany_top_in(sb_1__1__4_chany_bottom_out), + .ccff_head(cbx_1__1__3_ccff_tail), + .chany_bottom_out(cby_1__1__4_chany_bottom_out), + .chany_top_out(cby_1__1__4_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__4_ccff_tail) + ); + cby_1__1_ cby_1__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__4_chany_top_out), + .chany_top_in(sb_1__1__5_chany_bottom_out), + .ccff_head(cbx_1__1__4_ccff_tail), + .chany_bottom_out(cby_1__1__5_chany_bottom_out), + .chany_top_out(cby_1__1__5_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__5_ccff_tail) + ); + cby_1__1_ cby_1__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__5_chany_top_out), + .chany_top_in(sb_1__1__6_chany_bottom_out), + .ccff_head(cbx_1__1__5_ccff_tail), + .chany_bottom_out(cby_1__1__6_chany_bottom_out), + .chany_top_out(cby_1__1__6_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__6_ccff_tail) + ); + cby_1__1_ cby_1__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__6_chany_top_out), + .chany_top_in(sb_1__8__0_chany_bottom_out), + .ccff_head(cbx_1__1__6_ccff_tail), + .chany_bottom_out(cby_1__1__7_chany_bottom_out), + .chany_top_out(cby_1__1__7_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__7_ccff_tail) + ); + cby_1__1_ cby_2__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__1_chany_top_out), + .chany_top_in(sb_1__1__7_chany_bottom_out), + .ccff_head(cbx_1__0__1_ccff_tail), + .chany_bottom_out(cby_1__1__8_chany_bottom_out), + .chany_top_out(cby_1__1__8_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__8_ccff_tail) + ); + cby_1__1_ cby_2__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__7_chany_top_out), + .chany_top_in(sb_1__1__8_chany_bottom_out), + .ccff_head(cbx_1__1__7_ccff_tail), + .chany_bottom_out(cby_1__1__9_chany_bottom_out), + .chany_top_out(cby_1__1__9_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__9_ccff_tail) + ); + cby_1__1_ cby_2__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__8_chany_top_out), + .chany_top_in(sb_1__1__9_chany_bottom_out), + .ccff_head(cbx_1__1__8_ccff_tail), + .chany_bottom_out(cby_1__1__10_chany_bottom_out), + .chany_top_out(cby_1__1__10_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__10_ccff_tail) + ); + cby_1__1_ cby_2__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__9_chany_top_out), + .chany_top_in(sb_1__1__10_chany_bottom_out), + .ccff_head(cbx_1__1__9_ccff_tail), + .chany_bottom_out(cby_1__1__11_chany_bottom_out), + .chany_top_out(cby_1__1__11_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__11_ccff_tail) + ); + cby_1__1_ cby_2__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__10_chany_top_out), + .chany_top_in(sb_1__1__11_chany_bottom_out), + .ccff_head(cbx_1__1__10_ccff_tail), + .chany_bottom_out(cby_1__1__12_chany_bottom_out), + .chany_top_out(cby_1__1__12_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__12_ccff_tail) + ); + cby_1__1_ cby_2__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__11_chany_top_out), + .chany_top_in(sb_1__1__12_chany_bottom_out), + .ccff_head(cbx_1__1__11_ccff_tail), + .chany_bottom_out(cby_1__1__13_chany_bottom_out), + .chany_top_out(cby_1__1__13_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__13_ccff_tail) + ); + cby_1__1_ cby_2__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__12_chany_top_out), + .chany_top_in(sb_1__1__13_chany_bottom_out), + .ccff_head(cbx_1__1__12_ccff_tail), + .chany_bottom_out(cby_1__1__14_chany_bottom_out), + .chany_top_out(cby_1__1__14_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__14_ccff_tail) + ); + cby_1__1_ cby_2__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__13_chany_top_out), + .chany_top_in(sb_1__8__1_chany_bottom_out), + .ccff_head(cbx_1__1__13_ccff_tail), + .chany_bottom_out(cby_1__1__15_chany_bottom_out), + .chany_top_out(cby_1__1__15_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__15_ccff_tail) + ); + cby_1__1_ cby_3__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__2_chany_top_out), + .chany_top_in(sb_1__1__14_chany_bottom_out), + .ccff_head(cbx_1__0__2_ccff_tail), + .chany_bottom_out(cby_1__1__16_chany_bottom_out), + .chany_top_out(cby_1__1__16_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__16_ccff_tail) + ); + cby_1__1_ cby_3__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__14_chany_top_out), + .chany_top_in(sb_1__1__15_chany_bottom_out), + .ccff_head(cbx_1__1__14_ccff_tail), + .chany_bottom_out(cby_1__1__17_chany_bottom_out), + .chany_top_out(cby_1__1__17_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__17_ccff_tail) + ); + cby_1__1_ cby_3__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__15_chany_top_out), + .chany_top_in(sb_1__1__16_chany_bottom_out), + .ccff_head(cbx_1__1__15_ccff_tail), + .chany_bottom_out(cby_1__1__18_chany_bottom_out), + .chany_top_out(cby_1__1__18_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__18_ccff_tail) + ); + cby_1__1_ cby_3__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__16_chany_top_out), + .chany_top_in(sb_1__1__17_chany_bottom_out), + .ccff_head(cbx_1__1__16_ccff_tail), + .chany_bottom_out(cby_1__1__19_chany_bottom_out), + .chany_top_out(cby_1__1__19_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__19_ccff_tail) + ); + cby_1__1_ cby_3__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__17_chany_top_out), + .chany_top_in(sb_1__1__18_chany_bottom_out), + .ccff_head(cbx_1__1__17_ccff_tail), + .chany_bottom_out(cby_1__1__20_chany_bottom_out), + .chany_top_out(cby_1__1__20_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__20_ccff_tail) + ); + cby_1__1_ cby_3__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__18_chany_top_out), + .chany_top_in(sb_1__1__19_chany_bottom_out), + .ccff_head(cbx_1__1__18_ccff_tail), + .chany_bottom_out(cby_1__1__21_chany_bottom_out), + .chany_top_out(cby_1__1__21_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__21_ccff_tail) + ); + cby_1__1_ cby_3__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__19_chany_top_out), + .chany_top_in(sb_1__1__20_chany_bottom_out), + .ccff_head(cbx_1__1__19_ccff_tail), + .chany_bottom_out(cby_1__1__22_chany_bottom_out), + .chany_top_out(cby_1__1__22_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__22_ccff_tail) + ); + cby_1__1_ cby_3__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__20_chany_top_out), + .chany_top_in(sb_1__8__2_chany_bottom_out), + .ccff_head(cbx_1__1__20_ccff_tail), + .chany_bottom_out(cby_1__1__23_chany_bottom_out), + .chany_top_out(cby_1__1__23_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__23_ccff_tail) + ); + cby_1__1_ cby_4__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__3_chany_top_out), + .chany_top_in(sb_1__1__21_chany_bottom_out), + .ccff_head(cbx_1__0__3_ccff_tail), + .chany_bottom_out(cby_1__1__24_chany_bottom_out), + .chany_top_out(cby_1__1__24_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__24_ccff_tail) + ); + cby_1__1_ cby_4__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__21_chany_top_out), + .chany_top_in(sb_1__1__22_chany_bottom_out), + .ccff_head(cbx_1__1__21_ccff_tail), + .chany_bottom_out(cby_1__1__25_chany_bottom_out), + .chany_top_out(cby_1__1__25_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__25_ccff_tail) + ); + cby_1__1_ cby_4__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__22_chany_top_out), + .chany_top_in(sb_1__1__23_chany_bottom_out), + .ccff_head(cbx_1__1__22_ccff_tail), + .chany_bottom_out(cby_1__1__26_chany_bottom_out), + .chany_top_out(cby_1__1__26_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__26_ccff_tail) + ); + cby_1__1_ cby_4__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__23_chany_top_out), + .chany_top_in(sb_1__1__24_chany_bottom_out), + .ccff_head(cbx_1__1__23_ccff_tail), + .chany_bottom_out(cby_1__1__27_chany_bottom_out), + .chany_top_out(cby_1__1__27_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__27_ccff_tail) + ); + cby_1__1_ cby_4__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__24_chany_top_out), + .chany_top_in(sb_1__1__25_chany_bottom_out), + .ccff_head(cbx_1__1__24_ccff_tail), + .chany_bottom_out(cby_1__1__28_chany_bottom_out), + .chany_top_out(cby_1__1__28_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__28_ccff_tail) + ); + cby_1__1_ cby_4__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__25_chany_top_out), + .chany_top_in(sb_1__1__26_chany_bottom_out), + .ccff_head(cbx_1__1__25_ccff_tail), + .chany_bottom_out(cby_1__1__29_chany_bottom_out), + .chany_top_out(cby_1__1__29_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__29_ccff_tail) + ); + cby_1__1_ cby_4__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__26_chany_top_out), + .chany_top_in(sb_1__1__27_chany_bottom_out), + .ccff_head(cbx_1__1__26_ccff_tail), + .chany_bottom_out(cby_1__1__30_chany_bottom_out), + .chany_top_out(cby_1__1__30_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__30_ccff_tail) + ); + cby_1__1_ cby_4__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__27_chany_top_out), + .chany_top_in(sb_1__8__3_chany_bottom_out), + .ccff_head(cbx_1__1__27_ccff_tail), + .chany_bottom_out(cby_1__1__31_chany_bottom_out), + .chany_top_out(cby_1__1__31_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__31_ccff_tail) + ); + cby_1__1_ cby_5__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__4_chany_top_out), + .chany_top_in(sb_1__1__28_chany_bottom_out), + .ccff_head(cbx_1__0__4_ccff_tail), + .chany_bottom_out(cby_1__1__32_chany_bottom_out), + .chany_top_out(cby_1__1__32_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__32_ccff_tail) + ); + cby_1__1_ cby_5__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__28_chany_top_out), + .chany_top_in(sb_1__1__29_chany_bottom_out), + .ccff_head(cbx_1__1__28_ccff_tail), + .chany_bottom_out(cby_1__1__33_chany_bottom_out), + .chany_top_out(cby_1__1__33_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__33_ccff_tail) + ); + cby_1__1_ cby_5__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__29_chany_top_out), + .chany_top_in(sb_1__1__30_chany_bottom_out), + .ccff_head(cbx_1__1__29_ccff_tail), + .chany_bottom_out(cby_1__1__34_chany_bottom_out), + .chany_top_out(cby_1__1__34_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__34_ccff_tail) + ); + cby_1__1_ cby_5__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__30_chany_top_out), + .chany_top_in(sb_1__1__31_chany_bottom_out), + .ccff_head(cbx_1__1__30_ccff_tail), + .chany_bottom_out(cby_1__1__35_chany_bottom_out), + .chany_top_out(cby_1__1__35_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__35_ccff_tail) + ); + cby_1__1_ cby_5__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__31_chany_top_out), + .chany_top_in(sb_1__1__32_chany_bottom_out), + .ccff_head(cbx_1__1__31_ccff_tail), + .chany_bottom_out(cby_1__1__36_chany_bottom_out), + .chany_top_out(cby_1__1__36_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__36_ccff_tail) + ); + cby_1__1_ cby_5__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__32_chany_top_out), + .chany_top_in(sb_1__1__33_chany_bottom_out), + .ccff_head(cbx_1__1__32_ccff_tail), + .chany_bottom_out(cby_1__1__37_chany_bottom_out), + .chany_top_out(cby_1__1__37_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__37_ccff_tail) + ); + cby_1__1_ cby_5__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__33_chany_top_out), + .chany_top_in(sb_1__1__34_chany_bottom_out), + .ccff_head(cbx_1__1__33_ccff_tail), + .chany_bottom_out(cby_1__1__38_chany_bottom_out), + .chany_top_out(cby_1__1__38_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__38_ccff_tail) + ); + cby_1__1_ cby_5__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__34_chany_top_out), + .chany_top_in(sb_1__8__4_chany_bottom_out), + .ccff_head(cbx_1__1__34_ccff_tail), + .chany_bottom_out(cby_1__1__39_chany_bottom_out), + .chany_top_out(cby_1__1__39_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__39_ccff_tail) + ); + cby_1__1_ cby_6__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__5_chany_top_out), + .chany_top_in(sb_1__1__35_chany_bottom_out), + .ccff_head(cbx_1__0__5_ccff_tail), + .chany_bottom_out(cby_1__1__40_chany_bottom_out), + .chany_top_out(cby_1__1__40_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__40_ccff_tail) + ); + cby_1__1_ cby_6__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__35_chany_top_out), + .chany_top_in(sb_1__1__36_chany_bottom_out), + .ccff_head(cbx_1__1__35_ccff_tail), + .chany_bottom_out(cby_1__1__41_chany_bottom_out), + .chany_top_out(cby_1__1__41_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__41_ccff_tail) + ); + cby_1__1_ cby_6__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__36_chany_top_out), + .chany_top_in(sb_1__1__37_chany_bottom_out), + .ccff_head(cbx_1__1__36_ccff_tail), + .chany_bottom_out(cby_1__1__42_chany_bottom_out), + .chany_top_out(cby_1__1__42_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__42_ccff_tail) + ); + cby_1__1_ cby_6__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__37_chany_top_out), + .chany_top_in(sb_1__1__38_chany_bottom_out), + .ccff_head(cbx_1__1__37_ccff_tail), + .chany_bottom_out(cby_1__1__43_chany_bottom_out), + .chany_top_out(cby_1__1__43_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__43_ccff_tail) + ); + cby_1__1_ cby_6__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__38_chany_top_out), + .chany_top_in(sb_1__1__39_chany_bottom_out), + .ccff_head(cbx_1__1__38_ccff_tail), + .chany_bottom_out(cby_1__1__44_chany_bottom_out), + .chany_top_out(cby_1__1__44_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__44_ccff_tail) + ); + cby_1__1_ cby_6__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__39_chany_top_out), + .chany_top_in(sb_1__1__40_chany_bottom_out), + .ccff_head(cbx_1__1__39_ccff_tail), + .chany_bottom_out(cby_1__1__45_chany_bottom_out), + .chany_top_out(cby_1__1__45_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__45_ccff_tail) + ); + cby_1__1_ cby_6__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__40_chany_top_out), + .chany_top_in(sb_1__1__41_chany_bottom_out), + .ccff_head(cbx_1__1__40_ccff_tail), + .chany_bottom_out(cby_1__1__46_chany_bottom_out), + .chany_top_out(cby_1__1__46_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__46_ccff_tail) + ); + cby_1__1_ cby_6__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__41_chany_top_out), + .chany_top_in(sb_1__8__5_chany_bottom_out), + .ccff_head(cbx_1__1__41_ccff_tail), + .chany_bottom_out(cby_1__1__47_chany_bottom_out), + .chany_top_out(cby_1__1__47_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__47_ccff_tail) + ); + cby_1__1_ cby_7__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__6_chany_top_out), + .chany_top_in(sb_1__1__42_chany_bottom_out), + .ccff_head(cbx_1__0__6_ccff_tail), + .chany_bottom_out(cby_1__1__48_chany_bottom_out), + .chany_top_out(cby_1__1__48_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__48_ccff_tail) + ); + cby_1__1_ cby_7__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__42_chany_top_out), + .chany_top_in(sb_1__1__43_chany_bottom_out), + .ccff_head(cbx_1__1__42_ccff_tail), + .chany_bottom_out(cby_1__1__49_chany_bottom_out), + .chany_top_out(cby_1__1__49_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__49_ccff_tail) + ); + cby_1__1_ cby_7__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__43_chany_top_out), + .chany_top_in(sb_1__1__44_chany_bottom_out), + .ccff_head(cbx_1__1__43_ccff_tail), + .chany_bottom_out(cby_1__1__50_chany_bottom_out), + .chany_top_out(cby_1__1__50_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__50_ccff_tail) + ); + cby_1__1_ cby_7__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__44_chany_top_out), + .chany_top_in(sb_1__1__45_chany_bottom_out), + .ccff_head(cbx_1__1__44_ccff_tail), + .chany_bottom_out(cby_1__1__51_chany_bottom_out), + .chany_top_out(cby_1__1__51_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__51_ccff_tail) + ); + cby_1__1_ cby_7__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__45_chany_top_out), + .chany_top_in(sb_1__1__46_chany_bottom_out), + .ccff_head(cbx_1__1__45_ccff_tail), + .chany_bottom_out(cby_1__1__52_chany_bottom_out), + .chany_top_out(cby_1__1__52_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__52_ccff_tail) + ); + cby_1__1_ cby_7__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__46_chany_top_out), + .chany_top_in(sb_1__1__47_chany_bottom_out), + .ccff_head(cbx_1__1__46_ccff_tail), + .chany_bottom_out(cby_1__1__53_chany_bottom_out), + .chany_top_out(cby_1__1__53_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__53_ccff_tail) + ); + cby_1__1_ cby_7__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__47_chany_top_out), + .chany_top_in(sb_1__1__48_chany_bottom_out), + .ccff_head(cbx_1__1__47_ccff_tail), + .chany_bottom_out(cby_1__1__54_chany_bottom_out), + .chany_top_out(cby_1__1__54_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__54_ccff_tail) + ); + cby_1__1_ cby_7__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__1__48_chany_top_out), + .chany_top_in(sb_1__8__6_chany_bottom_out), + .ccff_head(cbx_1__1__48_ccff_tail), + .chany_bottom_out(cby_1__1__55_chany_bottom_out), + .chany_top_out(cby_1__1__55_chany_top_out), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_1__1__55_ccff_tail) + ); + cby_8__1_ cby_8__1_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__0__0_chany_top_out), + .chany_top_in(sb_8__1__0_chany_bottom_out), + .ccff_head(cbx_1__0__7_ccff_tail), + .chany_bottom_out(cby_8__1__0_chany_bottom_out), + .chany_top_out(cby_8__1__0_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__0_ccff_tail) + ); + cby_8__1_ cby_8__2_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__0_chany_top_out), + .chany_top_in(sb_8__1__1_chany_bottom_out), + .ccff_head(cbx_1__1__49_ccff_tail), + .chany_bottom_out(cby_8__1__1_chany_bottom_out), + .chany_top_out(cby_8__1__1_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__1_ccff_tail) + ); + cby_8__1_ cby_8__3_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__1_chany_top_out), + .chany_top_in(sb_8__1__2_chany_bottom_out), + .ccff_head(cbx_1__1__50_ccff_tail), + .chany_bottom_out(cby_8__1__2_chany_bottom_out), + .chany_top_out(cby_8__1__2_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__2_ccff_tail) + ); + cby_8__1_ cby_8__4_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__2_chany_top_out), + .chany_top_in(sb_8__1__3_chany_bottom_out), + .ccff_head(cbx_1__1__51_ccff_tail), + .chany_bottom_out(cby_8__1__3_chany_bottom_out), + .chany_top_out(cby_8__1__3_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__3_ccff_tail) + ); + cby_8__1_ cby_8__5_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__3_chany_top_out), + .chany_top_in(sb_8__1__4_chany_bottom_out), + .ccff_head(cbx_1__1__52_ccff_tail), + .chany_bottom_out(cby_8__1__4_chany_bottom_out), + .chany_top_out(cby_8__1__4_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__4_ccff_tail) + ); + cby_8__1_ cby_8__6_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__4_chany_top_out), + .chany_top_in(sb_8__1__5_chany_bottom_out), + .ccff_head(cbx_1__1__53_ccff_tail), + .chany_bottom_out(cby_8__1__5_chany_bottom_out), + .chany_top_out(cby_8__1__5_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__5_ccff_tail) + ); + cby_8__1_ cby_8__7_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__5_chany_top_out), + .chany_top_in(sb_8__1__6_chany_bottom_out), + .ccff_head(cbx_1__1__54_ccff_tail), + .chany_bottom_out(cby_8__1__6_chany_bottom_out), + .chany_top_out(cby_8__1__6_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__6_ccff_tail) + ); + cby_8__1_ cby_8__8_ + ( + .pReset(pReset), + .prog_clk(prog_clk), + .chany_bottom_in(sb_8__1__6_chany_top_out), + .chany_top_in(sb_8__8__0_chany_bottom_out), + .ccff_head(cbx_1__1__55_ccff_tail), + .chany_bottom_out(cby_8__1__7_chany_bottom_out), + .chany_top_out(cby_8__1__7_chany_top_out), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), + .ccff_tail(cby_8__1__7_ccff_tail) + ); + direct_interc direct_interc_0_ + ( + .in(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_0_out) + ); + direct_interc direct_interc_1_ + ( + .in(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_1_out) + ); + direct_interc direct_interc_2_ + ( + .in(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_2_out) + ); + direct_interc direct_interc_3_ + ( + .in(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_3_out) + ); + direct_interc direct_interc_4_ + ( + .in(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_4_out) + ); + direct_interc direct_interc_5_ + ( + .in(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_5_out) + ); + direct_interc direct_interc_6_ + ( + .in(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_6_out) + ); + direct_interc direct_interc_7_ + ( + .in(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_7_out) + ); + direct_interc direct_interc_8_ + ( + .in(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_8_out) + ); + direct_interc direct_interc_9_ + ( + .in(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_9_out) + ); + direct_interc direct_interc_10_ + ( + .in(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_10_out) + ); + direct_interc direct_interc_11_ + ( + .in(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_11_out) + ); + direct_interc direct_interc_12_ + ( + .in(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_12_out) + ); + direct_interc direct_interc_13_ + ( + .in(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_13_out) + ); + direct_interc direct_interc_14_ + ( + .in(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_14_out) + ); + direct_interc direct_interc_15_ + ( + .in(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_15_out) + ); + direct_interc direct_interc_16_ + ( + .in(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_16_out) + ); + direct_interc direct_interc_17_ + ( + .in(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_17_out) + ); + direct_interc direct_interc_18_ + ( + .in(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_18_out) + ); + direct_interc direct_interc_19_ + ( + .in(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_19_out) + ); + direct_interc direct_interc_20_ + ( + .in(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_20_out) + ); + direct_interc direct_interc_21_ + ( + .in(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_21_out) + ); + direct_interc direct_interc_22_ + ( + .in(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_22_out) + ); + direct_interc direct_interc_23_ + ( + .in(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_23_out) + ); + direct_interc direct_interc_24_ + ( + .in(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_24_out) + ); + direct_interc direct_interc_25_ + ( + .in(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_25_out) + ); + direct_interc direct_interc_26_ + ( + .in(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_26_out) + ); + direct_interc direct_interc_27_ + ( + .in(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_27_out) + ); + direct_interc direct_interc_28_ + ( + .in(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_28_out) + ); + direct_interc direct_interc_29_ + ( + .in(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_29_out) + ); + direct_interc direct_interc_30_ + ( + .in(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_30_out) + ); + direct_interc direct_interc_31_ + ( + .in(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_31_out) + ); + direct_interc direct_interc_32_ + ( + .in(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_32_out) + ); + direct_interc direct_interc_33_ + ( + .in(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_33_out) + ); + direct_interc direct_interc_34_ + ( + .in(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_34_out) + ); + direct_interc direct_interc_35_ + ( + .in(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_35_out) + ); + direct_interc direct_interc_36_ + ( + .in(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_36_out) + ); + direct_interc direct_interc_37_ + ( + .in(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_37_out) + ); + direct_interc direct_interc_38_ + ( + .in(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_38_out) + ); + direct_interc direct_interc_39_ + ( + .in(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_39_out) + ); + direct_interc direct_interc_40_ + ( + .in(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_40_out) + ); + direct_interc direct_interc_41_ + ( + .in(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_41_out) + ); + direct_interc direct_interc_42_ + ( + .in(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_42_out) + ); + direct_interc direct_interc_43_ + ( + .in(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_43_out) + ); + direct_interc direct_interc_44_ + ( + .in(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_44_out) + ); + direct_interc direct_interc_45_ + ( + .in(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_45_out) + ); + direct_interc direct_interc_46_ + ( + .in(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_46_out) + ); + direct_interc direct_interc_47_ + ( + .in(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_47_out) + ); + direct_interc direct_interc_48_ + ( + .in(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_48_out) + ); + direct_interc direct_interc_49_ + ( + .in(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_49_out) + ); + direct_interc direct_interc_50_ + ( + .in(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_50_out) + ); + direct_interc direct_interc_51_ + ( + .in(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_51_out) + ); + direct_interc direct_interc_52_ + ( + .in(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_52_out) + ); + direct_interc direct_interc_53_ + ( + .in(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_53_out) + ); + direct_interc direct_interc_54_ + ( + .in(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_54_out) + ); + direct_interc direct_interc_55_ + ( + .in(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_cout_0_), + .out(direct_interc_55_out) + ); + direct_interc direct_interc_56_ + ( + .in(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_56_out) + ); + direct_interc direct_interc_57_ + ( + .in(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_57_out) + ); + direct_interc direct_interc_58_ + ( + .in(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_58_out) + ); + direct_interc direct_interc_59_ + ( + .in(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_59_out) + ); + direct_interc direct_interc_60_ + ( + .in(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_60_out) + ); + direct_interc direct_interc_61_ + ( + .in(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_61_out) + ); + direct_interc direct_interc_62_ + ( + .in(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_62_out) + ); + direct_interc direct_interc_63_ + ( + .in(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_63_out) + ); + direct_interc direct_interc_64_ + ( + .in(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_64_out) + ); + direct_interc direct_interc_65_ + ( + .in(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_65_out) + ); + direct_interc direct_interc_66_ + ( + .in(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_66_out) + ); + direct_interc direct_interc_67_ + ( + .in(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_67_out) + ); + direct_interc direct_interc_68_ + ( + .in(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_68_out) + ); + direct_interc direct_interc_69_ + ( + .in(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_69_out) + ); + direct_interc direct_interc_70_ + ( + .in(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_70_out) + ); + direct_interc direct_interc_71_ + ( + .in(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_71_out) + ); + direct_interc direct_interc_72_ + ( + .in(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_72_out) + ); + direct_interc direct_interc_73_ + ( + .in(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_73_out) + ); + direct_interc direct_interc_74_ + ( + .in(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_74_out) + ); + direct_interc direct_interc_75_ + ( + .in(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_75_out) + ); + direct_interc direct_interc_76_ + ( + .in(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_76_out) + ); + direct_interc direct_interc_77_ + ( + .in(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_77_out) + ); + direct_interc direct_interc_78_ + ( + .in(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_78_out) + ); + direct_interc direct_interc_79_ + ( + .in(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_79_out) + ); + direct_interc direct_interc_80_ + ( + .in(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_80_out) + ); + direct_interc direct_interc_81_ + ( + .in(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_81_out) + ); + direct_interc direct_interc_82_ + ( + .in(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_82_out) + ); + direct_interc direct_interc_83_ + ( + .in(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_83_out) + ); + direct_interc direct_interc_84_ + ( + .in(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_84_out) + ); + direct_interc direct_interc_85_ + ( + .in(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_85_out) + ); + direct_interc direct_interc_86_ + ( + .in(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_86_out) + ); + direct_interc direct_interc_87_ + ( + .in(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_87_out) + ); + direct_interc direct_interc_88_ + ( + .in(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_88_out) + ); + direct_interc direct_interc_89_ + ( + .in(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_89_out) + ); + direct_interc direct_interc_90_ + ( + .in(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_90_out) + ); + direct_interc direct_interc_91_ + ( + .in(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_91_out) + ); + direct_interc direct_interc_92_ + ( + .in(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_92_out) + ); + direct_interc direct_interc_93_ + ( + .in(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_93_out) + ); + direct_interc direct_interc_94_ + ( + .in(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_94_out) + ); + direct_interc direct_interc_95_ + ( + .in(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_95_out) + ); + direct_interc direct_interc_96_ + ( + .in(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_96_out) + ); + direct_interc direct_interc_97_ + ( + .in(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_97_out) + ); + direct_interc direct_interc_98_ + ( + .in(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_98_out) + ); + direct_interc direct_interc_99_ + ( + .in(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_99_out) + ); + direct_interc direct_interc_100_ + ( + .in(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_100_out) + ); + direct_interc direct_interc_101_ + ( + .in(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_101_out) + ); + direct_interc direct_interc_102_ + ( + .in(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_102_out) + ); + direct_interc direct_interc_103_ + ( + .in(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_103_out) + ); + direct_interc direct_interc_104_ + ( + .in(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_104_out) + ); + direct_interc direct_interc_105_ + ( + .in(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_105_out) + ); + direct_interc direct_interc_106_ + ( + .in(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_106_out) + ); + direct_interc direct_interc_107_ + ( + .in(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_107_out) + ); + direct_interc direct_interc_108_ + ( + .in(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_108_out) + ); + direct_interc direct_interc_109_ + ( + .in(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_109_out) + ); + direct_interc direct_interc_110_ + ( + .in(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_110_out) + ); + direct_interc direct_interc_111_ + ( + .in(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .out(direct_interc_111_out) + ); + direct_interc direct_interc_112_ + ( + .in(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_112_out) + ); + direct_interc direct_interc_113_ + ( + .in(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_113_out) + ); + direct_interc direct_interc_114_ + ( + .in(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_114_out) + ); + direct_interc direct_interc_115_ + ( + .in(grid_clb_4_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_115_out) + ); + direct_interc direct_interc_116_ + ( + .in(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_116_out) + ); + direct_interc direct_interc_117_ + ( + .in(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_117_out) + ); + direct_interc direct_interc_118_ + ( + .in(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_118_out) + ); + direct_interc direct_interc_119_ + ( + .in(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_119_out) + ); + direct_interc direct_interc_120_ + ( + .in(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_120_out) + ); + direct_interc direct_interc_121_ + ( + .in(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_121_out) + ); + direct_interc direct_interc_122_ + ( + .in(grid_clb_12_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_122_out) + ); + direct_interc direct_interc_123_ + ( + .in(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_123_out) + ); + direct_interc direct_interc_124_ + ( + .in(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_124_out) + ); + direct_interc direct_interc_125_ + ( + .in(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_125_out) + ); + direct_interc direct_interc_126_ + ( + .in(grid_clb_17_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_126_out) + ); + direct_interc direct_interc_127_ + ( + .in(grid_clb_18_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_127_out) + ); + direct_interc direct_interc_128_ + ( + .in(grid_clb_19_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_128_out) + ); + direct_interc direct_interc_129_ + ( + .in(grid_clb_20_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_129_out) + ); + direct_interc direct_interc_130_ + ( + .in(grid_clb_21_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_130_out) + ); + direct_interc direct_interc_131_ + ( + .in(grid_clb_22_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_131_out) + ); + direct_interc direct_interc_132_ + ( + .in(grid_clb_23_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_132_out) + ); + direct_interc direct_interc_133_ + ( + .in(grid_clb_25_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_133_out) + ); + direct_interc direct_interc_134_ + ( + .in(grid_clb_26_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_134_out) + ); + direct_interc direct_interc_135_ + ( + .in(grid_clb_27_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_135_out) + ); + direct_interc direct_interc_136_ + ( + .in(grid_clb_28_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_136_out) + ); + direct_interc direct_interc_137_ + ( + .in(grid_clb_29_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_137_out) + ); + direct_interc direct_interc_138_ + ( + .in(grid_clb_30_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_138_out) + ); + direct_interc direct_interc_139_ + ( + .in(grid_clb_31_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_139_out) + ); + direct_interc direct_interc_140_ + ( + .in(grid_clb_33_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_140_out) + ); + direct_interc direct_interc_141_ + ( + .in(grid_clb_34_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_141_out) + ); + direct_interc direct_interc_142_ + ( + .in(grid_clb_35_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_142_out) + ); + direct_interc direct_interc_143_ + ( + .in(grid_clb_36_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_143_out) + ); + direct_interc direct_interc_144_ + ( + .in(grid_clb_37_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_144_out) + ); + direct_interc direct_interc_145_ + ( + .in(grid_clb_38_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_145_out) + ); + direct_interc direct_interc_146_ + ( + .in(grid_clb_39_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_146_out) + ); + direct_interc direct_interc_147_ + ( + .in(grid_clb_41_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_147_out) + ); + direct_interc direct_interc_148_ + ( + .in(grid_clb_42_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_148_out) + ); + direct_interc direct_interc_149_ + ( + .in(grid_clb_43_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_149_out) + ); + direct_interc direct_interc_150_ + ( + .in(grid_clb_44_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_150_out) + ); + direct_interc direct_interc_151_ + ( + .in(grid_clb_45_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_151_out) + ); + direct_interc direct_interc_152_ + ( + .in(grid_clb_46_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_152_out) + ); + direct_interc direct_interc_153_ + ( + .in(grid_clb_47_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_153_out) + ); + direct_interc direct_interc_154_ + ( + .in(grid_clb_49_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_154_out) + ); + direct_interc direct_interc_155_ + ( + .in(grid_clb_50_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_155_out) + ); + direct_interc direct_interc_156_ + ( + .in(grid_clb_51_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_156_out) + ); + direct_interc direct_interc_157_ + ( + .in(grid_clb_52_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_157_out) + ); + direct_interc direct_interc_158_ + ( + .in(grid_clb_53_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_158_out) + ); + direct_interc direct_interc_159_ + ( + .in(grid_clb_54_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_159_out) + ); + direct_interc direct_interc_160_ + ( + .in(grid_clb_55_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_160_out) + ); + direct_interc direct_interc_161_ + ( + .in(grid_clb_57_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_161_out) + ); + direct_interc direct_interc_162_ + ( + .in(grid_clb_58_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_162_out) + ); + direct_interc direct_interc_163_ + ( + .in(grid_clb_59_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_163_out) + ); + direct_interc direct_interc_164_ + ( + .in(grid_clb_60_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_164_out) + ); + direct_interc direct_interc_165_ + ( + .in(grid_clb_61_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_165_out) + ); + direct_interc direct_interc_166_ + ( + .in(grid_clb_62_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_166_out) + ); + direct_interc direct_interc_167_ + ( + .in(grid_clb_63_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_167_out) + ); + direct_interc direct_interc_168_ + ( + .in(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_168_out) + ); + direct_interc direct_interc_169_ + ( + .in(grid_clb_8_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_169_out) + ); + direct_interc direct_interc_170_ + ( + .in(grid_clb_16_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_170_out) + ); + direct_interc direct_interc_171_ + ( + .in(grid_clb_24_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_171_out) + ); + direct_interc direct_interc_172_ + ( + .in(grid_clb_32_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_172_out) + ); + direct_interc direct_interc_173_ + ( + .in(grid_clb_40_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_173_out) + ); + direct_interc direct_interc_174_ + ( + .in(grid_clb_48_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .out(direct_interc_174_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_clb.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_clb.v new file mode 100644 index 0000000..cde4367 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_clb.v @@ -0,0 +1,226 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module grid_clb +( + pReset, + prog_clk, + Test_en, + top_width_0_height_0_subtile_0__pin_I0_0_, + top_width_0_height_0_subtile_0__pin_I0_1_, + top_width_0_height_0_subtile_0__pin_I0i_0_, + top_width_0_height_0_subtile_0__pin_I0i_1_, + top_width_0_height_0_subtile_0__pin_I1_0_, + top_width_0_height_0_subtile_0__pin_I1_1_, + top_width_0_height_0_subtile_0__pin_I1i_0_, + top_width_0_height_0_subtile_0__pin_I1i_1_, + top_width_0_height_0_subtile_0__pin_I2_0_, + top_width_0_height_0_subtile_0__pin_I2_1_, + top_width_0_height_0_subtile_0__pin_I2i_0_, + top_width_0_height_0_subtile_0__pin_I2i_1_, + top_width_0_height_0_subtile_0__pin_I3_0_, + top_width_0_height_0_subtile_0__pin_I3_1_, + top_width_0_height_0_subtile_0__pin_I3i_0_, + top_width_0_height_0_subtile_0__pin_I3i_1_, + top_width_0_height_0_subtile_0__pin_reg_in_0_, + top_width_0_height_0_subtile_0__pin_sc_in_0_, + top_width_0_height_0_subtile_0__pin_cin_0_, + right_width_0_height_0_subtile_0__pin_I4_0_, + right_width_0_height_0_subtile_0__pin_I4_1_, + right_width_0_height_0_subtile_0__pin_I4i_0_, + right_width_0_height_0_subtile_0__pin_I4i_1_, + right_width_0_height_0_subtile_0__pin_I5_0_, + right_width_0_height_0_subtile_0__pin_I5_1_, + right_width_0_height_0_subtile_0__pin_I5i_0_, + right_width_0_height_0_subtile_0__pin_I5i_1_, + right_width_0_height_0_subtile_0__pin_I6_0_, + right_width_0_height_0_subtile_0__pin_I6_1_, + right_width_0_height_0_subtile_0__pin_I6i_0_, + right_width_0_height_0_subtile_0__pin_I6i_1_, + right_width_0_height_0_subtile_0__pin_I7_0_, + right_width_0_height_0_subtile_0__pin_I7_1_, + right_width_0_height_0_subtile_0__pin_I7i_0_, + right_width_0_height_0_subtile_0__pin_I7i_1_, + left_width_0_height_0_subtile_0__pin_reset_0_, + left_width_0_height_0_subtile_0__pin_clk_0_, + ccff_head, + top_width_0_height_0_subtile_0__pin_O_0_, + top_width_0_height_0_subtile_0__pin_O_1_, + top_width_0_height_0_subtile_0__pin_O_2_, + top_width_0_height_0_subtile_0__pin_O_3_, + top_width_0_height_0_subtile_0__pin_O_4_, + top_width_0_height_0_subtile_0__pin_O_5_, + top_width_0_height_0_subtile_0__pin_O_6_, + top_width_0_height_0_subtile_0__pin_O_7_, + right_width_0_height_0_subtile_0__pin_O_8_, + right_width_0_height_0_subtile_0__pin_O_9_, + right_width_0_height_0_subtile_0__pin_O_10_, + right_width_0_height_0_subtile_0__pin_O_11_, + right_width_0_height_0_subtile_0__pin_O_12_, + right_width_0_height_0_subtile_0__pin_O_13_, + right_width_0_height_0_subtile_0__pin_O_14_, + right_width_0_height_0_subtile_0__pin_O_15_, + bottom_width_0_height_0_subtile_0__pin_reg_out_0_, + bottom_width_0_height_0_subtile_0__pin_sc_out_0_, + bottom_width_0_height_0_subtile_0__pin_cout_0_, + ccff_tail +); + + input pReset; + input prog_clk; + input Test_en; + input top_width_0_height_0_subtile_0__pin_I0_0_; + input top_width_0_height_0_subtile_0__pin_I0_1_; + input top_width_0_height_0_subtile_0__pin_I0i_0_; + input top_width_0_height_0_subtile_0__pin_I0i_1_; + input top_width_0_height_0_subtile_0__pin_I1_0_; + input top_width_0_height_0_subtile_0__pin_I1_1_; + input top_width_0_height_0_subtile_0__pin_I1i_0_; + input top_width_0_height_0_subtile_0__pin_I1i_1_; + input top_width_0_height_0_subtile_0__pin_I2_0_; + input top_width_0_height_0_subtile_0__pin_I2_1_; + input top_width_0_height_0_subtile_0__pin_I2i_0_; + input top_width_0_height_0_subtile_0__pin_I2i_1_; + input top_width_0_height_0_subtile_0__pin_I3_0_; + input top_width_0_height_0_subtile_0__pin_I3_1_; + input top_width_0_height_0_subtile_0__pin_I3i_0_; + input top_width_0_height_0_subtile_0__pin_I3i_1_; + input top_width_0_height_0_subtile_0__pin_reg_in_0_; + input top_width_0_height_0_subtile_0__pin_sc_in_0_; + input top_width_0_height_0_subtile_0__pin_cin_0_; + input right_width_0_height_0_subtile_0__pin_I4_0_; + input right_width_0_height_0_subtile_0__pin_I4_1_; + input right_width_0_height_0_subtile_0__pin_I4i_0_; + input right_width_0_height_0_subtile_0__pin_I4i_1_; + input right_width_0_height_0_subtile_0__pin_I5_0_; + input right_width_0_height_0_subtile_0__pin_I5_1_; + input right_width_0_height_0_subtile_0__pin_I5i_0_; + input right_width_0_height_0_subtile_0__pin_I5i_1_; + input right_width_0_height_0_subtile_0__pin_I6_0_; + input right_width_0_height_0_subtile_0__pin_I6_1_; + input right_width_0_height_0_subtile_0__pin_I6i_0_; + input right_width_0_height_0_subtile_0__pin_I6i_1_; + input right_width_0_height_0_subtile_0__pin_I7_0_; + input right_width_0_height_0_subtile_0__pin_I7_1_; + input right_width_0_height_0_subtile_0__pin_I7i_0_; + input right_width_0_height_0_subtile_0__pin_I7i_1_; + input left_width_0_height_0_subtile_0__pin_reset_0_; + input left_width_0_height_0_subtile_0__pin_clk_0_; + input ccff_head; + output top_width_0_height_0_subtile_0__pin_O_0_; + output top_width_0_height_0_subtile_0__pin_O_1_; + output top_width_0_height_0_subtile_0__pin_O_2_; + output top_width_0_height_0_subtile_0__pin_O_3_; + output top_width_0_height_0_subtile_0__pin_O_4_; + output top_width_0_height_0_subtile_0__pin_O_5_; + output top_width_0_height_0_subtile_0__pin_O_6_; + output top_width_0_height_0_subtile_0__pin_O_7_; + output right_width_0_height_0_subtile_0__pin_O_8_; + output right_width_0_height_0_subtile_0__pin_O_9_; + output right_width_0_height_0_subtile_0__pin_O_10_; + output right_width_0_height_0_subtile_0__pin_O_11_; + output right_width_0_height_0_subtile_0__pin_O_12_; + output right_width_0_height_0_subtile_0__pin_O_13_; + output right_width_0_height_0_subtile_0__pin_O_14_; + output right_width_0_height_0_subtile_0__pin_O_15_; + output bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + output bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + output bottom_width_0_height_0_subtile_0__pin_cout_0_; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire Test_en; + wire top_width_0_height_0_subtile_0__pin_I0_0_; + wire top_width_0_height_0_subtile_0__pin_I0_1_; + wire top_width_0_height_0_subtile_0__pin_I0i_0_; + wire top_width_0_height_0_subtile_0__pin_I0i_1_; + wire top_width_0_height_0_subtile_0__pin_I1_0_; + wire top_width_0_height_0_subtile_0__pin_I1_1_; + wire top_width_0_height_0_subtile_0__pin_I1i_0_; + wire top_width_0_height_0_subtile_0__pin_I1i_1_; + wire top_width_0_height_0_subtile_0__pin_I2_0_; + wire top_width_0_height_0_subtile_0__pin_I2_1_; + wire top_width_0_height_0_subtile_0__pin_I2i_0_; + wire top_width_0_height_0_subtile_0__pin_I2i_1_; + wire top_width_0_height_0_subtile_0__pin_I3_0_; + wire top_width_0_height_0_subtile_0__pin_I3_1_; + wire top_width_0_height_0_subtile_0__pin_I3i_0_; + wire top_width_0_height_0_subtile_0__pin_I3i_1_; + wire top_width_0_height_0_subtile_0__pin_reg_in_0_; + wire top_width_0_height_0_subtile_0__pin_sc_in_0_; + wire top_width_0_height_0_subtile_0__pin_cin_0_; + wire right_width_0_height_0_subtile_0__pin_I4_0_; + wire right_width_0_height_0_subtile_0__pin_I4_1_; + wire right_width_0_height_0_subtile_0__pin_I4i_0_; + wire right_width_0_height_0_subtile_0__pin_I4i_1_; + wire right_width_0_height_0_subtile_0__pin_I5_0_; + wire right_width_0_height_0_subtile_0__pin_I5_1_; + wire right_width_0_height_0_subtile_0__pin_I5i_0_; + wire right_width_0_height_0_subtile_0__pin_I5i_1_; + wire right_width_0_height_0_subtile_0__pin_I6_0_; + wire right_width_0_height_0_subtile_0__pin_I6_1_; + wire right_width_0_height_0_subtile_0__pin_I6i_0_; + wire right_width_0_height_0_subtile_0__pin_I6i_1_; + wire right_width_0_height_0_subtile_0__pin_I7_0_; + wire right_width_0_height_0_subtile_0__pin_I7_1_; + wire right_width_0_height_0_subtile_0__pin_I7i_0_; + wire right_width_0_height_0_subtile_0__pin_I7i_1_; + wire left_width_0_height_0_subtile_0__pin_reset_0_; + wire left_width_0_height_0_subtile_0__pin_clk_0_; + wire ccff_head; + wire top_width_0_height_0_subtile_0__pin_O_0_; + wire top_width_0_height_0_subtile_0__pin_O_1_; + wire top_width_0_height_0_subtile_0__pin_O_2_; + wire top_width_0_height_0_subtile_0__pin_O_3_; + wire top_width_0_height_0_subtile_0__pin_O_4_; + wire top_width_0_height_0_subtile_0__pin_O_5_; + wire top_width_0_height_0_subtile_0__pin_O_6_; + wire top_width_0_height_0_subtile_0__pin_O_7_; + wire right_width_0_height_0_subtile_0__pin_O_8_; + wire right_width_0_height_0_subtile_0__pin_O_9_; + wire right_width_0_height_0_subtile_0__pin_O_10_; + wire right_width_0_height_0_subtile_0__pin_O_11_; + wire right_width_0_height_0_subtile_0__pin_O_12_; + wire right_width_0_height_0_subtile_0__pin_O_13_; + wire right_width_0_height_0_subtile_0__pin_O_14_; + wire right_width_0_height_0_subtile_0__pin_O_15_; + wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_; + wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_; + wire bottom_width_0_height_0_subtile_0__pin_cout_0_; + wire ccff_tail; + + logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}), + .clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}), + .clb_I1({top_width_0_height_0_subtile_0__pin_I1_0_, top_width_0_height_0_subtile_0__pin_I1_1_}), + .clb_I1i({top_width_0_height_0_subtile_0__pin_I1i_0_, top_width_0_height_0_subtile_0__pin_I1i_1_}), + .clb_I2({top_width_0_height_0_subtile_0__pin_I2_0_, top_width_0_height_0_subtile_0__pin_I2_1_}), + .clb_I2i({top_width_0_height_0_subtile_0__pin_I2i_0_, top_width_0_height_0_subtile_0__pin_I2i_1_}), + .clb_I3({top_width_0_height_0_subtile_0__pin_I3_0_, top_width_0_height_0_subtile_0__pin_I3_1_}), + .clb_I3i({top_width_0_height_0_subtile_0__pin_I3i_0_, top_width_0_height_0_subtile_0__pin_I3i_1_}), + .clb_I4({right_width_0_height_0_subtile_0__pin_I4_0_, right_width_0_height_0_subtile_0__pin_I4_1_}), + .clb_I4i({right_width_0_height_0_subtile_0__pin_I4i_0_, right_width_0_height_0_subtile_0__pin_I4i_1_}), + .clb_I5({right_width_0_height_0_subtile_0__pin_I5_0_, right_width_0_height_0_subtile_0__pin_I5_1_}), + .clb_I5i({right_width_0_height_0_subtile_0__pin_I5i_0_, right_width_0_height_0_subtile_0__pin_I5i_1_}), + .clb_I6({right_width_0_height_0_subtile_0__pin_I6_0_, right_width_0_height_0_subtile_0__pin_I6_1_}), + .clb_I6i({right_width_0_height_0_subtile_0__pin_I6i_0_, right_width_0_height_0_subtile_0__pin_I6i_1_}), + .clb_I7({right_width_0_height_0_subtile_0__pin_I7_0_, right_width_0_height_0_subtile_0__pin_I7_1_}), + .clb_I7i({right_width_0_height_0_subtile_0__pin_I7i_0_, right_width_0_height_0_subtile_0__pin_I7i_1_}), + .clb_reg_in(top_width_0_height_0_subtile_0__pin_reg_in_0_), + .clb_sc_in(top_width_0_height_0_subtile_0__pin_sc_in_0_), + .clb_cin(top_width_0_height_0_subtile_0__pin_cin_0_), + .clb_reset(left_width_0_height_0_subtile_0__pin_reset_0_), + .clb_clk(left_width_0_height_0_subtile_0__pin_clk_0_), + .ccff_head(ccff_head), + .clb_O({top_width_0_height_0_subtile_0__pin_O_0_, top_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, top_width_0_height_0_subtile_0__pin_O_3_, top_width_0_height_0_subtile_0__pin_O_4_, top_width_0_height_0_subtile_0__pin_O_5_, top_width_0_height_0_subtile_0__pin_O_6_, top_width_0_height_0_subtile_0__pin_O_7_, right_width_0_height_0_subtile_0__pin_O_8_, right_width_0_height_0_subtile_0__pin_O_9_, right_width_0_height_0_subtile_0__pin_O_10_, right_width_0_height_0_subtile_0__pin_O_11_, right_width_0_height_0_subtile_0__pin_O_12_, right_width_0_height_0_subtile_0__pin_O_13_, right_width_0_height_0_subtile_0__pin_O_14_, right_width_0_height_0_subtile_0__pin_O_15_}), + .clb_reg_out(bottom_width_0_height_0_subtile_0__pin_reg_out_0_), + .clb_sc_out(bottom_width_0_height_0_subtile_0__pin_sc_out_0_), + .clb_cout(bottom_width_0_height_0_subtile_0__pin_cout_0_), + .ccff_tail(ccff_tail) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_bottom_bottom.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_bottom_bottom.v new file mode 100644 index 0000000..053e8b5 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_bottom_bottom.v @@ -0,0 +1,113 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module grid_io_bottom_bottom +( + IO_ISOL_N, + pReset, + prog_clk, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + top_width_0_height_0_subtile_0__pin_outpad_0_, + top_width_0_height_0_subtile_1__pin_outpad_0_, + top_width_0_height_0_subtile_2__pin_outpad_0_, + top_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_head, + top_width_0_height_0_subtile_0__pin_inpad_0_, + top_width_0_height_0_subtile_1__pin_inpad_0_, + top_width_0_height_0_subtile_2__pin_inpad_0_, + top_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail +); + + input IO_ISOL_N; + input pReset; + input prog_clk; + input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + input top_width_0_height_0_subtile_0__pin_outpad_0_; + input top_width_0_height_0_subtile_1__pin_outpad_0_; + input top_width_0_height_0_subtile_2__pin_outpad_0_; + input top_width_0_height_0_subtile_3__pin_outpad_0_; + input ccff_head; + output top_width_0_height_0_subtile_0__pin_inpad_0_; + output top_width_0_height_0_subtile_1__pin_inpad_0_; + output top_width_0_height_0_subtile_2__pin_inpad_0_; + output top_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + + wire IO_ISOL_N; + wire pReset; + wire prog_clk; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire top_width_0_height_0_subtile_0__pin_outpad_0_; + wire top_width_0_height_0_subtile_1__pin_outpad_0_; + wire top_width_0_height_0_subtile_2__pin_outpad_0_; + wire top_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_head; + wire top_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_tail; + wire logical_tile_io_mode_io__0_ccff_tail; + wire logical_tile_io_mode_io__1_ccff_tail; + wire logical_tile_io_mode_io__2_ccff_tail; + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]), + .io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]), + .io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]), + .io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]), + .io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_left_left.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_left_left.v new file mode 100644 index 0000000..5d235de --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_left_left.v @@ -0,0 +1,113 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module grid_io_left_left +( + IO_ISOL_N, + pReset, + prog_clk, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + right_width_0_height_0_subtile_0__pin_outpad_0_, + right_width_0_height_0_subtile_1__pin_outpad_0_, + right_width_0_height_0_subtile_2__pin_outpad_0_, + right_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_head, + right_width_0_height_0_subtile_0__pin_inpad_0_, + right_width_0_height_0_subtile_1__pin_inpad_0_, + right_width_0_height_0_subtile_2__pin_inpad_0_, + right_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail +); + + input IO_ISOL_N; + input pReset; + input prog_clk; + input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + input right_width_0_height_0_subtile_0__pin_outpad_0_; + input right_width_0_height_0_subtile_1__pin_outpad_0_; + input right_width_0_height_0_subtile_2__pin_outpad_0_; + input right_width_0_height_0_subtile_3__pin_outpad_0_; + input ccff_head; + output right_width_0_height_0_subtile_0__pin_inpad_0_; + output right_width_0_height_0_subtile_1__pin_inpad_0_; + output right_width_0_height_0_subtile_2__pin_inpad_0_; + output right_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + + wire IO_ISOL_N; + wire pReset; + wire prog_clk; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire right_width_0_height_0_subtile_0__pin_outpad_0_; + wire right_width_0_height_0_subtile_1__pin_outpad_0_; + wire right_width_0_height_0_subtile_2__pin_outpad_0_; + wire right_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_head; + wire right_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_tail; + wire logical_tile_io_mode_io__0_ccff_tail; + wire logical_tile_io_mode_io__1_ccff_tail; + wire logical_tile_io_mode_io__2_ccff_tail; + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]), + .io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]), + .io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]), + .io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]), + .io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_right_right.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_right_right.v new file mode 100644 index 0000000..42d3271 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_right_right.v @@ -0,0 +1,113 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module grid_io_right_right +( + IO_ISOL_N, + pReset, + prog_clk, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + left_width_0_height_0_subtile_0__pin_outpad_0_, + left_width_0_height_0_subtile_1__pin_outpad_0_, + left_width_0_height_0_subtile_2__pin_outpad_0_, + left_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_head, + left_width_0_height_0_subtile_0__pin_inpad_0_, + left_width_0_height_0_subtile_1__pin_inpad_0_, + left_width_0_height_0_subtile_2__pin_inpad_0_, + left_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail +); + + input IO_ISOL_N; + input pReset; + input prog_clk; + input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + input left_width_0_height_0_subtile_0__pin_outpad_0_; + input left_width_0_height_0_subtile_1__pin_outpad_0_; + input left_width_0_height_0_subtile_2__pin_outpad_0_; + input left_width_0_height_0_subtile_3__pin_outpad_0_; + input ccff_head; + output left_width_0_height_0_subtile_0__pin_inpad_0_; + output left_width_0_height_0_subtile_1__pin_inpad_0_; + output left_width_0_height_0_subtile_2__pin_inpad_0_; + output left_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + + wire IO_ISOL_N; + wire pReset; + wire prog_clk; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire left_width_0_height_0_subtile_0__pin_outpad_0_; + wire left_width_0_height_0_subtile_1__pin_outpad_0_; + wire left_width_0_height_0_subtile_2__pin_outpad_0_; + wire left_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_head; + wire left_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_tail; + wire logical_tile_io_mode_io__0_ccff_tail; + wire logical_tile_io_mode_io__1_ccff_tail; + wire logical_tile_io_mode_io__2_ccff_tail; + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]), + .io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]), + .io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]), + .io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]), + .io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_top_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_top_top.v new file mode 100644 index 0000000..b2f5320 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_top_top.v @@ -0,0 +1,113 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module grid_io_top_top +( + IO_ISOL_N, + pReset, + prog_clk, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + bottom_width_0_height_0_subtile_0__pin_outpad_0_, + bottom_width_0_height_0_subtile_1__pin_outpad_0_, + bottom_width_0_height_0_subtile_2__pin_outpad_0_, + bottom_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_head, + bottom_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_tail +); + + input IO_ISOL_N; + input pReset; + input prog_clk; + input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + input bottom_width_0_height_0_subtile_0__pin_outpad_0_; + input bottom_width_0_height_0_subtile_1__pin_outpad_0_; + input bottom_width_0_height_0_subtile_2__pin_outpad_0_; + input bottom_width_0_height_0_subtile_3__pin_outpad_0_; + input ccff_head; + output bottom_width_0_height_0_subtile_0__pin_inpad_0_; + output bottom_width_0_height_0_subtile_1__pin_inpad_0_; + output bottom_width_0_height_0_subtile_2__pin_inpad_0_; + output bottom_width_0_height_0_subtile_3__pin_inpad_0_; + output ccff_tail; + + wire IO_ISOL_N; + wire pReset; + wire prog_clk; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_head; + wire bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_tail; + wire logical_tile_io_mode_io__0_ccff_tail; + wire logical_tile_io_mode_io__1_ccff_tail; + wire logical_tile_io_mode_io__2_ccff_tail; + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]), + .io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]), + .io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]), + .io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail) + ); + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]), + .io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(ccff_tail) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_clb_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_clb_.v new file mode 100644 index 0000000..8b2da1e --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_clb_.v @@ -0,0 +1,810 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_clb_ +( + pReset, + prog_clk, + Test_en, + clb_I0, + clb_I0i, + clb_I1, + clb_I1i, + clb_I2, + clb_I2i, + clb_I3, + clb_I3i, + clb_I4, + clb_I4i, + clb_I5, + clb_I5i, + clb_I6, + clb_I6i, + clb_I7, + clb_I7i, + clb_reg_in, + clb_sc_in, + clb_cin, + clb_reset, + clb_clk, + ccff_head, + clb_O, + clb_reg_out, + clb_sc_out, + clb_cout, + ccff_tail +); + + input pReset; + input prog_clk; + input Test_en; + input [0:1]clb_I0; + input [0:1]clb_I0i; + input [0:1]clb_I1; + input [0:1]clb_I1i; + input [0:1]clb_I2; + input [0:1]clb_I2i; + input [0:1]clb_I3; + input [0:1]clb_I3i; + input [0:1]clb_I4; + input [0:1]clb_I4i; + input [0:1]clb_I5; + input [0:1]clb_I5i; + input [0:1]clb_I6; + input [0:1]clb_I6i; + input [0:1]clb_I7; + input [0:1]clb_I7i; + input clb_reg_in; + input clb_sc_in; + input clb_cin; + input clb_reset; + input clb_clk; + input ccff_head; + output [0:15]clb_O; + output clb_reg_out; + output clb_sc_out; + output clb_cout; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire Test_en; + wire [0:1]clb_I0; + wire [0:1]clb_I0i; + wire [0:1]clb_I1; + wire [0:1]clb_I1i; + wire [0:1]clb_I2; + wire [0:1]clb_I2i; + wire [0:1]clb_I3; + wire [0:1]clb_I3i; + wire [0:1]clb_I4; + wire [0:1]clb_I4i; + wire [0:1]clb_I5; + wire [0:1]clb_I5i; + wire [0:1]clb_I6; + wire [0:1]clb_I6i; + wire [0:1]clb_I7; + wire [0:1]clb_I7i; + wire clb_reg_in; + wire clb_sc_in; + wire clb_cin; + wire clb_reset; + wire clb_clk; + wire ccff_head; + wire [0:15]clb_O; + wire clb_reg_out; + wire clb_sc_out; + wire clb_cout; + wire ccff_tail; + wire direct_interc_19_out; + wire direct_interc_20_out; + wire direct_interc_21_out; + wire direct_interc_22_out; + wire direct_interc_23_out; + wire direct_interc_24_out; + wire direct_interc_25_out; + wire direct_interc_26_out; + wire direct_interc_27_out; + wire direct_interc_28_out; + wire direct_interc_29_out; + wire direct_interc_30_out; + wire direct_interc_31_out; + wire direct_interc_32_out; + wire direct_interc_33_out; + wire direct_interc_34_out; + wire direct_interc_35_out; + wire direct_interc_36_out; + wire direct_interc_37_out; + wire direct_interc_38_out; + wire direct_interc_39_out; + wire direct_interc_40_out; + wire direct_interc_41_out; + wire direct_interc_42_out; + wire direct_interc_43_out; + wire direct_interc_44_out; + wire direct_interc_45_out; + wire direct_interc_46_out; + wire direct_interc_47_out; + wire direct_interc_48_out; + wire direct_interc_49_out; + wire direct_interc_50_out; + wire direct_interc_51_out; + wire direct_interc_52_out; + wire direct_interc_53_out; + wire direct_interc_54_out; + wire direct_interc_55_out; + wire direct_interc_56_out; + wire direct_interc_57_out; + wire direct_interc_58_out; + wire direct_interc_59_out; + wire direct_interc_60_out; + wire direct_interc_61_out; + wire direct_interc_62_out; + wire direct_interc_63_out; + wire direct_interc_64_out; + wire direct_interc_65_out; + wire direct_interc_66_out; + wire direct_interc_67_out; + wire direct_interc_68_out; + wire direct_interc_69_out; + wire direct_interc_70_out; + wire direct_interc_71_out; + wire direct_interc_72_out; + wire direct_interc_73_out; + wire direct_interc_74_out; + wire direct_interc_75_out; + wire direct_interc_76_out; + wire direct_interc_77_out; + wire direct_interc_78_out; + wire direct_interc_79_out; + wire direct_interc_80_out; + wire direct_interc_81_out; + wire direct_interc_82_out; + wire direct_interc_83_out; + wire direct_interc_84_out; + wire direct_interc_85_out; + wire direct_interc_86_out; + wire direct_interc_87_out; + wire direct_interc_88_out; + wire direct_interc_89_out; + wire direct_interc_90_out; + wire logical_tile_clb_mode_default__fle_0_ccff_tail; + wire logical_tile_clb_mode_default__fle_0_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_0_fle_out; + wire logical_tile_clb_mode_default__fle_0_fle_reg_out; + wire logical_tile_clb_mode_default__fle_0_fle_sc_out; + wire logical_tile_clb_mode_default__fle_1_ccff_tail; + wire logical_tile_clb_mode_default__fle_1_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_1_fle_out; + wire logical_tile_clb_mode_default__fle_1_fle_reg_out; + wire logical_tile_clb_mode_default__fle_1_fle_sc_out; + wire logical_tile_clb_mode_default__fle_2_ccff_tail; + wire logical_tile_clb_mode_default__fle_2_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_2_fle_out; + wire logical_tile_clb_mode_default__fle_2_fle_reg_out; + wire logical_tile_clb_mode_default__fle_2_fle_sc_out; + wire logical_tile_clb_mode_default__fle_3_ccff_tail; + wire logical_tile_clb_mode_default__fle_3_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_3_fle_out; + wire logical_tile_clb_mode_default__fle_3_fle_reg_out; + wire logical_tile_clb_mode_default__fle_3_fle_sc_out; + wire logical_tile_clb_mode_default__fle_4_ccff_tail; + wire logical_tile_clb_mode_default__fle_4_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_4_fle_out; + wire logical_tile_clb_mode_default__fle_4_fle_reg_out; + wire logical_tile_clb_mode_default__fle_4_fle_sc_out; + wire logical_tile_clb_mode_default__fle_5_ccff_tail; + wire logical_tile_clb_mode_default__fle_5_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_5_fle_out; + wire logical_tile_clb_mode_default__fle_5_fle_reg_out; + wire logical_tile_clb_mode_default__fle_5_fle_sc_out; + wire logical_tile_clb_mode_default__fle_6_ccff_tail; + wire logical_tile_clb_mode_default__fle_6_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_6_fle_out; + wire logical_tile_clb_mode_default__fle_6_fle_reg_out; + wire logical_tile_clb_mode_default__fle_6_fle_sc_out; + wire logical_tile_clb_mode_default__fle_7_fle_cout; + wire [0:1]logical_tile_clb_mode_default__fle_7_fle_out; + wire logical_tile_clb_mode_default__fle_7_fle_reg_out; + wire logical_tile_clb_mode_default__fle_7_fle_sc_out; + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_19_out, direct_interc_20_out, direct_interc_21_out, direct_interc_22_out}), + .fle_reg_in(direct_interc_23_out), + .fle_sc_in(direct_interc_24_out), + .fle_cin(direct_interc_25_out), + .fle_reset(direct_interc_26_out), + .fle_clk(direct_interc_27_out), + .ccff_head(ccff_head), + .fle_out(logical_tile_clb_mode_default__fle_0_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_0_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_0_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_0_fle_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_28_out, direct_interc_29_out, direct_interc_30_out, direct_interc_31_out}), + .fle_reg_in(direct_interc_32_out), + .fle_sc_in(direct_interc_33_out), + .fle_cin(direct_interc_34_out), + .fle_reset(direct_interc_35_out), + .fle_clk(direct_interc_36_out), + .ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_1_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_1_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_1_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_1_fle_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_37_out, direct_interc_38_out, direct_interc_39_out, direct_interc_40_out}), + .fle_reg_in(direct_interc_41_out), + .fle_sc_in(direct_interc_42_out), + .fle_cin(direct_interc_43_out), + .fle_reset(direct_interc_44_out), + .fle_clk(direct_interc_45_out), + .ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_2_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_2_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_2_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_2_fle_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_46_out, direct_interc_47_out, direct_interc_48_out, direct_interc_49_out}), + .fle_reg_in(direct_interc_50_out), + .fle_sc_in(direct_interc_51_out), + .fle_cin(direct_interc_52_out), + .fle_reset(direct_interc_53_out), + .fle_clk(direct_interc_54_out), + .ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_3_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_3_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_3_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_3_fle_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_55_out, direct_interc_56_out, direct_interc_57_out, direct_interc_58_out}), + .fle_reg_in(direct_interc_59_out), + .fle_sc_in(direct_interc_60_out), + .fle_cin(direct_interc_61_out), + .fle_reset(direct_interc_62_out), + .fle_clk(direct_interc_63_out), + .ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_4_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_4_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_4_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_4_fle_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_64_out, direct_interc_65_out, direct_interc_66_out, direct_interc_67_out}), + .fle_reg_in(direct_interc_68_out), + .fle_sc_in(direct_interc_69_out), + .fle_cin(direct_interc_70_out), + .fle_reset(direct_interc_71_out), + .fle_clk(direct_interc_72_out), + .ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_5_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_5_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_5_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_5_fle_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_73_out, direct_interc_74_out, direct_interc_75_out, direct_interc_76_out}), + .fle_reg_in(direct_interc_77_out), + .fle_sc_in(direct_interc_78_out), + .fle_cin(direct_interc_79_out), + .fle_reset(direct_interc_80_out), + .fle_clk(direct_interc_81_out), + .ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_6_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_6_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_6_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_6_fle_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail) + ); + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fle_in({direct_interc_82_out, direct_interc_83_out, direct_interc_84_out, direct_interc_85_out}), + .fle_reg_in(direct_interc_86_out), + .fle_sc_in(direct_interc_87_out), + .fle_cin(direct_interc_88_out), + .fle_reset(direct_interc_89_out), + .fle_clk(direct_interc_90_out), + .ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_7_fle_out), + .fle_reg_out(logical_tile_clb_mode_default__fle_7_fle_reg_out), + .fle_sc_out(logical_tile_clb_mode_default__fle_7_fle_sc_out), + .fle_cout(logical_tile_clb_mode_default__fle_7_fle_cout), + .ccff_tail(ccff_tail) + ); + direct_interc direct_interc_0_ + ( + .in(logical_tile_clb_mode_default__fle_0_fle_out[1]), + .out(clb_O[0]) + ); + direct_interc direct_interc_1_ + ( + .in(logical_tile_clb_mode_default__fle_0_fle_out[0]), + .out(clb_O[1]) + ); + direct_interc direct_interc_2_ + ( + .in(logical_tile_clb_mode_default__fle_1_fle_out[1]), + .out(clb_O[2]) + ); + direct_interc direct_interc_3_ + ( + .in(logical_tile_clb_mode_default__fle_1_fle_out[0]), + .out(clb_O[3]) + ); + direct_interc direct_interc_4_ + ( + .in(logical_tile_clb_mode_default__fle_2_fle_out[1]), + .out(clb_O[4]) + ); + direct_interc direct_interc_5_ + ( + .in(logical_tile_clb_mode_default__fle_2_fle_out[0]), + .out(clb_O[5]) + ); + direct_interc direct_interc_6_ + ( + .in(logical_tile_clb_mode_default__fle_3_fle_out[1]), + .out(clb_O[6]) + ); + direct_interc direct_interc_7_ + ( + .in(logical_tile_clb_mode_default__fle_3_fle_out[0]), + .out(clb_O[7]) + ); + direct_interc direct_interc_8_ + ( + .in(logical_tile_clb_mode_default__fle_4_fle_out[1]), + .out(clb_O[8]) + ); + direct_interc direct_interc_9_ + ( + .in(logical_tile_clb_mode_default__fle_4_fle_out[0]), + .out(clb_O[9]) + ); + direct_interc direct_interc_10_ + ( + .in(logical_tile_clb_mode_default__fle_5_fle_out[1]), + .out(clb_O[10]) + ); + direct_interc direct_interc_11_ + ( + .in(logical_tile_clb_mode_default__fle_5_fle_out[0]), + .out(clb_O[11]) + ); + direct_interc direct_interc_12_ + ( + .in(logical_tile_clb_mode_default__fle_6_fle_out[1]), + .out(clb_O[12]) + ); + direct_interc direct_interc_13_ + ( + .in(logical_tile_clb_mode_default__fle_6_fle_out[0]), + .out(clb_O[13]) + ); + direct_interc direct_interc_14_ + ( + .in(logical_tile_clb_mode_default__fle_7_fle_out[1]), + .out(clb_O[14]) + ); + direct_interc direct_interc_15_ + ( + .in(logical_tile_clb_mode_default__fle_7_fle_out[0]), + .out(clb_O[15]) + ); + direct_interc direct_interc_16_ + ( + .in(logical_tile_clb_mode_default__fle_7_fle_reg_out), + .out(clb_reg_out) + ); + direct_interc direct_interc_17_ + ( + .in(logical_tile_clb_mode_default__fle_7_fle_sc_out), + .out(clb_sc_out) + ); + direct_interc direct_interc_18_ + ( + .in(logical_tile_clb_mode_default__fle_7_fle_cout), + .out(clb_cout) + ); + direct_interc direct_interc_19_ + ( + .in(clb_I0[0]), + .out(direct_interc_19_out) + ); + direct_interc direct_interc_20_ + ( + .in(clb_I0[1]), + .out(direct_interc_20_out) + ); + direct_interc direct_interc_21_ + ( + .in(clb_I0i[0]), + .out(direct_interc_21_out) + ); + direct_interc direct_interc_22_ + ( + .in(clb_I0i[1]), + .out(direct_interc_22_out) + ); + direct_interc direct_interc_23_ + ( + .in(clb_reg_in), + .out(direct_interc_23_out) + ); + direct_interc direct_interc_24_ + ( + .in(clb_sc_in), + .out(direct_interc_24_out) + ); + direct_interc direct_interc_25_ + ( + .in(clb_cin), + .out(direct_interc_25_out) + ); + direct_interc direct_interc_26_ + ( + .in(clb_reset), + .out(direct_interc_26_out) + ); + direct_interc direct_interc_27_ + ( + .in(clb_clk), + .out(direct_interc_27_out) + ); + direct_interc direct_interc_28_ + ( + .in(clb_I1[0]), + .out(direct_interc_28_out) + ); + direct_interc direct_interc_29_ + ( + .in(clb_I1[1]), + .out(direct_interc_29_out) + ); + direct_interc direct_interc_30_ + ( + .in(clb_I1i[0]), + .out(direct_interc_30_out) + ); + direct_interc direct_interc_31_ + ( + .in(clb_I1i[1]), + .out(direct_interc_31_out) + ); + direct_interc direct_interc_32_ + ( + .in(logical_tile_clb_mode_default__fle_0_fle_reg_out), + .out(direct_interc_32_out) + ); + direct_interc direct_interc_33_ + ( + .in(logical_tile_clb_mode_default__fle_0_fle_sc_out), + .out(direct_interc_33_out) + ); + direct_interc direct_interc_34_ + ( + .in(logical_tile_clb_mode_default__fle_0_fle_cout), + .out(direct_interc_34_out) + ); + direct_interc direct_interc_35_ + ( + .in(clb_reset), + .out(direct_interc_35_out) + ); + direct_interc direct_interc_36_ + ( + .in(clb_clk), + .out(direct_interc_36_out) + ); + direct_interc direct_interc_37_ + ( + .in(clb_I2[0]), + .out(direct_interc_37_out) + ); + direct_interc direct_interc_38_ + ( + .in(clb_I2[1]), + .out(direct_interc_38_out) + ); + direct_interc direct_interc_39_ + ( + .in(clb_I2i[0]), + .out(direct_interc_39_out) + ); + direct_interc direct_interc_40_ + ( + .in(clb_I2i[1]), + .out(direct_interc_40_out) + ); + direct_interc direct_interc_41_ + ( + .in(logical_tile_clb_mode_default__fle_1_fle_reg_out), + .out(direct_interc_41_out) + ); + direct_interc direct_interc_42_ + ( + .in(logical_tile_clb_mode_default__fle_1_fle_sc_out), + .out(direct_interc_42_out) + ); + direct_interc direct_interc_43_ + ( + .in(logical_tile_clb_mode_default__fle_1_fle_cout), + .out(direct_interc_43_out) + ); + direct_interc direct_interc_44_ + ( + .in(clb_reset), + .out(direct_interc_44_out) + ); + direct_interc direct_interc_45_ + ( + .in(clb_clk), + .out(direct_interc_45_out) + ); + direct_interc direct_interc_46_ + ( + .in(clb_I3[0]), + .out(direct_interc_46_out) + ); + direct_interc direct_interc_47_ + ( + .in(clb_I3[1]), + .out(direct_interc_47_out) + ); + direct_interc direct_interc_48_ + ( + .in(clb_I3i[0]), + .out(direct_interc_48_out) + ); + direct_interc direct_interc_49_ + ( + .in(clb_I3i[1]), + .out(direct_interc_49_out) + ); + direct_interc direct_interc_50_ + ( + .in(logical_tile_clb_mode_default__fle_2_fle_reg_out), + .out(direct_interc_50_out) + ); + direct_interc direct_interc_51_ + ( + .in(logical_tile_clb_mode_default__fle_2_fle_sc_out), + .out(direct_interc_51_out) + ); + direct_interc direct_interc_52_ + ( + .in(logical_tile_clb_mode_default__fle_2_fle_cout), + .out(direct_interc_52_out) + ); + direct_interc direct_interc_53_ + ( + .in(clb_reset), + .out(direct_interc_53_out) + ); + direct_interc direct_interc_54_ + ( + .in(clb_clk), + .out(direct_interc_54_out) + ); + direct_interc direct_interc_55_ + ( + .in(clb_I4[0]), + .out(direct_interc_55_out) + ); + direct_interc direct_interc_56_ + ( + .in(clb_I4[1]), + .out(direct_interc_56_out) + ); + direct_interc direct_interc_57_ + ( + .in(clb_I4i[0]), + .out(direct_interc_57_out) + ); + direct_interc direct_interc_58_ + ( + .in(clb_I4i[1]), + .out(direct_interc_58_out) + ); + direct_interc direct_interc_59_ + ( + .in(logical_tile_clb_mode_default__fle_3_fle_reg_out), + .out(direct_interc_59_out) + ); + direct_interc direct_interc_60_ + ( + .in(logical_tile_clb_mode_default__fle_3_fle_sc_out), + .out(direct_interc_60_out) + ); + direct_interc direct_interc_61_ + ( + .in(logical_tile_clb_mode_default__fle_3_fle_cout), + .out(direct_interc_61_out) + ); + direct_interc direct_interc_62_ + ( + .in(clb_reset), + .out(direct_interc_62_out) + ); + direct_interc direct_interc_63_ + ( + .in(clb_clk), + .out(direct_interc_63_out) + ); + direct_interc direct_interc_64_ + ( + .in(clb_I5[0]), + .out(direct_interc_64_out) + ); + direct_interc direct_interc_65_ + ( + .in(clb_I5[1]), + .out(direct_interc_65_out) + ); + direct_interc direct_interc_66_ + ( + .in(clb_I5i[0]), + .out(direct_interc_66_out) + ); + direct_interc direct_interc_67_ + ( + .in(clb_I5i[1]), + .out(direct_interc_67_out) + ); + direct_interc direct_interc_68_ + ( + .in(logical_tile_clb_mode_default__fle_4_fle_reg_out), + .out(direct_interc_68_out) + ); + direct_interc direct_interc_69_ + ( + .in(logical_tile_clb_mode_default__fle_4_fle_sc_out), + .out(direct_interc_69_out) + ); + direct_interc direct_interc_70_ + ( + .in(logical_tile_clb_mode_default__fle_4_fle_cout), + .out(direct_interc_70_out) + ); + direct_interc direct_interc_71_ + ( + .in(clb_reset), + .out(direct_interc_71_out) + ); + direct_interc direct_interc_72_ + ( + .in(clb_clk), + .out(direct_interc_72_out) + ); + direct_interc direct_interc_73_ + ( + .in(clb_I6[0]), + .out(direct_interc_73_out) + ); + direct_interc direct_interc_74_ + ( + .in(clb_I6[1]), + .out(direct_interc_74_out) + ); + direct_interc direct_interc_75_ + ( + .in(clb_I6i[0]), + .out(direct_interc_75_out) + ); + direct_interc direct_interc_76_ + ( + .in(clb_I6i[1]), + .out(direct_interc_76_out) + ); + direct_interc direct_interc_77_ + ( + .in(logical_tile_clb_mode_default__fle_5_fle_reg_out), + .out(direct_interc_77_out) + ); + direct_interc direct_interc_78_ + ( + .in(logical_tile_clb_mode_default__fle_5_fle_sc_out), + .out(direct_interc_78_out) + ); + direct_interc direct_interc_79_ + ( + .in(logical_tile_clb_mode_default__fle_5_fle_cout), + .out(direct_interc_79_out) + ); + direct_interc direct_interc_80_ + ( + .in(clb_reset), + .out(direct_interc_80_out) + ); + direct_interc direct_interc_81_ + ( + .in(clb_clk), + .out(direct_interc_81_out) + ); + direct_interc direct_interc_82_ + ( + .in(clb_I7[0]), + .out(direct_interc_82_out) + ); + direct_interc direct_interc_83_ + ( + .in(clb_I7[1]), + .out(direct_interc_83_out) + ); + direct_interc direct_interc_84_ + ( + .in(clb_I7i[0]), + .out(direct_interc_84_out) + ); + direct_interc direct_interc_85_ + ( + .in(clb_I7i[1]), + .out(direct_interc_85_out) + ); + direct_interc direct_interc_86_ + ( + .in(logical_tile_clb_mode_default__fle_6_fle_reg_out), + .out(direct_interc_86_out) + ); + direct_interc direct_interc_87_ + ( + .in(logical_tile_clb_mode_default__fle_6_fle_sc_out), + .out(direct_interc_87_out) + ); + direct_interc direct_interc_88_ + ( + .in(logical_tile_clb_mode_default__fle_6_fle_cout), + .out(direct_interc_88_out) + ); + direct_interc direct_interc_89_ + ( + .in(clb_reset), + .out(direct_interc_89_out) + ); + direct_interc direct_interc_90_ + ( + .in(clb_clk), + .out(direct_interc_90_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle.v new file mode 100644 index 0000000..b19563a --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle.v @@ -0,0 +1,156 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle +( + pReset, + prog_clk, + Test_en, + fle_in, + fle_reg_in, + fle_sc_in, + fle_cin, + fle_reset, + fle_clk, + ccff_head, + fle_out, + fle_reg_out, + fle_sc_out, + fle_cout, + ccff_tail +); + + input pReset; + input prog_clk; + input Test_en; + input [0:3]fle_in; + input fle_reg_in; + input fle_sc_in; + input fle_cin; + input fle_reset; + input fle_clk; + input ccff_head; + output [0:1]fle_out; + output fle_reg_out; + output fle_sc_out; + output fle_cout; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire Test_en; + wire [0:3]fle_in; + wire fle_reg_in; + wire fle_sc_in; + wire fle_cin; + wire fle_reset; + wire fle_clk; + wire ccff_head; + wire [0:1]fle_out; + wire fle_reg_out; + wire fle_sc_out; + wire fle_cout; + wire ccff_tail; + wire direct_interc_10_out; + wire direct_interc_11_out; + wire direct_interc_12_out; + wire direct_interc_13_out; + wire direct_interc_5_out; + wire direct_interc_6_out; + wire direct_interc_7_out; + wire direct_interc_8_out; + wire direct_interc_9_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout; + wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out; + + logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .Test_en(Test_en), + .fabric_in({direct_interc_5_out, direct_interc_6_out, direct_interc_7_out, direct_interc_8_out}), + .fabric_reg_in(direct_interc_9_out), + .fabric_sc_in(direct_interc_10_out), + .fabric_cin(direct_interc_11_out), + .fabric_reset(direct_interc_12_out), + .fabric_clk(direct_interc_13_out), + .ccff_head(ccff_head), + .fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out), + .fabric_reg_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out), + .fabric_sc_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out), + .fabric_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout), + .ccff_tail(ccff_tail) + ); + direct_interc direct_interc_0_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0]), + .out(fle_out[0]) + ); + direct_interc direct_interc_1_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[1]), + .out(fle_out[1]) + ); + direct_interc direct_interc_2_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out), + .out(fle_reg_out) + ); + direct_interc direct_interc_3_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out), + .out(fle_sc_out) + ); + direct_interc direct_interc_4_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout), + .out(fle_cout) + ); + direct_interc direct_interc_5_ + ( + .in(fle_in[0]), + .out(direct_interc_5_out) + ); + direct_interc direct_interc_6_ + ( + .in(fle_in[1]), + .out(direct_interc_6_out) + ); + direct_interc direct_interc_7_ + ( + .in(fle_in[2]), + .out(direct_interc_7_out) + ); + direct_interc direct_interc_8_ + ( + .in(fle_in[3]), + .out(direct_interc_8_out) + ); + direct_interc direct_interc_9_ + ( + .in(fle_reg_in), + .out(direct_interc_9_out) + ); + direct_interc direct_interc_10_ + ( + .in(fle_sc_in), + .out(direct_interc_10_out) + ); + direct_interc direct_interc_11_ + ( + .in(fle_cin), + .out(direct_interc_11_out) + ); + direct_interc direct_interc_12_ + ( + .in(fle_reset), + .out(direct_interc_12_out) + ); + direct_interc direct_interc_13_ + ( + .in(fle_clk), + .out(direct_interc_13_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v new file mode 100644 index 0000000..817e939 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v @@ -0,0 +1,243 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle_mode_physical__fabric +( + pReset, + prog_clk, + Test_en, + fabric_in, + fabric_reg_in, + fabric_sc_in, + fabric_cin, + fabric_reset, + fabric_clk, + ccff_head, + fabric_out, + fabric_reg_out, + fabric_sc_out, + fabric_cout, + ccff_tail +); + + input pReset; + input prog_clk; + input Test_en; + input [0:3]fabric_in; + input fabric_reg_in; + input fabric_sc_in; + input fabric_cin; + input fabric_reset; + input fabric_clk; + input ccff_head; + output [0:1]fabric_out; + output fabric_reg_out; + output fabric_sc_out; + output fabric_cout; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire Test_en; + wire [0:3]fabric_in; + wire fabric_reg_in; + wire fabric_sc_in; + wire fabric_cin; + wire fabric_reset; + wire fabric_clk; + wire ccff_head; + wire [0:1]fabric_out; + wire fabric_reg_out; + wire fabric_sc_out; + wire fabric_cout; + wire ccff_tail; + wire direct_interc_10_out; + wire direct_interc_11_out; + wire direct_interc_12_out; + wire direct_interc_13_out; + wire direct_interc_3_out; + wire direct_interc_4_out; + wire direct_interc_5_out; + wire direct_interc_6_out; + wire direct_interc_7_out; + wire direct_interc_8_out; + wire direct_interc_9_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout; + wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out; + wire [0:1]mux_fabric_out_0_undriven_sram_inv; + wire [0:1]mux_fabric_out_1_undriven_sram_inv; + wire [0:1]mux_ff_0_D_0_undriven_sram_inv; + wire [0:1]mux_ff_1_D_0_undriven_sram_inv; + wire [0:1]mux_tree_size2_0_sram; + wire [0:1]mux_tree_size2_1_sram; + wire mux_tree_size2_2_out; + wire [0:1]mux_tree_size2_2_sram; + wire mux_tree_size2_3_out; + wire [0:1]mux_tree_size2_3_sram; + wire mux_tree_size2_mem_0_ccff_tail; + wire mux_tree_size2_mem_1_ccff_tail; + wire mux_tree_size2_mem_2_ccff_tail; + + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .frac_logic_in({direct_interc_3_out, direct_interc_4_out, direct_interc_5_out, direct_interc_6_out}), + .frac_logic_cin(direct_interc_7_out), + .ccff_head(ccff_head), + .frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out), + .frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout), + .ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail) + ); + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 + ( + .Test_en(Test_en), + .ff_D(mux_tree_size2_2_out), + .ff_DI(direct_interc_8_out), + .ff_reset(direct_interc_9_out), + .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q), + .ff_clk(direct_interc_10_out) + ); + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 + ( + .Test_en(Test_en), + .ff_D(mux_tree_size2_3_out), + .ff_DI(direct_interc_11_out), + .ff_reset(direct_interc_12_out), + .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q), + .ff_clk(direct_interc_13_out) + ); + mux_tree_size2 mux_fabric_out_0 + ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}), + .sram(mux_tree_size2_0_sram), + .sram_inv(mux_fabric_out_0_undriven_sram_inv), + .out(fabric_out[0]) + ); + mux_tree_size2 mux_fabric_out_1 + ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}), + .sram(mux_tree_size2_1_sram), + .sram_inv(mux_fabric_out_1_undriven_sram_inv), + .out(fabric_out[1]) + ); + mux_tree_size2 mux_ff_0_D_0 + ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_reg_in}), + .sram(mux_tree_size2_2_sram), + .sram_inv(mux_ff_0_D_0_undriven_sram_inv), + .out(mux_tree_size2_2_out) + ); + mux_tree_size2 mux_ff_1_D_0 + ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q}), + .sram(mux_tree_size2_3_sram), + .sram_inv(mux_ff_1_D_0_undriven_sram_inv), + .out(mux_tree_size2_3_out) + ); + mux_tree_size2_mem mem_fabric_out_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail), + .ccff_tail(mux_tree_size2_mem_0_ccff_tail), + .mem_out(mux_tree_size2_0_sram) + ); + mux_tree_size2_mem mem_fabric_out_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_size2_mem_1_ccff_tail), + .mem_out(mux_tree_size2_1_sram) + ); + mux_tree_size2_mem mem_ff_0_D_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_size2_mem_2_ccff_tail), + .mem_out(mux_tree_size2_2_sram) + ); + mux_tree_size2_mem mem_ff_1_D_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_size2_mem_2_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_size2_3_sram) + ); + direct_interc direct_interc_0_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q), + .out(fabric_reg_out) + ); + direct_interc direct_interc_1_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q), + .out(fabric_sc_out) + ); + direct_interc direct_interc_2_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout), + .out(fabric_cout) + ); + direct_interc direct_interc_3_ + ( + .in(fabric_in[0]), + .out(direct_interc_3_out) + ); + direct_interc direct_interc_4_ + ( + .in(fabric_in[1]), + .out(direct_interc_4_out) + ); + direct_interc direct_interc_5_ + ( + .in(fabric_in[2]), + .out(direct_interc_5_out) + ); + direct_interc direct_interc_6_ + ( + .in(fabric_in[3]), + .out(direct_interc_6_out) + ); + direct_interc direct_interc_7_ + ( + .in(fabric_cin), + .out(direct_interc_7_out) + ); + direct_interc direct_interc_8_ + ( + .in(fabric_sc_in), + .out(direct_interc_8_out) + ); + direct_interc direct_interc_9_ + ( + .in(fabric_reset), + .out(direct_interc_9_out) + ); + direct_interc direct_interc_10_ + ( + .in(fabric_clk), + .out(direct_interc_10_out) + ); + direct_interc direct_interc_11_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q), + .out(direct_interc_11_out) + ); + direct_interc direct_interc_12_ + ( + .in(fabric_reset), + .out(direct_interc_12_out) + ); + direct_interc direct_interc_13_ + ( + .in(fabric_clk), + .out(direct_interc_13_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v new file mode 100644 index 0000000..72a652c --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v @@ -0,0 +1,37 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff +( + Test_en, + ff_D, + ff_DI, + ff_reset, + ff_Q, + ff_clk +); + + input Test_en; + input ff_D; + input ff_DI; + input ff_reset; + output ff_Q; + input ff_clk; + + wire Test_en; + wire ff_D; + wire ff_DI; + wire ff_reset; + wire ff_Q; + wire ff_clk; + + sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ + ( + .SCE(Test_en), + .D(ff_D), + .SCD(ff_DI), + .RESET_B(ff_reset), + .CLK(ff_clk), + .Q(ff_Q) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v new file mode 100644 index 0000000..87e59c3 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v @@ -0,0 +1,139 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic +( + pReset, + prog_clk, + frac_logic_in, + frac_logic_cin, + ccff_head, + frac_logic_out, + frac_logic_cout, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:3]frac_logic_in; + input frac_logic_cin; + input ccff_head; + output [0:1]frac_logic_out; + output frac_logic_cout; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:3]frac_logic_in; + wire frac_logic_cin; + wire ccff_head; + wire [0:1]frac_logic_out; + wire frac_logic_cout; + wire ccff_tail; + wire direct_interc_2_out; + wire direct_interc_3_out; + wire direct_interc_4_out; + wire direct_interc_5_out; + wire direct_interc_6_out; + wire direct_interc_7_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail; + wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out; + wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out; + wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out; + wire [0:1]mux_frac_logic_out_0_undriven_sram_inv; + wire [0:1]mux_frac_lut4_0_in_2_undriven_sram_inv; + wire [0:1]mux_tree_size2_0_sram; + wire mux_tree_size2_1_out; + wire [0:1]mux_tree_size2_1_sram; + wire mux_tree_size2_mem_0_ccff_tail; + + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .frac_lut4_in({direct_interc_2_out, direct_interc_3_out, mux_tree_size2_1_out, direct_interc_4_out}), + .ccff_head(ccff_head), + .frac_lut4_lut2_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out), + .frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out), + .frac_lut4_lut4_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out), + .ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail) + ); + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 + ( + .carry_follower_a(direct_interc_5_out), + .carry_follower_b(direct_interc_6_out), + .carry_follower_cin(direct_interc_7_out), + .carry_follower_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout) + ); + mux_tree_size2 mux_frac_logic_out_0 + ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}), + .sram(mux_tree_size2_0_sram), + .sram_inv(mux_frac_logic_out_0_undriven_sram_inv), + .out(frac_logic_out[0]) + ); + mux_tree_size2 mux_frac_lut4_0_in_2 + ( + .in({frac_logic_cin, frac_logic_in[2]}), + .sram(mux_tree_size2_1_sram), + .sram_inv(mux_frac_lut4_0_in_2_undriven_sram_inv), + .out(mux_tree_size2_1_out) + ); + mux_tree_size2_mem mem_frac_logic_out_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail), + .ccff_tail(mux_tree_size2_mem_0_ccff_tail), + .mem_out(mux_tree_size2_0_sram) + ); + mux_tree_size2_mem mem_frac_lut4_0_in_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_size2_mem_0_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_size2_1_sram) + ); + direct_interc direct_interc_0_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]), + .out(frac_logic_out[1]) + ); + direct_interc direct_interc_1_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout), + .out(frac_logic_cout) + ); + direct_interc direct_interc_2_ + ( + .in(frac_logic_in[0]), + .out(direct_interc_2_out) + ); + direct_interc direct_interc_3_ + ( + .in(frac_logic_in[1]), + .out(direct_interc_3_out) + ); + direct_interc direct_interc_4_ + ( + .in(frac_logic_in[3]), + .out(direct_interc_4_out) + ); + direct_interc direct_interc_5_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[1]), + .out(direct_interc_5_out) + ); + direct_interc direct_interc_6_ + ( + .in(frac_logic_cin), + .out(direct_interc_6_out) + ); + direct_interc direct_interc_7_ + ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[0]), + .out(direct_interc_7_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v new file mode 100644 index 0000000..5264e03 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v @@ -0,0 +1,29 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower +( + carry_follower_a, + carry_follower_b, + carry_follower_cin, + carry_follower_cout +); + + input carry_follower_a; + input carry_follower_b; + input carry_follower_cin; + output carry_follower_cout; + + wire carry_follower_a; + wire carry_follower_b; + wire carry_follower_cin; + wire carry_follower_cout; + + sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_ + ( + .A0(carry_follower_a), + .A1(carry_follower_b), + .S(carry_follower_cin), + .X(carry_follower_cout) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v new file mode 100644 index 0000000..03b1192 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v @@ -0,0 +1,57 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 +( + pReset, + prog_clk, + frac_lut4_in, + ccff_head, + frac_lut4_lut2_out, + frac_lut4_lut3_out, + frac_lut4_lut4_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:3]frac_lut4_in; + input ccff_head; + output [0:1]frac_lut4_lut2_out; + output [0:1]frac_lut4_lut3_out; + output frac_lut4_lut4_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:3]frac_lut4_in; + wire ccff_head; + wire [0:1]frac_lut4_lut2_out; + wire [0:1]frac_lut4_lut3_out; + wire frac_lut4_lut4_out; + wire ccff_tail; + wire frac_lut4_0__undriven_mode_inv; + wire [0:15]frac_lut4_0__undriven_sram_inv; + wire frac_lut4_0_mode; + wire [0:15]frac_lut4_0_sram; + + frac_lut4 frac_lut4_0_ + ( + .in(frac_lut4_in), + .sram(frac_lut4_0_sram), + .sram_inv(frac_lut4_0__undriven_sram_inv), + .mode(frac_lut4_0_mode), + .mode_inv(frac_lut4_0__undriven_mode_inv), + .lut2_out(frac_lut4_lut2_out), + .lut3_out(frac_lut4_lut3_out), + .lut4_out(frac_lut4_lut4_out) + ); + frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(ccff_tail), + .mem_out({frac_lut4_0_sram[0], frac_lut4_0_sram[1], frac_lut4_0_sram[2], frac_lut4_0_sram[3], frac_lut4_0_sram[4], frac_lut4_0_sram[5], frac_lut4_0_sram[6], frac_lut4_0_sram[7], frac_lut4_0_sram[8], frac_lut4_0_sram[9], frac_lut4_0_sram[10], frac_lut4_0_sram[11], frac_lut4_0_sram[12], frac_lut4_0_sram[13], frac_lut4_0_sram[14], frac_lut4_0_sram[15], frac_lut4_0_mode}) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_io_mode_io_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_io_mode_io_.v new file mode 100644 index 0000000..73136e0 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_io_mode_io_.v @@ -0,0 +1,65 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_io_mode_io_ +( + IO_ISOL_N, + pReset, + prog_clk, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + io_outpad, + ccff_head, + io_inpad, + ccff_tail +); + + input IO_ISOL_N; + input pReset; + input prog_clk; + input gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + input io_outpad; + input ccff_head; + output io_inpad; + output ccff_tail; + + wire IO_ISOL_N; + wire pReset; + wire prog_clk; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire io_outpad; + wire ccff_head; + wire io_inpad; + wire ccff_tail; + wire direct_interc_1_out; + wire logical_tile_io_mode_physical__iopad_0_iopad_inpad; + + logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 + ( + .IO_ISOL_N(IO_ISOL_N), + .pReset(pReset), + .prog_clk(prog_clk), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .iopad_outpad(direct_interc_1_out), + .ccff_head(ccff_head), + .iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad), + .ccff_tail(ccff_tail) + ); + direct_interc direct_interc_0_ + ( + .in(logical_tile_io_mode_physical__iopad_0_iopad_inpad), + .out(io_inpad) + ); + direct_interc direct_interc_1_ + ( + .in(io_outpad), + .out(direct_interc_1_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_io_mode_physical__iopad.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_io_mode_physical__iopad.v new file mode 100644 index 0000000..3b88cdc --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_io_mode_physical__iopad.v @@ -0,0 +1,59 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module logical_tile_io_mode_physical__iopad +( + IO_ISOL_N, + pReset, + prog_clk, + gfpga_pad_EMBEDDED_IO_HD_SOC_IN, + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, + iopad_outpad, + ccff_head, + iopad_inpad, + ccff_tail +); + + input IO_ISOL_N; + input pReset; + input prog_clk; + input gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + input iopad_outpad; + input ccff_head; + output iopad_inpad; + output ccff_tail; + + wire IO_ISOL_N; + wire pReset; + wire prog_clk; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; + wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + wire iopad_outpad; + wire ccff_head; + wire iopad_inpad; + wire ccff_tail; + wire EMBEDDED_IO_HD_0_en; + + EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ + ( + .IO_ISOL_N(IO_ISOL_N), + .SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), + .SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), + .SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), + .FPGA_OUT(iopad_outpad), + .FPGA_DIR(EMBEDDED_IO_HD_0_en), + .FPGA_IN(iopad_inpad) + ); + EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(ccff_tail), + .mem_out(EMBEDDED_IO_HD_0_en) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__0_.v new file mode 100644 index 0000000..44990ca --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__0_.v @@ -0,0 +1,177 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cbx_1__0_ +( + pReset, + prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chanx_left_in; + input [0:29]chanx_right_in; + input ccff_head; + output [0:29]chanx_left_out; + output [0:29]chanx_right_out; + output bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + output bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + output bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + output bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chanx_left_in; + wire [0:29]chanx_right_in; + wire ccff_head; + wire [0:29]chanx_left_out; + wire [0:29]chanx_right_out; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; + wire bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; + wire bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; + wire bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_tail; + wire [0:3]mux_top_ipin_0_undriven_sram_inv; + wire [0:3]mux_top_ipin_1_undriven_sram_inv; + wire [0:3]mux_top_ipin_2_undriven_sram_inv; + wire [0:3]mux_top_ipin_3_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + +assign chanx_right_out[0] = chanx_left_in[0]; +assign chanx_right_out[1] = chanx_left_in[1]; +assign chanx_right_out[2] = chanx_left_in[2]; +assign chanx_right_out[3] = chanx_left_in[3]; +assign chanx_right_out[4] = chanx_left_in[4]; +assign chanx_right_out[5] = chanx_left_in[5]; +assign chanx_right_out[6] = chanx_left_in[6]; +assign chanx_right_out[7] = chanx_left_in[7]; +assign chanx_right_out[8] = chanx_left_in[8]; +assign chanx_right_out[9] = chanx_left_in[9]; +assign chanx_right_out[10] = chanx_left_in[10]; +assign chanx_right_out[11] = chanx_left_in[11]; +assign chanx_right_out[12] = chanx_left_in[12]; +assign chanx_right_out[13] = chanx_left_in[13]; +assign chanx_right_out[14] = chanx_left_in[14]; +assign chanx_right_out[15] = chanx_left_in[15]; +assign chanx_right_out[16] = chanx_left_in[16]; +assign chanx_right_out[17] = chanx_left_in[17]; +assign chanx_right_out[18] = chanx_left_in[18]; +assign chanx_right_out[19] = chanx_left_in[19]; +assign chanx_right_out[20] = chanx_left_in[20]; +assign chanx_right_out[21] = chanx_left_in[21]; +assign chanx_right_out[22] = chanx_left_in[22]; +assign chanx_right_out[23] = chanx_left_in[23]; +assign chanx_right_out[24] = chanx_left_in[24]; +assign chanx_right_out[25] = chanx_left_in[25]; +assign chanx_right_out[26] = chanx_left_in[26]; +assign chanx_right_out[27] = chanx_left_in[27]; +assign chanx_right_out[28] = chanx_left_in[28]; +assign chanx_right_out[29] = chanx_left_in[29]; +assign chanx_left_out[0] = chanx_right_in[0]; +assign chanx_left_out[1] = chanx_right_in[1]; +assign chanx_left_out[2] = chanx_right_in[2]; +assign chanx_left_out[3] = chanx_right_in[3]; +assign chanx_left_out[4] = chanx_right_in[4]; +assign chanx_left_out[5] = chanx_right_in[5]; +assign chanx_left_out[6] = chanx_right_in[6]; +assign chanx_left_out[7] = chanx_right_in[7]; +assign chanx_left_out[8] = chanx_right_in[8]; +assign chanx_left_out[9] = chanx_right_in[9]; +assign chanx_left_out[10] = chanx_right_in[10]; +assign chanx_left_out[11] = chanx_right_in[11]; +assign chanx_left_out[12] = chanx_right_in[12]; +assign chanx_left_out[13] = chanx_right_in[13]; +assign chanx_left_out[14] = chanx_right_in[14]; +assign chanx_left_out[15] = chanx_right_in[15]; +assign chanx_left_out[16] = chanx_right_in[16]; +assign chanx_left_out[17] = chanx_right_in[17]; +assign chanx_left_out[18] = chanx_right_in[18]; +assign chanx_left_out[19] = chanx_right_in[19]; +assign chanx_left_out[20] = chanx_right_in[20]; +assign chanx_left_out[21] = chanx_right_in[21]; +assign chanx_left_out[22] = chanx_right_in[22]; +assign chanx_left_out[23] = chanx_right_in[23]; +assign chanx_left_out[24] = chanx_right_in[24]; +assign chanx_left_out[25] = chanx_right_in[25]; +assign chanx_left_out[26] = chanx_right_in[26]; +assign chanx_left_out[27] = chanx_right_in[27]; +assign chanx_left_out[28] = chanx_right_in[28]; +assign chanx_left_out[29] = chanx_right_in[29]; + mux_tree_tapbuf_size12 mux_top_ipin_0 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_top_ipin_0_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_1 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_top_ipin_1_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_2 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_top_ipin_2_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_3 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21], chanx_left_in[27], chanx_right_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_top_ipin_3_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__1_.v new file mode 100644 index 0000000..b218cae --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__1_.v @@ -0,0 +1,429 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cbx_1__1_ +( + pReset, + prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chanx_left_in; + input [0:29]chanx_right_in; + input ccff_head; + output [0:29]chanx_left_out; + output [0:29]chanx_right_out; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chanx_left_in; + wire [0:29]chanx_right_in; + wire ccff_head; + wire [0:29]chanx_left_out; + wire [0:29]chanx_right_out; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire ccff_tail; + wire [0:3]mux_top_ipin_0_undriven_sram_inv; + wire [0:3]mux_top_ipin_10_undriven_sram_inv; + wire [0:3]mux_top_ipin_11_undriven_sram_inv; + wire [0:3]mux_top_ipin_12_undriven_sram_inv; + wire [0:3]mux_top_ipin_13_undriven_sram_inv; + wire [0:3]mux_top_ipin_14_undriven_sram_inv; + wire [0:3]mux_top_ipin_15_undriven_sram_inv; + wire [0:3]mux_top_ipin_1_undriven_sram_inv; + wire [0:3]mux_top_ipin_2_undriven_sram_inv; + wire [0:3]mux_top_ipin_3_undriven_sram_inv; + wire [0:3]mux_top_ipin_4_undriven_sram_inv; + wire [0:3]mux_top_ipin_5_undriven_sram_inv; + wire [0:3]mux_top_ipin_6_undriven_sram_inv; + wire [0:3]mux_top_ipin_7_undriven_sram_inv; + wire [0:3]mux_top_ipin_8_undriven_sram_inv; + wire [0:3]mux_top_ipin_9_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire [0:3]mux_tree_tapbuf_size10_1_sram; + wire [0:3]mux_tree_tapbuf_size10_2_sram; + wire [0:3]mux_tree_tapbuf_size10_3_sram; + wire [0:3]mux_tree_tapbuf_size10_4_sram; + wire [0:3]mux_tree_tapbuf_size10_5_sram; + wire [0:3]mux_tree_tapbuf_size10_6_sram; + wire [0:3]mux_tree_tapbuf_size10_7_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire [0:3]mux_tree_tapbuf_size12_4_sram; + wire [0:3]mux_tree_tapbuf_size12_5_sram; + wire [0:3]mux_tree_tapbuf_size12_6_sram; + wire [0:3]mux_tree_tapbuf_size12_7_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire mux_tree_tapbuf_size12_mem_7_ccff_tail; + +assign chanx_right_out[0] = chanx_left_in[0]; +assign chanx_right_out[1] = chanx_left_in[1]; +assign chanx_right_out[2] = chanx_left_in[2]; +assign chanx_right_out[3] = chanx_left_in[3]; +assign chanx_right_out[4] = chanx_left_in[4]; +assign chanx_right_out[5] = chanx_left_in[5]; +assign chanx_right_out[6] = chanx_left_in[6]; +assign chanx_right_out[7] = chanx_left_in[7]; +assign chanx_right_out[8] = chanx_left_in[8]; +assign chanx_right_out[9] = chanx_left_in[9]; +assign chanx_right_out[10] = chanx_left_in[10]; +assign chanx_right_out[11] = chanx_left_in[11]; +assign chanx_right_out[12] = chanx_left_in[12]; +assign chanx_right_out[13] = chanx_left_in[13]; +assign chanx_right_out[14] = chanx_left_in[14]; +assign chanx_right_out[15] = chanx_left_in[15]; +assign chanx_right_out[16] = chanx_left_in[16]; +assign chanx_right_out[17] = chanx_left_in[17]; +assign chanx_right_out[18] = chanx_left_in[18]; +assign chanx_right_out[19] = chanx_left_in[19]; +assign chanx_right_out[20] = chanx_left_in[20]; +assign chanx_right_out[21] = chanx_left_in[21]; +assign chanx_right_out[22] = chanx_left_in[22]; +assign chanx_right_out[23] = chanx_left_in[23]; +assign chanx_right_out[24] = chanx_left_in[24]; +assign chanx_right_out[25] = chanx_left_in[25]; +assign chanx_right_out[26] = chanx_left_in[26]; +assign chanx_right_out[27] = chanx_left_in[27]; +assign chanx_right_out[28] = chanx_left_in[28]; +assign chanx_right_out[29] = chanx_left_in[29]; +assign chanx_left_out[0] = chanx_right_in[0]; +assign chanx_left_out[1] = chanx_right_in[1]; +assign chanx_left_out[2] = chanx_right_in[2]; +assign chanx_left_out[3] = chanx_right_in[3]; +assign chanx_left_out[4] = chanx_right_in[4]; +assign chanx_left_out[5] = chanx_right_in[5]; +assign chanx_left_out[6] = chanx_right_in[6]; +assign chanx_left_out[7] = chanx_right_in[7]; +assign chanx_left_out[8] = chanx_right_in[8]; +assign chanx_left_out[9] = chanx_right_in[9]; +assign chanx_left_out[10] = chanx_right_in[10]; +assign chanx_left_out[11] = chanx_right_in[11]; +assign chanx_left_out[12] = chanx_right_in[12]; +assign chanx_left_out[13] = chanx_right_in[13]; +assign chanx_left_out[14] = chanx_right_in[14]; +assign chanx_left_out[15] = chanx_right_in[15]; +assign chanx_left_out[16] = chanx_right_in[16]; +assign chanx_left_out[17] = chanx_right_in[17]; +assign chanx_left_out[18] = chanx_right_in[18]; +assign chanx_left_out[19] = chanx_right_in[19]; +assign chanx_left_out[20] = chanx_right_in[20]; +assign chanx_left_out[21] = chanx_right_in[21]; +assign chanx_left_out[22] = chanx_right_in[22]; +assign chanx_left_out[23] = chanx_right_in[23]; +assign chanx_left_out[24] = chanx_right_in[24]; +assign chanx_left_out[25] = chanx_right_in[25]; +assign chanx_left_out[26] = chanx_right_in[26]; +assign chanx_left_out[27] = chanx_right_in[27]; +assign chanx_left_out[28] = chanx_right_in[28]; +assign chanx_left_out[29] = chanx_right_in[29]; + mux_tree_tapbuf_size12 mux_top_ipin_0 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_top_ipin_0_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_2 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_top_ipin_2_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_4 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_top_ipin_4_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_6 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_top_ipin_6_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_8 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_4_sram), + .sram_inv(mux_top_ipin_8_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_10 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_5_sram), + .sram_inv(mux_top_ipin_10_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_12 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_6_sram), + .sram_inv(mux_top_ipin_12_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_14 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_7_sram), + .sram_inv(mux_top_ipin_14_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram) + ); + mux_tree_tapbuf_size10 mux_top_ipin_1 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[16], chanx_right_in[16], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_top_ipin_1_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_3 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[18], chanx_right_in[18], chanx_left_in[27], chanx_right_in[27]}), + .sram(mux_tree_tapbuf_size10_1_sram), + .sram_inv(mux_top_ipin_3_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_5 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[20], chanx_right_in[20], chanx_left_in[29], chanx_right_in[29]}), + .sram(mux_tree_tapbuf_size10_2_sram), + .sram_inv(mux_top_ipin_5_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_7 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[22], chanx_right_in[22]}), + .sram(mux_tree_tapbuf_size10_3_sram), + .sram_inv(mux_top_ipin_7_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_9 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size10_4_sram), + .sram_inv(mux_top_ipin_9_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_11 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size10_5_sram), + .sram_inv(mux_top_ipin_11_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_13 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size10_6_sram), + .sram_inv(mux_top_ipin_13_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_15 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21]}), + .sram(mux_tree_tapbuf_size10_7_sram), + .sram_inv(mux_top_ipin_15_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__8_.v new file mode 100644 index 0000000..11749f0 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__8_.v @@ -0,0 +1,513 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cbx_1__8_ +( + pReset, + prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chanx_left_in; + input [0:29]chanx_right_in; + input ccff_head; + output [0:29]chanx_left_out; + output [0:29]chanx_right_out; + output top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + output top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + output top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + output top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chanx_left_in; + wire [0:29]chanx_right_in; + wire ccff_head; + wire [0:29]chanx_left_out; + wire [0:29]chanx_right_out; + wire top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; + wire top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; + wire top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; + wire top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; + wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; + wire ccff_tail; + wire [0:3]mux_bottom_ipin_0_undriven_sram_inv; + wire [0:3]mux_bottom_ipin_1_undriven_sram_inv; + wire [0:3]mux_bottom_ipin_2_undriven_sram_inv; + wire [0:3]mux_bottom_ipin_3_undriven_sram_inv; + wire [0:3]mux_top_ipin_0_undriven_sram_inv; + wire [0:3]mux_top_ipin_10_undriven_sram_inv; + wire [0:3]mux_top_ipin_11_undriven_sram_inv; + wire [0:3]mux_top_ipin_12_undriven_sram_inv; + wire [0:3]mux_top_ipin_13_undriven_sram_inv; + wire [0:3]mux_top_ipin_14_undriven_sram_inv; + wire [0:3]mux_top_ipin_15_undriven_sram_inv; + wire [0:3]mux_top_ipin_1_undriven_sram_inv; + wire [0:3]mux_top_ipin_2_undriven_sram_inv; + wire [0:3]mux_top_ipin_3_undriven_sram_inv; + wire [0:3]mux_top_ipin_4_undriven_sram_inv; + wire [0:3]mux_top_ipin_5_undriven_sram_inv; + wire [0:3]mux_top_ipin_6_undriven_sram_inv; + wire [0:3]mux_top_ipin_7_undriven_sram_inv; + wire [0:3]mux_top_ipin_8_undriven_sram_inv; + wire [0:3]mux_top_ipin_9_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire [0:3]mux_tree_tapbuf_size10_1_sram; + wire [0:3]mux_tree_tapbuf_size10_2_sram; + wire [0:3]mux_tree_tapbuf_size10_3_sram; + wire [0:3]mux_tree_tapbuf_size10_4_sram; + wire [0:3]mux_tree_tapbuf_size10_5_sram; + wire [0:3]mux_tree_tapbuf_size10_6_sram; + wire [0:3]mux_tree_tapbuf_size10_7_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_10_sram; + wire [0:3]mux_tree_tapbuf_size12_11_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire [0:3]mux_tree_tapbuf_size12_4_sram; + wire [0:3]mux_tree_tapbuf_size12_5_sram; + wire [0:3]mux_tree_tapbuf_size12_6_sram; + wire [0:3]mux_tree_tapbuf_size12_7_sram; + wire [0:3]mux_tree_tapbuf_size12_8_sram; + wire [0:3]mux_tree_tapbuf_size12_9_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_10_ccff_tail; + wire mux_tree_tapbuf_size12_mem_11_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire mux_tree_tapbuf_size12_mem_7_ccff_tail; + wire mux_tree_tapbuf_size12_mem_8_ccff_tail; + wire mux_tree_tapbuf_size12_mem_9_ccff_tail; + +assign chanx_right_out[0] = chanx_left_in[0]; +assign chanx_right_out[1] = chanx_left_in[1]; +assign chanx_right_out[2] = chanx_left_in[2]; +assign chanx_right_out[3] = chanx_left_in[3]; +assign chanx_right_out[4] = chanx_left_in[4]; +assign chanx_right_out[5] = chanx_left_in[5]; +assign chanx_right_out[6] = chanx_left_in[6]; +assign chanx_right_out[7] = chanx_left_in[7]; +assign chanx_right_out[8] = chanx_left_in[8]; +assign chanx_right_out[9] = chanx_left_in[9]; +assign chanx_right_out[10] = chanx_left_in[10]; +assign chanx_right_out[11] = chanx_left_in[11]; +assign chanx_right_out[12] = chanx_left_in[12]; +assign chanx_right_out[13] = chanx_left_in[13]; +assign chanx_right_out[14] = chanx_left_in[14]; +assign chanx_right_out[15] = chanx_left_in[15]; +assign chanx_right_out[16] = chanx_left_in[16]; +assign chanx_right_out[17] = chanx_left_in[17]; +assign chanx_right_out[18] = chanx_left_in[18]; +assign chanx_right_out[19] = chanx_left_in[19]; +assign chanx_right_out[20] = chanx_left_in[20]; +assign chanx_right_out[21] = chanx_left_in[21]; +assign chanx_right_out[22] = chanx_left_in[22]; +assign chanx_right_out[23] = chanx_left_in[23]; +assign chanx_right_out[24] = chanx_left_in[24]; +assign chanx_right_out[25] = chanx_left_in[25]; +assign chanx_right_out[26] = chanx_left_in[26]; +assign chanx_right_out[27] = chanx_left_in[27]; +assign chanx_right_out[28] = chanx_left_in[28]; +assign chanx_right_out[29] = chanx_left_in[29]; +assign chanx_left_out[0] = chanx_right_in[0]; +assign chanx_left_out[1] = chanx_right_in[1]; +assign chanx_left_out[2] = chanx_right_in[2]; +assign chanx_left_out[3] = chanx_right_in[3]; +assign chanx_left_out[4] = chanx_right_in[4]; +assign chanx_left_out[5] = chanx_right_in[5]; +assign chanx_left_out[6] = chanx_right_in[6]; +assign chanx_left_out[7] = chanx_right_in[7]; +assign chanx_left_out[8] = chanx_right_in[8]; +assign chanx_left_out[9] = chanx_right_in[9]; +assign chanx_left_out[10] = chanx_right_in[10]; +assign chanx_left_out[11] = chanx_right_in[11]; +assign chanx_left_out[12] = chanx_right_in[12]; +assign chanx_left_out[13] = chanx_right_in[13]; +assign chanx_left_out[14] = chanx_right_in[14]; +assign chanx_left_out[15] = chanx_right_in[15]; +assign chanx_left_out[16] = chanx_right_in[16]; +assign chanx_left_out[17] = chanx_right_in[17]; +assign chanx_left_out[18] = chanx_right_in[18]; +assign chanx_left_out[19] = chanx_right_in[19]; +assign chanx_left_out[20] = chanx_right_in[20]; +assign chanx_left_out[21] = chanx_right_in[21]; +assign chanx_left_out[22] = chanx_right_in[22]; +assign chanx_left_out[23] = chanx_right_in[23]; +assign chanx_left_out[24] = chanx_right_in[24]; +assign chanx_left_out[25] = chanx_right_in[25]; +assign chanx_left_out[26] = chanx_right_in[26]; +assign chanx_left_out[27] = chanx_right_in[27]; +assign chanx_left_out[28] = chanx_right_in[28]; +assign chanx_left_out[29] = chanx_right_in[29]; + mux_tree_tapbuf_size12 mux_bottom_ipin_0 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_bottom_ipin_0_undriven_sram_inv), + .out(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_bottom_ipin_1 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_bottom_ipin_1_undriven_sram_inv), + .out(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_bottom_ipin_2 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_bottom_ipin_2_undriven_sram_inv), + .out(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_bottom_ipin_3 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21], chanx_left_in[27], chanx_right_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_bottom_ipin_3_undriven_sram_inv), + .out(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_0 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_4_sram), + .sram_inv(mux_top_ipin_0_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_2 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_5_sram), + .sram_inv(mux_top_ipin_2_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_4 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_6_sram), + .sram_inv(mux_top_ipin_4_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_6 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_7_sram), + .sram_inv(mux_top_ipin_6_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_8 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_8_sram), + .sram_inv(mux_top_ipin_8_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_10 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size12_9_sram), + .sram_inv(mux_top_ipin_10_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_12 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size12_10_sram), + .sram_inv(mux_top_ipin_12_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_) + ); + mux_tree_tapbuf_size12 mux_top_ipin_14 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size12_11_sram), + .sram_inv(mux_top_ipin_14_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_) + ); + mux_tree_tapbuf_size12_mem mem_bottom_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_bottom_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_bottom_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_bottom_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_8_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_9_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_10_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_ipin_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_11_sram) + ); + mux_tree_tapbuf_size10 mux_top_ipin_1 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[20], chanx_right_in[20], chanx_left_in[29], chanx_right_in[29]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_top_ipin_1_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_3 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[22], chanx_right_in[22]}), + .sram(mux_tree_tapbuf_size10_1_sram), + .sram_inv(mux_top_ipin_3_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_5 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[24], chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size10_2_sram), + .sram_inv(mux_top_ipin_5_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_7 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17], chanx_left_in[26], chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size10_3_sram), + .sram_inv(mux_top_ipin_7_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_9 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[28], chanx_right_in[28]}), + .sram(mux_tree_tapbuf_size10_4_sram), + .sram_inv(mux_top_ipin_9_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_11 + ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21]}), + .sram(mux_tree_tapbuf_size10_5_sram), + .sram_inv(mux_top_ipin_11_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_13 + ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[17], chanx_right_in[17], chanx_left_in[23], chanx_right_in[23]}), + .sram(mux_tree_tapbuf_size10_6_sram), + .sram_inv(mux_top_ipin_13_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_) + ); + mux_tree_tapbuf_size10 mux_top_ipin_15 + ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size10_7_sram), + .sram_inv(mux_top_ipin_15_undriven_sram_inv), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_ipin_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_0__1_.v new file mode 100644 index 0000000..b25d4b1 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_0__1_.v @@ -0,0 +1,177 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cby_0__1_ +( + pReset, + prog_clk, + chany_bottom_in, + chany_top_in, + ccff_head, + chany_bottom_out, + chany_top_out, + left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_bottom_in; + input [0:29]chany_top_in; + input ccff_head; + output [0:29]chany_bottom_out; + output [0:29]chany_top_out; + output left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + output left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + output left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + output left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_bottom_in; + wire [0:29]chany_top_in; + wire ccff_head; + wire [0:29]chany_bottom_out; + wire [0:29]chany_top_out; + wire left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; + wire left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; + wire left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; + wire left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; + wire ccff_tail; + wire [0:3]mux_right_ipin_0_undriven_sram_inv; + wire [0:3]mux_right_ipin_1_undriven_sram_inv; + wire [0:3]mux_right_ipin_2_undriven_sram_inv; + wire [0:3]mux_right_ipin_3_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + +assign chany_top_out[0] = chany_bottom_in[0]; +assign chany_top_out[1] = chany_bottom_in[1]; +assign chany_top_out[2] = chany_bottom_in[2]; +assign chany_top_out[3] = chany_bottom_in[3]; +assign chany_top_out[4] = chany_bottom_in[4]; +assign chany_top_out[5] = chany_bottom_in[5]; +assign chany_top_out[6] = chany_bottom_in[6]; +assign chany_top_out[7] = chany_bottom_in[7]; +assign chany_top_out[8] = chany_bottom_in[8]; +assign chany_top_out[9] = chany_bottom_in[9]; +assign chany_top_out[10] = chany_bottom_in[10]; +assign chany_top_out[11] = chany_bottom_in[11]; +assign chany_top_out[12] = chany_bottom_in[12]; +assign chany_top_out[13] = chany_bottom_in[13]; +assign chany_top_out[14] = chany_bottom_in[14]; +assign chany_top_out[15] = chany_bottom_in[15]; +assign chany_top_out[16] = chany_bottom_in[16]; +assign chany_top_out[17] = chany_bottom_in[17]; +assign chany_top_out[18] = chany_bottom_in[18]; +assign chany_top_out[19] = chany_bottom_in[19]; +assign chany_top_out[20] = chany_bottom_in[20]; +assign chany_top_out[21] = chany_bottom_in[21]; +assign chany_top_out[22] = chany_bottom_in[22]; +assign chany_top_out[23] = chany_bottom_in[23]; +assign chany_top_out[24] = chany_bottom_in[24]; +assign chany_top_out[25] = chany_bottom_in[25]; +assign chany_top_out[26] = chany_bottom_in[26]; +assign chany_top_out[27] = chany_bottom_in[27]; +assign chany_top_out[28] = chany_bottom_in[28]; +assign chany_top_out[29] = chany_bottom_in[29]; +assign chany_bottom_out[0] = chany_top_in[0]; +assign chany_bottom_out[1] = chany_top_in[1]; +assign chany_bottom_out[2] = chany_top_in[2]; +assign chany_bottom_out[3] = chany_top_in[3]; +assign chany_bottom_out[4] = chany_top_in[4]; +assign chany_bottom_out[5] = chany_top_in[5]; +assign chany_bottom_out[6] = chany_top_in[6]; +assign chany_bottom_out[7] = chany_top_in[7]; +assign chany_bottom_out[8] = chany_top_in[8]; +assign chany_bottom_out[9] = chany_top_in[9]; +assign chany_bottom_out[10] = chany_top_in[10]; +assign chany_bottom_out[11] = chany_top_in[11]; +assign chany_bottom_out[12] = chany_top_in[12]; +assign chany_bottom_out[13] = chany_top_in[13]; +assign chany_bottom_out[14] = chany_top_in[14]; +assign chany_bottom_out[15] = chany_top_in[15]; +assign chany_bottom_out[16] = chany_top_in[16]; +assign chany_bottom_out[17] = chany_top_in[17]; +assign chany_bottom_out[18] = chany_top_in[18]; +assign chany_bottom_out[19] = chany_top_in[19]; +assign chany_bottom_out[20] = chany_top_in[20]; +assign chany_bottom_out[21] = chany_top_in[21]; +assign chany_bottom_out[22] = chany_top_in[22]; +assign chany_bottom_out[23] = chany_top_in[23]; +assign chany_bottom_out[24] = chany_top_in[24]; +assign chany_bottom_out[25] = chany_top_in[25]; +assign chany_bottom_out[26] = chany_top_in[26]; +assign chany_bottom_out[27] = chany_top_in[27]; +assign chany_bottom_out[28] = chany_top_in[28]; +assign chany_bottom_out[29] = chany_top_in[29]; + mux_tree_tapbuf_size12 mux_right_ipin_0 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_right_ipin_0_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_1 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_right_ipin_1_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_2 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_right_ipin_2_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_3 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21], chany_bottom_in[27], chany_top_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_right_ipin_3_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_1__1_.v new file mode 100644 index 0000000..e07ffde --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_1__1_.v @@ -0,0 +1,429 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cby_1__1_ +( + pReset, + prog_clk, + chany_bottom_in, + chany_top_in, + ccff_head, + chany_bottom_out, + chany_top_out, + left_grid_right_width_0_height_0_subtile_0__pin_I4_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_bottom_in; + input [0:29]chany_top_in; + input ccff_head; + output [0:29]chany_bottom_out; + output [0:29]chany_top_out; + output left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_bottom_in; + wire [0:29]chany_top_in; + wire ccff_head; + wire [0:29]chany_bottom_out; + wire [0:29]chany_top_out; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire ccff_tail; + wire [0:3]mux_right_ipin_0_undriven_sram_inv; + wire [0:3]mux_right_ipin_10_undriven_sram_inv; + wire [0:3]mux_right_ipin_11_undriven_sram_inv; + wire [0:3]mux_right_ipin_12_undriven_sram_inv; + wire [0:3]mux_right_ipin_13_undriven_sram_inv; + wire [0:3]mux_right_ipin_14_undriven_sram_inv; + wire [0:3]mux_right_ipin_15_undriven_sram_inv; + wire [0:3]mux_right_ipin_1_undriven_sram_inv; + wire [0:3]mux_right_ipin_2_undriven_sram_inv; + wire [0:3]mux_right_ipin_3_undriven_sram_inv; + wire [0:3]mux_right_ipin_4_undriven_sram_inv; + wire [0:3]mux_right_ipin_5_undriven_sram_inv; + wire [0:3]mux_right_ipin_6_undriven_sram_inv; + wire [0:3]mux_right_ipin_7_undriven_sram_inv; + wire [0:3]mux_right_ipin_8_undriven_sram_inv; + wire [0:3]mux_right_ipin_9_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire [0:3]mux_tree_tapbuf_size10_1_sram; + wire [0:3]mux_tree_tapbuf_size10_2_sram; + wire [0:3]mux_tree_tapbuf_size10_3_sram; + wire [0:3]mux_tree_tapbuf_size10_4_sram; + wire [0:3]mux_tree_tapbuf_size10_5_sram; + wire [0:3]mux_tree_tapbuf_size10_6_sram; + wire [0:3]mux_tree_tapbuf_size10_7_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire [0:3]mux_tree_tapbuf_size12_4_sram; + wire [0:3]mux_tree_tapbuf_size12_5_sram; + wire [0:3]mux_tree_tapbuf_size12_6_sram; + wire [0:3]mux_tree_tapbuf_size12_7_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire mux_tree_tapbuf_size12_mem_7_ccff_tail; + +assign chany_top_out[0] = chany_bottom_in[0]; +assign chany_top_out[1] = chany_bottom_in[1]; +assign chany_top_out[2] = chany_bottom_in[2]; +assign chany_top_out[3] = chany_bottom_in[3]; +assign chany_top_out[4] = chany_bottom_in[4]; +assign chany_top_out[5] = chany_bottom_in[5]; +assign chany_top_out[6] = chany_bottom_in[6]; +assign chany_top_out[7] = chany_bottom_in[7]; +assign chany_top_out[8] = chany_bottom_in[8]; +assign chany_top_out[9] = chany_bottom_in[9]; +assign chany_top_out[10] = chany_bottom_in[10]; +assign chany_top_out[11] = chany_bottom_in[11]; +assign chany_top_out[12] = chany_bottom_in[12]; +assign chany_top_out[13] = chany_bottom_in[13]; +assign chany_top_out[14] = chany_bottom_in[14]; +assign chany_top_out[15] = chany_bottom_in[15]; +assign chany_top_out[16] = chany_bottom_in[16]; +assign chany_top_out[17] = chany_bottom_in[17]; +assign chany_top_out[18] = chany_bottom_in[18]; +assign chany_top_out[19] = chany_bottom_in[19]; +assign chany_top_out[20] = chany_bottom_in[20]; +assign chany_top_out[21] = chany_bottom_in[21]; +assign chany_top_out[22] = chany_bottom_in[22]; +assign chany_top_out[23] = chany_bottom_in[23]; +assign chany_top_out[24] = chany_bottom_in[24]; +assign chany_top_out[25] = chany_bottom_in[25]; +assign chany_top_out[26] = chany_bottom_in[26]; +assign chany_top_out[27] = chany_bottom_in[27]; +assign chany_top_out[28] = chany_bottom_in[28]; +assign chany_top_out[29] = chany_bottom_in[29]; +assign chany_bottom_out[0] = chany_top_in[0]; +assign chany_bottom_out[1] = chany_top_in[1]; +assign chany_bottom_out[2] = chany_top_in[2]; +assign chany_bottom_out[3] = chany_top_in[3]; +assign chany_bottom_out[4] = chany_top_in[4]; +assign chany_bottom_out[5] = chany_top_in[5]; +assign chany_bottom_out[6] = chany_top_in[6]; +assign chany_bottom_out[7] = chany_top_in[7]; +assign chany_bottom_out[8] = chany_top_in[8]; +assign chany_bottom_out[9] = chany_top_in[9]; +assign chany_bottom_out[10] = chany_top_in[10]; +assign chany_bottom_out[11] = chany_top_in[11]; +assign chany_bottom_out[12] = chany_top_in[12]; +assign chany_bottom_out[13] = chany_top_in[13]; +assign chany_bottom_out[14] = chany_top_in[14]; +assign chany_bottom_out[15] = chany_top_in[15]; +assign chany_bottom_out[16] = chany_top_in[16]; +assign chany_bottom_out[17] = chany_top_in[17]; +assign chany_bottom_out[18] = chany_top_in[18]; +assign chany_bottom_out[19] = chany_top_in[19]; +assign chany_bottom_out[20] = chany_top_in[20]; +assign chany_bottom_out[21] = chany_top_in[21]; +assign chany_bottom_out[22] = chany_top_in[22]; +assign chany_bottom_out[23] = chany_top_in[23]; +assign chany_bottom_out[24] = chany_top_in[24]; +assign chany_bottom_out[25] = chany_top_in[25]; +assign chany_bottom_out[26] = chany_top_in[26]; +assign chany_bottom_out[27] = chany_top_in[27]; +assign chany_bottom_out[28] = chany_top_in[28]; +assign chany_bottom_out[29] = chany_top_in[29]; + mux_tree_tapbuf_size12 mux_right_ipin_0 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_right_ipin_0_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_2 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_right_ipin_2_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_4 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_right_ipin_4_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_6 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_right_ipin_6_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_8 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_4_sram), + .sram_inv(mux_right_ipin_8_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_10 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_5_sram), + .sram_inv(mux_right_ipin_10_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_12 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_6_sram), + .sram_inv(mux_right_ipin_12_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_14 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_7_sram), + .sram_inv(mux_right_ipin_14_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram) + ); + mux_tree_tapbuf_size10 mux_right_ipin_1 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_right_ipin_1_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_3 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[27], chany_top_in[27]}), + .sram(mux_tree_tapbuf_size10_1_sram), + .sram_inv(mux_right_ipin_3_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_5 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[29], chany_top_in[29]}), + .sram(mux_tree_tapbuf_size10_2_sram), + .sram_inv(mux_right_ipin_5_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_7 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[22], chany_top_in[22]}), + .sram(mux_tree_tapbuf_size10_3_sram), + .sram_inv(mux_right_ipin_7_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_9 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size10_4_sram), + .sram_inv(mux_right_ipin_9_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_11 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size10_5_sram), + .sram_inv(mux_right_ipin_11_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_13 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size10_6_sram), + .sram_inv(mux_right_ipin_13_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_15 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21]}), + .sram(mux_tree_tapbuf_size10_7_sram), + .sram_inv(mux_right_ipin_15_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_8__1_.v new file mode 100644 index 0000000..3400642 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_8__1_.v @@ -0,0 +1,513 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module cby_8__1_ +( + pReset, + prog_clk, + chany_bottom_in, + chany_top_in, + ccff_head, + chany_bottom_out, + chany_top_out, + right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_bottom_in; + input [0:29]chany_top_in; + input ccff_head; + output [0:29]chany_bottom_out; + output [0:29]chany_top_out; + output right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + output right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + output right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + output right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_bottom_in; + wire [0:29]chany_top_in; + wire ccff_head; + wire [0:29]chany_bottom_out; + wire [0:29]chany_top_out; + wire right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; + wire right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; + wire right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; + wire right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; + wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; + wire ccff_tail; + wire [0:3]mux_left_ipin_0_undriven_sram_inv; + wire [0:3]mux_left_ipin_1_undriven_sram_inv; + wire [0:3]mux_left_ipin_2_undriven_sram_inv; + wire [0:3]mux_left_ipin_3_undriven_sram_inv; + wire [0:3]mux_right_ipin_0_undriven_sram_inv; + wire [0:3]mux_right_ipin_10_undriven_sram_inv; + wire [0:3]mux_right_ipin_11_undriven_sram_inv; + wire [0:3]mux_right_ipin_12_undriven_sram_inv; + wire [0:3]mux_right_ipin_13_undriven_sram_inv; + wire [0:3]mux_right_ipin_14_undriven_sram_inv; + wire [0:3]mux_right_ipin_15_undriven_sram_inv; + wire [0:3]mux_right_ipin_1_undriven_sram_inv; + wire [0:3]mux_right_ipin_2_undriven_sram_inv; + wire [0:3]mux_right_ipin_3_undriven_sram_inv; + wire [0:3]mux_right_ipin_4_undriven_sram_inv; + wire [0:3]mux_right_ipin_5_undriven_sram_inv; + wire [0:3]mux_right_ipin_6_undriven_sram_inv; + wire [0:3]mux_right_ipin_7_undriven_sram_inv; + wire [0:3]mux_right_ipin_8_undriven_sram_inv; + wire [0:3]mux_right_ipin_9_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire [0:3]mux_tree_tapbuf_size10_1_sram; + wire [0:3]mux_tree_tapbuf_size10_2_sram; + wire [0:3]mux_tree_tapbuf_size10_3_sram; + wire [0:3]mux_tree_tapbuf_size10_4_sram; + wire [0:3]mux_tree_tapbuf_size10_5_sram; + wire [0:3]mux_tree_tapbuf_size10_6_sram; + wire [0:3]mux_tree_tapbuf_size10_7_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_10_sram; + wire [0:3]mux_tree_tapbuf_size12_11_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire [0:3]mux_tree_tapbuf_size12_4_sram; + wire [0:3]mux_tree_tapbuf_size12_5_sram; + wire [0:3]mux_tree_tapbuf_size12_6_sram; + wire [0:3]mux_tree_tapbuf_size12_7_sram; + wire [0:3]mux_tree_tapbuf_size12_8_sram; + wire [0:3]mux_tree_tapbuf_size12_9_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_10_ccff_tail; + wire mux_tree_tapbuf_size12_mem_11_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire mux_tree_tapbuf_size12_mem_7_ccff_tail; + wire mux_tree_tapbuf_size12_mem_8_ccff_tail; + wire mux_tree_tapbuf_size12_mem_9_ccff_tail; + +assign chany_top_out[0] = chany_bottom_in[0]; +assign chany_top_out[1] = chany_bottom_in[1]; +assign chany_top_out[2] = chany_bottom_in[2]; +assign chany_top_out[3] = chany_bottom_in[3]; +assign chany_top_out[4] = chany_bottom_in[4]; +assign chany_top_out[5] = chany_bottom_in[5]; +assign chany_top_out[6] = chany_bottom_in[6]; +assign chany_top_out[7] = chany_bottom_in[7]; +assign chany_top_out[8] = chany_bottom_in[8]; +assign chany_top_out[9] = chany_bottom_in[9]; +assign chany_top_out[10] = chany_bottom_in[10]; +assign chany_top_out[11] = chany_bottom_in[11]; +assign chany_top_out[12] = chany_bottom_in[12]; +assign chany_top_out[13] = chany_bottom_in[13]; +assign chany_top_out[14] = chany_bottom_in[14]; +assign chany_top_out[15] = chany_bottom_in[15]; +assign chany_top_out[16] = chany_bottom_in[16]; +assign chany_top_out[17] = chany_bottom_in[17]; +assign chany_top_out[18] = chany_bottom_in[18]; +assign chany_top_out[19] = chany_bottom_in[19]; +assign chany_top_out[20] = chany_bottom_in[20]; +assign chany_top_out[21] = chany_bottom_in[21]; +assign chany_top_out[22] = chany_bottom_in[22]; +assign chany_top_out[23] = chany_bottom_in[23]; +assign chany_top_out[24] = chany_bottom_in[24]; +assign chany_top_out[25] = chany_bottom_in[25]; +assign chany_top_out[26] = chany_bottom_in[26]; +assign chany_top_out[27] = chany_bottom_in[27]; +assign chany_top_out[28] = chany_bottom_in[28]; +assign chany_top_out[29] = chany_bottom_in[29]; +assign chany_bottom_out[0] = chany_top_in[0]; +assign chany_bottom_out[1] = chany_top_in[1]; +assign chany_bottom_out[2] = chany_top_in[2]; +assign chany_bottom_out[3] = chany_top_in[3]; +assign chany_bottom_out[4] = chany_top_in[4]; +assign chany_bottom_out[5] = chany_top_in[5]; +assign chany_bottom_out[6] = chany_top_in[6]; +assign chany_bottom_out[7] = chany_top_in[7]; +assign chany_bottom_out[8] = chany_top_in[8]; +assign chany_bottom_out[9] = chany_top_in[9]; +assign chany_bottom_out[10] = chany_top_in[10]; +assign chany_bottom_out[11] = chany_top_in[11]; +assign chany_bottom_out[12] = chany_top_in[12]; +assign chany_bottom_out[13] = chany_top_in[13]; +assign chany_bottom_out[14] = chany_top_in[14]; +assign chany_bottom_out[15] = chany_top_in[15]; +assign chany_bottom_out[16] = chany_top_in[16]; +assign chany_bottom_out[17] = chany_top_in[17]; +assign chany_bottom_out[18] = chany_top_in[18]; +assign chany_bottom_out[19] = chany_top_in[19]; +assign chany_bottom_out[20] = chany_top_in[20]; +assign chany_bottom_out[21] = chany_top_in[21]; +assign chany_bottom_out[22] = chany_top_in[22]; +assign chany_bottom_out[23] = chany_top_in[23]; +assign chany_bottom_out[24] = chany_top_in[24]; +assign chany_bottom_out[25] = chany_top_in[25]; +assign chany_bottom_out[26] = chany_top_in[26]; +assign chany_bottom_out[27] = chany_top_in[27]; +assign chany_bottom_out[28] = chany_top_in[28]; +assign chany_bottom_out[29] = chany_top_in[29]; + mux_tree_tapbuf_size12 mux_left_ipin_0 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_left_ipin_0_undriven_sram_inv), + .out(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_left_ipin_1 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_left_ipin_1_undriven_sram_inv), + .out(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_left_ipin_2 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_left_ipin_2_undriven_sram_inv), + .out(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_left_ipin_3 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21], chany_bottom_in[27], chany_top_in[27]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_left_ipin_3_undriven_sram_inv), + .out(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_0 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_4_sram), + .sram_inv(mux_right_ipin_0_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_2 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_5_sram), + .sram_inv(mux_right_ipin_2_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_4 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_6_sram), + .sram_inv(mux_right_ipin_4_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_6 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_7_sram), + .sram_inv(mux_right_ipin_6_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_8 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_8_sram), + .sram_inv(mux_right_ipin_8_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_10 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size12_9_sram), + .sram_inv(mux_right_ipin_10_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_12 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size12_10_sram), + .sram_inv(mux_right_ipin_12_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_) + ); + mux_tree_tapbuf_size12 mux_right_ipin_14 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size12_11_sram), + .sram_inv(mux_right_ipin_14_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_) + ); + mux_tree_tapbuf_size12_mem mem_left_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_left_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_left_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_left_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_8_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_9_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_10_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_ipin_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_11_sram) + ); + mux_tree_tapbuf_size10 mux_right_ipin_1 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[29], chany_top_in[29]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_right_ipin_1_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_3 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[22], chany_top_in[22]}), + .sram(mux_tree_tapbuf_size10_1_sram), + .sram_inv(mux_right_ipin_3_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_5 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[24], chany_top_in[24]}), + .sram(mux_tree_tapbuf_size10_2_sram), + .sram_inv(mux_right_ipin_5_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_7 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[26], chany_top_in[26]}), + .sram(mux_tree_tapbuf_size10_3_sram), + .sram_inv(mux_right_ipin_7_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_9 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[28], chany_top_in[28]}), + .sram(mux_tree_tapbuf_size10_4_sram), + .sram_inv(mux_right_ipin_9_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_11 + ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21]}), + .sram(mux_tree_tapbuf_size10_5_sram), + .sram_inv(mux_right_ipin_11_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_13 + ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[23], chany_top_in[23]}), + .sram(mux_tree_tapbuf_size10_6_sram), + .sram_inv(mux_right_ipin_13_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_) + ); + mux_tree_tapbuf_size10 mux_right_ipin_15 + ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}), + .sram(mux_tree_tapbuf_size10_7_sram), + .sram_inv(mux_right_ipin_15_undriven_sram_inv), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_ipin_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__0_.v new file mode 100644 index 0000000..cbaa50a --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__0_.v @@ -0,0 +1,729 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_0__0_ +( + pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + chanx_right_in, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_right_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_top_in; + input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + input [0:29]chanx_right_in; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + input ccff_head; + output [0:29]chany_top_out; + output [0:29]chanx_right_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_top_in; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire [0:29]chanx_right_in; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head; + wire [0:29]chany_top_out; + wire [0:29]chanx_right_out; + wire ccff_tail; + wire [0:1]mux_right_track_0_undriven_sram_inv; + wire [0:1]mux_right_track_10_undriven_sram_inv; + wire [0:1]mux_right_track_12_undriven_sram_inv; + wire [0:1]mux_right_track_14_undriven_sram_inv; + wire [0:1]mux_right_track_16_undriven_sram_inv; + wire [0:1]mux_right_track_18_undriven_sram_inv; + wire [0:1]mux_right_track_28_undriven_sram_inv; + wire [0:1]mux_right_track_2_undriven_sram_inv; + wire [0:1]mux_right_track_30_undriven_sram_inv; + wire [0:1]mux_right_track_32_undriven_sram_inv; + wire [0:1]mux_right_track_34_undriven_sram_inv; + wire [0:1]mux_right_track_44_undriven_sram_inv; + wire [0:1]mux_right_track_46_undriven_sram_inv; + wire [0:1]mux_right_track_48_undriven_sram_inv; + wire [0:1]mux_right_track_4_undriven_sram_inv; + wire [0:1]mux_right_track_50_undriven_sram_inv; + wire [0:1]mux_right_track_6_undriven_sram_inv; + wire [0:1]mux_right_track_8_undriven_sram_inv; + wire [0:1]mux_top_track_0_undriven_sram_inv; + wire [0:1]mux_top_track_10_undriven_sram_inv; + wire [0:1]mux_top_track_12_undriven_sram_inv; + wire [0:1]mux_top_track_14_undriven_sram_inv; + wire [0:1]mux_top_track_16_undriven_sram_inv; + wire [0:1]mux_top_track_18_undriven_sram_inv; + wire [0:1]mux_top_track_28_undriven_sram_inv; + wire [0:1]mux_top_track_2_undriven_sram_inv; + wire [0:1]mux_top_track_30_undriven_sram_inv; + wire [0:1]mux_top_track_32_undriven_sram_inv; + wire [0:1]mux_top_track_34_undriven_sram_inv; + wire [0:1]mux_top_track_44_undriven_sram_inv; + wire [0:1]mux_top_track_46_undriven_sram_inv; + wire [0:1]mux_top_track_48_undriven_sram_inv; + wire [0:1]mux_top_track_4_undriven_sram_inv; + wire [0:1]mux_top_track_50_undriven_sram_inv; + wire [0:1]mux_top_track_6_undriven_sram_inv; + wire [0:1]mux_top_track_8_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_11_sram; + wire [0:1]mux_tree_tapbuf_size2_12_sram; + wire [0:1]mux_tree_tapbuf_size2_13_sram; + wire [0:1]mux_tree_tapbuf_size2_14_sram; + wire [0:1]mux_tree_tapbuf_size2_15_sram; + wire [0:1]mux_tree_tapbuf_size2_16_sram; + wire [0:1]mux_tree_tapbuf_size2_17_sram; + wire [0:1]mux_tree_tapbuf_size2_18_sram; + wire [0:1]mux_tree_tapbuf_size2_19_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_20_sram; + wire [0:1]mux_tree_tapbuf_size2_21_sram; + wire [0:1]mux_tree_tapbuf_size2_22_sram; + wire [0:1]mux_tree_tapbuf_size2_23_sram; + wire [0:1]mux_tree_tapbuf_size2_24_sram; + wire [0:1]mux_tree_tapbuf_size2_25_sram; + wire [0:1]mux_tree_tapbuf_size2_26_sram; + wire [0:1]mux_tree_tapbuf_size2_27_sram; + wire [0:1]mux_tree_tapbuf_size2_28_sram; + wire [0:1]mux_tree_tapbuf_size2_29_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_30_sram; + wire [0:1]mux_tree_tapbuf_size2_31_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire mux_tree_tapbuf_size2_mem_19_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_20_ccff_tail; + wire mux_tree_tapbuf_size2_mem_21_ccff_tail; + wire mux_tree_tapbuf_size2_mem_22_ccff_tail; + wire mux_tree_tapbuf_size2_mem_23_ccff_tail; + wire mux_tree_tapbuf_size2_mem_24_ccff_tail; + wire mux_tree_tapbuf_size2_mem_25_ccff_tail; + wire mux_tree_tapbuf_size2_mem_26_ccff_tail; + wire mux_tree_tapbuf_size2_mem_27_ccff_tail; + wire mux_tree_tapbuf_size2_mem_28_ccff_tail; + wire mux_tree_tapbuf_size2_mem_29_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_30_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + +assign chanx_right_out[10] = chany_top_in[9]; +assign chanx_right_out[11] = chany_top_in[10]; +assign chanx_right_out[12] = chany_top_in[11]; +assign chanx_right_out[13] = chany_top_in[12]; +assign chanx_right_out[18] = chany_top_in[17]; +assign chanx_right_out[19] = chany_top_in[18]; +assign chanx_right_out[20] = chany_top_in[19]; +assign chanx_right_out[21] = chany_top_in[20]; +assign chanx_right_out[26] = chany_top_in[25]; +assign chanx_right_out[27] = chany_top_in[26]; +assign chanx_right_out[28] = chany_top_in[27]; +assign chanx_right_out[29] = chany_top_in[28]; +assign chany_top_out[29] = chanx_right_in[0]; +assign chany_top_out[10] = chanx_right_in[11]; +assign chany_top_out[11] = chanx_right_in[12]; +assign chany_top_out[12] = chanx_right_in[13]; +assign chany_top_out[13] = chanx_right_in[14]; +assign chany_top_out[18] = chanx_right_in[19]; +assign chany_top_out[19] = chanx_right_in[20]; +assign chany_top_out[20] = chanx_right_in[21]; +assign chany_top_out[21] = chanx_right_in[22]; +assign chany_top_out[26] = chanx_right_in[27]; +assign chany_top_out[27] = chanx_right_in[28]; +assign chany_top_out[28] = chanx_right_in[29]; + mux_tree_tapbuf_size3 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[1]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size3 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[4]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); + mux_tree_tapbuf_size3 mux_right_track_0 + ( + .in({chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size3 mux_right_track_6 + ( + .in({chany_top_in[2], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size3_mem mem_top_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size2 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[2]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size2 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[3]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size2 mux_top_track_8 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[5]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_top_track_8_undriven_sram_inv), + .out(chany_top_out[4]) + ); + mux_tree_tapbuf_size2 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[6]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size2 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[7]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size2 mux_top_track_14 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[8]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_top_track_14_undriven_sram_inv), + .out(chany_top_out[7]) + ); + mux_tree_tapbuf_size2 mux_top_track_16 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[9]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_top_track_16_undriven_sram_inv), + .out(chany_top_out[8]) + ); + mux_tree_tapbuf_size2 mux_top_track_18 + ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[10]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_top_track_18_undriven_sram_inv), + .out(chany_top_out[9]) + ); + mux_tree_tapbuf_size2 mux_top_track_28 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[15]}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size2 mux_top_track_30 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[16]}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_top_track_30_undriven_sram_inv), + .out(chany_top_out[15]) + ); + mux_tree_tapbuf_size2 mux_top_track_32 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[17]}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_top_track_32_undriven_sram_inv), + .out(chany_top_out[16]) + ); + mux_tree_tapbuf_size2 mux_top_track_34 + ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[18]}), + .sram(mux_tree_tapbuf_size2_11_sram), + .sram_inv(mux_top_track_34_undriven_sram_inv), + .out(chany_top_out[17]) + ); + mux_tree_tapbuf_size2 mux_top_track_44 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[23]}), + .sram(mux_tree_tapbuf_size2_12_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size2 mux_top_track_46 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[24]}), + .sram(mux_tree_tapbuf_size2_13_sram), + .sram_inv(mux_top_track_46_undriven_sram_inv), + .out(chany_top_out[23]) + ); + mux_tree_tapbuf_size2 mux_top_track_48 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[25]}), + .sram(mux_tree_tapbuf_size2_14_sram), + .sram_inv(mux_top_track_48_undriven_sram_inv), + .out(chany_top_out[24]) + ); + mux_tree_tapbuf_size2 mux_top_track_50 + ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[26]}), + .sram(mux_tree_tapbuf_size2_15_sram), + .sram_inv(mux_top_track_50_undriven_sram_inv), + .out(chany_top_out[25]) + ); + mux_tree_tapbuf_size2 mux_right_track_2 + ( + .in({chany_top_in[0], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_16_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size2 mux_right_track_4 + ( + .in({chany_top_in[1], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_17_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size2 mux_right_track_8 + ( + .in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_18_sram), + .sram_inv(mux_right_track_8_undriven_sram_inv), + .out(chanx_right_out[4]) + ); + mux_tree_tapbuf_size2 mux_right_track_10 + ( + .in({chany_top_in[4], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_19_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size2 mux_right_track_12 + ( + .in({chany_top_in[5], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_20_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size2 mux_right_track_14 + ( + .in({chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram), + .sram_inv(mux_right_track_14_undriven_sram_inv), + .out(chanx_right_out[7]) + ); + mux_tree_tapbuf_size2 mux_right_track_16 + ( + .in({chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_22_sram), + .sram_inv(mux_right_track_16_undriven_sram_inv), + .out(chanx_right_out[8]) + ); + mux_tree_tapbuf_size2 mux_right_track_18 + ( + .in({chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_23_sram), + .sram_inv(mux_right_track_18_undriven_sram_inv), + .out(chanx_right_out[9]) + ); + mux_tree_tapbuf_size2 mux_right_track_28 + ( + .in({chany_top_in[13], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_24_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size2 mux_right_track_30 + ( + .in({chany_top_in[14], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_25_sram), + .sram_inv(mux_right_track_30_undriven_sram_inv), + .out(chanx_right_out[15]) + ); + mux_tree_tapbuf_size2 mux_right_track_32 + ( + .in({chany_top_in[15], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_26_sram), + .sram_inv(mux_right_track_32_undriven_sram_inv), + .out(chanx_right_out[16]) + ); + mux_tree_tapbuf_size2 mux_right_track_34 + ( + .in({chany_top_in[16], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_27_sram), + .sram_inv(mux_right_track_34_undriven_sram_inv), + .out(chanx_right_out[17]) + ); + mux_tree_tapbuf_size2 mux_right_track_44 + ( + .in({chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_28_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size2 mux_right_track_46 + ( + .in({chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_29_sram), + .sram_inv(mux_right_track_46_undriven_sram_inv), + .out(chanx_right_out[23]) + ); + mux_tree_tapbuf_size2 mux_right_track_48 + ( + .in({chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_30_sram), + .sram_inv(mux_right_track_48_undriven_sram_inv), + .out(chanx_right_out[24]) + ); + mux_tree_tapbuf_size2 mux_right_track_50 + ( + .in({chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_31_sram), + .sram_inv(mux_right_track_50_undriven_sram_inv), + .out(chanx_right_out[25]) + ); + mux_tree_tapbuf_size2_mem mem_top_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_16 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_18 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_30 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_32 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_34 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_46 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_48 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_50 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_16 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_18 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_30 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_25_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_32 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_26_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_34 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_27_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_28_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_28_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_46 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_28_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_29_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_29_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_48 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_29_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_30_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_30_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_50 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_30_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_31_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__1_.v new file mode 100644 index 0000000..d28f361 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__1_.v @@ -0,0 +1,1026 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_0__1_ +( + pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + chanx_right_in, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + chany_bottom_in, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_right_out, + chany_bottom_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_top_in; + input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + input top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + input [0:29]chanx_right_in; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input [0:29]chany_bottom_in; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + input ccff_head; + output [0:29]chany_top_out; + output [0:29]chanx_right_out; + output [0:29]chany_bottom_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_top_in; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire [0:29]chanx_right_in; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire [0:29]chany_bottom_in; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head; + wire [0:29]chany_top_out; + wire [0:29]chanx_right_out; + wire [0:29]chany_bottom_out; + wire ccff_tail; + wire [0:2]mux_bottom_track_11_undriven_sram_inv; + wire [0:2]mux_bottom_track_13_undriven_sram_inv; + wire [0:2]mux_bottom_track_1_undriven_sram_inv; + wire [0:2]mux_bottom_track_21_undriven_sram_inv; + wire [0:2]mux_bottom_track_29_undriven_sram_inv; + wire [0:2]mux_bottom_track_37_undriven_sram_inv; + wire [0:2]mux_bottom_track_3_undriven_sram_inv; + wire [0:2]mux_bottom_track_45_undriven_sram_inv; + wire [0:1]mux_bottom_track_53_undriven_sram_inv; + wire [0:2]mux_bottom_track_5_undriven_sram_inv; + wire [0:2]mux_bottom_track_7_undriven_sram_inv; + wire [0:2]mux_right_track_0_undriven_sram_inv; + wire [0:2]mux_right_track_10_undriven_sram_inv; + wire [0:2]mux_right_track_12_undriven_sram_inv; + wire [0:2]mux_right_track_14_undriven_sram_inv; + wire [0:2]mux_right_track_16_undriven_sram_inv; + wire [0:2]mux_right_track_18_undriven_sram_inv; + wire [0:2]mux_right_track_20_undriven_sram_inv; + wire [0:2]mux_right_track_22_undriven_sram_inv; + wire [0:1]mux_right_track_24_undriven_sram_inv; + wire [0:1]mux_right_track_26_undriven_sram_inv; + wire [0:1]mux_right_track_28_undriven_sram_inv; + wire [0:2]mux_right_track_2_undriven_sram_inv; + wire [0:1]mux_right_track_30_undriven_sram_inv; + wire [0:1]mux_right_track_32_undriven_sram_inv; + wire [0:1]mux_right_track_34_undriven_sram_inv; + wire [0:2]mux_right_track_36_undriven_sram_inv; + wire [0:1]mux_right_track_38_undriven_sram_inv; + wire [0:1]mux_right_track_40_undriven_sram_inv; + wire [0:1]mux_right_track_44_undriven_sram_inv; + wire [0:1]mux_right_track_46_undriven_sram_inv; + wire [0:1]mux_right_track_48_undriven_sram_inv; + wire [0:2]mux_right_track_4_undriven_sram_inv; + wire [0:1]mux_right_track_50_undriven_sram_inv; + wire [0:1]mux_right_track_52_undriven_sram_inv; + wire [0:1]mux_right_track_54_undriven_sram_inv; + wire [0:1]mux_right_track_56_undriven_sram_inv; + wire [0:2]mux_right_track_6_undriven_sram_inv; + wire [0:2]mux_right_track_8_undriven_sram_inv; + wire [0:2]mux_top_track_0_undriven_sram_inv; + wire [0:2]mux_top_track_10_undriven_sram_inv; + wire [0:2]mux_top_track_12_undriven_sram_inv; + wire [0:2]mux_top_track_20_undriven_sram_inv; + wire [0:2]mux_top_track_28_undriven_sram_inv; + wire [0:2]mux_top_track_2_undriven_sram_inv; + wire [0:2]mux_top_track_36_undriven_sram_inv; + wire [0:1]mux_top_track_44_undriven_sram_inv; + wire [0:2]mux_top_track_4_undriven_sram_inv; + wire [0:2]mux_top_track_52_undriven_sram_inv; + wire [0:2]mux_top_track_6_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire [0:1]mux_tree_tapbuf_size3_7_sram; + wire [0:1]mux_tree_tapbuf_size3_8_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire mux_tree_tapbuf_size3_mem_7_ccff_tail; + wire [0:2]mux_tree_tapbuf_size4_0_sram; + wire [0:2]mux_tree_tapbuf_size4_1_sram; + wire [0:2]mux_tree_tapbuf_size4_2_sram; + wire [0:2]mux_tree_tapbuf_size4_3_sram; + wire [0:2]mux_tree_tapbuf_size4_4_sram; + wire [0:2]mux_tree_tapbuf_size4_5_sram; + wire [0:2]mux_tree_tapbuf_size4_6_sram; + wire [0:2]mux_tree_tapbuf_size4_7_sram; + wire [0:2]mux_tree_tapbuf_size4_8_sram; + wire [0:2]mux_tree_tapbuf_size4_9_sram; + wire mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire mux_tree_tapbuf_size4_mem_4_ccff_tail; + wire mux_tree_tapbuf_size4_mem_5_ccff_tail; + wire mux_tree_tapbuf_size4_mem_6_ccff_tail; + wire mux_tree_tapbuf_size4_mem_7_ccff_tail; + wire mux_tree_tapbuf_size4_mem_8_ccff_tail; + wire mux_tree_tapbuf_size4_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire [0:2]mux_tree_tapbuf_size5_5_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire mux_tree_tapbuf_size5_mem_5_ccff_tail; + wire [0:2]mux_tree_tapbuf_size6_0_sram; + wire [0:2]mux_tree_tapbuf_size6_10_sram; + wire [0:2]mux_tree_tapbuf_size6_11_sram; + wire [0:2]mux_tree_tapbuf_size6_1_sram; + wire [0:2]mux_tree_tapbuf_size6_2_sram; + wire [0:2]mux_tree_tapbuf_size6_3_sram; + wire [0:2]mux_tree_tapbuf_size6_4_sram; + wire [0:2]mux_tree_tapbuf_size6_5_sram; + wire [0:2]mux_tree_tapbuf_size6_6_sram; + wire [0:2]mux_tree_tapbuf_size6_7_sram; + wire [0:2]mux_tree_tapbuf_size6_8_sram; + wire [0:2]mux_tree_tapbuf_size6_9_sram; + wire mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire mux_tree_tapbuf_size6_mem_10_ccff_tail; + wire mux_tree_tapbuf_size6_mem_11_ccff_tail; + wire mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire mux_tree_tapbuf_size6_mem_7_ccff_tail; + wire mux_tree_tapbuf_size6_mem_8_ccff_tail; + wire mux_tree_tapbuf_size6_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size7_0_sram; + wire [0:2]mux_tree_tapbuf_size7_1_sram; + wire [0:2]mux_tree_tapbuf_size7_2_sram; + wire [0:2]mux_tree_tapbuf_size7_3_sram; + wire [0:2]mux_tree_tapbuf_size7_4_sram; + wire mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire mux_tree_tapbuf_size7_mem_4_ccff_tail; + +assign chany_bottom_out[4] = chany_top_in[3]; +assign chany_bottom_out[7] = chany_top_in[6]; +assign chany_bottom_out[8] = chany_top_in[7]; +assign chany_bottom_out[9] = chany_top_in[8]; +assign chany_bottom_out[11] = chany_top_in[10]; +assign chany_bottom_out[12] = chany_top_in[11]; +assign chany_bottom_out[13] = chany_top_in[12]; +assign chany_bottom_out[15] = chany_top_in[14]; +assign chany_bottom_out[16] = chany_top_in[15]; +assign chany_bottom_out[17] = chany_top_in[16]; +assign chany_bottom_out[19] = chany_top_in[18]; +assign chany_bottom_out[20] = chany_top_in[19]; +assign chany_bottom_out[21] = chany_top_in[20]; +assign chany_bottom_out[23] = chany_top_in[22]; +assign chany_bottom_out[24] = chany_top_in[23]; +assign chany_bottom_out[25] = chany_top_in[24]; +assign chany_bottom_out[27] = chany_top_in[26]; +assign chany_bottom_out[28] = chany_top_in[27]; +assign chany_bottom_out[29] = chany_top_in[28]; +assign chany_top_out[4] = chany_bottom_in[3]; +assign chany_top_out[7] = chany_bottom_in[6]; +assign chany_top_out[8] = chany_bottom_in[7]; +assign chany_top_out[9] = chany_bottom_in[8]; +assign chany_top_out[11] = chany_bottom_in[10]; +assign chany_top_out[12] = chany_bottom_in[11]; +assign chany_top_out[13] = chany_bottom_in[12]; +assign chany_top_out[15] = chany_bottom_in[14]; +assign chany_top_out[16] = chany_bottom_in[15]; +assign chany_top_out[17] = chany_bottom_in[16]; +assign chanx_right_out[21] = chany_bottom_in[17]; +assign chany_top_out[19] = chany_bottom_in[18]; +assign chany_top_out[20] = chany_bottom_in[19]; +assign chany_top_out[21] = chany_bottom_in[20]; +assign chany_top_out[23] = chany_bottom_in[22]; +assign chany_top_out[24] = chany_bottom_in[23]; +assign chany_top_out[25] = chany_bottom_in[24]; +assign chany_top_out[27] = chany_bottom_in[26]; +assign chany_top_out[28] = chany_bottom_in[27]; +assign chany_top_out[29] = chany_bottom_in[28]; + mux_tree_tapbuf_size7 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[1], chanx_right_in[12], chanx_right_in[23], chany_bottom_in[3], chany_bottom_in[19]}), + .sram(mux_tree_tapbuf_size7_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size7 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[4], chanx_right_in[15], chanx_right_in[26], chany_bottom_in[8], chany_bottom_in[23]}), + .sram(mux_tree_tapbuf_size7_1_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); + mux_tree_tapbuf_size7 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[5], chanx_right_in[16], chanx_right_in[27], chany_bottom_in[10], chany_bottom_in[24]}), + .sram(mux_tree_tapbuf_size7_2_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size7 mux_bottom_track_7 + ( + .in({chany_top_in[8], chany_top_in[23], chanx_right_in[6], chanx_right_in[17], chanx_right_in[28], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_3_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size7 mux_bottom_track_11 + ( + .in({chany_top_in[10], chany_top_in[24], chanx_right_in[5], chanx_right_in[16], chanx_right_in[27], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_4_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size7_mem mem_top_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram) + ); + mux_tree_tapbuf_size7_mem mem_top_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram) + ); + mux_tree_tapbuf_size7_mem mem_top_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram) + ); + mux_tree_tapbuf_size7_mem mem_bottom_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram) + ); + mux_tree_tapbuf_size7_mem mem_bottom_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram) + ); + mux_tree_tapbuf_size6 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[2], chanx_right_in[13], chanx_right_in[24], chany_bottom_in[6], chany_bottom_in[20]}), + .sram(mux_tree_tapbuf_size6_0_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size6 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[3], chanx_right_in[14], chanx_right_in[25], chany_bottom_in[7], chany_bottom_in[22]}), + .sram(mux_tree_tapbuf_size6_1_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size6 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[6], chanx_right_in[17], chanx_right_in[28], chany_bottom_in[11], chany_bottom_in[26]}), + .sram(mux_tree_tapbuf_size6_2_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size6 mux_top_track_20 + ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[7], chanx_right_in[18], chanx_right_in[29], chany_bottom_in[12], chany_bottom_in[27]}), + .sram(mux_tree_tapbuf_size6_3_sram), + .sram_inv(mux_top_track_20_undriven_sram_inv), + .out(chany_top_out[10]) + ); + mux_tree_tapbuf_size6 mux_right_track_2 + ( + .in({chany_top_in[0], chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[6]}), + .sram(mux_tree_tapbuf_size6_4_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size6 mux_right_track_6 + ( + .in({chany_top_in[2], chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[8]}), + .sram(mux_tree_tapbuf_size6_5_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size6 mux_right_track_8 + ( + .in({chany_top_in[4], chany_top_in[10], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[10]}), + .sram(mux_tree_tapbuf_size6_6_sram), + .sram_inv(mux_right_track_8_undriven_sram_inv), + .out(chanx_right_out[4]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_1 + ( + .in({chany_top_in[3], chany_top_in[19], chanx_right_in[9], chanx_right_in[20], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_7_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_5 + ( + .in({chany_top_in[7], chany_top_in[22], chanx_right_in[7], chanx_right_in[18], chanx_right_in[29], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_8_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_13 + ( + .in({chany_top_in[11], chany_top_in[26], chanx_right_in[4], chanx_right_in[15], chanx_right_in[26], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_9_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_21 + ( + .in({chany_top_in[12], chany_top_in[27], chanx_right_in[3], chanx_right_in[14], chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_10_sram), + .sram_inv(mux_bottom_track_21_undriven_sram_inv), + .out(chany_bottom_out[10]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_29 + ( + .in({chany_top_in[14], chany_top_in[28], chanx_right_in[2], chanx_right_in[13], chanx_right_in[24], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_11_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size6_mem mem_top_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_11_sram) + ); + mux_tree_tapbuf_size5 mux_top_track_28 + ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[8], chanx_right_in[19], chany_bottom_in[14], chany_bottom_in[28]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size5 mux_right_track_0 + ( + .in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[3]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size5 mux_right_track_4 + ( + .in({chany_top_in[1], chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[7]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size5 mux_right_track_10 + ( + .in({chany_top_in[5], chany_top_in[11], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[11]}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_3 + ( + .in({chany_top_in[6], chany_top_in[20], chanx_right_in[8], chanx_right_in[19], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_37 + ( + .in({chany_top_in[15], chanx_right_in[1], chanx_right_in[12], chanx_right_in[23], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_5_sram), + .sram_inv(mux_bottom_track_37_undriven_sram_inv), + .out(chany_bottom_out[18]) + ); + mux_tree_tapbuf_size5_mem mem_top_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram) + ); + mux_tree_tapbuf_size4 mux_top_track_36 + ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[9], chanx_right_in[20], chany_bottom_in[15]}), + .sram(mux_tree_tapbuf_size4_0_sram), + .sram_inv(mux_top_track_36_undriven_sram_inv), + .out(chany_top_out[18]) + ); + mux_tree_tapbuf_size4 mux_top_track_52 + ( + .in({chanx_right_in[0], chanx_right_in[11], chanx_right_in[22], chany_bottom_in[18]}), + .sram(mux_tree_tapbuf_size4_1_sram), + .sram_inv(mux_top_track_52_undriven_sram_inv), + .out(chany_top_out[26]) + ); + mux_tree_tapbuf_size4 mux_right_track_12 + ( + .in({chany_top_in[9], chany_top_in[12], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[12]}), + .sram(mux_tree_tapbuf_size4_2_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size4 mux_right_track_14 + ( + .in({chany_top_in[13], chany_top_in[14], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[14]}), + .sram(mux_tree_tapbuf_size4_3_sram), + .sram_inv(mux_right_track_14_undriven_sram_inv), + .out(chanx_right_out[7]) + ); + mux_tree_tapbuf_size4 mux_right_track_16 + ( + .in({chany_top_in[15], chany_top_in[17], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[15]}), + .sram(mux_tree_tapbuf_size4_4_sram), + .sram_inv(mux_right_track_16_undriven_sram_inv), + .out(chanx_right_out[8]) + ); + mux_tree_tapbuf_size4 mux_right_track_18 + ( + .in({chany_top_in[16], chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[16]}), + .sram(mux_tree_tapbuf_size4_5_sram), + .sram_inv(mux_right_track_18_undriven_sram_inv), + .out(chanx_right_out[9]) + ); + mux_tree_tapbuf_size4 mux_right_track_20 + ( + .in({chany_top_in[18], chany_top_in[25], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[18]}), + .sram(mux_tree_tapbuf_size4_6_sram), + .sram_inv(mux_right_track_20_undriven_sram_inv), + .out(chanx_right_out[10]) + ); + mux_tree_tapbuf_size4 mux_right_track_22 + ( + .in({chany_top_in[19], chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[19]}), + .sram(mux_tree_tapbuf_size4_7_sram), + .sram_inv(mux_right_track_22_undriven_sram_inv), + .out(chanx_right_out[11]) + ); + mux_tree_tapbuf_size4 mux_right_track_36 + ( + .in({chany_top_in[28], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[28], chany_bottom_in[29]}), + .sram(mux_tree_tapbuf_size4_8_sram), + .sram_inv(mux_right_track_36_undriven_sram_inv), + .out(chanx_right_out[18]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_45 + ( + .in({chany_top_in[16], chanx_right_in[0], chanx_right_in[11], chanx_right_in[22]}), + .sram(mux_tree_tapbuf_size4_9_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size4_mem mem_top_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram) + ); + mux_tree_tapbuf_size4_mem mem_top_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_16 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_18 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_6_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_22 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_7_sram) + ); + mux_tree_tapbuf_size4_mem mem_right_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_8_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_9_sram) + ); + mux_tree_tapbuf_size3 mux_top_track_44 + ( + .in({chanx_right_in[10], chanx_right_in[21], chany_bottom_in[16]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size3 mux_right_track_24 + ( + .in({chany_top_in[20], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[20]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_right_track_24_undriven_sram_inv), + .out(chanx_right_out[12]) + ); + mux_tree_tapbuf_size3 mux_right_track_26 + ( + .in({chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[22]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_right_track_26_undriven_sram_inv), + .out(chanx_right_out[13]) + ); + mux_tree_tapbuf_size3 mux_right_track_28 + ( + .in({chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[23]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size3 mux_right_track_30 + ( + .in({chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[24]}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_right_track_30_undriven_sram_inv), + .out(chanx_right_out[15]) + ); + mux_tree_tapbuf_size3 mux_right_track_32 + ( + .in({chany_top_in[26], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[26]}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_right_track_32_undriven_sram_inv), + .out(chanx_right_out[16]) + ); + mux_tree_tapbuf_size3 mux_right_track_34 + ( + .in({chany_top_in[27], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[27]}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_right_track_34_undriven_sram_inv), + .out(chanx_right_out[17]) + ); + mux_tree_tapbuf_size3 mux_right_track_50 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[4]}), + .sram(mux_tree_tapbuf_size3_7_sram), + .sram_inv(mux_right_track_50_undriven_sram_inv), + .out(chanx_right_out[25]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_53 + ( + .in({chany_top_in[18], chanx_right_in[10], chanx_right_in[21]}), + .sram(mux_tree_tapbuf_size3_8_sram), + .sram_inv(mux_bottom_track_53_undriven_sram_inv), + .out(chany_bottom_out[26]) + ); + mux_tree_tapbuf_size3_mem mem_top_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_24 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_26 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_30 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_32 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_34 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_50 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_9_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram) + ); + mux_tree_tapbuf_size2 mux_right_track_38 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[25]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_right_track_38_undriven_sram_inv), + .out(chanx_right_out[19]) + ); + mux_tree_tapbuf_size2 mux_right_track_40 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[21]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_right_track_40_undriven_sram_inv), + .out(chanx_right_out[20]) + ); + mux_tree_tapbuf_size2 mux_right_track_44 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[13]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size2 mux_right_track_46 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[9]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_right_track_46_undriven_sram_inv), + .out(chanx_right_out[23]) + ); + mux_tree_tapbuf_size2 mux_right_track_48 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[5]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_right_track_48_undriven_sram_inv), + .out(chanx_right_out[24]) + ); + mux_tree_tapbuf_size2 mux_right_track_52 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[2]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_right_track_52_undriven_sram_inv), + .out(chanx_right_out[26]) + ); + mux_tree_tapbuf_size2 mux_right_track_54 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[1]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_right_track_54_undriven_sram_inv), + .out(chanx_right_out[27]) + ); + mux_tree_tapbuf_size2 mux_right_track_56 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[0]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_right_track_56_undriven_sram_inv), + .out(chanx_right_out[28]) + ); + mux_tree_tapbuf_size2_mem mem_right_track_38 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_40 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_46 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_48 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_54 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_56 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__8_.v new file mode 100644 index 0000000..a9fc3df --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__8_.v @@ -0,0 +1,957 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_0__8_ +( + pReset, + prog_clk, + chanx_right_in, + right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + chany_bottom_in, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chanx_right_out, + chany_bottom_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chanx_right_in; + input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input [0:29]chany_bottom_in; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + input ccff_head; + output [0:29]chanx_right_out; + output [0:29]chany_bottom_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chanx_right_in; + wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire [0:29]chany_bottom_in; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head; + wire [0:29]chanx_right_out; + wire [0:29]chany_bottom_out; + wire ccff_tail; + wire [0:1]mux_bottom_track_11_undriven_sram_inv; + wire [0:1]mux_bottom_track_13_undriven_sram_inv; + wire [0:1]mux_bottom_track_15_undriven_sram_inv; + wire [0:1]mux_bottom_track_17_undriven_sram_inv; + wire [0:1]mux_bottom_track_19_undriven_sram_inv; + wire [0:1]mux_bottom_track_1_undriven_sram_inv; + wire [0:1]mux_bottom_track_29_undriven_sram_inv; + wire [0:1]mux_bottom_track_31_undriven_sram_inv; + wire [0:1]mux_bottom_track_33_undriven_sram_inv; + wire [0:1]mux_bottom_track_35_undriven_sram_inv; + wire [0:1]mux_bottom_track_3_undriven_sram_inv; + wire [0:1]mux_bottom_track_45_undriven_sram_inv; + wire [0:1]mux_bottom_track_47_undriven_sram_inv; + wire [0:1]mux_bottom_track_49_undriven_sram_inv; + wire [0:1]mux_bottom_track_51_undriven_sram_inv; + wire [0:1]mux_bottom_track_5_undriven_sram_inv; + wire [0:1]mux_bottom_track_7_undriven_sram_inv; + wire [0:1]mux_bottom_track_9_undriven_sram_inv; + wire [0:2]mux_right_track_0_undriven_sram_inv; + wire [0:2]mux_right_track_10_undriven_sram_inv; + wire [0:1]mux_right_track_12_undriven_sram_inv; + wire [0:1]mux_right_track_14_undriven_sram_inv; + wire [0:1]mux_right_track_16_undriven_sram_inv; + wire [0:1]mux_right_track_18_undriven_sram_inv; + wire [0:1]mux_right_track_20_undriven_sram_inv; + wire [0:1]mux_right_track_22_undriven_sram_inv; + wire [0:1]mux_right_track_24_undriven_sram_inv; + wire [0:1]mux_right_track_26_undriven_sram_inv; + wire [0:1]mux_right_track_28_undriven_sram_inv; + wire [0:2]mux_right_track_2_undriven_sram_inv; + wire [0:1]mux_right_track_30_undriven_sram_inv; + wire [0:1]mux_right_track_32_undriven_sram_inv; + wire [0:1]mux_right_track_34_undriven_sram_inv; + wire [0:1]mux_right_track_36_undriven_sram_inv; + wire [0:1]mux_right_track_38_undriven_sram_inv; + wire [0:1]mux_right_track_40_undriven_sram_inv; + wire [0:1]mux_right_track_42_undriven_sram_inv; + wire [0:1]mux_right_track_44_undriven_sram_inv; + wire [0:1]mux_right_track_46_undriven_sram_inv; + wire [0:1]mux_right_track_48_undriven_sram_inv; + wire [0:2]mux_right_track_4_undriven_sram_inv; + wire [0:1]mux_right_track_50_undriven_sram_inv; + wire [0:1]mux_right_track_52_undriven_sram_inv; + wire [0:1]mux_right_track_54_undriven_sram_inv; + wire [0:1]mux_right_track_56_undriven_sram_inv; + wire [0:1]mux_right_track_58_undriven_sram_inv; + wire [0:2]mux_right_track_6_undriven_sram_inv; + wire [0:2]mux_right_track_8_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_11_sram; + wire [0:1]mux_tree_tapbuf_size2_12_sram; + wire [0:1]mux_tree_tapbuf_size2_13_sram; + wire [0:1]mux_tree_tapbuf_size2_14_sram; + wire [0:1]mux_tree_tapbuf_size2_15_sram; + wire [0:1]mux_tree_tapbuf_size2_16_sram; + wire [0:1]mux_tree_tapbuf_size2_17_sram; + wire [0:1]mux_tree_tapbuf_size2_18_sram; + wire [0:1]mux_tree_tapbuf_size2_19_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_20_sram; + wire [0:1]mux_tree_tapbuf_size2_21_sram; + wire [0:1]mux_tree_tapbuf_size2_22_sram; + wire [0:1]mux_tree_tapbuf_size2_23_sram; + wire [0:1]mux_tree_tapbuf_size2_24_sram; + wire [0:1]mux_tree_tapbuf_size2_25_sram; + wire [0:1]mux_tree_tapbuf_size2_26_sram; + wire [0:1]mux_tree_tapbuf_size2_27_sram; + wire [0:1]mux_tree_tapbuf_size2_28_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire mux_tree_tapbuf_size2_mem_19_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_20_ccff_tail; + wire mux_tree_tapbuf_size2_mem_21_ccff_tail; + wire mux_tree_tapbuf_size2_mem_22_ccff_tail; + wire mux_tree_tapbuf_size2_mem_23_ccff_tail; + wire mux_tree_tapbuf_size2_mem_24_ccff_tail; + wire mux_tree_tapbuf_size2_mem_25_ccff_tail; + wire mux_tree_tapbuf_size2_mem_26_ccff_tail; + wire mux_tree_tapbuf_size2_mem_27_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_10_sram; + wire [0:1]mux_tree_tapbuf_size3_11_sram; + wire [0:1]mux_tree_tapbuf_size3_12_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire [0:1]mux_tree_tapbuf_size3_7_sram; + wire [0:1]mux_tree_tapbuf_size3_8_sram; + wire [0:1]mux_tree_tapbuf_size3_9_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_10_ccff_tail; + wire mux_tree_tapbuf_size3_mem_11_ccff_tail; + wire mux_tree_tapbuf_size3_mem_12_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire mux_tree_tapbuf_size3_mem_7_ccff_tail; + wire mux_tree_tapbuf_size3_mem_8_ccff_tail; + wire mux_tree_tapbuf_size3_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire [0:2]mux_tree_tapbuf_size5_5_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire mux_tree_tapbuf_size5_mem_5_ccff_tail; + +assign chany_bottom_out[28] = chanx_right_in[0]; +assign chany_bottom_out[27] = chanx_right_in[1]; +assign chany_bottom_out[26] = chanx_right_in[2]; +assign chany_bottom_out[21] = chanx_right_in[7]; +assign chany_bottom_out[20] = chanx_right_in[8]; +assign chany_bottom_out[19] = chanx_right_in[9]; +assign chany_bottom_out[18] = chanx_right_in[10]; +assign chany_bottom_out[13] = chanx_right_in[15]; +assign chany_bottom_out[12] = chanx_right_in[16]; +assign chany_bottom_out[11] = chanx_right_in[17]; +assign chany_bottom_out[10] = chanx_right_in[18]; +assign chany_bottom_out[29] = chanx_right_in[29]; + mux_tree_tapbuf_size5 mux_right_track_0 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[28]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size5 mux_right_track_2 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[27]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size5 mux_right_track_4 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[26]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size5 mux_right_track_6 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[25]}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size5 mux_right_track_8 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[24]}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_right_track_8_undriven_sram_inv), + .out(chanx_right_out[4]) + ); + mux_tree_tapbuf_size5 mux_right_track_10 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[23]}), + .sram(mux_tree_tapbuf_size5_5_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size5_mem mem_right_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram) + ); + mux_tree_tapbuf_size3 mux_right_track_12 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[22]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size3 mux_right_track_14 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[21]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_right_track_14_undriven_sram_inv), + .out(chanx_right_out[7]) + ); + mux_tree_tapbuf_size3 mux_right_track_16 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[20]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_right_track_16_undriven_sram_inv), + .out(chanx_right_out[8]) + ); + mux_tree_tapbuf_size3 mux_right_track_28 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[14]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size3 mux_right_track_30 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[13]}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_right_track_30_undriven_sram_inv), + .out(chanx_right_out[15]) + ); + mux_tree_tapbuf_size3 mux_right_track_32 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[12]}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_right_track_32_undriven_sram_inv), + .out(chanx_right_out[16]) + ); + mux_tree_tapbuf_size3 mux_right_track_34 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[11]}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_right_track_34_undriven_sram_inv), + .out(chanx_right_out[17]) + ); + mux_tree_tapbuf_size3 mux_right_track_44 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[6]}), + .sram(mux_tree_tapbuf_size3_7_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size3 mux_right_track_46 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[5]}), + .sram(mux_tree_tapbuf_size3_8_sram), + .sram_inv(mux_right_track_46_undriven_sram_inv), + .out(chanx_right_out[23]) + ); + mux_tree_tapbuf_size3 mux_right_track_48 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[4]}), + .sram(mux_tree_tapbuf_size3_9_sram), + .sram_inv(mux_right_track_48_undriven_sram_inv), + .out(chanx_right_out[24]) + ); + mux_tree_tapbuf_size3 mux_right_track_58 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[29]}), + .sram(mux_tree_tapbuf_size3_10_sram), + .sram_inv(mux_right_track_58_undriven_sram_inv), + .out(chanx_right_out[29]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_1 + ( + .in({chanx_right_in[28], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_11_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_7 + ( + .in({chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_12_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size3_mem mem_right_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_16 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_30 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_32 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_34 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_46 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_48 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_58 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_12_sram) + ); + mux_tree_tapbuf_size2 mux_right_track_18 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[19]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_right_track_18_undriven_sram_inv), + .out(chanx_right_out[9]) + ); + mux_tree_tapbuf_size2 mux_right_track_20 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[18]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_right_track_20_undriven_sram_inv), + .out(chanx_right_out[10]) + ); + mux_tree_tapbuf_size2 mux_right_track_22 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[17]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_right_track_22_undriven_sram_inv), + .out(chanx_right_out[11]) + ); + mux_tree_tapbuf_size2 mux_right_track_24 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[16]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_right_track_24_undriven_sram_inv), + .out(chanx_right_out[12]) + ); + mux_tree_tapbuf_size2 mux_right_track_26 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[15]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_right_track_26_undriven_sram_inv), + .out(chanx_right_out[13]) + ); + mux_tree_tapbuf_size2 mux_right_track_36 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[10]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_right_track_36_undriven_sram_inv), + .out(chanx_right_out[18]) + ); + mux_tree_tapbuf_size2 mux_right_track_38 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[9]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_right_track_38_undriven_sram_inv), + .out(chanx_right_out[19]) + ); + mux_tree_tapbuf_size2 mux_right_track_40 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[8]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_right_track_40_undriven_sram_inv), + .out(chanx_right_out[20]) + ); + mux_tree_tapbuf_size2 mux_right_track_42 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[7]}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_right_track_42_undriven_sram_inv), + .out(chanx_right_out[21]) + ); + mux_tree_tapbuf_size2 mux_right_track_50 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[3]}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_right_track_50_undriven_sram_inv), + .out(chanx_right_out[25]) + ); + mux_tree_tapbuf_size2 mux_right_track_52 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[2]}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_right_track_52_undriven_sram_inv), + .out(chanx_right_out[26]) + ); + mux_tree_tapbuf_size2 mux_right_track_54 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[1]}), + .sram(mux_tree_tapbuf_size2_11_sram), + .sram_inv(mux_right_track_54_undriven_sram_inv), + .out(chanx_right_out[27]) + ); + mux_tree_tapbuf_size2 mux_right_track_56 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[0]}), + .sram(mux_tree_tapbuf_size2_12_sram), + .sram_inv(mux_right_track_56_undriven_sram_inv), + .out(chanx_right_out[28]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_3 + ( + .in({chanx_right_in[27], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_13_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_5 + ( + .in({chanx_right_in[26], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_14_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_9 + ( + .in({chanx_right_in[24], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_15_sram), + .sram_inv(mux_bottom_track_9_undriven_sram_inv), + .out(chany_bottom_out[4]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_11 + ( + .in({chanx_right_in[23], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_16_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_13 + ( + .in({chanx_right_in[22], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_17_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_15 + ( + .in({chanx_right_in[21], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_18_sram), + .sram_inv(mux_bottom_track_15_undriven_sram_inv), + .out(chany_bottom_out[7]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_17 + ( + .in({chanx_right_in[20], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_19_sram), + .sram_inv(mux_bottom_track_17_undriven_sram_inv), + .out(chany_bottom_out[8]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_19 + ( + .in({chanx_right_in[19], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_20_sram), + .sram_inv(mux_bottom_track_19_undriven_sram_inv), + .out(chany_bottom_out[9]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_29 + ( + .in({chanx_right_in[14], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_31 + ( + .in({chanx_right_in[13], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_22_sram), + .sram_inv(mux_bottom_track_31_undriven_sram_inv), + .out(chany_bottom_out[15]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_33 + ( + .in({chanx_right_in[12], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_23_sram), + .sram_inv(mux_bottom_track_33_undriven_sram_inv), + .out(chany_bottom_out[16]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_35 + ( + .in({chanx_right_in[11], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_24_sram), + .sram_inv(mux_bottom_track_35_undriven_sram_inv), + .out(chany_bottom_out[17]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_45 + ( + .in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_25_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_47 + ( + .in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_26_sram), + .sram_inv(mux_bottom_track_47_undriven_sram_inv), + .out(chany_bottom_out[23]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_49 + ( + .in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_27_sram), + .sram_inv(mux_bottom_track_49_undriven_sram_inv), + .out(chany_bottom_out[24]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_51 + ( + .in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_28_sram), + .sram_inv(mux_bottom_track_51_undriven_sram_inv), + .out(chany_bottom_out[25]) + ); + mux_tree_tapbuf_size2_mem mem_right_track_18 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_22 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_24 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_26 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_38 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_40 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_42 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_50 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_54 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram) + ); + mux_tree_tapbuf_size2_mem mem_right_track_56 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_17 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_19 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_31 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_33 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_35 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_25_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_47 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_26_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_49 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_27_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_51 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_28_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__0_.v new file mode 100644 index 0000000..8e5fb2d --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__0_.v @@ -0,0 +1,993 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_1__0_ +( + pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_right_in, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + chanx_left_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_right_out, + chanx_left_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_top_in; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input [0:29]chanx_right_in; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + input [0:29]chanx_left_in; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + input ccff_head; + output [0:29]chany_top_out; + output [0:29]chanx_right_out; + output [0:29]chanx_left_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_top_in; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire [0:29]chanx_right_in; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire [0:29]chanx_left_in; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head; + wire [0:29]chany_top_out; + wire [0:29]chanx_right_out; + wire [0:29]chanx_left_out; + wire ccff_tail; + wire [0:2]mux_left_track_11_undriven_sram_inv; + wire [0:2]mux_left_track_13_undriven_sram_inv; + wire [0:2]mux_left_track_1_undriven_sram_inv; + wire [0:2]mux_left_track_21_undriven_sram_inv; + wire [0:2]mux_left_track_29_undriven_sram_inv; + wire [0:2]mux_left_track_37_undriven_sram_inv; + wire [0:2]mux_left_track_3_undriven_sram_inv; + wire [0:2]mux_left_track_45_undriven_sram_inv; + wire [0:2]mux_left_track_53_undriven_sram_inv; + wire [0:2]mux_left_track_5_undriven_sram_inv; + wire [0:2]mux_left_track_7_undriven_sram_inv; + wire [0:2]mux_right_track_0_undriven_sram_inv; + wire [0:2]mux_right_track_10_undriven_sram_inv; + wire [0:2]mux_right_track_12_undriven_sram_inv; + wire [0:2]mux_right_track_20_undriven_sram_inv; + wire [0:2]mux_right_track_28_undriven_sram_inv; + wire [0:2]mux_right_track_2_undriven_sram_inv; + wire [0:2]mux_right_track_36_undriven_sram_inv; + wire [0:1]mux_right_track_44_undriven_sram_inv; + wire [0:2]mux_right_track_4_undriven_sram_inv; + wire [0:1]mux_right_track_52_undriven_sram_inv; + wire [0:2]mux_right_track_6_undriven_sram_inv; + wire [0:2]mux_top_track_0_undriven_sram_inv; + wire [0:2]mux_top_track_10_undriven_sram_inv; + wire [0:2]mux_top_track_12_undriven_sram_inv; + wire [0:2]mux_top_track_14_undriven_sram_inv; + wire [0:2]mux_top_track_16_undriven_sram_inv; + wire [0:2]mux_top_track_18_undriven_sram_inv; + wire [0:1]mux_top_track_20_undriven_sram_inv; + wire [0:1]mux_top_track_22_undriven_sram_inv; + wire [0:1]mux_top_track_24_undriven_sram_inv; + wire [0:1]mux_top_track_26_undriven_sram_inv; + wire [0:1]mux_top_track_28_undriven_sram_inv; + wire [0:2]mux_top_track_2_undriven_sram_inv; + wire [0:1]mux_top_track_30_undriven_sram_inv; + wire [0:1]mux_top_track_32_undriven_sram_inv; + wire [0:1]mux_top_track_34_undriven_sram_inv; + wire [0:1]mux_top_track_36_undriven_sram_inv; + wire [0:1]mux_top_track_40_undriven_sram_inv; + wire [0:1]mux_top_track_42_undriven_sram_inv; + wire [0:1]mux_top_track_44_undriven_sram_inv; + wire [0:1]mux_top_track_46_undriven_sram_inv; + wire [0:1]mux_top_track_48_undriven_sram_inv; + wire [0:2]mux_top_track_4_undriven_sram_inv; + wire [0:1]mux_top_track_50_undriven_sram_inv; + wire [0:1]mux_top_track_58_undriven_sram_inv; + wire [0:2]mux_top_track_6_undriven_sram_inv; + wire [0:2]mux_top_track_8_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire [0:2]mux_tree_tapbuf_size4_0_sram; + wire [0:2]mux_tree_tapbuf_size4_1_sram; + wire [0:2]mux_tree_tapbuf_size4_2_sram; + wire [0:2]mux_tree_tapbuf_size4_3_sram; + wire [0:2]mux_tree_tapbuf_size4_4_sram; + wire [0:2]mux_tree_tapbuf_size4_5_sram; + wire mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire mux_tree_tapbuf_size4_mem_4_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire [0:2]mux_tree_tapbuf_size5_5_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire mux_tree_tapbuf_size5_mem_5_ccff_tail; + wire [0:2]mux_tree_tapbuf_size6_0_sram; + wire [0:2]mux_tree_tapbuf_size6_10_sram; + wire [0:2]mux_tree_tapbuf_size6_11_sram; + wire [0:2]mux_tree_tapbuf_size6_12_sram; + wire [0:2]mux_tree_tapbuf_size6_1_sram; + wire [0:2]mux_tree_tapbuf_size6_2_sram; + wire [0:2]mux_tree_tapbuf_size6_3_sram; + wire [0:2]mux_tree_tapbuf_size6_4_sram; + wire [0:2]mux_tree_tapbuf_size6_5_sram; + wire [0:2]mux_tree_tapbuf_size6_6_sram; + wire [0:2]mux_tree_tapbuf_size6_7_sram; + wire [0:2]mux_tree_tapbuf_size6_8_sram; + wire [0:2]mux_tree_tapbuf_size6_9_sram; + wire mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire mux_tree_tapbuf_size6_mem_10_ccff_tail; + wire mux_tree_tapbuf_size6_mem_11_ccff_tail; + wire mux_tree_tapbuf_size6_mem_12_ccff_tail; + wire mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire mux_tree_tapbuf_size6_mem_7_ccff_tail; + wire mux_tree_tapbuf_size6_mem_8_ccff_tail; + wire mux_tree_tapbuf_size6_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size7_0_sram; + wire [0:2]mux_tree_tapbuf_size7_1_sram; + wire [0:2]mux_tree_tapbuf_size7_2_sram; + wire [0:2]mux_tree_tapbuf_size7_3_sram; + wire [0:2]mux_tree_tapbuf_size7_4_sram; + wire mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire mux_tree_tapbuf_size7_mem_4_ccff_tail; + +assign chany_top_out[19] = top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; +assign chanx_left_out[4] = chanx_right_in[3]; +assign chanx_left_out[7] = chanx_right_in[6]; +assign chanx_left_out[8] = chanx_right_in[7]; +assign chanx_left_out[9] = chanx_right_in[8]; +assign chanx_left_out[11] = chanx_right_in[10]; +assign chanx_left_out[12] = chanx_right_in[11]; +assign chanx_left_out[13] = chanx_right_in[12]; +assign chanx_left_out[15] = chanx_right_in[14]; +assign chanx_left_out[16] = chanx_right_in[15]; +assign chanx_left_out[17] = chanx_right_in[16]; +assign chanx_left_out[19] = chanx_right_in[18]; +assign chanx_left_out[20] = chanx_right_in[19]; +assign chanx_left_out[21] = chanx_right_in[20]; +assign chanx_left_out[23] = chanx_right_in[22]; +assign chanx_left_out[24] = chanx_right_in[23]; +assign chanx_left_out[25] = chanx_right_in[24]; +assign chanx_left_out[27] = chanx_right_in[26]; +assign chanx_left_out[28] = chanx_right_in[27]; +assign chanx_left_out[29] = chanx_right_in[28]; +assign chany_top_out[28] = chanx_left_in[2]; +assign chanx_right_out[4] = chanx_left_in[3]; +assign chany_top_out[27] = chanx_left_in[4]; +assign chany_top_out[26] = chanx_left_in[5]; +assign chanx_right_out[7] = chanx_left_in[6]; +assign chanx_right_out[8] = chanx_left_in[7]; +assign chanx_right_out[9] = chanx_left_in[8]; +assign chanx_right_out[11] = chanx_left_in[10]; +assign chanx_right_out[12] = chanx_left_in[11]; +assign chanx_right_out[13] = chanx_left_in[12]; +assign chanx_right_out[15] = chanx_left_in[14]; +assign chanx_right_out[16] = chanx_left_in[15]; +assign chanx_right_out[17] = chanx_left_in[16]; +assign chanx_right_out[19] = chanx_left_in[18]; +assign chanx_right_out[20] = chanx_left_in[19]; +assign chanx_right_out[21] = chanx_left_in[20]; +assign chanx_right_out[23] = chanx_left_in[22]; +assign chanx_right_out[24] = chanx_left_in[23]; +assign chanx_right_out[25] = chanx_left_in[24]; +assign chanx_right_out[27] = chanx_left_in[26]; +assign chanx_right_out[28] = chanx_left_in[27]; +assign chanx_right_out[29] = chanx_left_in[28]; + mux_tree_tapbuf_size7 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[1], chanx_right_in[3], chanx_left_in[0], chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size7_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size7 mux_right_track_6 + ( + .in({chany_top_in[2], chany_top_in[13], chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size7_1_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size7 mux_right_track_10 + ( + .in({chany_top_in[3], chany_top_in[14], chany_top_in[25], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size7_2_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size7 mux_left_track_1 + ( + .in({chany_top_in[0], chany_top_in[11], chany_top_in[22], chanx_right_in[3], chanx_right_in[19], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_3_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size7 mux_left_track_11 + ( + .in({chany_top_in[7], chany_top_in[18], chany_top_in[29], chanx_right_in[10], chanx_right_in[24], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size7_4_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size7_mem mem_top_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram) + ); + mux_tree_tapbuf_size7_mem mem_right_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram) + ); + mux_tree_tapbuf_size7_mem mem_right_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram) + ); + mux_tree_tapbuf_size7_mem mem_left_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram) + ); + mux_tree_tapbuf_size7_mem mem_left_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram) + ); + mux_tree_tapbuf_size6 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[2], chanx_right_in[6], chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size6_0_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size6 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[5], chanx_right_in[8], chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size6_1_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); + mux_tree_tapbuf_size6 mux_top_track_8 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[9], chanx_right_in[10], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size6_2_sram), + .sram_inv(mux_top_track_8_undriven_sram_inv), + .out(chany_top_out[4]) + ); + mux_tree_tapbuf_size6 mux_right_track_0 + ( + .in({chany_top_in[10], chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size6_3_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size6 mux_right_track_2 + ( + .in({chany_top_in[0], chany_top_in[11], chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size6_4_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size6 mux_right_track_4 + ( + .in({chany_top_in[1], chany_top_in[12], chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size6_5_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size6 mux_right_track_12 + ( + .in({chany_top_in[4], chany_top_in[15], chany_top_in[26], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[11], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size6_6_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size6 mux_right_track_20 + ( + .in({chany_top_in[5], chany_top_in[16], chany_top_in[27], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size6_7_sram), + .sram_inv(mux_right_track_20_undriven_sram_inv), + .out(chanx_right_out[10]) + ); + mux_tree_tapbuf_size6 mux_right_track_28 + ( + .in({chany_top_in[6], chany_top_in[17], chany_top_in[28], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size6_8_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size6 mux_left_track_7 + ( + .in({chany_top_in[8], chany_top_in[19], chanx_right_in[8], chanx_right_in[23], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_9_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size6 mux_left_track_13 + ( + .in({chany_top_in[6], chany_top_in[17], chany_top_in[28], chanx_right_in[11], chanx_right_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_10_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size6 mux_left_track_21 + ( + .in({chany_top_in[5], chany_top_in[16], chany_top_in[27], chanx_right_in[12], chanx_right_in[27], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_11_sram), + .sram_inv(mux_left_track_21_undriven_sram_inv), + .out(chanx_left_out[10]) + ); + mux_tree_tapbuf_size6 mux_left_track_29 + ( + .in({chany_top_in[4], chany_top_in[15], chany_top_in[26], chanx_right_in[14], chanx_right_in[28], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size6_12_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size6_mem mem_top_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_11_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_12_sram) + ); + mux_tree_tapbuf_size5 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[4], chanx_right_in[7], chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size5 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[11], chanx_right_in[13], chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size5 mux_right_track_36 + ( + .in({chany_top_in[7], chany_top_in[18], chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_right_track_36_undriven_sram_inv), + .out(chanx_right_out[18]) + ); + mux_tree_tapbuf_size5 mux_left_track_3 + ( + .in({chany_top_in[10], chany_top_in[21], chanx_right_in[6], chanx_right_in[20], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size5 mux_left_track_5 + ( + .in({chany_top_in[9], chany_top_in[20], chanx_right_in[7], chanx_right_in[22], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size5 mux_left_track_37 + ( + .in({chany_top_in[3], chany_top_in[14], chany_top_in[25], chanx_right_in[15], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size5_5_sram), + .sram_inv(mux_left_track_37_undriven_sram_inv), + .out(chanx_left_out[18]) + ); + mux_tree_tapbuf_size5_mem mem_top_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_right_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram) + ); + mux_tree_tapbuf_size4 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_right_in[12], chanx_right_in[17], chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size4_0_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size4 mux_top_track_14 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_right_in[14], chanx_right_in[21], chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size4_1_sram), + .sram_inv(mux_top_track_14_undriven_sram_inv), + .out(chany_top_out[7]) + ); + mux_tree_tapbuf_size4 mux_top_track_16 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_right_in[15], chanx_right_in[25], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size4_2_sram), + .sram_inv(mux_top_track_16_undriven_sram_inv), + .out(chany_top_out[8]) + ); + mux_tree_tapbuf_size4 mux_top_track_18 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_right_in[16], chanx_right_in[29], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size4_3_sram), + .sram_inv(mux_top_track_18_undriven_sram_inv), + .out(chany_top_out[9]) + ); + mux_tree_tapbuf_size4 mux_left_track_45 + ( + .in({chany_top_in[2], chany_top_in[13], chany_top_in[24], chanx_right_in[16]}), + .sram(mux_tree_tapbuf_size4_4_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size4 mux_left_track_53 + ( + .in({chany_top_in[1], chany_top_in[12], chany_top_in[23], chanx_right_in[18]}), + .sram(mux_tree_tapbuf_size4_5_sram), + .sram_inv(mux_left_track_53_undriven_sram_inv), + .out(chanx_left_out[26]) + ); + mux_tree_tapbuf_size4_mem mem_top_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram) + ); + mux_tree_tapbuf_size4_mem mem_top_track_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram) + ); + mux_tree_tapbuf_size4_mem mem_top_track_16 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram) + ); + mux_tree_tapbuf_size4_mem mem_top_track_18 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram) + ); + mux_tree_tapbuf_size3 mux_top_track_20 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_right_in[18], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_top_track_20_undriven_sram_inv), + .out(chany_top_out[10]) + ); + mux_tree_tapbuf_size3 mux_top_track_22 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[19], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_top_track_22_undriven_sram_inv), + .out(chany_top_out[11]) + ); + mux_tree_tapbuf_size3 mux_top_track_24 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[20], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_top_track_24_undriven_sram_inv), + .out(chany_top_out[12]) + ); + mux_tree_tapbuf_size3 mux_top_track_26 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[22], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_top_track_26_undriven_sram_inv), + .out(chany_top_out[13]) + ); + mux_tree_tapbuf_size3 mux_top_track_36 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_right_in[28], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_top_track_36_undriven_sram_inv), + .out(chany_top_out[18]) + ); + mux_tree_tapbuf_size3 mux_right_track_44 + ( + .in({chany_top_in[8], chany_top_in[19], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size3 mux_right_track_52 + ( + .in({chany_top_in[9], chany_top_in[20], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_right_track_52_undriven_sram_inv), + .out(chanx_right_out[26]) + ); + mux_tree_tapbuf_size3_mem mem_top_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_22 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_24 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_26 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_right_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size2 mux_top_track_28 + ( + .in({chanx_right_in[23], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size2 mux_top_track_30 + ( + .in({chanx_right_in[24], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_top_track_30_undriven_sram_inv), + .out(chany_top_out[15]) + ); + mux_tree_tapbuf_size2 mux_top_track_32 + ( + .in({chanx_right_in[26], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_top_track_32_undriven_sram_inv), + .out(chany_top_out[16]) + ); + mux_tree_tapbuf_size2 mux_top_track_34 + ( + .in({chanx_right_in[27], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_top_track_34_undriven_sram_inv), + .out(chany_top_out[17]) + ); + mux_tree_tapbuf_size2 mux_top_track_40 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_top_track_40_undriven_sram_inv), + .out(chany_top_out[20]) + ); + mux_tree_tapbuf_size2 mux_top_track_42 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_top_track_42_undriven_sram_inv), + .out(chany_top_out[21]) + ); + mux_tree_tapbuf_size2 mux_top_track_44 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size2 mux_top_track_46 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_top_track_46_undriven_sram_inv), + .out(chany_top_out[23]) + ); + mux_tree_tapbuf_size2 mux_top_track_48 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_top_track_48_undriven_sram_inv), + .out(chany_top_out[24]) + ); + mux_tree_tapbuf_size2 mux_top_track_50 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_top_track_50_undriven_sram_inv), + .out(chany_top_out[25]) + ); + mux_tree_tapbuf_size2 mux_top_track_58 + ( + .in({chanx_right_in[0], chanx_left_in[1]}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_top_track_58_undriven_sram_inv), + .out(chany_top_out[29]) + ); + mux_tree_tapbuf_size2_mem mem_top_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_30 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_32 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_34 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_40 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_42 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_46 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_48 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_50 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_58 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__1_.v new file mode 100644 index 0000000..834c68d --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__1_.v @@ -0,0 +1,1009 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_1__1_ +( + pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_right_in, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + chany_bottom_in, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_left_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + ccff_head, + chany_top_out, + chanx_right_out, + chany_bottom_out, + chanx_left_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_top_in; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input [0:29]chanx_right_in; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input [0:29]chany_bottom_in; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input [0:29]chanx_left_in; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input ccff_head; + output [0:29]chany_top_out; + output [0:29]chanx_right_out; + output [0:29]chany_bottom_out; + output [0:29]chanx_left_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_top_in; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire [0:29]chanx_right_in; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire [0:29]chany_bottom_in; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire [0:29]chanx_left_in; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire ccff_head; + wire [0:29]chany_top_out; + wire [0:29]chanx_right_out; + wire [0:29]chany_bottom_out; + wire [0:29]chanx_left_out; + wire ccff_tail; + wire [0:3]mux_bottom_track_11_undriven_sram_inv; + wire [0:3]mux_bottom_track_13_undriven_sram_inv; + wire [0:3]mux_bottom_track_1_undriven_sram_inv; + wire [0:3]mux_bottom_track_21_undriven_sram_inv; + wire [0:3]mux_bottom_track_29_undriven_sram_inv; + wire [0:2]mux_bottom_track_37_undriven_sram_inv; + wire [0:3]mux_bottom_track_3_undriven_sram_inv; + wire [0:2]mux_bottom_track_45_undriven_sram_inv; + wire [0:2]mux_bottom_track_53_undriven_sram_inv; + wire [0:3]mux_bottom_track_5_undriven_sram_inv; + wire [0:3]mux_bottom_track_7_undriven_sram_inv; + wire [0:3]mux_left_track_11_undriven_sram_inv; + wire [0:3]mux_left_track_13_undriven_sram_inv; + wire [0:3]mux_left_track_1_undriven_sram_inv; + wire [0:3]mux_left_track_21_undriven_sram_inv; + wire [0:3]mux_left_track_29_undriven_sram_inv; + wire [0:2]mux_left_track_37_undriven_sram_inv; + wire [0:3]mux_left_track_3_undriven_sram_inv; + wire [0:2]mux_left_track_45_undriven_sram_inv; + wire [0:2]mux_left_track_53_undriven_sram_inv; + wire [0:3]mux_left_track_5_undriven_sram_inv; + wire [0:3]mux_left_track_7_undriven_sram_inv; + wire [0:3]mux_right_track_0_undriven_sram_inv; + wire [0:3]mux_right_track_10_undriven_sram_inv; + wire [0:3]mux_right_track_12_undriven_sram_inv; + wire [0:3]mux_right_track_20_undriven_sram_inv; + wire [0:3]mux_right_track_28_undriven_sram_inv; + wire [0:3]mux_right_track_2_undriven_sram_inv; + wire [0:2]mux_right_track_36_undriven_sram_inv; + wire [0:2]mux_right_track_44_undriven_sram_inv; + wire [0:3]mux_right_track_4_undriven_sram_inv; + wire [0:2]mux_right_track_52_undriven_sram_inv; + wire [0:3]mux_right_track_6_undriven_sram_inv; + wire [0:3]mux_top_track_0_undriven_sram_inv; + wire [0:3]mux_top_track_10_undriven_sram_inv; + wire [0:3]mux_top_track_12_undriven_sram_inv; + wire [0:3]mux_top_track_20_undriven_sram_inv; + wire [0:3]mux_top_track_28_undriven_sram_inv; + wire [0:3]mux_top_track_2_undriven_sram_inv; + wire [0:2]mux_top_track_36_undriven_sram_inv; + wire [0:2]mux_top_track_44_undriven_sram_inv; + wire [0:3]mux_top_track_4_undriven_sram_inv; + wire [0:2]mux_top_track_52_undriven_sram_inv; + wire [0:3]mux_top_track_6_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire [0:3]mux_tree_tapbuf_size10_10_sram; + wire [0:3]mux_tree_tapbuf_size10_11_sram; + wire [0:3]mux_tree_tapbuf_size10_1_sram; + wire [0:3]mux_tree_tapbuf_size10_2_sram; + wire [0:3]mux_tree_tapbuf_size10_3_sram; + wire [0:3]mux_tree_tapbuf_size10_4_sram; + wire [0:3]mux_tree_tapbuf_size10_5_sram; + wire [0:3]mux_tree_tapbuf_size10_6_sram; + wire [0:3]mux_tree_tapbuf_size10_7_sram; + wire [0:3]mux_tree_tapbuf_size10_8_sram; + wire [0:3]mux_tree_tapbuf_size10_9_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire mux_tree_tapbuf_size10_mem_10_ccff_tail; + wire mux_tree_tapbuf_size10_mem_11_ccff_tail; + wire mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire mux_tree_tapbuf_size10_mem_7_ccff_tail; + wire mux_tree_tapbuf_size10_mem_8_ccff_tail; + wire mux_tree_tapbuf_size10_mem_9_ccff_tail; + wire [0:3]mux_tree_tapbuf_size11_0_sram; + wire [0:3]mux_tree_tapbuf_size11_1_sram; + wire [0:3]mux_tree_tapbuf_size11_2_sram; + wire [0:3]mux_tree_tapbuf_size11_3_sram; + wire [0:3]mux_tree_tapbuf_size11_4_sram; + wire [0:3]mux_tree_tapbuf_size11_5_sram; + wire [0:3]mux_tree_tapbuf_size11_6_sram; + wire [0:3]mux_tree_tapbuf_size11_7_sram; + wire mux_tree_tapbuf_size11_mem_0_ccff_tail; + wire mux_tree_tapbuf_size11_mem_1_ccff_tail; + wire mux_tree_tapbuf_size11_mem_2_ccff_tail; + wire mux_tree_tapbuf_size11_mem_3_ccff_tail; + wire mux_tree_tapbuf_size11_mem_4_ccff_tail; + wire mux_tree_tapbuf_size11_mem_5_ccff_tail; + wire mux_tree_tapbuf_size11_mem_6_ccff_tail; + wire mux_tree_tapbuf_size11_mem_7_ccff_tail; + wire [0:3]mux_tree_tapbuf_size12_0_sram; + wire [0:3]mux_tree_tapbuf_size12_1_sram; + wire [0:3]mux_tree_tapbuf_size12_2_sram; + wire [0:3]mux_tree_tapbuf_size12_3_sram; + wire [0:3]mux_tree_tapbuf_size12_4_sram; + wire [0:3]mux_tree_tapbuf_size12_5_sram; + wire [0:3]mux_tree_tapbuf_size12_6_sram; + wire [0:3]mux_tree_tapbuf_size12_7_sram; + wire mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire mux_tree_tapbuf_size12_mem_7_ccff_tail; + wire [0:2]mux_tree_tapbuf_size6_0_sram; + wire [0:2]mux_tree_tapbuf_size6_10_sram; + wire [0:2]mux_tree_tapbuf_size6_11_sram; + wire [0:2]mux_tree_tapbuf_size6_1_sram; + wire [0:2]mux_tree_tapbuf_size6_2_sram; + wire [0:2]mux_tree_tapbuf_size6_3_sram; + wire [0:2]mux_tree_tapbuf_size6_4_sram; + wire [0:2]mux_tree_tapbuf_size6_5_sram; + wire [0:2]mux_tree_tapbuf_size6_6_sram; + wire [0:2]mux_tree_tapbuf_size6_7_sram; + wire [0:2]mux_tree_tapbuf_size6_8_sram; + wire [0:2]mux_tree_tapbuf_size6_9_sram; + wire mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire mux_tree_tapbuf_size6_mem_10_ccff_tail; + wire mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire mux_tree_tapbuf_size6_mem_7_ccff_tail; + wire mux_tree_tapbuf_size6_mem_8_ccff_tail; + wire mux_tree_tapbuf_size6_mem_9_ccff_tail; + wire [0:3]mux_tree_tapbuf_size9_0_sram; + wire [0:3]mux_tree_tapbuf_size9_1_sram; + wire [0:3]mux_tree_tapbuf_size9_2_sram; + wire [0:3]mux_tree_tapbuf_size9_3_sram; + wire mux_tree_tapbuf_size9_mem_0_ccff_tail; + wire mux_tree_tapbuf_size9_mem_1_ccff_tail; + wire mux_tree_tapbuf_size9_mem_2_ccff_tail; + wire mux_tree_tapbuf_size9_mem_3_ccff_tail; + +assign chany_bottom_out[4] = chany_top_in[3]; +assign chany_bottom_out[7] = chany_top_in[6]; +assign chany_bottom_out[8] = chany_top_in[7]; +assign chany_bottom_out[9] = chany_top_in[8]; +assign chany_bottom_out[11] = chany_top_in[10]; +assign chany_bottom_out[12] = chany_top_in[11]; +assign chany_bottom_out[13] = chany_top_in[12]; +assign chany_bottom_out[15] = chany_top_in[14]; +assign chany_bottom_out[16] = chany_top_in[15]; +assign chany_bottom_out[17] = chany_top_in[16]; +assign chany_bottom_out[19] = chany_top_in[18]; +assign chany_bottom_out[20] = chany_top_in[19]; +assign chany_bottom_out[21] = chany_top_in[20]; +assign chany_bottom_out[23] = chany_top_in[22]; +assign chany_bottom_out[24] = chany_top_in[23]; +assign chany_bottom_out[25] = chany_top_in[24]; +assign chany_bottom_out[27] = chany_top_in[26]; +assign chany_bottom_out[28] = chany_top_in[27]; +assign chany_bottom_out[29] = chany_top_in[28]; +assign chanx_left_out[4] = chanx_right_in[3]; +assign chanx_left_out[7] = chanx_right_in[6]; +assign chanx_left_out[8] = chanx_right_in[7]; +assign chanx_left_out[9] = chanx_right_in[8]; +assign chanx_left_out[11] = chanx_right_in[10]; +assign chanx_left_out[12] = chanx_right_in[11]; +assign chanx_left_out[13] = chanx_right_in[12]; +assign chanx_left_out[15] = chanx_right_in[14]; +assign chanx_left_out[16] = chanx_right_in[15]; +assign chanx_left_out[17] = chanx_right_in[16]; +assign chanx_left_out[19] = chanx_right_in[18]; +assign chanx_left_out[20] = chanx_right_in[19]; +assign chanx_left_out[21] = chanx_right_in[20]; +assign chanx_left_out[23] = chanx_right_in[22]; +assign chanx_left_out[24] = chanx_right_in[23]; +assign chanx_left_out[25] = chanx_right_in[24]; +assign chanx_left_out[27] = chanx_right_in[26]; +assign chanx_left_out[28] = chanx_right_in[27]; +assign chanx_left_out[29] = chanx_right_in[28]; +assign chany_top_out[4] = chany_bottom_in[3]; +assign chany_top_out[7] = chany_bottom_in[6]; +assign chany_top_out[8] = chany_bottom_in[7]; +assign chany_top_out[9] = chany_bottom_in[8]; +assign chany_top_out[11] = chany_bottom_in[10]; +assign chany_top_out[12] = chany_bottom_in[11]; +assign chany_top_out[13] = chany_bottom_in[12]; +assign chany_top_out[15] = chany_bottom_in[14]; +assign chany_top_out[16] = chany_bottom_in[15]; +assign chany_top_out[17] = chany_bottom_in[16]; +assign chany_top_out[19] = chany_bottom_in[18]; +assign chany_top_out[20] = chany_bottom_in[19]; +assign chany_top_out[21] = chany_bottom_in[20]; +assign chany_top_out[23] = chany_bottom_in[22]; +assign chany_top_out[24] = chany_bottom_in[23]; +assign chany_top_out[25] = chany_bottom_in[24]; +assign chany_top_out[27] = chany_bottom_in[26]; +assign chany_top_out[28] = chany_bottom_in[27]; +assign chany_top_out[29] = chany_bottom_in[28]; +assign chanx_right_out[4] = chanx_left_in[3]; +assign chanx_right_out[7] = chanx_left_in[6]; +assign chanx_right_out[8] = chanx_left_in[7]; +assign chanx_right_out[9] = chanx_left_in[8]; +assign chanx_right_out[11] = chanx_left_in[10]; +assign chanx_right_out[12] = chanx_left_in[11]; +assign chanx_right_out[13] = chanx_left_in[12]; +assign chanx_right_out[15] = chanx_left_in[14]; +assign chanx_right_out[16] = chanx_left_in[15]; +assign chanx_right_out[17] = chanx_left_in[16]; +assign chanx_right_out[19] = chanx_left_in[18]; +assign chanx_right_out[20] = chanx_left_in[19]; +assign chanx_right_out[21] = chanx_left_in[20]; +assign chanx_right_out[23] = chanx_left_in[22]; +assign chanx_right_out[24] = chanx_left_in[23]; +assign chanx_right_out[25] = chanx_left_in[24]; +assign chanx_right_out[27] = chanx_left_in[26]; +assign chanx_right_out[28] = chanx_left_in[27]; +assign chanx_right_out[29] = chanx_left_in[28]; + mux_tree_tapbuf_size11 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[1], chanx_right_in[3], chanx_right_in[19], chany_bottom_in[3], chany_bottom_in[19], chanx_left_in[0], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size11_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size11 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[2], chanx_right_in[6], chanx_right_in[20], chany_bottom_in[6], chany_bottom_in[20], chanx_left_in[6], chanx_left_in[20], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size11_1_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size11 mux_right_track_0 + ( + .in({chany_top_in[3], chany_top_in[19], chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[3], chany_bottom_in[19], chany_bottom_in[25], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size11_2_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size11 mux_right_track_2 + ( + .in({chany_top_in[0], chany_top_in[6], chany_top_in[20], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[6], chany_bottom_in[20], chany_bottom_in[21], chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size11_3_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size11 mux_bottom_track_1 + ( + .in({chany_top_in[3], chany_top_in[19], chanx_right_in[3], chanx_right_in[19], chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[1], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size11_4_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size11 mux_bottom_track_3 + ( + .in({chany_top_in[6], chany_top_in[20], chanx_right_in[6], chanx_right_in[20], chanx_right_in[21], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[2], chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size11_5_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size11 mux_left_track_1 + ( + .in({chany_top_in[0], chany_top_in[3], chany_top_in[19], chanx_right_in[3], chanx_right_in[19], chany_bottom_in[3], chany_bottom_in[19], chany_bottom_in[29], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size11_6_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size11 mux_left_track_3 + ( + .in({chany_top_in[6], chany_top_in[20], chany_top_in[29], chanx_right_in[6], chanx_right_in[20], chany_bottom_in[0], chany_bottom_in[6], chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size11_7_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size11_mem mem_top_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_0_sram) + ); + mux_tree_tapbuf_size11_mem mem_top_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_1_sram) + ); + mux_tree_tapbuf_size11_mem mem_right_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_2_sram) + ); + mux_tree_tapbuf_size11_mem mem_right_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_3_sram) + ); + mux_tree_tapbuf_size11_mem mem_bottom_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_4_sram) + ); + mux_tree_tapbuf_size11_mem mem_bottom_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_5_sram) + ); + mux_tree_tapbuf_size11_mem mem_left_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_6_sram) + ); + mux_tree_tapbuf_size11_mem mem_left_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_7_sram) + ); + mux_tree_tapbuf_size10 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[4], chanx_right_in[7], chanx_right_in[22], chany_bottom_in[7], chany_bottom_in[22], chanx_left_in[7], chanx_left_in[22], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size10 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[11], chanx_right_in[13], chanx_right_in[26], chany_bottom_in[11], chany_bottom_in[26], chanx_left_in[11], chanx_left_in[13], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size10_1_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size10 mux_top_track_20 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[12], chanx_right_in[17], chanx_right_in[27], chany_bottom_in[12], chany_bottom_in[27], chanx_left_in[9], chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size10_2_sram), + .sram_inv(mux_top_track_20_undriven_sram_inv), + .out(chany_top_out[10]) + ); + mux_tree_tapbuf_size10 mux_right_track_4 + ( + .in({chany_top_in[1], chany_top_in[7], chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[7], chany_bottom_in[17], chany_bottom_in[22], chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size10_3_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size10 mux_right_track_12 + ( + .in({chany_top_in[5], chany_top_in[11], chany_top_in[26], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[5], chany_bottom_in[11], chany_bottom_in[26], chanx_left_in[11], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size10_4_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size10 mux_right_track_20 + ( + .in({chany_top_in[9], chany_top_in[12], chany_top_in[27], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[4], chany_bottom_in[12], chany_bottom_in[27], chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size10_5_sram), + .sram_inv(mux_right_track_20_undriven_sram_inv), + .out(chanx_right_out[10]) + ); + mux_tree_tapbuf_size10 mux_bottom_track_5 + ( + .in({chany_top_in[7], chany_top_in[22], chanx_right_in[7], chanx_right_in[17], chanx_right_in[22], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[4], chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size10_6_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size10 mux_bottom_track_13 + ( + .in({chany_top_in[11], chany_top_in[26], chanx_right_in[5], chanx_right_in[11], chanx_right_in[26], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[11], chanx_left_in[13], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size10_7_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size10 mux_bottom_track_21 + ( + .in({chany_top_in[12], chany_top_in[27], chanx_right_in[4], chanx_right_in[12], chanx_right_in[27], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[12], chanx_left_in[17], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size10_8_sram), + .sram_inv(mux_bottom_track_21_undriven_sram_inv), + .out(chany_bottom_out[10]) + ); + mux_tree_tapbuf_size10 mux_left_track_5 + ( + .in({chany_top_in[7], chany_top_in[22], chany_top_in[25], chanx_right_in[7], chanx_right_in[22], chany_bottom_in[1], chany_bottom_in[7], chany_bottom_in[22], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size10_9_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size10 mux_left_track_13 + ( + .in({chany_top_in[11], chany_top_in[13], chany_top_in[26], chanx_right_in[11], chanx_right_in[26], chany_bottom_in[5], chany_bottom_in[11], chany_bottom_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size10_10_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size10 mux_left_track_21 + ( + .in({chany_top_in[9], chany_top_in[12], chany_top_in[27], chanx_right_in[12], chanx_right_in[27], chany_bottom_in[9], chany_bottom_in[12], chany_bottom_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size10_11_sram), + .sram_inv(mux_left_track_21_undriven_sram_inv), + .out(chanx_left_out[10]) + ); + mux_tree_tapbuf_size10_mem mem_top_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_1_sram) + ); + mux_tree_tapbuf_size10_mem mem_top_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_2_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_3_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_4_sram) + ); + mux_tree_tapbuf_size10_mem mem_right_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_5_sram) + ); + mux_tree_tapbuf_size10_mem mem_bottom_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_6_sram) + ); + mux_tree_tapbuf_size10_mem mem_bottom_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_7_sram) + ); + mux_tree_tapbuf_size10_mem mem_bottom_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_8_sram) + ); + mux_tree_tapbuf_size10_mem mem_left_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_9_sram) + ); + mux_tree_tapbuf_size10_mem mem_left_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_10_sram) + ); + mux_tree_tapbuf_size10_mem mem_left_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_11_sram) + ); + mux_tree_tapbuf_size12 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[5], chanx_right_in[8], chanx_right_in[23], chany_bottom_in[8], chany_bottom_in[23], chanx_left_in[8], chanx_left_in[21], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size12_0_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); + mux_tree_tapbuf_size12 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[9], chanx_right_in[10], chanx_right_in[24], chany_bottom_in[10], chany_bottom_in[24], chanx_left_in[10], chanx_left_in[17], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size12_1_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size12 mux_right_track_6 + ( + .in({chany_top_in[2], chany_top_in[8], chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[8], chany_bottom_in[13], chany_bottom_in[23], chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size12_2_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size12 mux_right_track_10 + ( + .in({chany_top_in[4], chany_top_in[10], chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[9], chany_bottom_in[10], chany_bottom_in[24], chanx_left_in[10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size12_3_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size12 mux_bottom_track_7 + ( + .in({chany_top_in[8], chany_top_in[23], chanx_right_in[8], chanx_right_in[13], chanx_right_in[23], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[5], chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size12_4_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size12 mux_bottom_track_11 + ( + .in({chany_top_in[10], chany_top_in[24], chanx_right_in[9], chanx_right_in[10], chanx_right_in[24], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[9], chanx_left_in[10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size12_5_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size12 mux_left_track_7 + ( + .in({chany_top_in[8], chany_top_in[21], chany_top_in[23], chanx_right_in[8], chanx_right_in[23], chany_bottom_in[2], chany_bottom_in[8], chany_bottom_in[23], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size12_6_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size12 mux_left_track_11 + ( + .in({chany_top_in[10], chany_top_in[17], chany_top_in[24], chanx_right_in[10], chanx_right_in[24], chany_bottom_in[4], chany_bottom_in[10], chany_bottom_in[24], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size12_7_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size12_mem mem_top_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_0_sram) + ); + mux_tree_tapbuf_size12_mem mem_top_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_1_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_2_sram) + ); + mux_tree_tapbuf_size12_mem mem_right_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_3_sram) + ); + mux_tree_tapbuf_size12_mem mem_bottom_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_4_sram) + ); + mux_tree_tapbuf_size12_mem mem_bottom_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_5_sram) + ); + mux_tree_tapbuf_size12_mem mem_left_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_6_sram) + ); + mux_tree_tapbuf_size12_mem mem_left_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size12_7_sram) + ); + mux_tree_tapbuf_size9 mux_top_track_28 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_right_in[14], chanx_right_in[21], chanx_right_in[28], chany_bottom_in[14], chany_bottom_in[28], chanx_left_in[5], chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size9_0_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size9 mux_right_track_28 + ( + .in({chany_top_in[13], chany_top_in[14], chany_top_in[28], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[2], chany_bottom_in[14], chany_bottom_in[28], chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size9_1_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size9 mux_bottom_track_29 + ( + .in({chany_top_in[14], chany_top_in[28], chanx_right_in[2], chanx_right_in[14], chanx_right_in[28], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[14], chanx_left_in[21], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size9_2_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size9 mux_left_track_29 + ( + .in({chany_top_in[5], chany_top_in[14], chany_top_in[28], chanx_right_in[14], chanx_right_in[28], chany_bottom_in[13], chany_bottom_in[14], chany_bottom_in[28], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size9_3_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size9_mem mem_top_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_0_sram) + ); + mux_tree_tapbuf_size9_mem mem_right_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_1_sram) + ); + mux_tree_tapbuf_size9_mem mem_bottom_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_2_sram) + ); + mux_tree_tapbuf_size9_mem mem_left_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_3_sram) + ); + mux_tree_tapbuf_size6 mux_top_track_36 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_right_in[15], chanx_right_in[25], chany_bottom_in[15], chanx_left_in[4], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size6_0_sram), + .sram_inv(mux_top_track_36_undriven_sram_inv), + .out(chany_top_out[18]) + ); + mux_tree_tapbuf_size6 mux_top_track_44 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_right_in[16], chanx_right_in[29], chany_bottom_in[16], chanx_left_in[2], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size6_1_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size6 mux_top_track_52 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[0], chanx_right_in[18], chany_bottom_in[18], chanx_left_in[1], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size6_2_sram), + .sram_inv(mux_top_track_52_undriven_sram_inv), + .out(chany_top_out[26]) + ); + mux_tree_tapbuf_size6 mux_right_track_36 + ( + .in({chany_top_in[15], chany_top_in[17], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[1], chany_bottom_in[15], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size6_3_sram), + .sram_inv(mux_right_track_36_undriven_sram_inv), + .out(chanx_right_out[18]) + ); + mux_tree_tapbuf_size6 mux_right_track_44 + ( + .in({chany_top_in[16], chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[0], chany_bottom_in[16], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size6_4_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size6 mux_right_track_52 + ( + .in({chany_top_in[18], chany_top_in[25], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[18], chany_bottom_in[29], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size6_5_sram), + .sram_inv(mux_right_track_52_undriven_sram_inv), + .out(chanx_right_out[26]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_37 + ( + .in({chany_top_in[15], chanx_right_in[1], chanx_right_in[15], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[15], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size6_6_sram), + .sram_inv(mux_bottom_track_37_undriven_sram_inv), + .out(chany_bottom_out[18]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_45 + ( + .in({chany_top_in[16], chanx_right_in[0], chanx_right_in[16], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[16], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size6_7_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_53 + ( + .in({chany_top_in[18], chanx_right_in[18], chanx_right_in[29], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[0], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size6_8_sram), + .sram_inv(mux_bottom_track_53_undriven_sram_inv), + .out(chany_bottom_out[26]) + ); + mux_tree_tapbuf_size6 mux_left_track_37 + ( + .in({chany_top_in[4], chany_top_in[15], chanx_right_in[15], chany_bottom_in[15], chany_bottom_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size6_9_sram), + .sram_inv(mux_left_track_37_undriven_sram_inv), + .out(chanx_left_out[18]) + ); + mux_tree_tapbuf_size6 mux_left_track_45 + ( + .in({chany_top_in[2], chany_top_in[16], chanx_right_in[16], chany_bottom_in[16], chany_bottom_in[21], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size6_10_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size6 mux_left_track_53 + ( + .in({chany_top_in[1], chany_top_in[18], chanx_right_in[18], chany_bottom_in[18], chany_bottom_in[25], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size6_11_sram), + .sram_inv(mux_left_track_53_undriven_sram_inv), + .out(chanx_left_out[26]) + ); + mux_tree_tapbuf_size6_mem mem_top_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size6_11_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__8_.v new file mode 100644 index 0000000..0d620a7 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__8_.v @@ -0,0 +1,1041 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_1__8_ +( + pReset, + prog_clk, + chanx_right_in, + right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + chany_bottom_in, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_left_in, + left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + ccff_head, + chanx_right_out, + chany_bottom_out, + chanx_left_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chanx_right_in; + input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input [0:29]chany_bottom_in; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input [0:29]chanx_left_in; + input left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input ccff_head; + output [0:29]chanx_right_out; + output [0:29]chany_bottom_out; + output [0:29]chanx_left_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chanx_right_in; + wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire [0:29]chany_bottom_in; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire [0:29]chanx_left_in; + wire left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire ccff_head; + wire [0:29]chanx_right_out; + wire [0:29]chany_bottom_out; + wire [0:29]chanx_left_out; + wire ccff_tail; + wire [0:2]mux_bottom_track_11_undriven_sram_inv; + wire [0:2]mux_bottom_track_13_undriven_sram_inv; + wire [0:2]mux_bottom_track_15_undriven_sram_inv; + wire [0:2]mux_bottom_track_17_undriven_sram_inv; + wire [0:2]mux_bottom_track_19_undriven_sram_inv; + wire [0:2]mux_bottom_track_1_undriven_sram_inv; + wire [0:1]mux_bottom_track_21_undriven_sram_inv; + wire [0:1]mux_bottom_track_23_undriven_sram_inv; + wire [0:1]mux_bottom_track_25_undriven_sram_inv; + wire [0:1]mux_bottom_track_27_undriven_sram_inv; + wire [0:1]mux_bottom_track_29_undriven_sram_inv; + wire [0:1]mux_bottom_track_31_undriven_sram_inv; + wire [0:1]mux_bottom_track_33_undriven_sram_inv; + wire [0:1]mux_bottom_track_35_undriven_sram_inv; + wire [0:2]mux_bottom_track_37_undriven_sram_inv; + wire [0:1]mux_bottom_track_39_undriven_sram_inv; + wire [0:2]mux_bottom_track_3_undriven_sram_inv; + wire [0:1]mux_bottom_track_41_undriven_sram_inv; + wire [0:1]mux_bottom_track_43_undriven_sram_inv; + wire [0:1]mux_bottom_track_45_undriven_sram_inv; + wire [0:1]mux_bottom_track_47_undriven_sram_inv; + wire [0:1]mux_bottom_track_49_undriven_sram_inv; + wire [0:1]mux_bottom_track_51_undriven_sram_inv; + wire [0:2]mux_bottom_track_5_undriven_sram_inv; + wire [0:2]mux_bottom_track_7_undriven_sram_inv; + wire [0:2]mux_bottom_track_9_undriven_sram_inv; + wire [0:3]mux_left_track_11_undriven_sram_inv; + wire [0:2]mux_left_track_13_undriven_sram_inv; + wire [0:3]mux_left_track_1_undriven_sram_inv; + wire [0:2]mux_left_track_21_undriven_sram_inv; + wire [0:2]mux_left_track_29_undriven_sram_inv; + wire [0:2]mux_left_track_37_undriven_sram_inv; + wire [0:3]mux_left_track_3_undriven_sram_inv; + wire [0:2]mux_left_track_45_undriven_sram_inv; + wire [0:2]mux_left_track_53_undriven_sram_inv; + wire [0:3]mux_left_track_5_undriven_sram_inv; + wire [0:3]mux_left_track_7_undriven_sram_inv; + wire [0:3]mux_right_track_0_undriven_sram_inv; + wire [0:3]mux_right_track_10_undriven_sram_inv; + wire [0:2]mux_right_track_12_undriven_sram_inv; + wire [0:2]mux_right_track_20_undriven_sram_inv; + wire [0:2]mux_right_track_28_undriven_sram_inv; + wire [0:3]mux_right_track_2_undriven_sram_inv; + wire [0:2]mux_right_track_36_undriven_sram_inv; + wire [0:2]mux_right_track_44_undriven_sram_inv; + wire [0:3]mux_right_track_4_undriven_sram_inv; + wire [0:2]mux_right_track_52_undriven_sram_inv; + wire [0:3]mux_right_track_6_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size11_0_sram; + wire [0:3]mux_tree_tapbuf_size11_1_sram; + wire [0:3]mux_tree_tapbuf_size11_2_sram; + wire [0:3]mux_tree_tapbuf_size11_3_sram; + wire mux_tree_tapbuf_size11_mem_0_ccff_tail; + wire mux_tree_tapbuf_size11_mem_1_ccff_tail; + wire mux_tree_tapbuf_size11_mem_2_ccff_tail; + wire mux_tree_tapbuf_size11_mem_3_ccff_tail; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire [0:2]mux_tree_tapbuf_size4_0_sram; + wire [0:2]mux_tree_tapbuf_size4_1_sram; + wire [0:2]mux_tree_tapbuf_size4_2_sram; + wire [0:2]mux_tree_tapbuf_size4_3_sram; + wire [0:2]mux_tree_tapbuf_size4_4_sram; + wire mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire mux_tree_tapbuf_size4_mem_4_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire [0:2]mux_tree_tapbuf_size6_0_sram; + wire [0:2]mux_tree_tapbuf_size6_1_sram; + wire [0:2]mux_tree_tapbuf_size6_2_sram; + wire [0:2]mux_tree_tapbuf_size6_3_sram; + wire [0:2]mux_tree_tapbuf_size6_4_sram; + wire [0:2]mux_tree_tapbuf_size6_5_sram; + wire [0:2]mux_tree_tapbuf_size6_6_sram; + wire mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire [0:2]mux_tree_tapbuf_size7_0_sram; + wire [0:2]mux_tree_tapbuf_size7_1_sram; + wire [0:2]mux_tree_tapbuf_size7_2_sram; + wire [0:2]mux_tree_tapbuf_size7_3_sram; + wire [0:2]mux_tree_tapbuf_size7_4_sram; + wire [0:2]mux_tree_tapbuf_size7_5_sram; + wire mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire mux_tree_tapbuf_size7_mem_4_ccff_tail; + wire mux_tree_tapbuf_size7_mem_5_ccff_tail; + wire [0:3]mux_tree_tapbuf_size8_0_sram; + wire [0:3]mux_tree_tapbuf_size8_1_sram; + wire [0:3]mux_tree_tapbuf_size8_2_sram; + wire mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire mux_tree_tapbuf_size8_mem_2_ccff_tail; + wire [0:3]mux_tree_tapbuf_size9_0_sram; + wire [0:3]mux_tree_tapbuf_size9_1_sram; + wire [0:3]mux_tree_tapbuf_size9_2_sram; + wire mux_tree_tapbuf_size9_mem_0_ccff_tail; + wire mux_tree_tapbuf_size9_mem_1_ccff_tail; + wire mux_tree_tapbuf_size9_mem_2_ccff_tail; + +assign chany_bottom_out[28] = chanx_right_in[0]; +assign chany_bottom_out[27] = chanx_right_in[1]; +assign chany_bottom_out[26] = chanx_right_in[2]; +assign chanx_left_out[4] = chanx_right_in[3]; +assign chanx_left_out[7] = chanx_right_in[6]; +assign chanx_left_out[8] = chanx_right_in[7]; +assign chanx_left_out[9] = chanx_right_in[8]; +assign chanx_left_out[11] = chanx_right_in[10]; +assign chanx_left_out[12] = chanx_right_in[11]; +assign chanx_left_out[13] = chanx_right_in[12]; +assign chanx_left_out[15] = chanx_right_in[14]; +assign chanx_left_out[16] = chanx_right_in[15]; +assign chanx_left_out[17] = chanx_right_in[16]; +assign chanx_left_out[19] = chanx_right_in[18]; +assign chanx_left_out[20] = chanx_right_in[19]; +assign chanx_left_out[21] = chanx_right_in[20]; +assign chanx_left_out[23] = chanx_right_in[22]; +assign chanx_left_out[24] = chanx_right_in[23]; +assign chanx_left_out[25] = chanx_right_in[24]; +assign chanx_left_out[27] = chanx_right_in[26]; +assign chanx_left_out[28] = chanx_right_in[27]; +assign chanx_left_out[29] = chanx_right_in[28]; +assign chany_bottom_out[29] = chanx_left_in[0]; +assign chanx_right_out[4] = chanx_left_in[3]; +assign chanx_right_out[7] = chanx_left_in[6]; +assign chanx_right_out[8] = chanx_left_in[7]; +assign chanx_right_out[9] = chanx_left_in[8]; +assign chanx_right_out[11] = chanx_left_in[10]; +assign chanx_right_out[12] = chanx_left_in[11]; +assign chanx_right_out[13] = chanx_left_in[12]; +assign chanx_right_out[15] = chanx_left_in[14]; +assign chanx_right_out[16] = chanx_left_in[15]; +assign chanx_right_out[17] = chanx_left_in[16]; +assign chanx_right_out[19] = chanx_left_in[18]; +assign chanx_right_out[20] = chanx_left_in[19]; +assign chanx_right_out[21] = chanx_left_in[20]; +assign chanx_right_out[23] = chanx_left_in[22]; +assign chanx_right_out[24] = chanx_left_in[23]; +assign chanx_right_out[25] = chanx_left_in[24]; +assign chanx_right_out[27] = chanx_left_in[26]; +assign chanx_right_out[28] = chanx_left_in[27]; +assign chanx_right_out[29] = chanx_left_in[28]; + mux_tree_tapbuf_size8 mux_right_track_0 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[9], chany_bottom_in[20], chanx_left_in[3], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size8_0_sram), + .sram_inv(mux_right_track_0_undriven_sram_inv), + .out(chanx_right_out[0]) + ); + mux_tree_tapbuf_size8 mux_right_track_2 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[8], chany_bottom_in[19], chanx_left_in[6], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size8_1_sram), + .sram_inv(mux_right_track_2_undriven_sram_inv), + .out(chanx_right_out[1]) + ); + mux_tree_tapbuf_size8 mux_left_track_1 + ( + .in({chanx_right_in[3], chanx_right_in[19], chany_bottom_in[10], chany_bottom_in[21], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size8_2_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size8_mem mem_right_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_0_sram) + ); + mux_tree_tapbuf_size8_mem mem_right_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_1_sram) + ); + mux_tree_tapbuf_size8_mem mem_left_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_2_sram) + ); + mux_tree_tapbuf_size9 mux_right_track_4 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[7], chany_bottom_in[18], chany_bottom_in[29], chanx_left_in[7], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size9_0_sram), + .sram_inv(mux_right_track_4_undriven_sram_inv), + .out(chanx_right_out[2]) + ); + mux_tree_tapbuf_size9 mux_left_track_3 + ( + .in({chanx_right_in[6], chanx_right_in[20], chany_bottom_in[0], chany_bottom_in[11], chany_bottom_in[22], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size9_1_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size9 mux_left_track_5 + ( + .in({chanx_right_in[7], chanx_right_in[22], chany_bottom_in[1], chany_bottom_in[12], chany_bottom_in[23], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size9_2_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size9_mem mem_right_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_0_sram) + ); + mux_tree_tapbuf_size9_mem mem_left_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_1_sram) + ); + mux_tree_tapbuf_size9_mem mem_left_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_2_sram) + ); + mux_tree_tapbuf_size11 mux_right_track_6 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[6], chany_bottom_in[17], chany_bottom_in[28], chanx_left_in[8], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size11_0_sram), + .sram_inv(mux_right_track_6_undriven_sram_inv), + .out(chanx_right_out[3]) + ); + mux_tree_tapbuf_size11 mux_right_track_10 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[5], chany_bottom_in[16], chany_bottom_in[27], chanx_left_in[10], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size11_1_sram), + .sram_inv(mux_right_track_10_undriven_sram_inv), + .out(chanx_right_out[5]) + ); + mux_tree_tapbuf_size11 mux_left_track_7 + ( + .in({chanx_right_in[8], chanx_right_in[23], chany_bottom_in[2], chany_bottom_in[13], chany_bottom_in[24], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size11_2_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size11 mux_left_track_11 + ( + .in({chanx_right_in[10], chanx_right_in[24], chany_bottom_in[3], chany_bottom_in[14], chany_bottom_in[25], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size11_3_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size11_mem mem_right_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_0_sram) + ); + mux_tree_tapbuf_size11_mem mem_right_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_1_sram) + ); + mux_tree_tapbuf_size11_mem mem_left_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_2_sram) + ); + mux_tree_tapbuf_size11_mem mem_left_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_3_sram) + ); + mux_tree_tapbuf_size7 mux_right_track_12 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[4], chany_bottom_in[15], chany_bottom_in[26], chanx_left_in[11], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size7_0_sram), + .sram_inv(mux_right_track_12_undriven_sram_inv), + .out(chanx_right_out[6]) + ); + mux_tree_tapbuf_size7 mux_right_track_20 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[3], chany_bottom_in[14], chany_bottom_in[25], chanx_left_in[12], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size7_1_sram), + .sram_inv(mux_right_track_20_undriven_sram_inv), + .out(chanx_right_out[10]) + ); + mux_tree_tapbuf_size7 mux_right_track_28 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[2], chany_bottom_in[13], chany_bottom_in[24], chanx_left_in[14], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size7_2_sram), + .sram_inv(mux_right_track_28_undriven_sram_inv), + .out(chanx_right_out[14]) + ); + mux_tree_tapbuf_size7 mux_left_track_13 + ( + .in({chanx_right_in[11], chanx_right_in[26], chany_bottom_in[4], chany_bottom_in[15], chany_bottom_in[26], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size7_3_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size7 mux_left_track_21 + ( + .in({chanx_right_in[12], chanx_right_in[27], chany_bottom_in[5], chany_bottom_in[16], chany_bottom_in[27], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size7_4_sram), + .sram_inv(mux_left_track_21_undriven_sram_inv), + .out(chanx_left_out[10]) + ); + mux_tree_tapbuf_size7 mux_left_track_29 + ( + .in({chanx_right_in[14], chanx_right_in[28], chany_bottom_in[6], chany_bottom_in[17], chany_bottom_in[28], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size7_5_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size7_mem mem_right_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram) + ); + mux_tree_tapbuf_size7_mem mem_right_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram) + ); + mux_tree_tapbuf_size7_mem mem_right_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram) + ); + mux_tree_tapbuf_size7_mem mem_left_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram) + ); + mux_tree_tapbuf_size7_mem mem_left_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram) + ); + mux_tree_tapbuf_size7_mem mem_left_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_5_sram) + ); + mux_tree_tapbuf_size6 mux_right_track_36 + ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[1], chany_bottom_in[12], chany_bottom_in[23], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size6_0_sram), + .sram_inv(mux_right_track_36_undriven_sram_inv), + .out(chanx_right_out[18]) + ); + mux_tree_tapbuf_size6 mux_right_track_44 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[0], chany_bottom_in[11], chany_bottom_in[22], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size6_1_sram), + .sram_inv(mux_right_track_44_undriven_sram_inv), + .out(chanx_right_out[22]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_1 + ( + .in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[1], chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size6_2_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_3 + ( + .in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[2], chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size6_3_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_7 + ( + .in({chanx_right_in[8], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[5], chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size6_4_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_9 + ( + .in({chanx_right_in[10], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[9], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size6_5_sram), + .sram_inv(mux_bottom_track_9_undriven_sram_inv), + .out(chany_bottom_out[4]) + ); + mux_tree_tapbuf_size6 mux_left_track_37 + ( + .in({chanx_right_in[15], chany_bottom_in[7], chany_bottom_in[18], chany_bottom_in[29], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size6_6_sram), + .sram_inv(mux_left_track_37_undriven_sram_inv), + .out(chanx_left_out[18]) + ); + mux_tree_tapbuf_size6_mem mem_right_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_right_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram) + ); + mux_tree_tapbuf_size5 mux_right_track_52 + ( + .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[10], chany_bottom_in[21], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_right_track_52_undriven_sram_inv), + .out(chanx_right_out[26]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_5 + ( + .in({chanx_right_in[7], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[4], chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_11 + ( + .in({chanx_right_in[11], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[11], chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size5 mux_left_track_45 + ( + .in({chanx_right_in[16], chany_bottom_in[8], chany_bottom_in[19], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size5 mux_left_track_53 + ( + .in({chanx_right_in[18], chany_bottom_in[9], chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_left_track_53_undriven_sram_inv), + .out(chanx_left_out[26]) + ); + mux_tree_tapbuf_size5_mem mem_right_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size4 mux_bottom_track_13 + ( + .in({chanx_right_in[12], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[12], chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size4_0_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_15 + ( + .in({chanx_right_in[14], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[14], chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size4_1_sram), + .sram_inv(mux_bottom_track_15_undriven_sram_inv), + .out(chany_bottom_out[7]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_17 + ( + .in({chanx_right_in[15], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[15], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size4_2_sram), + .sram_inv(mux_bottom_track_17_undriven_sram_inv), + .out(chany_bottom_out[8]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_19 + ( + .in({chanx_right_in[16], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[16], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size4_3_sram), + .sram_inv(mux_bottom_track_19_undriven_sram_inv), + .out(chany_bottom_out[9]) + ); + mux_tree_tapbuf_size4 mux_bottom_track_37 + ( + .in({chanx_right_in[28], chanx_right_in[29], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size4_4_sram), + .sram_inv(mux_bottom_track_37_undriven_sram_inv), + .out(chany_bottom_out[18]) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_17 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_19 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram) + ); + mux_tree_tapbuf_size4_mem mem_bottom_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram) + ); + mux_tree_tapbuf_size3 mux_bottom_track_21 + ( + .in({chanx_right_in[18], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_bottom_track_21_undriven_sram_inv), + .out(chany_bottom_out[10]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_23 + ( + .in({chanx_right_in[19], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_bottom_track_23_undriven_sram_inv), + .out(chany_bottom_out[11]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_25 + ( + .in({chanx_right_in[20], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_bottom_track_25_undriven_sram_inv), + .out(chany_bottom_out[12]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_27 + ( + .in({chanx_right_in[22], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_bottom_track_27_undriven_sram_inv), + .out(chany_bottom_out[13]) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_23 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_25 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_27 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size2 mux_bottom_track_29 + ( + .in({chanx_right_in[23], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_31 + ( + .in({chanx_right_in[24], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_bottom_track_31_undriven_sram_inv), + .out(chany_bottom_out[15]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_33 + ( + .in({chanx_right_in[26], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_bottom_track_33_undriven_sram_inv), + .out(chany_bottom_out[16]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_35 + ( + .in({chanx_right_in[27], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_bottom_track_35_undriven_sram_inv), + .out(chany_bottom_out[17]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_39 + ( + .in({chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_bottom_track_39_undriven_sram_inv), + .out(chany_bottom_out[19]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_41 + ( + .in({chanx_right_in[21], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_bottom_track_41_undriven_sram_inv), + .out(chany_bottom_out[20]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_43 + ( + .in({chanx_right_in[17], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_bottom_track_43_undriven_sram_inv), + .out(chany_bottom_out[21]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_45 + ( + .in({chanx_right_in[13], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_47 + ( + .in({chanx_right_in[9], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_bottom_track_47_undriven_sram_inv), + .out(chany_bottom_out[23]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_49 + ( + .in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_bottom_track_49_undriven_sram_inv), + .out(chany_bottom_out[24]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_51 + ( + .in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_bottom_track_51_undriven_sram_inv), + .out(chany_bottom_out[25]) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_31 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_33 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_35 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_39 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_41 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_43 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_47 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_49 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_51 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__0_.v new file mode 100644 index 0000000..51920ee --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__0_.v @@ -0,0 +1,889 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_8__0_ +( + pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + chanx_left_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_left_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_top_in; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + input [0:29]chanx_left_in; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + input ccff_head; + output [0:29]chany_top_out; + output [0:29]chanx_left_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_top_in; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire [0:29]chanx_left_in; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; + wire ccff_head; + wire [0:29]chany_top_out; + wire [0:29]chanx_left_out; + wire ccff_tail; + wire [0:1]mux_left_track_11_undriven_sram_inv; + wire [0:1]mux_left_track_13_undriven_sram_inv; + wire [0:1]mux_left_track_15_undriven_sram_inv; + wire [0:1]mux_left_track_17_undriven_sram_inv; + wire [0:1]mux_left_track_19_undriven_sram_inv; + wire [0:1]mux_left_track_1_undriven_sram_inv; + wire [0:1]mux_left_track_29_undriven_sram_inv; + wire [0:1]mux_left_track_31_undriven_sram_inv; + wire [0:1]mux_left_track_33_undriven_sram_inv; + wire [0:1]mux_left_track_35_undriven_sram_inv; + wire [0:1]mux_left_track_3_undriven_sram_inv; + wire [0:1]mux_left_track_45_undriven_sram_inv; + wire [0:1]mux_left_track_47_undriven_sram_inv; + wire [0:1]mux_left_track_49_undriven_sram_inv; + wire [0:1]mux_left_track_51_undriven_sram_inv; + wire [0:1]mux_left_track_5_undriven_sram_inv; + wire [0:1]mux_left_track_7_undriven_sram_inv; + wire [0:1]mux_left_track_9_undriven_sram_inv; + wire [0:2]mux_top_track_0_undriven_sram_inv; + wire [0:2]mux_top_track_10_undriven_sram_inv; + wire [0:1]mux_top_track_12_undriven_sram_inv; + wire [0:1]mux_top_track_14_undriven_sram_inv; + wire [0:1]mux_top_track_16_undriven_sram_inv; + wire [0:1]mux_top_track_18_undriven_sram_inv; + wire [0:1]mux_top_track_20_undriven_sram_inv; + wire [0:1]mux_top_track_22_undriven_sram_inv; + wire [0:1]mux_top_track_24_undriven_sram_inv; + wire [0:1]mux_top_track_26_undriven_sram_inv; + wire [0:1]mux_top_track_28_undriven_sram_inv; + wire [0:2]mux_top_track_2_undriven_sram_inv; + wire [0:1]mux_top_track_30_undriven_sram_inv; + wire [0:1]mux_top_track_32_undriven_sram_inv; + wire [0:1]mux_top_track_34_undriven_sram_inv; + wire [0:1]mux_top_track_36_undriven_sram_inv; + wire [0:1]mux_top_track_38_undriven_sram_inv; + wire [0:1]mux_top_track_40_undriven_sram_inv; + wire [0:1]mux_top_track_42_undriven_sram_inv; + wire [0:1]mux_top_track_44_undriven_sram_inv; + wire [0:1]mux_top_track_46_undriven_sram_inv; + wire [0:1]mux_top_track_48_undriven_sram_inv; + wire [0:2]mux_top_track_4_undriven_sram_inv; + wire [0:1]mux_top_track_50_undriven_sram_inv; + wire [0:2]mux_top_track_6_undriven_sram_inv; + wire [0:2]mux_top_track_8_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_11_sram; + wire [0:1]mux_tree_tapbuf_size2_12_sram; + wire [0:1]mux_tree_tapbuf_size2_13_sram; + wire [0:1]mux_tree_tapbuf_size2_14_sram; + wire [0:1]mux_tree_tapbuf_size2_15_sram; + wire [0:1]mux_tree_tapbuf_size2_16_sram; + wire [0:1]mux_tree_tapbuf_size2_17_sram; + wire [0:1]mux_tree_tapbuf_size2_18_sram; + wire [0:1]mux_tree_tapbuf_size2_19_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_20_sram; + wire [0:1]mux_tree_tapbuf_size2_21_sram; + wire [0:1]mux_tree_tapbuf_size2_22_sram; + wire [0:1]mux_tree_tapbuf_size2_23_sram; + wire [0:1]mux_tree_tapbuf_size2_24_sram; + wire [0:1]mux_tree_tapbuf_size2_25_sram; + wire [0:1]mux_tree_tapbuf_size2_26_sram; + wire [0:1]mux_tree_tapbuf_size2_27_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire mux_tree_tapbuf_size2_mem_19_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_20_ccff_tail; + wire mux_tree_tapbuf_size2_mem_21_ccff_tail; + wire mux_tree_tapbuf_size2_mem_22_ccff_tail; + wire mux_tree_tapbuf_size2_mem_23_ccff_tail; + wire mux_tree_tapbuf_size2_mem_24_ccff_tail; + wire mux_tree_tapbuf_size2_mem_25_ccff_tail; + wire mux_tree_tapbuf_size2_mem_26_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire [0:1]mux_tree_tapbuf_size3_7_sram; + wire [0:1]mux_tree_tapbuf_size3_8_sram; + wire [0:1]mux_tree_tapbuf_size3_9_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire mux_tree_tapbuf_size3_mem_7_ccff_tail; + wire mux_tree_tapbuf_size3_mem_8_ccff_tail; + wire mux_tree_tapbuf_size3_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire [0:2]mux_tree_tapbuf_size5_5_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire mux_tree_tapbuf_size5_mem_5_ccff_tail; + +assign chanx_left_out[29] = chany_top_in[1]; +assign chanx_left_out[28] = chany_top_in[2]; +assign chanx_left_out[27] = chany_top_in[3]; +assign chanx_left_out[26] = chany_top_in[4]; +assign chanx_left_out[21] = chany_top_in[9]; +assign chanx_left_out[20] = chany_top_in[10]; +assign chanx_left_out[19] = chany_top_in[11]; +assign chanx_left_out[18] = chany_top_in[12]; +assign chanx_left_out[13] = chany_top_in[17]; +assign chanx_left_out[12] = chany_top_in[18]; +assign chanx_left_out[11] = chany_top_in[19]; +assign chanx_left_out[10] = chany_top_in[20]; +assign chany_top_out[29] = chanx_left_in[1]; +assign chany_top_out[28] = chanx_left_in[2]; +assign chany_top_out[27] = chanx_left_in[3]; +assign chany_top_out[26] = chanx_left_in[4]; + mux_tree_tapbuf_size5 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[0]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size5 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size5 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size5 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); + mux_tree_tapbuf_size5 mux_top_track_8 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_top_track_8_undriven_sram_inv), + .out(chany_top_out[4]) + ); + mux_tree_tapbuf_size5 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size5_5_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size5_mem mem_top_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_8 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size5_mem mem_top_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram) + ); + mux_tree_tapbuf_size3 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size3 mux_top_track_14 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_top_track_14_undriven_sram_inv), + .out(chany_top_out[7]) + ); + mux_tree_tapbuf_size3 mux_top_track_16 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_top_track_16_undriven_sram_inv), + .out(chany_top_out[8]) + ); + mux_tree_tapbuf_size3 mux_top_track_18 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_top_track_18_undriven_sram_inv), + .out(chany_top_out[9]) + ); + mux_tree_tapbuf_size3 mux_top_track_44 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size3 mux_top_track_46 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_top_track_46_undriven_sram_inv), + .out(chany_top_out[23]) + ); + mux_tree_tapbuf_size3 mux_top_track_48 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_top_track_48_undriven_sram_inv), + .out(chany_top_out[24]) + ); + mux_tree_tapbuf_size3 mux_top_track_50 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[5]}), + .sram(mux_tree_tapbuf_size3_7_sram), + .sram_inv(mux_top_track_50_undriven_sram_inv), + .out(chany_top_out[25]) + ); + mux_tree_tapbuf_size3 mux_left_track_1 + ( + .in({chany_top_in[0], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_8_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size3 mux_left_track_7 + ( + .in({chany_top_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_9_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size3_mem mem_top_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_14 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_16 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_18 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_46 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_48 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size3_mem mem_top_track_50 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram) + ); + mux_tree_tapbuf_size2 mux_top_track_20 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_top_track_20_undriven_sram_inv), + .out(chany_top_out[10]) + ); + mux_tree_tapbuf_size2 mux_top_track_22 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_top_track_22_undriven_sram_inv), + .out(chany_top_out[11]) + ); + mux_tree_tapbuf_size2 mux_top_track_24 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_top_track_24_undriven_sram_inv), + .out(chany_top_out[12]) + ); + mux_tree_tapbuf_size2 mux_top_track_26 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_top_track_26_undriven_sram_inv), + .out(chany_top_out[13]) + ); + mux_tree_tapbuf_size2 mux_top_track_28 + ( + .in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size2 mux_top_track_30 + ( + .in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_top_track_30_undriven_sram_inv), + .out(chany_top_out[15]) + ); + mux_tree_tapbuf_size2 mux_top_track_32 + ( + .in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_top_track_32_undriven_sram_inv), + .out(chany_top_out[16]) + ); + mux_tree_tapbuf_size2 mux_top_track_34 + ( + .in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_top_track_34_undriven_sram_inv), + .out(chany_top_out[17]) + ); + mux_tree_tapbuf_size2 mux_top_track_36 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_top_track_36_undriven_sram_inv), + .out(chany_top_out[18]) + ); + mux_tree_tapbuf_size2 mux_top_track_38 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_top_track_38_undriven_sram_inv), + .out(chany_top_out[19]) + ); + mux_tree_tapbuf_size2 mux_top_track_40 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_top_track_40_undriven_sram_inv), + .out(chany_top_out[20]) + ); + mux_tree_tapbuf_size2 mux_top_track_42 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size2_11_sram), + .sram_inv(mux_top_track_42_undriven_sram_inv), + .out(chany_top_out[21]) + ); + mux_tree_tapbuf_size2 mux_left_track_3 + ( + .in({chany_top_in[29], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_12_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size2 mux_left_track_5 + ( + .in({chany_top_in[28], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_13_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size2 mux_left_track_9 + ( + .in({chany_top_in[26], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_14_sram), + .sram_inv(mux_left_track_9_undriven_sram_inv), + .out(chanx_left_out[4]) + ); + mux_tree_tapbuf_size2 mux_left_track_11 + ( + .in({chany_top_in[25], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_15_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size2 mux_left_track_13 + ( + .in({chany_top_in[24], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_16_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size2 mux_left_track_15 + ( + .in({chany_top_in[23], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_17_sram), + .sram_inv(mux_left_track_15_undriven_sram_inv), + .out(chanx_left_out[7]) + ); + mux_tree_tapbuf_size2 mux_left_track_17 + ( + .in({chany_top_in[22], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_18_sram), + .sram_inv(mux_left_track_17_undriven_sram_inv), + .out(chanx_left_out[8]) + ); + mux_tree_tapbuf_size2 mux_left_track_19 + ( + .in({chany_top_in[21], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_19_sram), + .sram_inv(mux_left_track_19_undriven_sram_inv), + .out(chanx_left_out[9]) + ); + mux_tree_tapbuf_size2 mux_left_track_29 + ( + .in({chany_top_in[16], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_20_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size2 mux_left_track_31 + ( + .in({chany_top_in[15], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram), + .sram_inv(mux_left_track_31_undriven_sram_inv), + .out(chanx_left_out[15]) + ); + mux_tree_tapbuf_size2 mux_left_track_33 + ( + .in({chany_top_in[14], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_22_sram), + .sram_inv(mux_left_track_33_undriven_sram_inv), + .out(chanx_left_out[16]) + ); + mux_tree_tapbuf_size2 mux_left_track_35 + ( + .in({chany_top_in[13], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_23_sram), + .sram_inv(mux_left_track_35_undriven_sram_inv), + .out(chanx_left_out[17]) + ); + mux_tree_tapbuf_size2 mux_left_track_45 + ( + .in({chany_top_in[8], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_24_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size2 mux_left_track_47 + ( + .in({chany_top_in[7], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_25_sram), + .sram_inv(mux_left_track_47_undriven_sram_inv), + .out(chanx_left_out[23]) + ); + mux_tree_tapbuf_size2 mux_left_track_49 + ( + .in({chany_top_in[6], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_26_sram), + .sram_inv(mux_left_track_49_undriven_sram_inv), + .out(chanx_left_out[24]) + ); + mux_tree_tapbuf_size2 mux_left_track_51 + ( + .in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_27_sram), + .sram_inv(mux_left_track_51_undriven_sram_inv), + .out(chanx_left_out[25]) + ); + mux_tree_tapbuf_size2_mem mem_top_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_22 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_24 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_26 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_30 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_32 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_34 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_38 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_40 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); + mux_tree_tapbuf_size2_mem mem_top_track_42 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_17 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_19 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_31 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_33 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_35 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_47 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_25_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_49 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_26_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_51 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_27_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__1_.v new file mode 100644 index 0000000..bdabe6b --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__1_.v @@ -0,0 +1,1058 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_8__1_ +( + pReset, + prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + chany_bottom_in, + bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_left_in, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + ccff_head, + chany_top_out, + chany_bottom_out, + chanx_left_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_top_in; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + input top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + input [0:29]chany_bottom_in; + input bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input [0:29]chanx_left_in; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input ccff_head; + output [0:29]chany_top_out; + output [0:29]chany_bottom_out; + output [0:29]chanx_left_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_top_in; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire [0:29]chany_bottom_in; + wire bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire [0:29]chanx_left_in; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire ccff_head; + wire [0:29]chany_top_out; + wire [0:29]chany_bottom_out; + wire [0:29]chanx_left_out; + wire ccff_tail; + wire [0:3]mux_bottom_track_11_undriven_sram_inv; + wire [0:2]mux_bottom_track_13_undriven_sram_inv; + wire [0:3]mux_bottom_track_1_undriven_sram_inv; + wire [0:2]mux_bottom_track_21_undriven_sram_inv; + wire [0:2]mux_bottom_track_29_undriven_sram_inv; + wire [0:2]mux_bottom_track_37_undriven_sram_inv; + wire [0:3]mux_bottom_track_3_undriven_sram_inv; + wire [0:2]mux_bottom_track_45_undriven_sram_inv; + wire [0:2]mux_bottom_track_53_undriven_sram_inv; + wire [0:3]mux_bottom_track_5_undriven_sram_inv; + wire [0:3]mux_bottom_track_7_undriven_sram_inv; + wire [0:2]mux_left_track_11_undriven_sram_inv; + wire [0:2]mux_left_track_13_undriven_sram_inv; + wire [0:2]mux_left_track_15_undriven_sram_inv; + wire [0:2]mux_left_track_17_undriven_sram_inv; + wire [0:2]mux_left_track_19_undriven_sram_inv; + wire [0:2]mux_left_track_1_undriven_sram_inv; + wire [0:2]mux_left_track_21_undriven_sram_inv; + wire [0:2]mux_left_track_23_undriven_sram_inv; + wire [0:1]mux_left_track_25_undriven_sram_inv; + wire [0:1]mux_left_track_27_undriven_sram_inv; + wire [0:1]mux_left_track_29_undriven_sram_inv; + wire [0:1]mux_left_track_31_undriven_sram_inv; + wire [0:1]mux_left_track_33_undriven_sram_inv; + wire [0:1]mux_left_track_35_undriven_sram_inv; + wire [0:1]mux_left_track_37_undriven_sram_inv; + wire [0:2]mux_left_track_3_undriven_sram_inv; + wire [0:1]mux_left_track_41_undriven_sram_inv; + wire [0:1]mux_left_track_45_undriven_sram_inv; + wire [0:1]mux_left_track_47_undriven_sram_inv; + wire [0:1]mux_left_track_49_undriven_sram_inv; + wire [0:1]mux_left_track_51_undriven_sram_inv; + wire [0:1]mux_left_track_53_undriven_sram_inv; + wire [0:1]mux_left_track_55_undriven_sram_inv; + wire [0:1]mux_left_track_57_undriven_sram_inv; + wire [0:2]mux_left_track_5_undriven_sram_inv; + wire [0:2]mux_left_track_7_undriven_sram_inv; + wire [0:2]mux_left_track_9_undriven_sram_inv; + wire [0:3]mux_top_track_0_undriven_sram_inv; + wire [0:3]mux_top_track_10_undriven_sram_inv; + wire [0:2]mux_top_track_12_undriven_sram_inv; + wire [0:2]mux_top_track_20_undriven_sram_inv; + wire [0:2]mux_top_track_28_undriven_sram_inv; + wire [0:3]mux_top_track_2_undriven_sram_inv; + wire [0:2]mux_top_track_36_undriven_sram_inv; + wire [0:2]mux_top_track_44_undriven_sram_inv; + wire [0:3]mux_top_track_4_undriven_sram_inv; + wire [0:2]mux_top_track_52_undriven_sram_inv; + wire [0:3]mux_top_track_6_undriven_sram_inv; + wire [0:3]mux_tree_tapbuf_size10_0_sram; + wire mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:3]mux_tree_tapbuf_size11_0_sram; + wire [0:3]mux_tree_tapbuf_size11_1_sram; + wire [0:3]mux_tree_tapbuf_size11_2_sram; + wire mux_tree_tapbuf_size11_mem_0_ccff_tail; + wire mux_tree_tapbuf_size11_mem_1_ccff_tail; + wire mux_tree_tapbuf_size11_mem_2_ccff_tail; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire [0:1]mux_tree_tapbuf_size3_7_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire mux_tree_tapbuf_size3_mem_7_ccff_tail; + wire [0:2]mux_tree_tapbuf_size4_0_sram; + wire [0:2]mux_tree_tapbuf_size4_1_sram; + wire [0:2]mux_tree_tapbuf_size4_2_sram; + wire [0:2]mux_tree_tapbuf_size4_3_sram; + wire [0:2]mux_tree_tapbuf_size4_4_sram; + wire [0:2]mux_tree_tapbuf_size4_5_sram; + wire mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire mux_tree_tapbuf_size4_mem_4_ccff_tail; + wire mux_tree_tapbuf_size4_mem_5_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire [0:2]mux_tree_tapbuf_size6_0_sram; + wire [0:2]mux_tree_tapbuf_size6_1_sram; + wire [0:2]mux_tree_tapbuf_size6_2_sram; + wire [0:2]mux_tree_tapbuf_size6_3_sram; + wire [0:2]mux_tree_tapbuf_size6_4_sram; + wire [0:2]mux_tree_tapbuf_size6_5_sram; + wire [0:2]mux_tree_tapbuf_size6_6_sram; + wire [0:2]mux_tree_tapbuf_size6_7_sram; + wire [0:2]mux_tree_tapbuf_size6_8_sram; + wire mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire mux_tree_tapbuf_size6_mem_7_ccff_tail; + wire mux_tree_tapbuf_size6_mem_8_ccff_tail; + wire [0:2]mux_tree_tapbuf_size7_0_sram; + wire [0:2]mux_tree_tapbuf_size7_1_sram; + wire [0:2]mux_tree_tapbuf_size7_2_sram; + wire [0:2]mux_tree_tapbuf_size7_3_sram; + wire [0:2]mux_tree_tapbuf_size7_4_sram; + wire mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire mux_tree_tapbuf_size7_mem_4_ccff_tail; + wire [0:3]mux_tree_tapbuf_size8_0_sram; + wire [0:3]mux_tree_tapbuf_size8_1_sram; + wire mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:3]mux_tree_tapbuf_size9_0_sram; + wire [0:3]mux_tree_tapbuf_size9_1_sram; + wire [0:3]mux_tree_tapbuf_size9_2_sram; + wire [0:3]mux_tree_tapbuf_size9_3_sram; + wire mux_tree_tapbuf_size9_mem_0_ccff_tail; + wire mux_tree_tapbuf_size9_mem_1_ccff_tail; + wire mux_tree_tapbuf_size9_mem_2_ccff_tail; + wire mux_tree_tapbuf_size9_mem_3_ccff_tail; + +assign chanx_left_out[29] = chany_top_in[1]; +assign chany_bottom_out[4] = chany_top_in[3]; +assign chany_bottom_out[7] = chany_top_in[6]; +assign chany_bottom_out[8] = chany_top_in[7]; +assign chany_bottom_out[9] = chany_top_in[8]; +assign chany_bottom_out[11] = chany_top_in[10]; +assign chany_bottom_out[12] = chany_top_in[11]; +assign chany_bottom_out[13] = chany_top_in[12]; +assign chany_bottom_out[15] = chany_top_in[14]; +assign chany_bottom_out[16] = chany_top_in[15]; +assign chany_bottom_out[17] = chany_top_in[16]; +assign chany_bottom_out[19] = chany_top_in[18]; +assign chany_bottom_out[20] = chany_top_in[19]; +assign chany_bottom_out[21] = chany_top_in[20]; +assign chany_bottom_out[23] = chany_top_in[22]; +assign chany_bottom_out[24] = chany_top_in[23]; +assign chany_bottom_out[25] = chany_top_in[24]; +assign chanx_left_out[21] = chany_top_in[25]; +assign chany_bottom_out[27] = chany_top_in[26]; +assign chany_bottom_out[28] = chany_top_in[27]; +assign chany_bottom_out[29] = chany_top_in[28]; +assign chany_top_out[4] = chany_bottom_in[3]; +assign chany_top_out[7] = chany_bottom_in[6]; +assign chany_top_out[8] = chany_bottom_in[7]; +assign chany_top_out[9] = chany_bottom_in[8]; +assign chany_top_out[11] = chany_bottom_in[10]; +assign chany_top_out[12] = chany_bottom_in[11]; +assign chany_top_out[13] = chany_bottom_in[12]; +assign chany_top_out[15] = chany_bottom_in[14]; +assign chany_top_out[16] = chany_bottom_in[15]; +assign chany_top_out[17] = chany_bottom_in[16]; +assign chany_top_out[19] = chany_bottom_in[18]; +assign chany_top_out[20] = chany_bottom_in[19]; +assign chany_top_out[21] = chany_bottom_in[20]; +assign chany_top_out[23] = chany_bottom_in[22]; +assign chany_top_out[24] = chany_bottom_in[23]; +assign chany_top_out[25] = chany_bottom_in[24]; +assign chany_top_out[27] = chany_bottom_in[26]; +assign chany_top_out[28] = chany_bottom_in[27]; +assign chany_top_out[29] = chany_bottom_in[28]; +assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + mux_tree_tapbuf_size9 mux_top_track_0 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chany_bottom_in[3], chany_bottom_in[19], chanx_left_in[0], chanx_left_in[11], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size9_0_sram), + .sram_inv(mux_top_track_0_undriven_sram_inv), + .out(chany_top_out[0]) + ); + mux_tree_tapbuf_size9 mux_bottom_track_1 + ( + .in({chany_top_in[3], chany_top_in[19], bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[1], chanx_left_in[12], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size9_1_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size9 mux_bottom_track_3 + ( + .in({chany_top_in[6], chany_top_in[20], bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[2], chanx_left_in[13], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size9_2_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size9 mux_bottom_track_5 + ( + .in({chany_top_in[7], chany_top_in[22], bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[3], chanx_left_in[14], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size9_3_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size9_mem mem_top_track_0 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_0_sram) + ); + mux_tree_tapbuf_size9_mem mem_bottom_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_1_sram) + ); + mux_tree_tapbuf_size9_mem mem_bottom_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_2_sram) + ); + mux_tree_tapbuf_size9_mem mem_bottom_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size9_3_sram) + ); + mux_tree_tapbuf_size8 mux_top_track_2 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[6], chany_bottom_in[20], chanx_left_in[10], chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size8_0_sram), + .sram_inv(mux_top_track_2_undriven_sram_inv), + .out(chany_top_out[1]) + ); + mux_tree_tapbuf_size8 mux_top_track_4 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[7], chany_bottom_in[22], chanx_left_in[9], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size8_1_sram), + .sram_inv(mux_top_track_4_undriven_sram_inv), + .out(chany_top_out[2]) + ); + mux_tree_tapbuf_size8_mem mem_top_track_2 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_0_sram) + ); + mux_tree_tapbuf_size8_mem mem_top_track_4 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size8_1_sram) + ); + mux_tree_tapbuf_size10 mux_top_track_6 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[8], chany_bottom_in[23], chanx_left_in[8], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size10_0_sram), + .sram_inv(mux_top_track_6_undriven_sram_inv), + .out(chany_top_out[3]) + ); + mux_tree_tapbuf_size10_mem mem_top_track_6 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size10_0_sram) + ); + mux_tree_tapbuf_size11 mux_top_track_10 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[10], chany_bottom_in[24], chanx_left_in[7], chanx_left_in[18], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size11_0_sram), + .sram_inv(mux_top_track_10_undriven_sram_inv), + .out(chany_top_out[5]) + ); + mux_tree_tapbuf_size11 mux_bottom_track_7 + ( + .in({chany_top_in[8], chany_top_in[23], bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[4], chanx_left_in[15], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size11_1_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size11 mux_bottom_track_11 + ( + .in({chany_top_in[10], chany_top_in[24], bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[5], chanx_left_in[16], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size11_2_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size11_mem mem_top_track_10 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_0_sram) + ); + mux_tree_tapbuf_size11_mem mem_bottom_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_1_sram) + ); + mux_tree_tapbuf_size11_mem mem_bottom_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size11_2_sram) + ); + mux_tree_tapbuf_size7 mux_top_track_12 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chany_bottom_in[11], chany_bottom_in[26], chanx_left_in[6], chanx_left_in[17], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size7_0_sram), + .sram_inv(mux_top_track_12_undriven_sram_inv), + .out(chany_top_out[6]) + ); + mux_tree_tapbuf_size7 mux_top_track_20 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chany_bottom_in[12], chany_bottom_in[27], chanx_left_in[5], chanx_left_in[16], chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size7_1_sram), + .sram_inv(mux_top_track_20_undriven_sram_inv), + .out(chany_top_out[10]) + ); + mux_tree_tapbuf_size7 mux_top_track_28 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chany_bottom_in[14], chany_bottom_in[28], chanx_left_in[4], chanx_left_in[15], chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size7_2_sram), + .sram_inv(mux_top_track_28_undriven_sram_inv), + .out(chany_top_out[14]) + ); + mux_tree_tapbuf_size7 mux_bottom_track_13 + ( + .in({chany_top_in[11], chany_top_in[26], bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[6], chanx_left_in[17], chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size7_3_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size7 mux_bottom_track_21 + ( + .in({chany_top_in[12], chany_top_in[27], bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[7], chanx_left_in[18], chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size7_4_sram), + .sram_inv(mux_bottom_track_21_undriven_sram_inv), + .out(chany_bottom_out[10]) + ); + mux_tree_tapbuf_size7_mem mem_top_track_12 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_0_sram) + ); + mux_tree_tapbuf_size7_mem mem_top_track_20 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_1_sram) + ); + mux_tree_tapbuf_size7_mem mem_top_track_28 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_2_sram) + ); + mux_tree_tapbuf_size7_mem mem_bottom_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_3_sram) + ); + mux_tree_tapbuf_size7_mem mem_bottom_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size7_4_sram) + ); + mux_tree_tapbuf_size6 mux_top_track_36 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chany_bottom_in[15], chanx_left_in[3], chanx_left_in[14], chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size6_0_sram), + .sram_inv(mux_top_track_36_undriven_sram_inv), + .out(chany_top_out[18]) + ); + mux_tree_tapbuf_size6 mux_top_track_44 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[16], chanx_left_in[2], chanx_left_in[13], chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size6_1_sram), + .sram_inv(mux_top_track_44_undriven_sram_inv), + .out(chany_top_out[22]) + ); + mux_tree_tapbuf_size6 mux_top_track_52 + ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[18], chanx_left_in[1], chanx_left_in[12], chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size6_2_sram), + .sram_inv(mux_top_track_52_undriven_sram_inv), + .out(chany_top_out[26]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_29 + ( + .in({chany_top_in[14], chany_top_in[28], bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[8], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size6_3_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size6 mux_bottom_track_53 + ( + .in({chany_top_in[18], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[0], chanx_left_in[11], chanx_left_in[22]}), + .sram(mux_tree_tapbuf_size6_4_sram), + .sram_inv(mux_bottom_track_53_undriven_sram_inv), + .out(chany_bottom_out[26]) + ); + mux_tree_tapbuf_size6 mux_left_track_1 + ( + .in({chany_top_in[0], chany_top_in[3], chany_bottom_in[3], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size6_5_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size6 mux_left_track_3 + ( + .in({chany_top_in[6], chany_bottom_in[0], chany_bottom_in[6], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size6_6_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size6 mux_left_track_7 + ( + .in({chany_top_in[8], chany_bottom_in[2], chany_bottom_in[8], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size6_7_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size6 mux_left_track_9 + ( + .in({chany_top_in[10], chany_bottom_in[4], chany_bottom_in[10], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size6_8_sram), + .sram_inv(mux_left_track_9_undriven_sram_inv), + .out(chanx_left_out[4]) + ); + mux_tree_tapbuf_size6_mem mem_top_track_36 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_44 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram) + ); + mux_tree_tapbuf_size6_mem mem_top_track_52 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram) + ); + mux_tree_tapbuf_size6_mem mem_bottom_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram) + ); + mux_tree_tapbuf_size6_mem mem_left_track_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram) + ); + mux_tree_tapbuf_size5 mux_bottom_track_37 + ( + .in({chany_top_in[15], bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[9], chanx_left_in[20]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_bottom_track_37_undriven_sram_inv), + .out(chany_bottom_out[18]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_45 + ( + .in({chany_top_in[16], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[10], chanx_left_in[21]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size5 mux_left_track_5 + ( + .in({chany_top_in[7], chany_bottom_in[1], chany_bottom_in[7], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size5 mux_left_track_11 + ( + .in({chany_top_in[11], chany_bottom_in[5], chany_bottom_in[11], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size4 mux_left_track_13 + ( + .in({chany_top_in[12], chany_bottom_in[9], chany_bottom_in[12], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size4_0_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size4 mux_left_track_15 + ( + .in({chany_top_in[14], chany_bottom_in[13], chany_bottom_in[14], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size4_1_sram), + .sram_inv(mux_left_track_15_undriven_sram_inv), + .out(chanx_left_out[7]) + ); + mux_tree_tapbuf_size4 mux_left_track_17 + ( + .in({chany_top_in[15], chany_bottom_in[15], chany_bottom_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size4_2_sram), + .sram_inv(mux_left_track_17_undriven_sram_inv), + .out(chanx_left_out[8]) + ); + mux_tree_tapbuf_size4 mux_left_track_19 + ( + .in({chany_top_in[16], chany_bottom_in[16], chany_bottom_in[21], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size4_3_sram), + .sram_inv(mux_left_track_19_undriven_sram_inv), + .out(chanx_left_out[9]) + ); + mux_tree_tapbuf_size4 mux_left_track_21 + ( + .in({chany_top_in[18], chany_bottom_in[18], chany_bottom_in[25], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size4_4_sram), + .sram_inv(mux_left_track_21_undriven_sram_inv), + .out(chanx_left_out[10]) + ); + mux_tree_tapbuf_size4 mux_left_track_23 + ( + .in({chany_top_in[19], chany_bottom_in[19], chany_bottom_in[29], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size4_5_sram), + .sram_inv(mux_left_track_23_undriven_sram_inv), + .out(chanx_left_out[11]) + ); + mux_tree_tapbuf_size4_mem mem_left_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_17 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_19 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram) + ); + mux_tree_tapbuf_size4_mem mem_left_track_23 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram) + ); + mux_tree_tapbuf_size3 mux_left_track_25 + ( + .in({chany_top_in[20], chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_left_track_25_undriven_sram_inv), + .out(chanx_left_out[12]) + ); + mux_tree_tapbuf_size3 mux_left_track_27 + ( + .in({chany_top_in[22], chany_bottom_in[22], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_left_track_27_undriven_sram_inv), + .out(chanx_left_out[13]) + ); + mux_tree_tapbuf_size3 mux_left_track_29 + ( + .in({chany_top_in[23], chany_bottom_in[23], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size3 mux_left_track_31 + ( + .in({chany_top_in[24], chany_bottom_in[24], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_left_track_31_undriven_sram_inv), + .out(chanx_left_out[15]) + ); + mux_tree_tapbuf_size3 mux_left_track_33 + ( + .in({chany_top_in[26], chany_bottom_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_left_track_33_undriven_sram_inv), + .out(chanx_left_out[16]) + ); + mux_tree_tapbuf_size3 mux_left_track_35 + ( + .in({chany_top_in[27], chany_bottom_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_left_track_35_undriven_sram_inv), + .out(chanx_left_out[17]) + ); + mux_tree_tapbuf_size3 mux_left_track_37 + ( + .in({chany_top_in[28], chany_bottom_in[28], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_left_track_37_undriven_sram_inv), + .out(chanx_left_out[18]) + ); + mux_tree_tapbuf_size3 mux_left_track_51 + ( + .in({chany_top_in[9], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_7_sram), + .sram_inv(mux_left_track_51_undriven_sram_inv), + .out(chanx_left_out[25]) + ); + mux_tree_tapbuf_size3_mem mem_left_track_25 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_27 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_31 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_33 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_35 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_51 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram) + ); + mux_tree_tapbuf_size2 mux_left_track_41 + ( + .in({chany_top_in[29], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_left_track_41_undriven_sram_inv), + .out(chanx_left_out[20]) + ); + mux_tree_tapbuf_size2 mux_left_track_45 + ( + .in({chany_top_in[21], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size2 mux_left_track_47 + ( + .in({chany_top_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_left_track_47_undriven_sram_inv), + .out(chanx_left_out[23]) + ); + mux_tree_tapbuf_size2 mux_left_track_49 + ( + .in({chany_top_in[13], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_left_track_49_undriven_sram_inv), + .out(chanx_left_out[24]) + ); + mux_tree_tapbuf_size2 mux_left_track_53 + ( + .in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_left_track_53_undriven_sram_inv), + .out(chanx_left_out[26]) + ); + mux_tree_tapbuf_size2 mux_left_track_55 + ( + .in({chany_top_in[4], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_left_track_55_undriven_sram_inv), + .out(chanx_left_out[27]) + ); + mux_tree_tapbuf_size2 mux_left_track_57 + ( + .in({chany_top_in[2], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_left_track_57_undriven_sram_inv), + .out(chanx_left_out[28]) + ); + mux_tree_tapbuf_size2_mem mem_left_track_41 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_47 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_49 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_55 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_57 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__8_.v new file mode 100644 index 0000000..79a9f96 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__8_.v @@ -0,0 +1,1117 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sb_8__8_ +( + pReset, + prog_clk, + chany_bottom_in, + bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, + chanx_left_in, + left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, + ccff_head, + chany_bottom_out, + chanx_left_out, + ccff_tail +); + + input pReset; + input prog_clk; + input [0:29]chany_bottom_in; + input bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + input bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + input bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + input [0:29]chanx_left_in; + input left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + input left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + input ccff_head; + output [0:29]chany_bottom_out; + output [0:29]chanx_left_out; + output ccff_tail; + + wire pReset; + wire prog_clk; + wire [0:29]chany_bottom_in; + wire bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; + wire bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; + wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_; + wire [0:29]chanx_left_in; + wire left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; + wire left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; + wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; + wire ccff_head; + wire [0:29]chany_bottom_out; + wire [0:29]chanx_left_out; + wire ccff_tail; + wire [0:2]mux_bottom_track_11_undriven_sram_inv; + wire [0:1]mux_bottom_track_13_undriven_sram_inv; + wire [0:1]mux_bottom_track_15_undriven_sram_inv; + wire [0:1]mux_bottom_track_17_undriven_sram_inv; + wire [0:1]mux_bottom_track_19_undriven_sram_inv; + wire [0:2]mux_bottom_track_1_undriven_sram_inv; + wire [0:1]mux_bottom_track_21_undriven_sram_inv; + wire [0:1]mux_bottom_track_23_undriven_sram_inv; + wire [0:1]mux_bottom_track_25_undriven_sram_inv; + wire [0:1]mux_bottom_track_27_undriven_sram_inv; + wire [0:1]mux_bottom_track_29_undriven_sram_inv; + wire [0:1]mux_bottom_track_31_undriven_sram_inv; + wire [0:1]mux_bottom_track_33_undriven_sram_inv; + wire [0:1]mux_bottom_track_35_undriven_sram_inv; + wire [0:2]mux_bottom_track_3_undriven_sram_inv; + wire [0:1]mux_bottom_track_45_undriven_sram_inv; + wire [0:1]mux_bottom_track_47_undriven_sram_inv; + wire [0:1]mux_bottom_track_49_undriven_sram_inv; + wire [0:1]mux_bottom_track_51_undriven_sram_inv; + wire [0:1]mux_bottom_track_53_undriven_sram_inv; + wire [0:1]mux_bottom_track_55_undriven_sram_inv; + wire [0:1]mux_bottom_track_57_undriven_sram_inv; + wire [0:1]mux_bottom_track_59_undriven_sram_inv; + wire [0:2]mux_bottom_track_5_undriven_sram_inv; + wire [0:2]mux_bottom_track_7_undriven_sram_inv; + wire [0:2]mux_bottom_track_9_undriven_sram_inv; + wire [0:2]mux_left_track_11_undriven_sram_inv; + wire [0:1]mux_left_track_13_undriven_sram_inv; + wire [0:1]mux_left_track_15_undriven_sram_inv; + wire [0:1]mux_left_track_17_undriven_sram_inv; + wire [0:1]mux_left_track_19_undriven_sram_inv; + wire [0:2]mux_left_track_1_undriven_sram_inv; + wire [0:1]mux_left_track_21_undriven_sram_inv; + wire [0:1]mux_left_track_23_undriven_sram_inv; + wire [0:1]mux_left_track_25_undriven_sram_inv; + wire [0:1]mux_left_track_27_undriven_sram_inv; + wire [0:1]mux_left_track_29_undriven_sram_inv; + wire [0:1]mux_left_track_31_undriven_sram_inv; + wire [0:1]mux_left_track_33_undriven_sram_inv; + wire [0:1]mux_left_track_35_undriven_sram_inv; + wire [0:1]mux_left_track_37_undriven_sram_inv; + wire [0:1]mux_left_track_39_undriven_sram_inv; + wire [0:2]mux_left_track_3_undriven_sram_inv; + wire [0:1]mux_left_track_41_undriven_sram_inv; + wire [0:1]mux_left_track_43_undriven_sram_inv; + wire [0:1]mux_left_track_45_undriven_sram_inv; + wire [0:1]mux_left_track_47_undriven_sram_inv; + wire [0:1]mux_left_track_49_undriven_sram_inv; + wire [0:1]mux_left_track_51_undriven_sram_inv; + wire [0:1]mux_left_track_53_undriven_sram_inv; + wire [0:1]mux_left_track_55_undriven_sram_inv; + wire [0:1]mux_left_track_57_undriven_sram_inv; + wire [0:1]mux_left_track_59_undriven_sram_inv; + wire [0:2]mux_left_track_5_undriven_sram_inv; + wire [0:2]mux_left_track_7_undriven_sram_inv; + wire [0:2]mux_left_track_9_undriven_sram_inv; + wire [0:1]mux_tree_tapbuf_size2_0_sram; + wire [0:1]mux_tree_tapbuf_size2_10_sram; + wire [0:1]mux_tree_tapbuf_size2_11_sram; + wire [0:1]mux_tree_tapbuf_size2_12_sram; + wire [0:1]mux_tree_tapbuf_size2_13_sram; + wire [0:1]mux_tree_tapbuf_size2_14_sram; + wire [0:1]mux_tree_tapbuf_size2_15_sram; + wire [0:1]mux_tree_tapbuf_size2_16_sram; + wire [0:1]mux_tree_tapbuf_size2_17_sram; + wire [0:1]mux_tree_tapbuf_size2_18_sram; + wire [0:1]mux_tree_tapbuf_size2_19_sram; + wire [0:1]mux_tree_tapbuf_size2_1_sram; + wire [0:1]mux_tree_tapbuf_size2_20_sram; + wire [0:1]mux_tree_tapbuf_size2_21_sram; + wire [0:1]mux_tree_tapbuf_size2_22_sram; + wire [0:1]mux_tree_tapbuf_size2_23_sram; + wire [0:1]mux_tree_tapbuf_size2_24_sram; + wire [0:1]mux_tree_tapbuf_size2_2_sram; + wire [0:1]mux_tree_tapbuf_size2_3_sram; + wire [0:1]mux_tree_tapbuf_size2_4_sram; + wire [0:1]mux_tree_tapbuf_size2_5_sram; + wire [0:1]mux_tree_tapbuf_size2_6_sram; + wire [0:1]mux_tree_tapbuf_size2_7_sram; + wire [0:1]mux_tree_tapbuf_size2_8_sram; + wire [0:1]mux_tree_tapbuf_size2_9_sram; + wire mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire mux_tree_tapbuf_size2_mem_19_ccff_tail; + wire mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire mux_tree_tapbuf_size2_mem_20_ccff_tail; + wire mux_tree_tapbuf_size2_mem_21_ccff_tail; + wire mux_tree_tapbuf_size2_mem_22_ccff_tail; + wire mux_tree_tapbuf_size2_mem_23_ccff_tail; + wire mux_tree_tapbuf_size2_mem_24_ccff_tail; + wire mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1]mux_tree_tapbuf_size3_0_sram; + wire [0:1]mux_tree_tapbuf_size3_10_sram; + wire [0:1]mux_tree_tapbuf_size3_11_sram; + wire [0:1]mux_tree_tapbuf_size3_12_sram; + wire [0:1]mux_tree_tapbuf_size3_13_sram; + wire [0:1]mux_tree_tapbuf_size3_14_sram; + wire [0:1]mux_tree_tapbuf_size3_15_sram; + wire [0:1]mux_tree_tapbuf_size3_16_sram; + wire [0:1]mux_tree_tapbuf_size3_17_sram; + wire [0:1]mux_tree_tapbuf_size3_18_sram; + wire [0:1]mux_tree_tapbuf_size3_1_sram; + wire [0:1]mux_tree_tapbuf_size3_2_sram; + wire [0:1]mux_tree_tapbuf_size3_3_sram; + wire [0:1]mux_tree_tapbuf_size3_4_sram; + wire [0:1]mux_tree_tapbuf_size3_5_sram; + wire [0:1]mux_tree_tapbuf_size3_6_sram; + wire [0:1]mux_tree_tapbuf_size3_7_sram; + wire [0:1]mux_tree_tapbuf_size3_8_sram; + wire [0:1]mux_tree_tapbuf_size3_9_sram; + wire mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire mux_tree_tapbuf_size3_mem_10_ccff_tail; + wire mux_tree_tapbuf_size3_mem_11_ccff_tail; + wire mux_tree_tapbuf_size3_mem_12_ccff_tail; + wire mux_tree_tapbuf_size3_mem_13_ccff_tail; + wire mux_tree_tapbuf_size3_mem_14_ccff_tail; + wire mux_tree_tapbuf_size3_mem_15_ccff_tail; + wire mux_tree_tapbuf_size3_mem_16_ccff_tail; + wire mux_tree_tapbuf_size3_mem_17_ccff_tail; + wire mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire mux_tree_tapbuf_size3_mem_7_ccff_tail; + wire mux_tree_tapbuf_size3_mem_8_ccff_tail; + wire mux_tree_tapbuf_size3_mem_9_ccff_tail; + wire [0:2]mux_tree_tapbuf_size5_0_sram; + wire [0:2]mux_tree_tapbuf_size5_10_sram; + wire [0:2]mux_tree_tapbuf_size5_11_sram; + wire [0:2]mux_tree_tapbuf_size5_1_sram; + wire [0:2]mux_tree_tapbuf_size5_2_sram; + wire [0:2]mux_tree_tapbuf_size5_3_sram; + wire [0:2]mux_tree_tapbuf_size5_4_sram; + wire [0:2]mux_tree_tapbuf_size5_5_sram; + wire [0:2]mux_tree_tapbuf_size5_6_sram; + wire [0:2]mux_tree_tapbuf_size5_7_sram; + wire [0:2]mux_tree_tapbuf_size5_8_sram; + wire [0:2]mux_tree_tapbuf_size5_9_sram; + wire mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire mux_tree_tapbuf_size5_mem_10_ccff_tail; + wire mux_tree_tapbuf_size5_mem_11_ccff_tail; + wire mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire mux_tree_tapbuf_size5_mem_5_ccff_tail; + wire mux_tree_tapbuf_size5_mem_6_ccff_tail; + wire mux_tree_tapbuf_size5_mem_7_ccff_tail; + wire mux_tree_tapbuf_size5_mem_8_ccff_tail; + wire mux_tree_tapbuf_size5_mem_9_ccff_tail; + +assign chany_bottom_out[18] = chanx_left_in[19]; +assign chany_bottom_out[19] = chanx_left_in[20]; +assign chany_bottom_out[20] = chanx_left_in[21]; +assign chany_bottom_out[21] = chanx_left_in[22]; + mux_tree_tapbuf_size5 mux_bottom_track_1 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[1]}), + .sram(mux_tree_tapbuf_size5_0_sram), + .sram_inv(mux_bottom_track_1_undriven_sram_inv), + .out(chany_bottom_out[0]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_3 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[2]}), + .sram(mux_tree_tapbuf_size5_1_sram), + .sram_inv(mux_bottom_track_3_undriven_sram_inv), + .out(chany_bottom_out[1]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_5 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size5_2_sram), + .sram_inv(mux_bottom_track_5_undriven_sram_inv), + .out(chany_bottom_out[2]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_7 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[4]}), + .sram(mux_tree_tapbuf_size5_3_sram), + .sram_inv(mux_bottom_track_7_undriven_sram_inv), + .out(chany_bottom_out[3]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_9 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[5]}), + .sram(mux_tree_tapbuf_size5_4_sram), + .sram_inv(mux_bottom_track_9_undriven_sram_inv), + .out(chany_bottom_out[4]) + ); + mux_tree_tapbuf_size5 mux_bottom_track_11 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size5_5_sram), + .sram_inv(mux_bottom_track_11_undriven_sram_inv), + .out(chany_bottom_out[5]) + ); + mux_tree_tapbuf_size5 mux_left_track_1 + ( + .in({chany_bottom_in[29], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_6_sram), + .sram_inv(mux_left_track_1_undriven_sram_inv), + .out(chanx_left_out[0]) + ); + mux_tree_tapbuf_size5 mux_left_track_3 + ( + .in({chany_bottom_in[0], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size5_7_sram), + .sram_inv(mux_left_track_3_undriven_sram_inv), + .out(chanx_left_out[1]) + ); + mux_tree_tapbuf_size5 mux_left_track_5 + ( + .in({chany_bottom_in[1], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size5_8_sram), + .sram_inv(mux_left_track_5_undriven_sram_inv), + .out(chanx_left_out[2]) + ); + mux_tree_tapbuf_size5 mux_left_track_7 + ( + .in({chany_bottom_in[2], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size5_9_sram), + .sram_inv(mux_left_track_7_undriven_sram_inv), + .out(chanx_left_out[3]) + ); + mux_tree_tapbuf_size5 mux_left_track_9 + ( + .in({chany_bottom_in[3], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size5_10_sram), + .sram_inv(mux_left_track_9_undriven_sram_inv), + .out(chanx_left_out[4]) + ); + mux_tree_tapbuf_size5 mux_left_track_11 + ( + .in({chany_bottom_in[4], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size5_11_sram), + .sram_inv(mux_left_track_11_undriven_sram_inv), + .out(chanx_left_out[5]) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_0_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_1_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_2_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_3_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_4_sram) + ); + mux_tree_tapbuf_size5_mem mem_bottom_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_5_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_1 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_6_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_3 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_7_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_5 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_8_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_7 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_9_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_9 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_10_sram) + ); + mux_tree_tapbuf_size5_mem mem_left_track_11 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size5_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size5_11_sram) + ); + mux_tree_tapbuf_size2 mux_bottom_track_13 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size2_0_sram), + .sram_inv(mux_bottom_track_13_undriven_sram_inv), + .out(chany_bottom_out[6]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_15 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size2_1_sram), + .sram_inv(mux_bottom_track_15_undriven_sram_inv), + .out(chany_bottom_out[7]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_17 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size2_2_sram), + .sram_inv(mux_bottom_track_17_undriven_sram_inv), + .out(chany_bottom_out[8]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_19 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size2_3_sram), + .sram_inv(mux_bottom_track_19_undriven_sram_inv), + .out(chany_bottom_out[9]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_21 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size2_4_sram), + .sram_inv(mux_bottom_track_21_undriven_sram_inv), + .out(chany_bottom_out[10]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_23 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size2_5_sram), + .sram_inv(mux_bottom_track_23_undriven_sram_inv), + .out(chany_bottom_out[11]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_25 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size2_6_sram), + .sram_inv(mux_bottom_track_25_undriven_sram_inv), + .out(chany_bottom_out[12]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_27 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size2_7_sram), + .sram_inv(mux_bottom_track_27_undriven_sram_inv), + .out(chany_bottom_out[13]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_53 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[27]}), + .sram(mux_tree_tapbuf_size2_8_sram), + .sram_inv(mux_bottom_track_53_undriven_sram_inv), + .out(chany_bottom_out[26]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_55 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[28]}), + .sram(mux_tree_tapbuf_size2_9_sram), + .sram_inv(mux_bottom_track_55_undriven_sram_inv), + .out(chany_bottom_out[27]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_57 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[29]}), + .sram(mux_tree_tapbuf_size2_10_sram), + .sram_inv(mux_bottom_track_57_undriven_sram_inv), + .out(chany_bottom_out[28]) + ); + mux_tree_tapbuf_size2 mux_bottom_track_59 + ( + .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[0]}), + .sram(mux_tree_tapbuf_size2_11_sram), + .sram_inv(mux_bottom_track_59_undriven_sram_inv), + .out(chany_bottom_out[29]) + ); + mux_tree_tapbuf_size2 mux_left_track_19 + ( + .in({chany_bottom_in[8], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_12_sram), + .sram_inv(mux_left_track_19_undriven_sram_inv), + .out(chanx_left_out[9]) + ); + mux_tree_tapbuf_size2 mux_left_track_21 + ( + .in({chany_bottom_in[9], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_13_sram), + .sram_inv(mux_left_track_21_undriven_sram_inv), + .out(chanx_left_out[10]) + ); + mux_tree_tapbuf_size2 mux_left_track_23 + ( + .in({chany_bottom_in[10], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_14_sram), + .sram_inv(mux_left_track_23_undriven_sram_inv), + .out(chanx_left_out[11]) + ); + mux_tree_tapbuf_size2 mux_left_track_25 + ( + .in({chany_bottom_in[11], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_15_sram), + .sram_inv(mux_left_track_25_undriven_sram_inv), + .out(chanx_left_out[12]) + ); + mux_tree_tapbuf_size2 mux_left_track_27 + ( + .in({chany_bottom_in[12], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size2_16_sram), + .sram_inv(mux_left_track_27_undriven_sram_inv), + .out(chanx_left_out[13]) + ); + mux_tree_tapbuf_size2 mux_left_track_37 + ( + .in({chany_bottom_in[17], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_17_sram), + .sram_inv(mux_left_track_37_undriven_sram_inv), + .out(chanx_left_out[18]) + ); + mux_tree_tapbuf_size2 mux_left_track_39 + ( + .in({chany_bottom_in[18], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_18_sram), + .sram_inv(mux_left_track_39_undriven_sram_inv), + .out(chanx_left_out[19]) + ); + mux_tree_tapbuf_size2 mux_left_track_41 + ( + .in({chany_bottom_in[19], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_19_sram), + .sram_inv(mux_left_track_41_undriven_sram_inv), + .out(chanx_left_out[20]) + ); + mux_tree_tapbuf_size2 mux_left_track_43 + ( + .in({chany_bottom_in[20], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), + .sram(mux_tree_tapbuf_size2_20_sram), + .sram_inv(mux_left_track_43_undriven_sram_inv), + .out(chanx_left_out[21]) + ); + mux_tree_tapbuf_size2 mux_left_track_51 + ( + .in({chany_bottom_in[24], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_21_sram), + .sram_inv(mux_left_track_51_undriven_sram_inv), + .out(chanx_left_out[25]) + ); + mux_tree_tapbuf_size2 mux_left_track_53 + ( + .in({chany_bottom_in[25], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), + .sram(mux_tree_tapbuf_size2_22_sram), + .sram_inv(mux_left_track_53_undriven_sram_inv), + .out(chanx_left_out[26]) + ); + mux_tree_tapbuf_size2 mux_left_track_55 + ( + .in({chany_bottom_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), + .sram(mux_tree_tapbuf_size2_23_sram), + .sram_inv(mux_left_track_55_undriven_sram_inv), + .out(chanx_left_out[27]) + ); + mux_tree_tapbuf_size2 mux_left_track_57 + ( + .in({chany_bottom_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size2_24_sram), + .sram_inv(mux_left_track_57_undriven_sram_inv), + .out(chanx_left_out[28]) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_17 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_19 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_23 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_25 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_27 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_7_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_8_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_55 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_9_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_57 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_10_sram) + ); + mux_tree_tapbuf_size2_mem mem_bottom_track_59 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_11_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_19 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_12_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_21 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_13_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_23 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_14_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_25 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_15_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_27 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_16_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_37 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_17_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_39 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_18_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_41 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_19_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_43 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_20_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_51 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_17_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_21_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_53 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_22_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_55 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_23_sram) + ); + mux_tree_tapbuf_size2_mem mem_left_track_57 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_24_sram) + ); + mux_tree_tapbuf_size3 mux_bottom_track_29 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size3_0_sram), + .sram_inv(mux_bottom_track_29_undriven_sram_inv), + .out(chany_bottom_out[14]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_31 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size3_1_sram), + .sram_inv(mux_bottom_track_31_undriven_sram_inv), + .out(chany_bottom_out[15]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_33 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size3_2_sram), + .sram_inv(mux_bottom_track_33_undriven_sram_inv), + .out(chany_bottom_out[16]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_35 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_3_sram), + .sram_inv(mux_bottom_track_35_undriven_sram_inv), + .out(chany_bottom_out[17]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_45 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[23]}), + .sram(mux_tree_tapbuf_size3_4_sram), + .sram_inv(mux_bottom_track_45_undriven_sram_inv), + .out(chany_bottom_out[22]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_47 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[24]}), + .sram(mux_tree_tapbuf_size3_5_sram), + .sram_inv(mux_bottom_track_47_undriven_sram_inv), + .out(chany_bottom_out[23]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_49 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[25]}), + .sram(mux_tree_tapbuf_size3_6_sram), + .sram_inv(mux_bottom_track_49_undriven_sram_inv), + .out(chany_bottom_out[24]) + ); + mux_tree_tapbuf_size3 mux_bottom_track_51 + ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[26]}), + .sram(mux_tree_tapbuf_size3_7_sram), + .sram_inv(mux_bottom_track_51_undriven_sram_inv), + .out(chany_bottom_out[25]) + ); + mux_tree_tapbuf_size3 mux_left_track_13 + ( + .in({chany_bottom_in[5], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_8_sram), + .sram_inv(mux_left_track_13_undriven_sram_inv), + .out(chanx_left_out[6]) + ); + mux_tree_tapbuf_size3 mux_left_track_15 + ( + .in({chany_bottom_in[6], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size3_9_sram), + .sram_inv(mux_left_track_15_undriven_sram_inv), + .out(chanx_left_out[7]) + ); + mux_tree_tapbuf_size3 mux_left_track_17 + ( + .in({chany_bottom_in[7], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_10_sram), + .sram_inv(mux_left_track_17_undriven_sram_inv), + .out(chanx_left_out[8]) + ); + mux_tree_tapbuf_size3 mux_left_track_29 + ( + .in({chany_bottom_in[13], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_11_sram), + .sram_inv(mux_left_track_29_undriven_sram_inv), + .out(chanx_left_out[14]) + ); + mux_tree_tapbuf_size3 mux_left_track_31 + ( + .in({chany_bottom_in[14], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size3_12_sram), + .sram_inv(mux_left_track_31_undriven_sram_inv), + .out(chanx_left_out[15]) + ); + mux_tree_tapbuf_size3 mux_left_track_33 + ( + .in({chany_bottom_in[15], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_13_sram), + .sram_inv(mux_left_track_33_undriven_sram_inv), + .out(chanx_left_out[16]) + ); + mux_tree_tapbuf_size3 mux_left_track_35 + ( + .in({chany_bottom_in[16], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_14_sram), + .sram_inv(mux_left_track_35_undriven_sram_inv), + .out(chanx_left_out[17]) + ); + mux_tree_tapbuf_size3 mux_left_track_45 + ( + .in({chany_bottom_in[21], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), + .sram(mux_tree_tapbuf_size3_15_sram), + .sram_inv(mux_left_track_45_undriven_sram_inv), + .out(chanx_left_out[22]) + ); + mux_tree_tapbuf_size3 mux_left_track_47 + ( + .in({chany_bottom_in[22], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), + .sram(mux_tree_tapbuf_size3_16_sram), + .sram_inv(mux_left_track_47_undriven_sram_inv), + .out(chanx_left_out[23]) + ); + mux_tree_tapbuf_size3 mux_left_track_49 + ( + .in({chany_bottom_in[23], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), + .sram(mux_tree_tapbuf_size3_17_sram), + .sram_inv(mux_left_track_49_undriven_sram_inv), + .out(chanx_left_out[24]) + ); + mux_tree_tapbuf_size3 mux_left_track_59 + ( + .in({chany_bottom_in[28], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), + .sram(mux_tree_tapbuf_size3_18_sram), + .sram_inv(mux_left_track_59_undriven_sram_inv), + .out(chanx_left_out[29]) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_31 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_33 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_35 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_47 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_49 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram) + ); + mux_tree_tapbuf_size3_mem mem_bottom_track_51 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_13 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size5_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_15 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_17 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_29 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_31 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_12_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_33 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_13_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_35 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_14_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_45 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_15_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_15_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_47 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_15_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_16_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_16_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_49 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_16_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_17_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_17_sram) + ); + mux_tree_tapbuf_size3_mem mem_left_track_59 + ( + .pReset(pReset), + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size3_18_sram) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/inv_buf_passgate.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/inv_buf_passgate.v new file mode 100644 index 0000000..5fbf891 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/inv_buf_passgate.v @@ -0,0 +1,28 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module const0 +( + const0 +); + + output const0; + + wire const0; + wire \ ; + +assign const0 = \ ; +endmodule + +module const1 +( + const1 +); + + output const1; + + wire const1; + wire \ ; + +assign const1 = \ ; +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/luts.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/luts.v new file mode 100644 index 0000000..ed44c51 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/luts.v @@ -0,0 +1,98 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module frac_lut4 +( + in, + sram, + sram_inv, + mode, + mode_inv, + lut2_out, + lut3_out, + lut4_out +); + + input [0:3]in; + input [0:15]sram; + input [0:15]sram_inv; + input mode; + input mode_inv; + output [0:1]lut2_out; + output [0:1]lut3_out; + output lut4_out; + + wire [0:3]in; + wire [0:15]sram; + wire [0:15]sram_inv; + wire mode; + wire mode_inv; + wire [0:1]lut2_out; + wire [0:1]lut3_out; + wire lut4_out; + wire sky130_fd_sc_hd__buf_2_0_X; + wire sky130_fd_sc_hd__buf_2_1_X; + wire sky130_fd_sc_hd__buf_2_2_X; + wire sky130_fd_sc_hd__buf_2_3_X; + wire sky130_fd_sc_hd__inv_1_0_Y; + wire sky130_fd_sc_hd__inv_1_1_Y; + wire sky130_fd_sc_hd__inv_1_2_Y; + wire sky130_fd_sc_hd__inv_1_3_Y; + wire sky130_fd_sc_hd__or2_1_0_X; + + sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_ + ( + .A(mode), + .B(in[3]), + .X(sky130_fd_sc_hd__or2_1_0_X) + ); + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ + ( + .A(in[0]), + .Y(sky130_fd_sc_hd__inv_1_0_Y) + ); + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ + ( + .A(in[1]), + .Y(sky130_fd_sc_hd__inv_1_1_Y) + ); + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ + ( + .A(in[2]), + .Y(sky130_fd_sc_hd__inv_1_2_Y) + ); + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ + ( + .A(sky130_fd_sc_hd__or2_1_0_X), + .Y(sky130_fd_sc_hd__inv_1_3_Y) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ + ( + .A(in[0]), + .X(sky130_fd_sc_hd__buf_2_0_X) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ + ( + .A(in[1]), + .X(sky130_fd_sc_hd__buf_2_1_X) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ + ( + .A(in[2]), + .X(sky130_fd_sc_hd__buf_2_2_X) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ + ( + .A(sky130_fd_sc_hd__or2_1_0_X), + .X(sky130_fd_sc_hd__buf_2_3_X) + ); + frac_lut4_mux frac_lut4_mux_0_ + ( + .in(sram), + .sram({sky130_fd_sc_hd__buf_2_0_X, sky130_fd_sc_hd__buf_2_1_X, sky130_fd_sc_hd__buf_2_2_X, sky130_fd_sc_hd__buf_2_3_X}), + .sram_inv({sky130_fd_sc_hd__inv_1_0_Y, sky130_fd_sc_hd__inv_1_1_Y, sky130_fd_sc_hd__inv_1_2_Y, sky130_fd_sc_hd__inv_1_3_Y}), + .lut2_out(lut2_out), + .lut3_out(lut3_out), + .lut4_out(lut4_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/memories.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/memories.v new file mode 100644 index 0000000..7c86232 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/memories.v @@ -0,0 +1,730 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size12_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:3]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:3]mem_out; + +assign ccff_tail = mem_out[3]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]) + ); +endmodule + +module mux_tree_tapbuf_size10_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:3]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:3]mem_out; + +assign ccff_tail = mem_out[3]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]) + ); +endmodule + +module mux_tree_tapbuf_size3_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:1]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:1]mem_out; + +assign ccff_tail = mem_out[1]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); +endmodule + +module mux_tree_tapbuf_size7_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:2]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:2]mem_out; + +assign ccff_tail = mem_out[2]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); +endmodule + +module mux_tree_tapbuf_size2_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:1]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:1]mem_out; + +assign ccff_tail = mem_out[1]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); +endmodule + +module mux_tree_tapbuf_size5_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:2]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:2]mem_out; + +assign ccff_tail = mem_out[2]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); +endmodule + +module mux_tree_tapbuf_size6_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:2]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:2]mem_out; + +assign ccff_tail = mem_out[2]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); +endmodule + +module mux_tree_tapbuf_size4_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:2]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:2]mem_out; + +assign ccff_tail = mem_out[2]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); +endmodule + +module mux_tree_tapbuf_size11_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:3]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:3]mem_out; + +assign ccff_tail = mem_out[3]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]) + ); +endmodule + +module mux_tree_tapbuf_size9_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:3]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:3]mem_out; + +assign ccff_tail = mem_out[3]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]) + ); +endmodule + +module mux_tree_tapbuf_size8_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:3]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:3]mem_out; + +assign ccff_tail = mem_out[3]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]) + ); +endmodule + +module mux_tree_size2_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:1]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:1]mem_out; + +assign ccff_tail = mem_out[1]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); +endmodule + +module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output [0:16]mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire [0:16]mem_out; + +assign ccff_tail = mem_out[16]; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[3]), + .Q(mem_out[4]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[4]), + .Q(mem_out[5]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[5]), + .Q(mem_out[6]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[6]), + .Q(mem_out[7]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[7]), + .Q(mem_out[8]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[8]), + .Q(mem_out[9]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[9]), + .Q(mem_out[10]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[10]), + .Q(mem_out[11]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[11]), + .Q(mem_out[12]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[12]), + .Q(mem_out[13]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[13]), + .Q(mem_out[14]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[14]), + .Q(mem_out[15]) + ); + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(mem_out[15]), + .Q(mem_out[16]) + ); +endmodule + +module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem +( + pReset, + prog_clk, + ccff_head, + ccff_tail, + mem_out +); + + input pReset; + input prog_clk; + input ccff_head; + output ccff_tail; + output mem_out; + + wire pReset; + wire prog_clk; + wire ccff_head; + wire ccff_tail; + wire mem_out; + +assign ccff_tail = mem_out; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ + ( + .RESET_B(pReset), + .CLK(prog_clk), + .D(ccff_head), + .Q(mem_out) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/muxes.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/muxes.v new file mode 100644 index 0000000..6a57e06 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/muxes.v @@ -0,0 +1,1171 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module mux_tree_tapbuf_size12 +( + in, + sram, + sram_inv, + out +); + + input [0:11]in; + input [0:3]sram; + input [0:3]sram_inv; + output out; + + wire [0:11]in; + wire [0:3]sram; + wire [0:3]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_10_X; + wire sky130_fd_sc_hd__mux2_1_11_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire sky130_fd_sc_hd__mux2_1_8_X; + wire sky130_fd_sc_hd__mux2_1_9_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_11_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ + ( + .A1(in[6]), + .A0(in[7]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ + ( + .A1(in[8]), + .A0(in[9]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .A0(in[10]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A1(in[11]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_8_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_5_X), + .A0(sky130_fd_sc_hd__mux2_1_6_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_9_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_7_X), + .A0(sky130_fd_sc_hd__mux2_1_8_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_10_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_9_X), + .A0(sky130_fd_sc_hd__mux2_1_10_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_11_X) + ); +endmodule + +module mux_tree_tapbuf_size10 +( + in, + sram, + sram_inv, + out +); + + input [0:9]in; + input [0:3]sram; + input [0:3]sram_inv; + output out; + + wire [0:9]in; + wire [0:3]sram; + wire [0:3]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire sky130_fd_sc_hd__mux2_1_8_X; + wire sky130_fd_sc_hd__mux2_1_9_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_9_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(in[6]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A1(in[7]), + .A0(in[8]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A1(in[9]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_3_X), + .A0(sky130_fd_sc_hd__mux2_1_4_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_5_X), + .A0(sky130_fd_sc_hd__mux2_1_6_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_8_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_7_X), + .A0(sky130_fd_sc_hd__mux2_1_8_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_9_X) + ); +endmodule + +module mux_tree_tapbuf_size3 +( + in, + sram, + sram_inv, + out +); + + input [0:2]in; + input [0:1]sram; + input [0:1]sram_inv; + output out; + + wire [0:2]in; + wire [0:1]sram; + wire [0:1]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_2_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(const1_0_const1), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); +endmodule + +module mux_tree_tapbuf_size7 +( + in, + sram, + sram_inv, + out +); + + input [0:6]in; + input [0:2]sram; + input [0:2]sram_inv; + output out; + + wire [0:6]in; + wire [0:2]sram; + wire [0:2]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_6_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ + ( + .A1(in[6]), + .A0(const1_0_const1), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .A0(sky130_fd_sc_hd__mux2_1_5_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); +endmodule + +module mux_tree_tapbuf_size2 +( + in, + sram, + sram_inv, + out +); + + input [0:1]in; + input [0:1]sram; + input [0:1]sram_inv; + output out; + + wire [0:1]in; + wire [0:1]sram; + wire [0:1]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_1_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); +endmodule + +module mux_tree_tapbuf_size5 +( + in, + sram, + sram_inv, + out +); + + input [0:4]in; + input [0:2]sram; + input [0:2]sram_inv; + output out; + + wire [0:4]in; + wire [0:2]sram; + wire [0:2]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_4_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(in[4]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); +endmodule + +module mux_tree_tapbuf_size6 +( + in, + sram, + sram_inv, + out +); + + input [0:5]in; + input [0:2]sram; + input [0:2]sram_inv; + output out; + + wire [0:5]in; + wire [0:2]sram; + wire [0:2]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_5_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_3_X), + .A0(sky130_fd_sc_hd__mux2_1_4_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); +endmodule + +module mux_tree_tapbuf_size4 +( + in, + sram, + sram_inv, + out +); + + input [0:3]in; + input [0:2]sram; + input [0:2]sram_inv; + output out; + + wire [0:3]in; + wire [0:2]sram; + wire [0:2]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_3_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(in[2]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(in[3]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_1_X), + .A0(sky130_fd_sc_hd__mux2_1_2_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); +endmodule + +module mux_tree_tapbuf_size11 +( + in, + sram, + sram_inv, + out +); + + input [0:10]in; + input [0:3]sram; + input [0:3]sram_inv; + output out; + + wire [0:10]in; + wire [0:3]sram; + wire [0:3]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_10_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire sky130_fd_sc_hd__mux2_1_8_X; + wire sky130_fd_sc_hd__mux2_1_9_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_10_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ + ( + .A1(in[6]), + .A0(in[7]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A1(in[8]), + .A0(in[9]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A1(in[10]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .A0(sky130_fd_sc_hd__mux2_1_5_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_8_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_6_X), + .A0(sky130_fd_sc_hd__mux2_1_7_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_9_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_8_X), + .A0(sky130_fd_sc_hd__mux2_1_9_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_10_X) + ); +endmodule + +module mux_tree_tapbuf_size9 +( + in, + sram, + sram_inv, + out +); + + input [0:8]in; + input [0:3]sram; + input [0:3]sram_inv; + output out; + + wire [0:8]in; + wire [0:3]sram; + wire [0:3]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire sky130_fd_sc_hd__mux2_1_8_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_8_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(in[4]), + .A0(in[5]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A1(in[6]), + .A0(in[7]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A1(in[8]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .A0(sky130_fd_sc_hd__mux2_1_5_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_6_X), + .A0(sky130_fd_sc_hd__mux2_1_7_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_8_X) + ); +endmodule + +module mux_tree_tapbuf_size8 +( + in, + sram, + sram_inv, + out +); + + input [0:7]in; + input [0:3]sram; + input [0:3]sram_inv; + output out; + + wire [0:7]in; + wire [0:3]sram; + wire [0:3]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_7_X), + .X(out) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(in[2]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(in[3]), + .A0(in[4]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A1(in[5]), + .A0(in[6]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A1(in[7]), + .A0(const1_0_const1), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_1_X), + .A0(sky130_fd_sc_hd__mux2_1_2_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_3_X), + .A0(sky130_fd_sc_hd__mux2_1_4_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_5_X), + .A0(sky130_fd_sc_hd__mux2_1_6_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); +endmodule + +module mux_tree_size2 +( + in, + sram, + sram_inv, + out +); + + input [0:1]in; + input [0:1]sram; + input [0:1]sram_inv; + output out; + + wire [0:1]in; + wire [0:1]sram; + wire [0:1]sram_inv; + wire out; + wire const1_0_const1; + wire sky130_fd_sc_hd__mux2_1_0_X; + + const1 const1_0_ + ( + .const1(const1_0_const1) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(const1_0_const1), + .S(sram[1]), + .X(out) + ); +endmodule + +module frac_lut4_mux +( + in, + sram, + sram_inv, + lut2_out, + lut3_out, + lut4_out +); + + input [0:15]in; + input [0:3]sram; + input [0:3]sram_inv; + output [0:1]lut2_out; + output [0:1]lut3_out; + output lut4_out; + + wire [0:15]in; + wire [0:3]sram; + wire [0:3]sram_inv; + wire [0:1]lut2_out; + wire [0:1]lut3_out; + wire lut4_out; + wire sky130_fd_sc_hd__buf_2_5_X; + wire sky130_fd_sc_hd__buf_2_6_X; + wire sky130_fd_sc_hd__mux2_1_0_X; + wire sky130_fd_sc_hd__mux2_1_10_X; + wire sky130_fd_sc_hd__mux2_1_11_X; + wire sky130_fd_sc_hd__mux2_1_12_X; + wire sky130_fd_sc_hd__mux2_1_13_X; + wire sky130_fd_sc_hd__mux2_1_14_X; + wire sky130_fd_sc_hd__mux2_1_1_X; + wire sky130_fd_sc_hd__mux2_1_2_X; + wire sky130_fd_sc_hd__mux2_1_3_X; + wire sky130_fd_sc_hd__mux2_1_4_X; + wire sky130_fd_sc_hd__mux2_1_5_X; + wire sky130_fd_sc_hd__mux2_1_6_X; + wire sky130_fd_sc_hd__mux2_1_7_X; + wire sky130_fd_sc_hd__mux2_1_8_X; + wire sky130_fd_sc_hd__mux2_1_9_X; + + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ + ( + .A(sky130_fd_sc_hd__mux2_1_10_X), + .X(lut2_out[0]) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ + ( + .A(sky130_fd_sc_hd__mux2_1_11_X), + .X(lut2_out[1]) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ + ( + .A(sky130_fd_sc_hd__mux2_1_12_X), + .X(lut3_out[0]) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ + ( + .A(sky130_fd_sc_hd__mux2_1_13_X), + .X(lut3_out[1]) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ + ( + .A(sky130_fd_sc_hd__mux2_1_14_X), + .X(lut4_out) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ + ( + .A(sky130_fd_sc_hd__mux2_1_8_X), + .X(sky130_fd_sc_hd__buf_2_5_X) + ); + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ + ( + .A(sky130_fd_sc_hd__mux2_1_9_X), + .X(sky130_fd_sc_hd__buf_2_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ + ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ + ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ + ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ + ( + .A1(in[6]), + .A0(in[7]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ + ( + .A1(in[8]), + .A0(in[9]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_4_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ + ( + .A1(in[10]), + .A0(in[11]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_5_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ + ( + .A1(in[12]), + .A0(in[13]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_6_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ + ( + .A1(in[14]), + .A0(in[15]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_7_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_0_X), + .A0(sky130_fd_sc_hd__mux2_1_1_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_8_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_2_X), + .A0(sky130_fd_sc_hd__mux2_1_3_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_9_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ + ( + .A1(sky130_fd_sc_hd__mux2_1_4_X), + .A0(sky130_fd_sc_hd__mux2_1_5_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_10_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ + ( + .A1(sky130_fd_sc_hd__mux2_1_6_X), + .A0(sky130_fd_sc_hd__mux2_1_7_X), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_11_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ + ( + .A1(sky130_fd_sc_hd__buf_2_5_X), + .A0(sky130_fd_sc_hd__buf_2_6_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_12_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ + ( + .A1(sky130_fd_sc_hd__mux2_1_10_X), + .A0(sky130_fd_sc_hd__mux2_1_11_X), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_13_X) + ); + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ + ( + .A1(sky130_fd_sc_hd__mux2_1_12_X), + .A0(sky130_fd_sc_hd__mux2_1_13_X), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_14_X) + ); +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/user_defined_templates.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/user_defined_templates.v new file mode 100644 index 0000000..6647581 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/user_defined_templates.v @@ -0,0 +1,190 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module sky130_fd_sc_hd__inv_1 +( + A, + Y +); + + input A; + output Y; + + wire A; + wire Y; + +endmodule + +module sky130_fd_sc_hd__buf_2 +( + A, + X +); + + input A; + output X; + + wire A; + wire X; + +endmodule + +module sky130_fd_sc_hd__buf_4 +( + A, + X +); + + input A; + output X; + + wire A; + wire X; + +endmodule + +module sky130_fd_sc_hd__inv_2 +( + A, + Y +); + + input A; + output Y; + + wire A; + wire Y; + +endmodule + +module sky130_fd_sc_hd__or2_1 +( + A, + B, + X +); + + input A; + input B; + output X; + + wire A; + wire B; + wire X; + +endmodule + +module sky130_fd_sc_hd__mux2_1 +( + A1, + A0, + S, + X +); + + input A1; + input A0; + input S; + output X; + + wire A1; + wire A0; + wire S; + wire X; + +endmodule + +module sky130_fd_sc_hd__sdfrtp_1 +( + SCE, + D, + SCD, + RESET_B, + CLK, + Q +); + + input SCE; + input D; + input SCD; + input RESET_B; + input CLK; + output Q; + + wire SCE; + wire D; + wire SCD; + wire RESET_B; + wire CLK; + wire Q; + +endmodule + +module sky130_fd_sc_hd__dfrtp_1 +( + RESET_B, + CLK, + D, + Q +); + + input RESET_B; + input CLK; + input D; + output Q; + + wire RESET_B; + wire CLK; + wire D; + wire Q; + +endmodule + +module EMBEDDED_IO_HD +( + IO_ISOL_N, + SOC_IN, + SOC_OUT, + SOC_DIR, + FPGA_OUT, + FPGA_DIR, + FPGA_IN +); + + input IO_ISOL_N; + input SOC_IN; + output SOC_OUT; + output SOC_DIR; + input FPGA_OUT; + input FPGA_DIR; + output FPGA_IN; + + wire IO_ISOL_N; + wire SOC_IN; + wire SOC_OUT; + wire SOC_DIR; + wire FPGA_OUT; + wire FPGA_DIR; + wire FPGA_IN; + +endmodule + +module sky130_fd_sc_hd__mux2_1_wrapper +( + A0, + A1, + S, + X +); + + input A0; + input A1; + input S; + output X; + + wire A0; + wire A1; + wire S; + wire X; + +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/wires.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/wires.v new file mode 100644 index 0000000..304b7eb --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/wires.v @@ -0,0 +1,17 @@ +//Generated from netlist by SpyDrNet +//netlist name: FPGA88_SOFA_A +module direct_interc +( + in, + out +); + + input in; + output out; + + wire in; + wire out; + +assign out = in; +endmodule + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/top_hierarchy.yml b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/top_hierarchy.yml new file mode 100644 index 0000000..6b64b64 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/top_hierarchy.yml @@ -0,0 +1,517 @@ +cbx_1__0_: +- cbx_1__0_ +- cbx_2__0_ +- cbx_3__0_ +- cbx_4__0_ +- cbx_5__0_ +- cbx_6__0_ +- cbx_7__0_ +- cbx_8__0_ +cbx_1__1_: +- cbx_1__1_ +- cbx_1__2_ +- cbx_1__3_ +- cbx_1__4_ +- cbx_1__5_ +- cbx_1__6_ +- cbx_1__7_ +- cbx_2__1_ +- cbx_2__2_ +- cbx_2__3_ +- cbx_2__4_ +- cbx_2__5_ +- cbx_2__6_ +- cbx_2__7_ +- cbx_3__1_ +- cbx_3__2_ +- cbx_3__3_ +- cbx_3__4_ +- cbx_3__5_ +- cbx_3__6_ +- cbx_3__7_ +- cbx_4__1_ +- cbx_4__2_ +- cbx_4__3_ +- cbx_4__4_ +- cbx_4__5_ +- cbx_4__6_ +- cbx_4__7_ +- cbx_5__1_ +- cbx_5__2_ +- cbx_5__3_ +- cbx_5__4_ +- cbx_5__5_ +- cbx_5__6_ +- cbx_5__7_ +- cbx_6__1_ +- cbx_6__2_ +- cbx_6__3_ +- cbx_6__4_ +- cbx_6__5_ +- cbx_6__6_ +- cbx_6__7_ +- cbx_7__1_ +- cbx_7__2_ +- cbx_7__3_ +- cbx_7__4_ +- cbx_7__5_ +- cbx_7__6_ +- cbx_7__7_ +- cbx_8__1_ +- cbx_8__2_ +- cbx_8__3_ +- cbx_8__4_ +- cbx_8__5_ +- cbx_8__6_ +- cbx_8__7_ +cbx_1__8_: +- cbx_1__8_ +- cbx_2__8_ +- cbx_3__8_ +- cbx_4__8_ +- cbx_5__8_ +- cbx_6__8_ +- cbx_7__8_ +- cbx_8__8_ +cby_0__1_: +- cby_0__1_ +- cby_0__2_ +- cby_0__3_ +- cby_0__4_ +- cby_0__5_ +- cby_0__6_ +- cby_0__7_ +- cby_0__8_ +cby_1__1_: +- cby_1__1_ +- cby_1__2_ +- cby_1__3_ +- cby_1__4_ +- cby_1__5_ +- cby_1__6_ +- cby_1__7_ +- cby_1__8_ +- cby_2__1_ +- cby_2__2_ +- cby_2__3_ +- cby_2__4_ +- cby_2__5_ +- cby_2__6_ +- cby_2__7_ +- cby_2__8_ +- cby_3__1_ +- cby_3__2_ +- cby_3__3_ +- cby_3__4_ +- cby_3__5_ +- cby_3__6_ +- cby_3__7_ +- cby_3__8_ +- cby_4__1_ +- cby_4__2_ +- cby_4__3_ +- cby_4__4_ +- cby_4__5_ +- cby_4__6_ +- cby_4__7_ +- cby_4__8_ +- cby_5__1_ +- cby_5__2_ +- cby_5__3_ +- cby_5__4_ +- cby_5__5_ +- cby_5__6_ +- cby_5__7_ +- cby_5__8_ +- cby_6__1_ +- cby_6__2_ +- cby_6__3_ +- cby_6__4_ +- cby_6__5_ +- cby_6__6_ +- cby_6__7_ +- cby_6__8_ +- cby_7__1_ +- cby_7__2_ +- cby_7__3_ +- cby_7__4_ +- cby_7__5_ +- cby_7__6_ +- cby_7__7_ +- cby_7__8_ +cby_8__1_: +- cby_8__1_ +- cby_8__2_ +- cby_8__3_ +- cby_8__4_ +- cby_8__5_ +- cby_8__6_ +- cby_8__7_ +- cby_8__8_ +direct_interc: +- direct_interc_0_ +- direct_interc_100_ +- direct_interc_101_ +- direct_interc_102_ +- direct_interc_103_ +- direct_interc_104_ +- direct_interc_105_ +- direct_interc_106_ +- direct_interc_107_ +- direct_interc_108_ +- direct_interc_109_ +- direct_interc_10_ +- direct_interc_110_ +- direct_interc_111_ +- direct_interc_112_ +- direct_interc_113_ +- direct_interc_114_ +- direct_interc_115_ +- direct_interc_116_ +- direct_interc_117_ +- direct_interc_118_ +- direct_interc_119_ +- direct_interc_11_ +- direct_interc_120_ +- direct_interc_121_ +- direct_interc_122_ +- direct_interc_123_ +- direct_interc_124_ +- direct_interc_125_ +- direct_interc_126_ +- direct_interc_127_ +- direct_interc_128_ +- direct_interc_129_ +- direct_interc_12_ +- direct_interc_130_ +- direct_interc_131_ +- direct_interc_132_ +- direct_interc_133_ +- direct_interc_134_ +- direct_interc_135_ +- direct_interc_136_ +- direct_interc_137_ +- direct_interc_138_ +- direct_interc_139_ +- direct_interc_13_ +- direct_interc_140_ +- direct_interc_141_ +- direct_interc_142_ +- direct_interc_143_ +- direct_interc_144_ +- direct_interc_145_ +- direct_interc_146_ +- direct_interc_147_ +- direct_interc_148_ +- direct_interc_149_ +- direct_interc_14_ +- direct_interc_150_ +- direct_interc_151_ +- direct_interc_152_ +- direct_interc_153_ +- direct_interc_154_ +- direct_interc_155_ +- direct_interc_156_ +- direct_interc_157_ +- direct_interc_158_ +- direct_interc_159_ +- direct_interc_15_ +- direct_interc_160_ +- direct_interc_161_ +- direct_interc_162_ +- direct_interc_163_ +- direct_interc_164_ +- direct_interc_165_ +- direct_interc_166_ +- direct_interc_167_ +- direct_interc_168_ +- direct_interc_169_ +- direct_interc_16_ +- direct_interc_170_ +- direct_interc_171_ +- direct_interc_172_ +- direct_interc_173_ +- direct_interc_174_ +- direct_interc_17_ +- direct_interc_18_ +- direct_interc_19_ +- direct_interc_1_ +- direct_interc_20_ +- direct_interc_21_ +- direct_interc_22_ +- direct_interc_23_ +- direct_interc_24_ +- direct_interc_25_ +- direct_interc_26_ +- direct_interc_27_ +- direct_interc_28_ +- direct_interc_29_ +- direct_interc_2_ +- direct_interc_30_ +- direct_interc_31_ +- direct_interc_32_ +- direct_interc_33_ +- direct_interc_34_ +- direct_interc_35_ +- direct_interc_36_ +- direct_interc_37_ +- direct_interc_38_ +- direct_interc_39_ +- direct_interc_3_ +- direct_interc_40_ +- direct_interc_41_ +- direct_interc_42_ +- direct_interc_43_ +- direct_interc_44_ +- direct_interc_45_ +- direct_interc_46_ +- direct_interc_47_ +- direct_interc_48_ +- direct_interc_49_ +- direct_interc_4_ +- direct_interc_50_ +- direct_interc_51_ +- direct_interc_52_ +- direct_interc_53_ +- direct_interc_54_ +- direct_interc_55_ +- direct_interc_56_ +- direct_interc_57_ +- direct_interc_58_ +- direct_interc_59_ +- direct_interc_5_ +- direct_interc_60_ +- direct_interc_61_ +- direct_interc_62_ +- direct_interc_63_ +- direct_interc_64_ +- direct_interc_65_ +- direct_interc_66_ +- direct_interc_67_ +- direct_interc_68_ +- direct_interc_69_ +- direct_interc_6_ +- direct_interc_70_ +- direct_interc_71_ +- direct_interc_72_ +- direct_interc_73_ +- direct_interc_74_ +- direct_interc_75_ +- direct_interc_76_ +- direct_interc_77_ +- direct_interc_78_ +- direct_interc_79_ +- direct_interc_7_ +- direct_interc_80_ +- direct_interc_81_ +- direct_interc_82_ +- direct_interc_83_ +- direct_interc_84_ +- direct_interc_85_ +- direct_interc_86_ +- direct_interc_87_ +- direct_interc_88_ +- direct_interc_89_ +- direct_interc_8_ +- direct_interc_90_ +- direct_interc_91_ +- direct_interc_92_ +- direct_interc_93_ +- direct_interc_94_ +- direct_interc_95_ +- direct_interc_96_ +- direct_interc_97_ +- direct_interc_98_ +- direct_interc_99_ +- direct_interc_9_ +grid_clb: +- grid_clb_1__1_ +- grid_clb_1__2_ +- grid_clb_1__3_ +- grid_clb_1__4_ +- grid_clb_1__5_ +- grid_clb_1__6_ +- grid_clb_1__7_ +- grid_clb_1__8_ +- grid_clb_2__1_ +- grid_clb_2__2_ +- grid_clb_2__3_ +- grid_clb_2__4_ +- grid_clb_2__5_ +- grid_clb_2__6_ +- grid_clb_2__7_ +- grid_clb_2__8_ +- grid_clb_3__1_ +- grid_clb_3__2_ +- grid_clb_3__3_ +- grid_clb_3__4_ +- grid_clb_3__5_ +- grid_clb_3__6_ +- grid_clb_3__7_ +- grid_clb_3__8_ +- grid_clb_4__1_ +- grid_clb_4__2_ +- grid_clb_4__3_ +- grid_clb_4__4_ +- grid_clb_4__5_ +- grid_clb_4__6_ +- grid_clb_4__7_ +- grid_clb_4__8_ +- grid_clb_5__1_ +- grid_clb_5__2_ +- grid_clb_5__3_ +- grid_clb_5__4_ +- grid_clb_5__5_ +- grid_clb_5__6_ +- grid_clb_5__7_ +- grid_clb_5__8_ +- grid_clb_6__1_ +- grid_clb_6__2_ +- grid_clb_6__3_ +- grid_clb_6__4_ +- grid_clb_6__5_ +- grid_clb_6__6_ +- grid_clb_6__7_ +- grid_clb_6__8_ +- grid_clb_7__1_ +- grid_clb_7__2_ +- grid_clb_7__3_ +- grid_clb_7__4_ +- grid_clb_7__5_ +- grid_clb_7__6_ +- grid_clb_7__7_ +- grid_clb_7__8_ +- grid_clb_8__1_ +- grid_clb_8__2_ +- grid_clb_8__3_ +- grid_clb_8__4_ +- grid_clb_8__5_ +- grid_clb_8__6_ +- grid_clb_8__7_ +- grid_clb_8__8_ +grid_io_bottom_bottom: +- grid_io_bottom_bottom_1__0_ +- grid_io_bottom_bottom_2__0_ +- grid_io_bottom_bottom_3__0_ +- grid_io_bottom_bottom_4__0_ +- grid_io_bottom_bottom_5__0_ +- grid_io_bottom_bottom_6__0_ +- grid_io_bottom_bottom_7__0_ +- grid_io_bottom_bottom_8__0_ +grid_io_left_left: +- grid_io_left_left_0__1_ +- grid_io_left_left_0__2_ +- grid_io_left_left_0__3_ +- grid_io_left_left_0__4_ +- grid_io_left_left_0__5_ +- grid_io_left_left_0__6_ +- grid_io_left_left_0__7_ +- grid_io_left_left_0__8_ +grid_io_right_right: +- grid_io_right_right_9__1_ +- grid_io_right_right_9__2_ +- grid_io_right_right_9__3_ +- grid_io_right_right_9__4_ +- grid_io_right_right_9__5_ +- grid_io_right_right_9__6_ +- grid_io_right_right_9__7_ +- grid_io_right_right_9__8_ +grid_io_top_top: +- grid_io_top_top_1__9_ +- grid_io_top_top_2__9_ +- grid_io_top_top_3__9_ +- grid_io_top_top_4__9_ +- grid_io_top_top_5__9_ +- grid_io_top_top_6__9_ +- grid_io_top_top_7__9_ +- grid_io_top_top_8__9_ +sb_0__0_: +- sb_0__0_ +sb_0__1_: +- sb_0__1_ +- sb_0__2_ +- sb_0__3_ +- sb_0__4_ +- sb_0__5_ +- sb_0__6_ +- sb_0__7_ +sb_0__8_: +- sb_0__8_ +sb_1__0_: +- sb_1__0_ +- sb_2__0_ +- sb_3__0_ +- sb_4__0_ +- sb_5__0_ +- sb_6__0_ +- sb_7__0_ +sb_1__1_: +- sb_1__1_ +- sb_1__2_ +- sb_1__3_ +- sb_1__4_ +- sb_1__5_ +- sb_1__6_ +- sb_1__7_ +- sb_2__1_ +- sb_2__2_ +- sb_2__3_ +- sb_2__4_ +- sb_2__5_ +- sb_2__6_ +- sb_2__7_ +- sb_3__1_ +- sb_3__2_ +- sb_3__3_ +- sb_3__4_ +- sb_3__5_ +- sb_3__6_ +- sb_3__7_ +- sb_4__1_ +- sb_4__2_ +- sb_4__3_ +- sb_4__4_ +- sb_4__5_ +- sb_4__6_ +- sb_4__7_ +- sb_5__1_ +- sb_5__2_ +- sb_5__3_ +- sb_5__4_ +- sb_5__5_ +- sb_5__6_ +- sb_5__7_ +- sb_6__1_ +- sb_6__2_ +- sb_6__3_ +- sb_6__4_ +- sb_6__5_ +- sb_6__6_ +- sb_6__7_ +- sb_7__1_ +- sb_7__2_ +- sb_7__3_ +- sb_7__4_ +- sb_7__5_ +- sb_7__6_ +- sb_7__7_ +sb_1__8_: +- sb_1__8_ +- sb_2__8_ +- sb_3__8_ +- sb_4__8_ +- sb_5__8_ +- sb_6__8_ +- sb_7__8_ +sb_8__0_: +- sb_8__0_ +sb_8__1_: +- sb_8__1_ +- sb_8__2_ +- sb_8__3_ +- sb_8__4_ +- sb_8__5_ +- sb_8__6_ +- sb_8__7_ +sb_8__8_: +- sb_8__8_ diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/XML/fabric_independent_bitstream.xml b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/XML/fabric_independent_bitstream.xml new file mode 100644 index 0000000..aeda3a2 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/XML/fabric_independent_bitstream.xml @@ -0,0 +1,230712 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/openfpgashell.log b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/openfpgashell.log new file mode 100644 index 0000000..68bb7a9 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/openfpgashell.log @@ -0,0 +1,1322 @@ +--line removed-- openfpga -batch -f top_run.openfpga +Reading script file top_run.openfpga... + + ___ _____ ____ ____ _ + / _ \ _ __ ___ _ __ | ___| _ \ / ___| / \ + | | | | '_ \ / _ \ '_ \| |_ | |_) | | _ / _ \ + | |_| | |_) | __/ | | | _| | __/| |_| |/ ___ \ + \___/| .__/ \___|_| |_|_| |_| \____/_/ \_\ + |_| + + OpenFPGA: An Open-source FPGA IP Generator + Versatile Place and Route (VPR) + FPGA-Verilog + FPGA-SPICE + FPGA-SDC + FPGA-Bitstream + + This is a free software under the MIT License + + Copyright (c) 2018 LNIS - The University of Utah + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + + + +Command line to execute: vpr --line removed-- --skip_sync_clustering_and_routing_results on +VPR FPGA Placement and Routing. +Version: 8.1.0-dev+9e53e9a0a +Revision: v8.0.0-7093-g9e53e9a0a +--line removed-- +Compiler: GNU 8.4.0 on Linux-4.18.0-372.13.1.el8_6.x86_64 x86_64 +Build Info: release IPO VTR_ASSERT_LEVEL=2 + +University of Toronto +verilogtorouting.org +vtr-users@googlegroups.com +This is free open source code under MIT license. + +VPR was run with the following command-line: +vpr --line removed-- --skip_sync_clustering_and_routing_results on + + +Architecture file: --line removed-- +Circuit name: top + +# Loading Architecture Description +Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 3: Model 'frac_lut4' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 6: Model 'frac_lut4' output port 'lut2_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 7: Model 'carry_follower' input port 'cin' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 8: Model 'carry_follower' input port 'b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 9: Model 'carry_follower' input port 'a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 10: Model 'carry_follower' output port 'cout' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +--line removed-- + +Timing analysis: ON +Circuit netlist file: top.net +Circuit placement file: top.place +Circuit routing file: top.route +Circuit SDC file: top.sdc +Vpr floorplanning constraints file: not specified + +Packer: ENABLED +Placer: ENABLED +Router: ENABLED +Analysis: ENABLED + +VPR was run with the following options: + +NetlistOpts.abosrb_buffer_luts : false +NetlistOpts.sweep_dangling_primary_ios : true +NetlistOpts.sweep_dangling_nets : true +NetlistOpts.sweep_dangling_blocks : true +NetlistOpts.sweep_constant_primary_outputs: false +NetlistOpts.netlist_verbosity : 1 +NetlistOpts.const_gen_inference : COMB_SEQ + +PackerOpts.allow_unrelated_clustering: auto +PackerOpts.alpha_clustering: 0.750000 +PackerOpts.beta_clustering: 0.900000 +PackerOpts.cluster_seed_type: BLEND2 +PackerOpts.connection_driven: true +PackerOpts.global_clocks: true +PackerOpts.hill_climbing_flag: false +PackerOpts.inter_cluster_net_delay: 1.000000 +PackerOpts.timing_driven: true +PackerOpts.target_external_pin_util: auto + +PlacerOpts.place_freq: PLACE_ONCE +PlacerOpts.place_algorithm: CRITICALITY_TIMING_PLACE +PlacerOpts.pad_loc_type: FREE +PlacerOpts.constraints_file: No constraints file given +PlacerOpts.place_cost_exp: 1.000000 +PlacerOpts.place_chan_width: 60 +PlacerOpts.inner_loop_recompute_divider: 0 +PlacerOpts.recompute_crit_iter: 1 +PlacerOpts.timing_tradeoff: 0.500000 +PlacerOpts.td_place_exp_first: 1.000000 +PlacerOpts.td_place_exp_last: 8.000000 +PlacerOpts.delay_offset: 0.000000 +PlacerOpts.delay_ramp_delta_threshold: -1 +PlacerOpts.delay_ramp_slope: 0.000000 +PlacerOpts.tsu_rel_margin: 1.000000 +PlacerOpts.tsu_abs_margin: 0.000000 +PlacerOpts.post_place_timing_report_file: +PlacerOpts.allowed_tiles_for_delay_model: +PlacerOpts.delay_model_reducer: MIN +PlacerOpts.delay_model_type: DELTA +PlacerOpts.rlim_escape_fraction: 0.000000 +PlacerOpts.move_stats_file: +PlacerOpts.placement_saves_per_temperature: 0 +PlacerOpts.effort_scaling: CIRCUIT +PlacerOpts.place_delta_delay_matrix_calculation_method: ASTAR_ROUTE +PlaceOpts.seed: 0 +AnnealSched.type: AUTO_SCHED +AnnealSched.inner_num: 0.500000 + +RouterOpts.route_type: DETAILED +RouterOpts.flat_routing: false +RouterOpts.router_algorithm: TIMING_DRIVEN +RouterOpts.base_cost_type: DELAY_NORMALIZED_LENGTH +RouterOpts.fixed_channel_width: 60 +RouterOpts.check_route: FULL +RouterOpts.trim_empty_chan: false +RouterOpts.trim_obs_chan: false +RouterOpts.acc_fac: 1.000000 +RouterOpts.bb_factor: 3 +RouterOpts.bend_cost: 0.000000 +RouterOpts.first_iter_pres_fac: 0.000000 +RouterOpts.initial_pres_fac: 0.500000 +RouterOpts.pres_fac_mult: 1.300000 +RouterOpts.max_router_iterations: 50 +RouterOpts.min_incremental_reroute_fanout: 16 +RouterOpts.do_check_rr_graph: true +RouterOpts.verify_binary_search: false +RouterOpts.min_channel_width_hint: 0 +RouterOpts.read_rr_edge_metadata: false +RouterOpts.exit_after_first_routing_iteration: false +RouterOpts.astar_fac: 1.200000 +RouterOpts.router_profiler_astar_fac: 1.200000 +RouterOpts.criticality_exp: 1.000000 +RouterOpts.max_criticality: 0.990000 +RouterOpts.init_wirelength_abort_threshold: 0.850000 +RouterOpts.save_routing_per_iteration: false +RouterOpts.congested_routing_iteration_threshold_frac: 1.000000 +RouterOpts.high_fanout_threshold: 64 +RouterOpts.router_debug_net: -2 +RouterOpts.router_debug_sink_rr: -2 +RouterOpts.router_debug_iteration: -2 +RouterOpts.max_convergence_count: 1 +RouterOpts.reconvergence_cpd_threshold: 0.990000 +RouterOpts.update_lower_bound_delays: true +RouterOpts.first_iteration_timing_report_file: +RouterOpts.incr_reroute_delay_ripup: AUTO +RouterOpts.route_bb_update: DYNAMIC +RouterOpts.lookahead_type: MAP +RouterOpts.initial_timing: LOOKAHEAD +RouterOpts.router_heap: BINARY_HEAP +RouterOpts.routing_failure_predictor = SAFE +RouterOpts.routing_budgets_algorithm = DISABLE + +AnalysisOpts.gen_post_synthesis_netlist: false +AnalysisOpts.timing_report_npaths: 100 +AnalysisOpts.timing_report_skew: false +AnalysisOpts.echo_dot_timing_graph_node: -1 +AnalysisOpts.timing_report_detail: NETLIST +AnalysisOpts.post_synth_netlist_unconn_input_handling: UNCONNECTED +AnalysisOpts.post_synth_netlist_unconn_output_handling: UNCONNECTED + +# Building complex block graph +Warning 11: [LINE 607] false logically-equivalent pin clb[0].I0[1]. +Warning 12: [LINE 611] false logically-equivalent pin clb[0].I1[1]. +Warning 13: [LINE 615] false logically-equivalent pin clb[0].I2[1]. +Warning 14: [LINE 619] false logically-equivalent pin clb[0].I3[1]. +Warning 15: [LINE 623] false logically-equivalent pin clb[0].I4[1]. +Warning 16: [LINE 627] false logically-equivalent pin clb[0].I5[1]. +Warning 17: [LINE 631] false logically-equivalent pin clb[0].I6[1]. +Warning 18: [LINE 635] false logically-equivalent pin clb[0].I7[1]. +--line removed-- +Circuit file: top.blif +# Load circuit +--line removed-- +# Clean circuit +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 0 additional primitive pins as constant generators due to constant inputs +Swept input(s) : 0 +Swept output(s) : 0 (0 dangling, 0 constant) +Swept net(s) : 0 +Swept block(s) : 0 +Constant Pins Marked: 0 +--line removed-- +# Compress circuit +--line removed-- +# Verify circuit +--line removed-- +Circuit Statistics: + Blocks: 4 + .input : 2 + .output: 1 + 4-LUT : 1 + Nets : 3 + Avg Fanout: 1.0 + Max Fanout: 1.0 + Min Fanout: 1.0 + Netlist Clocks: 0 +# Build Timing Graph + Timing Graph Nodes: 6 + Timing Graph Edges: 5 + Timing Graph Levels: 4 +--line removed-- +Netlist contains 0 clocks +# Load Timing Constraints + +SDC file 'top.sdc' not found +Setting default timing constraints: + * constrain all primay inputs and primary outputs on a virtual external clock 'virtual_io_clock' + * optimize virtual clock to run as fast as possible +Timing constraints created 1 clocks + Constrained Clock 'virtual_io_clock' (Virtual Clock) + +--line removed-- +# Packing +Warning 19: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 20: Ambiguous block type specification at grid location (0,9). Existing block type 'io_top' at (0,9) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 21: Ambiguous block type specification at grid location (9,0). Existing block type 'io_bottom' at (9,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 22: Ambiguous block type specification at grid location (9,9). Existing block type 'io_top' at (9,9) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Begin packing 'top.blif'. + +After removing unused inputs... + total blocks: 4, total nets: 3, total inputs: 2, total outputs: 1 +Begin prepacking. +0 attraction groups were created during prepacking. +Finish prepacking. +Using inter-cluster delay: 2.344e-08 +Packing with pin utilization targets: io_top:1,1 io_right:1,1 io_bottom:1,1 io_left:1,1 clb:0.8,1 +Packing with high fanout thresholds: io_top:128 io_right:128 io_bottom:128 io_left:128 clb:32 +Starting Clustering - Clustering Progress: +------------------- -------------------------- --------- +Molecules processed Number of clusters created FPGA size +------------------- -------------------------- --------- +Warning 23: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 24: Ambiguous block type specification at grid location (0,9). Existing block type 'io_top' at (0,9) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 25: Ambiguous block type specification at grid location (9,0). Existing block type 'io_bottom' at (9,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 26: Ambiguous block type specification at grid location (9,9). Existing block type 'io_top' at (9,9) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. + +Logic Element (fle) detailed count: + Total number of Logic Elements used : 1 + LEs used for logic and registers : 0 + LEs used for logic only : 1 + LEs used for registers only : 0 + +Incr Slack updates 1 in 2.246e-06 sec +Full Max Req/Worst Slack updates 1 in 1.637e-06 sec +Incr Max Req/Worst Slack updates 0 in 0 sec +Incr Criticality updates 0 in 0 sec +Full Criticality updates 1 in 1.825e-06 sec +Warning 27: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 28: Ambiguous block type specification at grid location (0,9). Existing block type 'io_top' at (0,9) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 29: Ambiguous block type specification at grid location (9,0). Existing block type 'io_bottom' at (9,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 30: Ambiguous block type specification at grid location (9,9). Existing block type 'io_top' at (9,9) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +FPGA sized to 10 x 10 (FPGA88) +Device Utilization: 0.02 (target 1.00) + Block Utilization: 0.02 Type: io + Block Utilization: 0.02 Type: clb + +Start the iterative improvement process +the iterative improvement process is done +Final Clustering Statistics: +---------- -------- ------------------------------------ -------------------------- +Block Type # Blocks Avg. # of input clocks and pins used Avg. # of output pins used +---------- -------- ------------------------------------ -------------------------- + EMPTY 0 0 0 + io 3 0.333333 0.666667 + clb 1 2 1 +Absorbed logical nets 0 out of 3 nets, 3 nets not absorbed. + +Netlist conversion complete. + +--line removed-- +# Load packing +Begin loading packed FPGA netlist file. +Netlist generated from file 'top.net'. +Detected 0 constant generators (to see names run with higher pack verbosity) +--line removed-- +Warning 31: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity). +--line removed-- +Warning 32: Netlist contains 0 global net to non-global architecture pin connections +Cluster level netlist and block usage statistics +Netlist num_nets: 3 +Netlist num_blocks: 4 +Netlist EMPTY blocks: 0. +Netlist io blocks: 3. +Netlist clb blocks: 1. +Netlist inputs pins: 2 +Netlist output pins: 1 + +Pb types usage... + io : 3 + inpad : 2 + outpad : 1 + clb : 1 + fle : 1 + lut3inter : 1 + ble3 : 1 + lut3 : 1 + lut : 1 + +# Create Device +## Build Device Grid +Warning 33: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 34: Ambiguous block type specification at grid location (0,9). Existing block type 'io_top' at (0,9) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 35: Ambiguous block type specification at grid location (9,0). Existing block type 'io_bottom' at (9,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 36: Ambiguous block type specification at grid location (9,9). Existing block type 'io_top' at (9,9) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +FPGA sized to 10 x 10: 100 grid tiles (FPGA88) + +Resource usage... + Netlist + 3 blocks of type: io + Architecture + 32 blocks of type: io_top + 32 blocks of type: io_right + 32 blocks of type: io_bottom + 32 blocks of type: io_left + Netlist + 1 blocks of type: clb + Architecture + 64 blocks of type: clb + +Device Utilization: 0.02 (target 1.00) + Physical Tile io_top: + Block Utilization: 0.09 Logical Block: io + Physical Tile io_right: + Block Utilization: 0.09 Logical Block: io + Physical Tile io_bottom: + Block Utilization: 0.09 Logical Block: io + Physical Tile io_left: + Block Utilization: 0.09 Logical Block: io + Physical Tile clb: + Block Utilization: 0.02 Logical Block: clb + +--line removed-- +Warning 37: Tileable routing resource graph does not support clock modeling yet! Related options are ignored... +## Build tileable routing resource graph +X-direction routing channel width is 60 +Y-direction routing channel width is 60 +Warning 38: Sized nonsensical R=0 transistor to minimum width +Warning 39: Sized nonsensical R=0 transistor to minimum width +Warning 40: Sized nonsensical R=0 transistor to minimum width +Warning 41: Sized nonsensical R=0 transistor to minimum width +Warning 42: Node: 7440 with RR_type: CHANX at Location:CHANX:7440 L4 length:1 (1,1)->(1,1), had no out-going switches +Warning 43: Node: 7654 with RR_type: CHANX at Location:CHANX:7654 L4 length:1 (1,2)->(1,2), had no out-going switches +Warning 44: Node: 7868 with RR_type: CHANX at Location:CHANX:7868 L4 length:1 (1,3)->(1,3), had no out-going switches +Warning 45: Node: 8082 with RR_type: CHANX at Location:CHANX:8082 L4 length:1 (1,4)->(1,4), had no out-going switches +Warning 46: Node: 8296 with RR_type: CHANX at Location:CHANX:8296 L4 length:1 (1,5)->(1,5), had no out-going switches +Warning 47: Node: 8510 with RR_type: CHANX at Location:CHANX:8510 L4 length:1 (1,6)->(1,6), had no out-going switches +Warning 48: Node: 8724 with RR_type: CHANX at Location:CHANX:8724 L4 length:1 (1,7)->(1,7), had no out-going switches +Warning 49: in check_rr_graph: fringe node 7440 CHANX at (1,1) has no fanin. + This is possible on a fringe node based on low Fc_out, N, and certain lengths. +--line removed-- + RR Graph Nodes: 11020 + RR Graph Edges: 55564 +--line removed-- + +# Computing router lookahead map +## Computing wire lookahead +--line removed-- +## Computing src/opin lookahead +--line removed-- +--line removed-- +# Computing placement delta delay look-up +RR graph channel widths unchanged, skipping RR graph rebuild +## Computing delta delays +--line removed-- +--line removed-- +Using simple RL 'Softmax agent' for choosing move types +# Placement +## Initial Placement +Initial placement iteration 0 has finished successfully +--line removed-- + +There are 3 point to point connections in this circuit. + + +BB estimate of min-dist (placement) wire length: 19 + +Completed placement consistency check successfully. +Initial placement cost: 1 bb_cost: 0.316667 td_cost: 1.566e-08 +Initial placement estimated Critical Path Delay (CPD): 12.54 ns +Initial placement estimated setup Total Negative Slack (sTNS): -12.54 ns +Initial placement estimated setup Worst Negative Slack (sWNS): -12.54 ns + +Initial placement estimated setup slack histogram: +[ -1.3e-08: -1.3e-08) 1 (100.0%) |************************************************** +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +Placement contains 0 placement macros involving 0 blocks (average macro size -nan) + +Moves per temperature: 3 +Warning 50: Starting t: 0 of 3 configurations accepted. + +---- ------ ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------ +Tnum Time T Av Cost Av BB Cost Av TD Cost CPD sTNS sWNS Ac Rate Std Dev R lim Crit Exp Tot Moves Alpha + (sec) (ns) (ns) (ns) +---- ------ ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------ + 1 0.0 0.0e+00 0.947 0.28 1.566e-08 12.540 -12.5 -12.540 0.667 0.0000 9.0 1.00 3 0.200 + 2 0.0 0.0e+00 0.971 0.27 1.566e-08 12.540 -12.5 -12.540 0.333 0.0000 9.0 1.00 6 0.950 +--line removed-- +post-quench CPD = 12.54 (ns) + +BB estimate of min-dist (placement) wire length: 16 + +Completed placement consistency check successfully. + +Swaps called: 9 + +Aborted Move Reasons: + No moves aborted + +Placement estimated critical path delay (least slack): 12.54 ns, Fmax: 79.7448 MHz +Placement estimated setup Worst Negative Slack (sWNS): -12.54 ns +Placement estimated setup Total Negative Slack (sTNS): -12.54 ns + +Placement estimated setup slack histogram: +[ -1.3e-08: -1.3e-08) 1 (100.0%) |************************************************** +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | +[ -1.3e-08: -1.3e-08) 0 ( 0.0%) | + +Placement estimated geomean non-virtual intra-domain period: nan ns (nan MHz) +Placement estimated fanout-weighted geomean non-virtual intra-domain period: nan ns (nan MHz) + +Placement cost: 0.970588, bb_cost: 0.266667, td_cost: 1.566e-08, + +Placement resource usage: + io implemented as io_top : 1 + io implemented as io_bottom: 2 + clb implemented as clb : 1 + +Placement number of temperatures: 2 +Placement total # of swap attempts: 9 + Swaps accepted: 3 (33.3 %) + Swaps rejected: 6 (66.7 %) + Swaps aborted : 0 ( 0.0 %) + + +Percentage of different move types: + Uniform move: 22.22 % (acc=0.00 %, rej=100.00 %, aborted=0.00 %) + W. Centroid move: 44.44 % (acc=50.00 %, rej=50.00 %, aborted=0.00 %) + Centroid move: 11.11 % (acc=0.00 %, rej=100.00 %, aborted=0.00 %) + Crit. Uniform move: 22.22 % (acc=50.00 %, rej=50.00 %, aborted=0.00 %) + +--line removed-- +--line removed-- +update_td_costs: connections 0 nets 0 sum_nets 0 total 0 +--line removed-- + +# Routing +RR graph channel widths unchanged, skipping RR graph rebuild +Confirming router algorithm: TIMING_DRIVEN. +## Initializing router criticalities +Initial Net Connection Criticality Histogram: +[ 0: 0.1) 0 ( 0.0%) | +[ 0.1: 0.2) 0 ( 0.0%) | +[ 0.2: 0.3) 0 ( 0.0%) | +[ 0.3: 0.4) 0 ( 0.0%) | +[ 0.4: 0.5) 0 ( 0.0%) | +[ 0.5: 0.6) 0 ( 0.0%) | +[ 0.6: 0.7) 0 ( 0.0%) | +[ 0.7: 0.8) 0 ( 0.0%) | +[ 0.8: 0.9) 0 ( 0.0%) | +[ 0.9: 1) 3 (100.0%) |************************************************* +--line removed-- +---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- -------- +Iter Time pres BBs Heap Re-Rtd Re-Rtd Overused RR Nodes Wirelength CPD sTNS sWNS hTNS hWNS Est Succ + (sec) fac Updt push Nets Conns (ns) (ns) (ns) (ns) (ns) Iter +---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- -------- + 1 0.0 0.0 0 226 3 3 0 ( 0.000%) 27 ( 0.3%) 13.980 -13.98 -13.980 0.000 0.000 N/A +Incr Slack updates 4 in 1.4576e-05 sec +Full Max Req/Worst Slack updates 1 in 1.984e-06 sec +Incr Max Req/Worst Slack updates 3 in 8.537e-06 sec +Incr Criticality updates 3 in 7.854e-06 sec +Full Criticality updates 1 in 1.766e-06 sec +Restoring best routing +Critical path: 13.98 ns +Successfully routed after 1 routing iterations. +Final Net Connection Criticality Histogram: +[ 0: 0.1) 0 ( 0.0%) | +[ 0.1: 0.2) 0 ( 0.0%) | +[ 0.2: 0.3) 0 ( 0.0%) | +[ 0.3: 0.4) 0 ( 0.0%) | +[ 0.4: 0.5) 0 ( 0.0%) | +[ 0.5: 0.6) 0 ( 0.0%) | +[ 0.6: 0.7) 0 ( 0.0%) | +[ 0.7: 0.8) 0 ( 0.0%) | +[ 0.8: 0.9) 1 ( 33.3%) |************************* +[ 0.9: 1) 2 ( 66.7%) |************************************************* +Router Stats: total_nets_routed: 3 total_connections_routed: 3 total_heap_pushes: 226 total_heap_pops: 67 +--line removed-- + +Checking to ensure routing is legal... +# Checking to ensure non-configurable edges are legal +--line removed-- +Completed routing consistency check successfully. + +Serial number (magic cookie) for the routing is: -17767 +Circuit successfully routed with a channel width factor of 60. +Warning 51: Sychronization between packing and routing results is not applied due to users select to skip it + + +Average number of bends per net: 1.00000 Maximum # of bends: 1 + +Number of global nets: 0 +Number of routed nets (nonglobal): 3 +Wire length results (in units of 1 clb segments)... + Total wirelength: 27, average net length: 9.00000 + Maximum net length: 10 + +Wire length results in terms of physical segments... + Total wiring segments used: 8, average wire segments per net: 2.66667 + Maximum segments used by a net: 3 + Total local nets with reserved CLB opins: 0 + +Routing channel utilization histogram: +[ 1: inf) 0 ( 0.0%) | +[ 0.9: 1) 0 ( 0.0%) | +[ 0.8: 0.9) 0 ( 0.0%) | +[ 0.7: 0.8) 0 ( 0.0%) | +[ 0.5: 0.6) 0 ( 0.0%) | +[ 0.4: 0.5) 0 ( 0.0%) | +[ 0.3: 0.4) 0 ( 0.0%) | +[ 0.2: 0.3) 0 ( 0.0%) | +[ 0.1: 0.2) 0 ( 0.0%) | +[ 0: 0.1) 162 (100.0%) |*********************************************** +Maximum routing channel utilization: 0.033 at (5,0) + +X - Directed channels: j max occ ave occ capacity + ---- ------- ------- -------- + 0 2 0.500 60 + 1 0 0.000 60 + 2 0 0.000 60 + 3 0 0.000 60 + 4 0 0.000 60 + 5 0 0.000 60 + 6 0 0.000 60 + 7 0 0.000 60 + 8 1 0.400 60 +Y - Directed channels: i max occ ave occ capacity + ---- ------- ------- -------- + 0 0 0.000 60 + 1 0 0.000 60 + 2 0 0.000 60 + 3 0 0.000 60 + 4 0 0.000 60 + 5 4 1.800 60 + 6 0 0.000 60 + 7 0 0.000 60 + 8 0 0.000 60 + +Total tracks in x-direction: 540, in y-direction: 540 + +Logic area (in minimum width transistor areas, excludes I/Os and empty grid tiles)... + Total logic block area (Warning, need to add pitch of routing to blocks with height > 3): 3.44922e+06 + Total used logic block area: 53894 + +Routing area (in minimum width transistor areas)... + Total routing area: 373865., per logic tile: 3738.65 + +Total Number of Wiring Segments by Direction: direction length number + --------- ------ ------- + X 1 432 + Y 1 432 + X 2 306 + Y 2 306 + X 4 1188 + Y 4 1188 + +X - Directed Wiring Segment usage by length: length utilization + ------ ----------- + 1 0 + 2 0.00327 + 4 0.00168 + +Y - Directed Wiring Segment usage by length: length utilization + ------ ----------- + 1 0 + 2 0.00327 + 4 0.00337 + +Segment usage by type (index): name type utilization + ---- ---- ----------- + L1 0 0 + L2 1 0.00654 + L4 2 0.00505 + +Final hold Worst Negative Slack (hWNS): 0 ns +Final hold Total Negative Slack (hTNS): 0 ns + +Final hold slack histogram: +[ 1.1e-08: 1.1e-08) 1 (100.0%) |************************************************** +[ 1.1e-08: 1.1e-08) 0 ( 0.0%) | +[ 1.1e-08: 1.1e-08) 0 ( 0.0%) | +[ 1.1e-08: 1.1e-08) 0 ( 0.0%) | +[ 1.1e-08: 1.1e-08) 0 ( 0.0%) | +[ 1.1e-08: 1.1e-08) 0 ( 0.0%) | +[ 1.1e-08: 1.1e-08) 0 ( 0.0%) | +[ 1.1e-08: 1.1e-08) 0 ( 0.0%) | +[ 1.1e-08: 1.1e-08) 0 ( 0.0%) | +[ 1.1e-08: 1.1e-08) 0 ( 0.0%) | + +Final critical path delay (least slack): 13.98 ns, Fmax: 71.5308 MHz +Final setup Worst Negative Slack (sWNS): -13.98 ns +Final setup Total Negative Slack (sTNS): -13.98 ns + +Final setup slack histogram: +[ -1.4e-08: -1.4e-08) 1 (100.0%) |************************************************** +[ -1.4e-08: -1.4e-08) 0 ( 0.0%) | +[ -1.4e-08: -1.4e-08) 0 ( 0.0%) | +[ -1.4e-08: -1.4e-08) 0 ( 0.0%) | +[ -1.4e-08: -1.4e-08) 0 ( 0.0%) | +[ -1.4e-08: -1.4e-08) 0 ( 0.0%) | +[ -1.4e-08: -1.4e-08) 0 ( 0.0%) | +[ -1.4e-08: -1.4e-08) 0 ( 0.0%) | +[ -1.4e-08: -1.4e-08) 0 ( 0.0%) | +[ -1.4e-08: -1.4e-08) 0 ( 0.0%) | + +Final geomean non-virtual intra-domain period: nan ns (nan MHz) +Final fanout-weighted geomean non-virtual intra-domain period: nan ns (nan MHz) + +Incr Slack updates 1 in 1.9716e-05 sec +Full Max Req/Worst Slack updates 1 in 3.349e-06 sec +Incr Max Req/Worst Slack updates 0 in 0 sec +Incr Criticality updates 0 in 0 sec +Full Criticality updates 1 in 3.35e-06 sec +--line removed-- +VPR suceeded +--line removed-- + +Command line to execute: read_openfpga_arch -f --line removed-- + +Confirm selected options when call command 'read_openfpga_arch': +--file, -f: --line removed-- +Reading XML architecture '--line removed--'... +Read OpenFPGA architecture +Warning 52: Automatically set circuit model 'frac_lut4' to be default in its type. +Warning 53: Automatically set circuit model 'sky130_fd_sc_hd__sdfrtp_1' to be default in its type. +Warning 54: Automatically set circuit model 'sky130_fd_sc_hd__mux2_1_wrapper' to be default in its type. +Warning 55: Automatically set circuit model 'sky130_fd_sc_hd__dfrtp_1' to be default in its type. +Use the default configurable memory model 'sky130_fd_sc_hd__dfrtp_1' for circuit model 'mux_tree' port 'sram') +Use the default configurable memory model 'sky130_fd_sc_hd__dfrtp_1' for circuit model 'mux_tree_tapbuf' port 'sram') +Use the default configurable memory model 'sky130_fd_sc_hd__dfrtp_1' for circuit model 'frac_lut4' port 'sram') +--line removed-- +Check circuit library +Checking circuit library passed. +--line removed-- +Found 0 errors when checking configurable memory circuit models! +Found 0 errors when checking tile annotation! + +Command line to execute: read_openfpga_simulation_setting -f --line removed-- + +Confirm selected options when call command 'read_openfpga_simulation_setting': +--file, -f: --line removed-- +Reading XML simulation setting '--line removed--'... +Read OpenFPGA simulation settings +--line removed-- + +Command line to execute: link_openfpga_arch --activity_file top_ace_out.act --sort_gsb_chan_node_in_edges + +Confirm selected options when call command 'link_openfpga_arch': +--activity_file: top_ace_out.act +--sort_gsb_chan_node_in_edges: on +--verbose: off +Link OpenFPGA architecture to VPR architecture +# Build fast look-up for physical tile pins +--line removed-- + +Building annotation for physical modes in pb_type...Done +Check physical mode annotation for pb_types passed. + +Building annotation about physical types for pb_type interconnection...Done + +Building annotation between operating and physical pb_types...Done +Check physical pb_type annotation for pb_types passed. + +Building annotation between physical pb_types and circuit models...Done +Check physical pb_type annotation for circuit model passed. + +Building annotation between physical pb_types and mode selection bits...Done +Check pb_type annotation for mode selection bits passed. +Assigning unique indices for primitive pb_graph nodes...Done +Binding operating pb_graph nodes/pins to physical pb_graph nodes/pins...Done +Check pb_graph annotation for physical nodes and pins passed. +Binded 4 routing resource graph switches to circuit models +Binded 3 routing segments to circuit models +Binded 3 direct connections to circuit models +# Annotating rr_node with routed nets +--line removed-- +Loaded node-to-net mapping +Annotating previous nodes for rr_node...Done with 17 nodes mapping +Built 55564 incoming edges for routing resource graph +# Build General Switch Block(GSB) annotation on top of routing resource graph +[1%] Backannotated GSB[0][0] +[2%] Backannotated GSB[0][1] +[3%] Backannotated GSB[0][2] +[4%] Backannotated GSB[0][3] +[6%] Backannotated GSB[0][4] +[7%] Backannotated GSB[0][5] +[8%] Backannotated GSB[0][6] +[9%] Backannotated GSB[0][7] +[11%] Backannotated GSB[0][8] +[12%] Backannotated GSB[1][0] +[13%] Backannotated GSB[1][1] +[14%] Backannotated GSB[1][2] +[16%] Backannotated GSB[1][3] +[17%] Backannotated GSB[1][4] +[18%] Backannotated GSB[1][5] +[19%] Backannotated GSB[1][6] +[20%] Backannotated GSB[1][7] +[22%] Backannotated GSB[1][8] +[23%] Backannotated GSB[2][0] +[24%] Backannotated GSB[2][1] +[25%] Backannotated GSB[2][2] +[27%] Backannotated GSB[2][3] +[28%] Backannotated GSB[2][4] +[29%] Backannotated GSB[2][5] +[30%] Backannotated GSB[2][6] +[32%] Backannotated GSB[2][7] +[33%] Backannotated GSB[2][8] +[34%] Backannotated GSB[3][0] +[35%] Backannotated GSB[3][1] +[37%] Backannotated GSB[3][2] +[38%] Backannotated GSB[3][3] +[39%] Backannotated GSB[3][4] +[40%] Backannotated GSB[3][5] +[41%] Backannotated GSB[3][6] +[43%] Backannotated GSB[3][7] +[44%] Backannotated GSB[3][8] +[45%] Backannotated GSB[4][0] +[46%] Backannotated GSB[4][1] +[48%] Backannotated GSB[4][2] +[49%] Backannotated GSB[4][3] +[50%] Backannotated GSB[4][4] +[51%] Backannotated GSB[4][5] +[53%] Backannotated GSB[4][6] +[54%] Backannotated GSB[4][7] +[55%] Backannotated GSB[4][8] +[56%] Backannotated GSB[5][0] +[58%] Backannotated GSB[5][1] +[59%] Backannotated GSB[5][2] +[60%] Backannotated GSB[5][3] +[61%] Backannotated GSB[5][4] +[62%] Backannotated GSB[5][5] +[64%] Backannotated GSB[5][6] +[65%] Backannotated GSB[5][7] +[66%] Backannotated GSB[5][8] +[67%] Backannotated GSB[6][0] +[69%] Backannotated GSB[6][1] +[70%] Backannotated GSB[6][2] +[71%] Backannotated GSB[6][3] +[72%] Backannotated GSB[6][4] +[74%] Backannotated GSB[6][5] +[75%] Backannotated GSB[6][6] +[76%] Backannotated GSB[6][7] +[77%] Backannotated GSB[6][8] +[79%] Backannotated GSB[7][0] +[80%] Backannotated GSB[7][1] +[81%] Backannotated GSB[7][2] +[82%] Backannotated GSB[7][3] +[83%] Backannotated GSB[7][4] +[85%] Backannotated GSB[7][5] +[86%] Backannotated GSB[7][6] +[87%] Backannotated GSB[7][7] +[88%] Backannotated GSB[7][8] +[90%] Backannotated GSB[8][0] +[91%] Backannotated GSB[8][1] +[92%] Backannotated GSB[8][2] +[93%] Backannotated GSB[8][3] +[95%] Backannotated GSB[8][4] +[96%] Backannotated GSB[8][5] +[97%] Backannotated GSB[8][6] +[98%] Backannotated GSB[8][7] +[100%] Backannotated GSB[8][8] +Backannotated 81 General Switch Blocks (GSBs). +--line removed-- +# Sort incoming edges for each routing track output node of General Switch Block(GSB) +[1%] Sorted incoming edges for each routing track output node of GSB[0][0] +[2%] Sorted incoming edges for each routing track output node of GSB[0][1] +[3%] Sorted incoming edges for each routing track output node of GSB[0][2] +[4%] Sorted incoming edges for each routing track output node of GSB[0][3] +[6%] Sorted incoming edges for each routing track output node of GSB[0][4] +[7%] Sorted incoming edges for each routing track output node of GSB[0][5] +[8%] Sorted incoming edges for each routing track output node of GSB[0][6] +[9%] Sorted incoming edges for each routing track output node of GSB[0][7] +[11%] Sorted incoming edges for each routing track output node of GSB[0][8] +[12%] Sorted incoming edges for each routing track output node of GSB[1][0] +[13%] Sorted incoming edges for each routing track output node of GSB[1][1] +[14%] Sorted incoming edges for each routing track output node of GSB[1][2] +[16%] Sorted incoming edges for each routing track output node of GSB[1][3] +[17%] Sorted incoming edges for each routing track output node of GSB[1][4] +[18%] Sorted incoming edges for each routing track output node of GSB[1][5] +[19%] Sorted incoming edges for each routing track output node of GSB[1][6] +[20%] Sorted incoming edges for each routing track output node of GSB[1][7] +[22%] Sorted incoming edges for each routing track output node of GSB[1][8] +[23%] Sorted incoming edges for each routing track output node of GSB[2][0] +[24%] Sorted incoming edges for each routing track output node of GSB[2][1] +[25%] Sorted incoming edges for each routing track output node of GSB[2][2] +[27%] Sorted incoming edges for each routing track output node of GSB[2][3] +[28%] Sorted incoming edges for each routing track output node of GSB[2][4] +[29%] Sorted incoming edges for each routing track output node of GSB[2][5] +[30%] Sorted incoming edges for each routing track output node of GSB[2][6] +[32%] Sorted incoming edges for each routing track output node of GSB[2][7] +[33%] Sorted incoming edges for each routing track output node of GSB[2][8] +[34%] Sorted incoming edges for each routing track output node of GSB[3][0] +[35%] Sorted incoming edges for each routing track output node of GSB[3][1] +[37%] Sorted incoming edges for each routing track output node of GSB[3][2] +[38%] Sorted incoming edges for each routing track output node of GSB[3][3] +[39%] Sorted incoming edges for each routing track output node of GSB[3][4] +[40%] Sorted incoming edges for each routing track output node of GSB[3][5] +[41%] Sorted incoming edges for each routing track output node of GSB[3][6] +[43%] Sorted incoming edges for each routing track output node of GSB[3][7] +[44%] Sorted incoming edges for each routing track output node of GSB[3][8] +[45%] Sorted incoming edges for each routing track output node of GSB[4][0] +[46%] Sorted incoming edges for each routing track output node of GSB[4][1] +[48%] Sorted incoming edges for each routing track output node of GSB[4][2] +[49%] Sorted incoming edges for each routing track output node of GSB[4][3] +[50%] Sorted incoming edges for each routing track output node of GSB[4][4] +[51%] Sorted incoming edges for each routing track output node of GSB[4][5] +[53%] Sorted incoming edges for each routing track output node of GSB[4][6] +[54%] Sorted incoming edges for each routing track output node of GSB[4][7] +[55%] Sorted incoming edges for each routing track output node of GSB[4][8] +[56%] Sorted incoming edges for each routing track output node of GSB[5][0] +[58%] Sorted incoming edges for each routing track output node of GSB[5][1] +[59%] Sorted incoming edges for each routing track output node of GSB[5][2] +[60%] Sorted incoming edges for each routing track output node of GSB[5][3] +[61%] Sorted incoming edges for each routing track output node of GSB[5][4] +[62%] Sorted incoming edges for each routing track output node of GSB[5][5] +[64%] Sorted incoming edges for each routing track output node of GSB[5][6] +[65%] Sorted incoming edges for each routing track output node of GSB[5][7] +[66%] Sorted incoming edges for each routing track output node of GSB[5][8] +[67%] Sorted incoming edges for each routing track output node of GSB[6][0] +[69%] Sorted incoming edges for each routing track output node of GSB[6][1] +[70%] Sorted incoming edges for each routing track output node of GSB[6][2] +[71%] Sorted incoming edges for each routing track output node of GSB[6][3] +[72%] Sorted incoming edges for each routing track output node of GSB[6][4] +[74%] Sorted incoming edges for each routing track output node of GSB[6][5] +[75%] Sorted incoming edges for each routing track output node of GSB[6][6] +[76%] Sorted incoming edges for each routing track output node of GSB[6][7] +[77%] Sorted incoming edges for each routing track output node of GSB[6][8] +[79%] Sorted incoming edges for each routing track output node of GSB[7][0] +[80%] Sorted incoming edges for each routing track output node of GSB[7][1] +[81%] Sorted incoming edges for each routing track output node of GSB[7][2] +[82%] Sorted incoming edges for each routing track output node of GSB[7][3] +[83%] Sorted incoming edges for each routing track output node of GSB[7][4] +[85%] Sorted incoming edges for each routing track output node of GSB[7][5] +[86%] Sorted incoming edges for each routing track output node of GSB[7][6] +[87%] Sorted incoming edges for each routing track output node of GSB[7][7] +[88%] Sorted incoming edges for each routing track output node of GSB[7][8] +[90%] Sorted incoming edges for each routing track output node of GSB[8][0] +[91%] Sorted incoming edges for each routing track output node of GSB[8][1] +[92%] Sorted incoming edges for each routing track output node of GSB[8][2] +[93%] Sorted incoming edges for each routing track output node of GSB[8][3] +[95%] Sorted incoming edges for each routing track output node of GSB[8][4] +[96%] Sorted incoming edges for each routing track output node of GSB[8][5] +[97%] Sorted incoming edges for each routing track output node of GSB[8][6] +[98%] Sorted incoming edges for each routing track output node of GSB[8][7] +[100%] Sorted incoming edges for each routing track output node of GSB[8][8] +Sorted incoming edges for each routing track output node of 81 General Switch Blocks (GSBs). +--line removed-- +# Sort incoming edges for each input pin node of General Switch Block(GSB) +[1%] Sorted incoming edges for each input pin node of GSB[0][0] +[2%] Sorted incoming edges for each input pin node of GSB[0][1] +[3%] Sorted incoming edges for each input pin node of GSB[0][2] +[4%] Sorted incoming edges for each input pin node of GSB[0][3] +[6%] Sorted incoming edges for each input pin node of GSB[0][4] +[7%] Sorted incoming edges for each input pin node of GSB[0][5] +[8%] Sorted incoming edges for each input pin node of GSB[0][6] +[9%] Sorted incoming edges for each input pin node of GSB[0][7] +[11%] Sorted incoming edges for each input pin node of GSB[0][8] +[12%] Sorted incoming edges for each input pin node of GSB[1][0] +[13%] Sorted incoming edges for each input pin node of GSB[1][1] +[14%] Sorted incoming edges for each input pin node of GSB[1][2] +[16%] Sorted incoming edges for each input pin node of GSB[1][3] +[17%] Sorted incoming edges for each input pin node of GSB[1][4] +[18%] Sorted incoming edges for each input pin node of GSB[1][5] +[19%] Sorted incoming edges for each input pin node of GSB[1][6] +[20%] Sorted incoming edges for each input pin node of GSB[1][7] +[22%] Sorted incoming edges for each input pin node of GSB[1][8] +[23%] Sorted incoming edges for each input pin node of GSB[2][0] +[24%] Sorted incoming edges for each input pin node of GSB[2][1] +[25%] Sorted incoming edges for each input pin node of GSB[2][2] +[27%] Sorted incoming edges for each input pin node of GSB[2][3] +[28%] Sorted incoming edges for each input pin node of GSB[2][4] +[29%] Sorted incoming edges for each input pin node of GSB[2][5] +[30%] Sorted incoming edges for each input pin node of GSB[2][6] +[32%] Sorted incoming edges for each input pin node of GSB[2][7] +[33%] Sorted incoming edges for each input pin node of GSB[2][8] +[34%] Sorted incoming edges for each input pin node of GSB[3][0] +[35%] Sorted incoming edges for each input pin node of GSB[3][1] +[37%] Sorted incoming edges for each input pin node of GSB[3][2] +[38%] Sorted incoming edges for each input pin node of GSB[3][3] +[39%] Sorted incoming edges for each input pin node of GSB[3][4] +[40%] Sorted incoming edges for each input pin node of GSB[3][5] +[41%] Sorted incoming edges for each input pin node of GSB[3][6] +[43%] Sorted incoming edges for each input pin node of GSB[3][7] +[44%] Sorted incoming edges for each input pin node of GSB[3][8] +[45%] Sorted incoming edges for each input pin node of GSB[4][0] +[46%] Sorted incoming edges for each input pin node of GSB[4][1] +[48%] Sorted incoming edges for each input pin node of GSB[4][2] +[49%] Sorted incoming edges for each input pin node of GSB[4][3] +[50%] Sorted incoming edges for each input pin node of GSB[4][4] +[51%] Sorted incoming edges for each input pin node of GSB[4][5] +[53%] Sorted incoming edges for each input pin node of GSB[4][6] +[54%] Sorted incoming edges for each input pin node of GSB[4][7] +[55%] Sorted incoming edges for each input pin node of GSB[4][8] +[56%] Sorted incoming edges for each input pin node of GSB[5][0] +[58%] Sorted incoming edges for each input pin node of GSB[5][1] +[59%] Sorted incoming edges for each input pin node of GSB[5][2] +[60%] Sorted incoming edges for each input pin node of GSB[5][3] +[61%] Sorted incoming edges for each input pin node of GSB[5][4] +[62%] Sorted incoming edges for each input pin node of GSB[5][5] +[64%] Sorted incoming edges for each input pin node of GSB[5][6] +[65%] Sorted incoming edges for each input pin node of GSB[5][7] +[66%] Sorted incoming edges for each input pin node of GSB[5][8] +[67%] Sorted incoming edges for each input pin node of GSB[6][0] +[69%] Sorted incoming edges for each input pin node of GSB[6][1] +[70%] Sorted incoming edges for each input pin node of GSB[6][2] +[71%] Sorted incoming edges for each input pin node of GSB[6][3] +[72%] Sorted incoming edges for each input pin node of GSB[6][4] +[74%] Sorted incoming edges for each input pin node of GSB[6][5] +[75%] Sorted incoming edges for each input pin node of GSB[6][6] +[76%] Sorted incoming edges for each input pin node of GSB[6][7] +[77%] Sorted incoming edges for each input pin node of GSB[6][8] +[79%] Sorted incoming edges for each input pin node of GSB[7][0] +[80%] Sorted incoming edges for each input pin node of GSB[7][1] +[81%] Sorted incoming edges for each input pin node of GSB[7][2] +[82%] Sorted incoming edges for each input pin node of GSB[7][3] +[83%] Sorted incoming edges for each input pin node of GSB[7][4] +[85%] Sorted incoming edges for each input pin node of GSB[7][5] +[86%] Sorted incoming edges for each input pin node of GSB[7][6] +[87%] Sorted incoming edges for each input pin node of GSB[7][7] +[88%] Sorted incoming edges for each input pin node of GSB[7][8] +[90%] Sorted incoming edges for each input pin node of GSB[8][0] +[91%] Sorted incoming edges for each input pin node of GSB[8][1] +[92%] Sorted incoming edges for each input pin node of GSB[8][2] +[93%] Sorted incoming edges for each input pin node of GSB[8][3] +[95%] Sorted incoming edges for each input pin node of GSB[8][4] +[96%] Sorted incoming edges for each input pin node of GSB[8][5] +[97%] Sorted incoming edges for each input pin node of GSB[8][6] +[98%] Sorted incoming edges for each input pin node of GSB[8][7] +[100%] Sorted incoming edges for each input pin node of GSB[8][8] +Sorted incoming edges for each input pin node of 81 General Switch Blocks (GSBs). +--line removed-- +# Build a library of physical multiplexers +Built a multiplexer library of 13 physical multiplexers. +Maximum multiplexer size is 16. +--line removed-- +# Build the annotation about direct connection between tiles +Built 175 tile-to-tile direct connections +--line removed-- +Building annotation for post-routing and clustering synchornization results...Done +Building annotation for mapped blocks on grid locations...Done +User specified the operating clock frequency to use VPR results +Use VPR critical path delay 1.6776e-17 [ns] with a 20 [%] slack in OpenFPGA. +Incr Slack updates 1 in 6.449e-06 sec +Full Max Req/Worst Slack updates 1 in 3.564e-06 sec +Incr Max Req/Worst Slack updates 0 in 0 sec +Incr Criticality updates 0 in 0 sec +Full Criticality updates 1 in 4.624e-06 sec +Will apply operating clock frequency 59.609 [MHz] to simulations +User specified the number of operating clock cycles to be inferred from signal activities +Average net density: 0.42 +Median net density: 0.00 +Average net density after weighting: 0.42 +Will apply 2 operating clock cycles to simulations +--line removed-- + +Command line to execute: check_netlist_naming_conflict --fix --report .--line removed-- + +Confirm selected options when call command 'check_netlist_naming_conflict': +--fix: on +--report: .--line removed-- +Check naming violations of netlist blocks and nets +Fixed 1 naming conflicts in the netlist. +Naming fix-up report is generated to file '.--line removed--' +--line removed-- + +Command line to execute: pb_pin_fixup --verbose + +Confirm selected options when call command 'pb_pin_fixup': +--verbose: on +Fix up pb pin mapping results after routing optimization +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I0[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I0[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I0i[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I0i[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I1[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I1[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I1i[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I1i[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I2[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I2[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I2i[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I2i[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I3[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I3[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I3i[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I3i[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I4[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I4[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I4i[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I4i[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I5[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I5[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I5i[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I5i[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I6[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I6[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I6i[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I6i[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I7[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I7[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I7i[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.I7i[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.reg_in[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.sc_in[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.cin[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.reset[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[1]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[2]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[3]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[4]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[5]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[6]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[7]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[8]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[9]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[10]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[11]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[12]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[13]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[14]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.O[15]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.reg_out[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.sc_out[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.cout[0]' as it matches cluster routing +Bypass net at clustered block 'c' pin 'grid[5][4].clb.clk[0]' as it matches cluster routing +Bypass net at clustered block 'out:c' pin 'grid[5][9].io.outpad[0]' as it matches cluster routing +Bypass net at clustered block 'out:c' pin 'grid[5][9].io.inpad[0]' as it matches cluster routing +Bypass net at clustered block 'a' pin 'grid[5][0].io.outpad[0]' as it matches cluster routing +Bypass net at clustered block 'a' pin 'grid[5][0].io.inpad[0]' as it matches cluster routing +Bypass net at clustered block 'b' pin 'grid[5][0].io.outpad[0]' as it matches cluster routing +Bypass net at clustered block 'b' pin 'grid[5][0].io.inpad[0]' as it matches cluster routing +--line removed-- + +Command line to execute: lut_truth_table_fixup + +Confirm selected options when call command 'lut_truth_table_fixup': +--verbose: off +Fix up LUT truth tables after packing optimization +--line removed-- + +Command line to execute: build_fabric --compress_routing + +Confirm selected options when call command 'build_fabric': +--frame_view: off +--compress_routing: on +--duplicate_grid_pin: off +--load_fabric_key: off +--write_fabric_key: off +--generate_random_fabric_key: off +--verbose: off +Identify unique General Switch Blocks (GSBs) +Detected 9 unique general switch blocks from a total of 81 (compression rate=800.00%) +--line removed-- + + +Build fabric module graph +# Build constant generator modules +--line removed-- +# Build user-defined modules +--line removed-- +# Build essential (inverter/buffer/logic gate) modules +--line removed-- +# Build local encoder (for multiplexers) modules +--line removed-- +# Building multiplexer modules +--line removed-- +# Build Look-Up Table (LUT) modules +--line removed-- +# Build wire modules +--line removed-- +# Build memory modules +--line removed-- +# Build grid modules +Building logical tiles...Done +Building physical tiles...Done +--line removed-- +# Build unique routing modules... +--line removed-- +# Build FPGA fabric module +## Add grid instances to top module +--line removed-- +## Add switch block instances to top module +--line removed-- +## Add connection block instances to top module +--line removed-- +## Add connection block instances to top module +--line removed-- +## Add module nets between grids and GSBs +--line removed-- +## Add module nets for inter-tile connections +--line removed-- +## Build configurable regions for the top module +--line removed-- +## Add module nets for configuration buses +--line removed-- +--line removed-- +--line removed-- +Create I/O location mapping for top module +--line removed-- +Create global port info for top module +--line removed-- + +Command line to execute: write_fabric_hierarchy --file ./fabric_hierarchy.txt + +Confirm selected options when call command 'write_fabric_hierarchy': +--file, -f: ./fabric_hierarchy.txt +--depth: off +--verbose: off +Warning 56: Directory '.' already exists. Will overwrite contents +Write fabric hierarchy to plain-text file './fabric_hierarchy.txt' +--line removed-- + +Command line to execute: repack + +Confirm selected options when call command 'repack': +--design_constraints: off +--ignore_global_nets_on_pins: off +--verbose: off +Build routing resource graph for the physical implementation of logical tile +--line removed-- +Repack clustered blocks to physical implementation of logical tile +Repack clustered block 'c'...Done +Repack clustered block 'out:c'...Done +Repack clustered block 'a'...Done +Repack clustered block 'b'...Done +--line removed-- +Identify wire LUTs created by repacking +Identified 0 wire LUTs created by repacker +--line removed-- +Build truth tables for physical LUTs +--line removed-- + +Command line to execute: build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +Confirm selected options when call command 'build_architecture_bitstream': +--write_file: fabric_independent_bitstream.xml +--read_file: off +--no_time_stamp: off +--verbose: on + +Build fabric-independent bitstream for implementation 'top' + +Reserved 12283 configurable blocks +Reserved 35888 configuration bits +Building grid bitstream... +Generating bitstream for core grids...Done +Generating bitstream for I/O grids...Done +Done +Building routing bitstream... +Generating bitstream for Switch blocks...Done +Generating bitstream for X-direction Connection blocks ...Done +Generating bitstream for Y-direction Connection blocks ...Done +Done +Decoded 35888 configuration bits into 12283 blocks + +Build fabric-independent bitstream for implementation 'top' +--line removed-- +Warning 57: Directory path is empty and nothing will be created. +Write 35888 architecture independent bitstream into XML file 'fabric_independent_bitstream.xml' +--line removed-- + +Command line to execute: build_fabric_bitstream --verbose + +Confirm selected options when call command 'build_fabric_bitstream': +--verbose: on + +Build fabric dependent bitstream + +Built 35888 configuration bits for fabric + +Build fabric dependent bitstream +--line removed-- + +Command line to execute: write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +Confirm selected options when call command 'write_fabric_bitstream': +--file, -f: fabric_bitstream.bit +--format: plain_text +--fast_configuration: off +--keep_dont_care_bits: off +--no_time_stamp: off +--verbose: off +Warning 58: Directory path is empty and nothing will be created. +Write 35888 fabric bitstream into plain text file 'fabric_bitstream.bit' +--line removed-- + +Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +Confirm selected options when call command 'write_fabric_verilog': +--file, -f: ./SRC +--explicit_port_mapping: on +--include_timing: on +--print_user_defined_template: on +--default_net_type: off +--no_time_stamp: off +--use_relative_path: off +--verbose: on +Write Verilog netlists for FPGA fabric + +Succeed to create directory './SRC' +Succeed to create directory './SRC/sub_module' +Succeed to create directory './SRC/lb' +Succeed to create directory './SRC/routing' +Generating Verilog netlist './SRC/sub_module/inv_buf_passgate.v' for essential gates...Done +Writing Verilog netlist for configuration decoders './SRC/sub_module/arch_encoder.v'...Done +Writing Verilog netlist for local decoders for multiplexers './SRC/sub_module/local_encoder.v'...Done +Writing Verilog netlist for Multiplexer primitives './SRC/sub_module/mux_primitives.v' ...Done +Writing Verilog netlist for Multiplexers './SRC/sub_module/muxes.v' ...Done +Writing Verilog netlist for LUTs './SRC/sub_module/luts.v'...Done +Writing Verilog netlist for wires './SRC/sub_module/wires.v'...Done +Writing Verilog netlist for memories './SRC/sub_module/memories.v' ...Done +Writing Verilog netlist for shift register banks './SRC/sub_module/shift_register_banks.v' ...Done +Creating template for user-defined Verilog modules './SRC/sub_module/user_defined_templates.v'...Done + +Writing logical tiles... +Writing Verilog netlists for logic tile 'io' ... +Writing Verilog netlist './SRC/lb/logical_tile_io_mode_physical__iopad.v' for primitive pb_type 'iopad' ... +Writing Verilog codes of logical tile primitive block 'logical_tile_io_mode_physical__iopad'...Done +Writing Verilog netlist './SRC/lb/logical_tile_io_mode_io_.v' for pb_type 'io' ... +Writing Verilog codes of pb_type 'logical_tile_io_mode_io_'...Done +Done + +Writing Verilog netlists for logic tile 'clb' ... +Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v' for primitive pb_type 'frac_lut4' ... +Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4'...Done +Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v' for primitive pb_type 'carry_follower' ... +Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower'...Done +Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v' for pb_type 'frac_logic' ... +Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic'...Done +Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v' for primitive pb_type 'ff' ... +Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff'...Done +Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v' for pb_type 'fabric' ... +Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric'...Done +Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle.v' for pb_type 'fle' ... +Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle'...Done +Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_clb_.v' for pb_type 'clb' ... +Writing Verilog codes of pb_type 'logical_tile_clb_mode_clb_'...Done +Done + +Writing logical tiles...Done + +Building physical tiles... +Writing Verilog Netlist './SRC/lb/grid_io_top_top.v' for physical tile 'io_top' at top side ...Done +Writing Verilog Netlist './SRC/lb/grid_io_right_right.v' for physical tile 'io_right' at right side ...Done +Writing Verilog Netlist './SRC/lb/grid_io_bottom_bottom.v' for physical tile 'io_bottom' at bottom side ...Done +Writing Verilog Netlist './SRC/lb/grid_io_left_left.v' for physical tile 'io_left' at left side ...Done +Writing Verilog Netlist './SRC/lb/grid_clb.v' for physical_tile 'clb'...Done +Building physical tiles...Done + +Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done +Written 71 Verilog modules in total +Write Verilog netlists for FPGA fabric +--line removed-- + +Command line to execute: exit + +Confirm selected options when call command 'exit': + +Finish execution with 0 errors + +--line removed-- + +Thank you for using OpenFPGA! +Incr Slack updates 2 in 1.4547e-05 sec +Full Max Req/Worst Slack updates 1 in 3.044e-06 sec +Incr Max Req/Worst Slack updates 1 in 5.177e-06 sec +Incr Criticality updates 0 in 0 sec +Full Criticality updates 2 in 8.542e-06 sec +0 \ No newline at end of file diff --git a/SOFA_A/FPGA88_SOFA_A/Makefile b/SOFA_A/FPGA88_SOFA_A/Makefile new file mode 120000 index 0000000..da6d52f --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/Makefile @@ -0,0 +1 @@ +../../openfpga-physical/Makefile \ No newline at end of file diff --git a/SOFA_A/README.md b/SOFA_A/FPGA88_SOFA_A/README.md similarity index 100% rename from SOFA_A/README.md rename to SOFA_A/FPGA88_SOFA_A/README.md diff --git a/SOFA_A/FPGA88_SOFA_A/config.sh b/SOFA_A/FPGA88_SOFA_A/config.sh new file mode 100644 index 0000000..f7ee0ca --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/config.sh @@ -0,0 +1,57 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# = = = = = = = = = = = = = = Variables Sections = = = = = = = = = = = = = = = +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +source ../../openfpga-physical/conf_template.sh + +export_ PROJ_NAME = FPGA88_SOFA_A # Project Name +export_ FPGA_SIZE_X = 8 # Grid X Size +export_ FPGA_SIZE_Y = 8 # Grid Y Size + +export_ LAYOUT = "FPGA88" +export_ DESIGN_STYLE = hier +export_ TECHNOLOGY = "skywater" + +export_ TASK_DIR_NAME = "${PROJ_NAME}_task" +export_ VERILOG_PROJ_DIR = "${RELEASE_DIRECTORY}/${PROJ_NAME}_verilog" +export_ GENERATE_FABRIC_KEY = "../CommonFiles/render_sofa_a_fabric_key.py" +export_ NETLIST_SYNTH_SCRIPT = "../CommonFiles/sofa_netlist_synth_script.sh" +export_ RESTRUCT_NETLIST = "../CommonFiles/restructure_fabric_sofa_a.py" +export_ CUSTOM_MODULES_LIST = "./${TASK_DIR_NAME}/CustomModules/custom_module.txt" + +# Complete Chip (fpga_top) or eFPGA (fpga_core) +export_ DESIGN_NAME = fpga_core + +# Pin Information Source Automatic or Sheet +export_ PIN_MAP = Automatic +export_ PIN_MAP_CSV_SPREADSHEET_LINK = "" # Required only if PIN_MAP==Sheet + +# Core Dimension, requires if DESIGN_NAME=fpga_core +# if DESIGN_NAME=fpga_top its Optional if defined it overrides the +# Calculated DIE_DIMENSION +export_ DIE_DIMENSION = 3200 + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Derived Or Fixed Variables +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +export_ OPENFPGA_ENGINE_PATH = ${OPENFPGA_PATH} +export_ TASK_DIR_NAME = ${PROJ_NAME}_task +export_ VERILOG_PROJ_DIR = ${PROJ_NAME}_verilog +export_ SPY_HACK_FILE = ${TASK_DIR_NAME}/spy_hack.txt +export_ POST_OPENFPGA_SCRIPT = ./PostOpenFPGAScript.sh +export_ POST_GENERATION_SCRIPT = ./generate_scandef_and_case_analysis.sh + + +export_ TAPEOUT_DIRECTORY = /research/ece/lnis/USERS/DARPA_ERI/Tapeout/SOFA +export_ TAPEOUT_SCRIPT = + +export_ RENDER_FABRIC_SCRIPT = "../CommonFiles/render_sofa_a.py" + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# PNR RELATED FLOW +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +export_ INIT_DESIGN_INPUT="ASCII" + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Extra variables availble during flow (suuffix FLOWVAR_) +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +export_ FLOWVAR_STANDARD_CELLS="sc_hd" diff --git a/SOFA_A/FPGA88_SOFA_A/release/post_synth/top_instances_ports.txt b/SOFA_A/FPGA88_SOFA_A/release/post_synth/top_instances_ports.txt new file mode 100644 index 0000000..a4a2127 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/release/post_synth/top_instances_ports.txt @@ -0,0 +1,575 @@ +{ + "sb_8__8_": [ + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_", + "0001_Direction.IN,bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_", + "0001_Direction.IN,left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.OUT,ccff_tail", + "0030_Direction.IN,chanx_left_in", + "0030_Direction.IN,chany_bottom_in", + "0030_Direction.OUT,chanx_left_out", + "0030_Direction.OUT,chany_bottom_out" + ], + "sb_8__1_": [ + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_", + "0001_Direction.IN,bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_", + "0001_Direction.IN,top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.OUT,ccff_tail", + "0030_Direction.IN,chanx_left_in", + "0030_Direction.IN,chany_bottom_in", + "0030_Direction.IN,chany_top_in", + "0030_Direction.OUT,chanx_left_out", + "0030_Direction.OUT,chany_bottom_out", + "0030_Direction.OUT,chany_top_out" + ], + "sb_8__0_": [ + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_", + "0001_Direction.IN,top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.OUT,ccff_tail", + "0030_Direction.IN,chanx_left_in", + "0030_Direction.IN,chany_top_in", + "0030_Direction.OUT,chanx_left_out", + "0030_Direction.OUT,chany_top_out" + ], + "sb_1__8_": [ + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_", + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_", + "0001_Direction.IN,left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_", + "0001_Direction.IN,right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.OUT,ccff_tail", + "0030_Direction.IN,chanx_left_in", + "0030_Direction.IN,chanx_right_in", + "0030_Direction.IN,chany_bottom_in", + "0030_Direction.OUT,chanx_left_out", + "0030_Direction.OUT,chanx_right_out", + "0030_Direction.OUT,chany_bottom_out" + ], + "sb_1__1_": [ + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_", + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_", + "0001_Direction.OUT,ccff_tail", + "0030_Direction.IN,chanx_left_in", + "0030_Direction.IN,chanx_right_in", + "0030_Direction.IN,chany_bottom_in", + "0030_Direction.IN,chany_top_in", + "0030_Direction.OUT,chanx_left_out", + "0030_Direction.OUT,chanx_right_out", + "0030_Direction.OUT,chany_bottom_out", + "0030_Direction.OUT,chany_top_out" + ], + "sb_1__0_": [ + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_", + "0001_Direction.OUT,ccff_tail", + "0030_Direction.IN,chanx_left_in", + "0030_Direction.IN,chanx_right_in", + "0030_Direction.IN,chany_top_in", + "0030_Direction.OUT,chanx_left_out", + "0030_Direction.OUT,chanx_right_out", + "0030_Direction.OUT,chany_top_out" + ], + "sb_0__8_": [ + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_", + "0001_Direction.IN,right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.OUT,ccff_tail", + "0030_Direction.IN,chanx_right_in", + "0030_Direction.IN,chany_bottom_in", + "0030_Direction.OUT,chanx_right_out", + "0030_Direction.OUT,chany_bottom_out" + ], + "sb_0__1_": [ + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.OUT,ccff_tail", + "0030_Direction.IN,chanx_right_in", + "0030_Direction.IN,chany_bottom_in", + "0030_Direction.IN,chany_top_in", + "0030_Direction.OUT,chanx_right_out", + "0030_Direction.OUT,chany_bottom_out", + "0030_Direction.OUT,chany_top_out" + ], + "sb_0__0_": [ + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.OUT,ccff_tail", + "0030_Direction.IN,chanx_right_in", + "0030_Direction.IN,chany_top_in", + "0030_Direction.OUT,chanx_right_out", + "0030_Direction.OUT,chany_top_out" + ], + "grid_io_top_top": [ + "0001_Direction.IN,IO_ISOL_N", + "0001_Direction.IN,bottom_width_0_height_0_subtile_0__pin_outpad_0_", + "0001_Direction.IN,bottom_width_0_height_0_subtile_1__pin_outpad_0_", + "0001_Direction.IN,bottom_width_0_height_0_subtile_2__pin_outpad_0_", + "0001_Direction.IN,bottom_width_0_height_0_subtile_3__pin_outpad_0_", + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.OUT,bottom_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.OUT,bottom_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.OUT,bottom_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.OUT,bottom_width_0_height_0_subtile_3__pin_inpad_0_", + "0001_Direction.OUT,ccff_tail", + "0004_Direction.IN,gfpga_pad_EMBEDDED_IO_HD_SOC_IN", + "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_DIR", + "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_OUT" + ], + "grid_io_right_right": [ + "0001_Direction.IN,IO_ISOL_N", + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,left_width_0_height_0_subtile_0__pin_outpad_0_", + "0001_Direction.IN,left_width_0_height_0_subtile_1__pin_outpad_0_", + "0001_Direction.IN,left_width_0_height_0_subtile_2__pin_outpad_0_", + "0001_Direction.IN,left_width_0_height_0_subtile_3__pin_outpad_0_", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.OUT,ccff_tail", + "0001_Direction.OUT,left_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.OUT,left_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.OUT,left_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.OUT,left_width_0_height_0_subtile_3__pin_inpad_0_", + "0004_Direction.IN,gfpga_pad_EMBEDDED_IO_HD_SOC_IN", + "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_DIR", + "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_OUT" + ], + "grid_io_left_left": [ + "0001_Direction.IN,IO_ISOL_N", + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_outpad_0_", + "0001_Direction.IN,right_width_0_height_0_subtile_1__pin_outpad_0_", + "0001_Direction.IN,right_width_0_height_0_subtile_2__pin_outpad_0_", + "0001_Direction.IN,right_width_0_height_0_subtile_3__pin_outpad_0_", + "0001_Direction.OUT,ccff_tail", + "0001_Direction.OUT,right_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.OUT,right_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.OUT,right_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.OUT,right_width_0_height_0_subtile_3__pin_inpad_0_", + "0004_Direction.IN,gfpga_pad_EMBEDDED_IO_HD_SOC_IN", + "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_DIR", + "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_OUT" + ], + "grid_io_bottom_bottom": [ + "0001_Direction.IN,IO_ISOL_N", + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_outpad_0_", + "0001_Direction.IN,top_width_0_height_0_subtile_1__pin_outpad_0_", + "0001_Direction.IN,top_width_0_height_0_subtile_2__pin_outpad_0_", + "0001_Direction.IN,top_width_0_height_0_subtile_3__pin_outpad_0_", + "0001_Direction.OUT,ccff_tail", + "0001_Direction.OUT,top_width_0_height_0_subtile_0__pin_inpad_0_", + "0001_Direction.OUT,top_width_0_height_0_subtile_1__pin_inpad_0_", + "0001_Direction.OUT,top_width_0_height_0_subtile_2__pin_inpad_0_", + "0001_Direction.OUT,top_width_0_height_0_subtile_3__pin_inpad_0_", + "0004_Direction.IN,gfpga_pad_EMBEDDED_IO_HD_SOC_IN", + "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_DIR", + "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_OUT" + ], + "grid_clb": [ + "0001_Direction.IN,Test_en", + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,left_width_0_height_0_subtile_0__pin_clk_0_", + "0001_Direction.IN,left_width_0_height_0_subtile_0__pin_reset_0_", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I4_0_", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I4_1_", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I4i_0_", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I4i_1_", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I5_0_", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I5_1_", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I5i_0_", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I5i_1_", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I6_0_", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I6_1_", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I6i_0_", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I6i_1_", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I7_0_", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I7_1_", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I7i_0_", + "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I7i_1_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I0_0_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I0_1_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I0i_0_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I0i_1_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I1_0_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I1_1_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I1i_0_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I1i_1_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I2_0_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I2_1_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I2i_0_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I2i_1_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I3_0_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I3_1_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I3i_0_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I3i_1_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_cin_0_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_reg_in_0_", + "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_sc_in_0_", + "0001_Direction.OUT,bottom_width_0_height_0_subtile_0__pin_cout_0_", + "0001_Direction.OUT,bottom_width_0_height_0_subtile_0__pin_reg_out_0_", + "0001_Direction.OUT,bottom_width_0_height_0_subtile_0__pin_sc_out_0_", + "0001_Direction.OUT,ccff_tail", + "0001_Direction.OUT,right_width_0_height_0_subtile_0__pin_O_10_", + "0001_Direction.OUT,right_width_0_height_0_subtile_0__pin_O_11_", + "0001_Direction.OUT,right_width_0_height_0_subtile_0__pin_O_12_", + "0001_Direction.OUT,right_width_0_height_0_subtile_0__pin_O_13_", + "0001_Direction.OUT,right_width_0_height_0_subtile_0__pin_O_14_", + "0001_Direction.OUT,right_width_0_height_0_subtile_0__pin_O_15_", + "0001_Direction.OUT,right_width_0_height_0_subtile_0__pin_O_8_", + "0001_Direction.OUT,right_width_0_height_0_subtile_0__pin_O_9_", + "0001_Direction.OUT,top_width_0_height_0_subtile_0__pin_O_0_", + "0001_Direction.OUT,top_width_0_height_0_subtile_0__pin_O_1_", + "0001_Direction.OUT,top_width_0_height_0_subtile_0__pin_O_2_", + "0001_Direction.OUT,top_width_0_height_0_subtile_0__pin_O_3_", + "0001_Direction.OUT,top_width_0_height_0_subtile_0__pin_O_4_", + "0001_Direction.OUT,top_width_0_height_0_subtile_0__pin_O_5_", + "0001_Direction.OUT,top_width_0_height_0_subtile_0__pin_O_6_", + "0001_Direction.OUT,top_width_0_height_0_subtile_0__pin_O_7_" + ], + "direct_interc": [ + "0001_Direction.IN,in", + "0001_Direction.OUT,out" + ], + "cby_8__1_": [ + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.OUT,ccff_tail", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I4_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I4_1_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I5_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I5_1_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I6_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I6_1_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I7_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I7_1_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_", + "0001_Direction.OUT,right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_", + "0001_Direction.OUT,right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_", + "0001_Direction.OUT,right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_", + "0001_Direction.OUT,right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_", + "0030_Direction.IN,chany_bottom_in", + "0030_Direction.IN,chany_top_in", + "0030_Direction.OUT,chany_bottom_out", + "0030_Direction.OUT,chany_top_out" + ], + "cby_1__1_": [ + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.OUT,ccff_tail", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I4_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I4_1_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I5_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I5_1_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I6_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I6_1_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I7_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I7_1_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_", + "0030_Direction.IN,chany_bottom_in", + "0030_Direction.IN,chany_top_in", + "0030_Direction.OUT,chany_bottom_out", + "0030_Direction.OUT,chany_top_out" + ], + "cby_0__1_": [ + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.OUT,ccff_tail", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_", + "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_", + "0030_Direction.IN,chany_bottom_in", + "0030_Direction.IN,chany_top_in", + "0030_Direction.OUT,chany_bottom_out", + "0030_Direction.OUT,chany_top_out" + ], + "cbx_1__8_": [ + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_", + "0001_Direction.OUT,ccff_tail", + "0001_Direction.OUT,top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_", + "0001_Direction.OUT,top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_", + "0001_Direction.OUT,top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_", + "0001_Direction.OUT,top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_", + "0030_Direction.IN,chanx_left_in", + "0030_Direction.IN,chanx_right_in", + "0030_Direction.OUT,chanx_left_out", + "0030_Direction.OUT,chanx_right_out" + ], + "cbx_1__1_": [ + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_", + "0001_Direction.OUT,ccff_tail", + "0030_Direction.IN,chanx_left_in", + "0030_Direction.IN,chanx_right_in", + "0030_Direction.OUT,chanx_left_out", + "0030_Direction.OUT,chanx_right_out" + ], + "cbx_1__0_": [ + "0001_Direction.IN,ccff_head", + "0001_Direction.IN,pReset", + "0001_Direction.IN,prog_clk", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_", + "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_", + "0001_Direction.OUT,ccff_tail", + "0030_Direction.IN,chanx_left_in", + "0030_Direction.IN,chanx_right_in", + "0030_Direction.OUT,chanx_left_out", + "0030_Direction.OUT,chanx_right_out" + ] +} \ No newline at end of file diff --git a/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/shaping.txt b/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/shaping.txt new file mode 100644 index 0000000..5c3aa77 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/shaping.txt @@ -0,0 +1,292 @@ + INSTANCE MODULE LOC_X LOC_Y SHAPE BBOX_PT POINTS + = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + grid_clb_1__1_ grid_clb 34.176 24.480 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_1__2_ grid_clb 34.176 92.640 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_1__3_ grid_clb 34.176 160.800 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_1__4_ grid_clb 34.176 228.960 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_1__5_ grid_clb 34.176 297.120 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_1__6_ grid_clb 34.176 365.280 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_1__7_ grid_clb 34.176 433.440 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_1__8_ grid_clb 34.176 501.600 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_2__1_ grid_clb 93.408 24.480 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_2__2_ grid_clb 93.408 92.640 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_2__3_ grid_clb 93.408 160.800 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_2__4_ grid_clb 93.408 228.960 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_2__5_ grid_clb 93.408 297.120 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_2__6_ grid_clb 93.408 365.280 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_2__7_ grid_clb 93.408 433.440 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_2__8_ grid_clb 93.408 501.600 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_3__1_ grid_clb 152.640 24.480 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_3__2_ grid_clb 152.640 92.640 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_3__3_ grid_clb 152.640 160.800 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_3__4_ grid_clb 152.640 228.960 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_3__5_ grid_clb 152.640 297.120 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_3__6_ grid_clb 152.640 365.280 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_3__7_ grid_clb 152.640 433.440 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_3__8_ grid_clb 152.640 501.600 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_4__1_ grid_clb 211.872 24.480 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_4__2_ grid_clb 211.872 92.640 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_4__3_ grid_clb 211.872 160.800 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_4__4_ grid_clb 211.872 228.960 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_4__5_ grid_clb 211.872 297.120 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_4__6_ grid_clb 211.872 365.280 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_4__7_ grid_clb 211.872 433.440 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_4__8_ grid_clb 211.872 501.600 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_5__1_ grid_clb 271.104 24.480 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_5__2_ grid_clb 271.104 92.640 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_5__3_ grid_clb 271.104 160.800 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_5__4_ grid_clb 271.104 228.960 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_5__5_ grid_clb 271.104 297.120 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_5__6_ grid_clb 271.104 365.280 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_5__7_ grid_clb 271.104 433.440 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_5__8_ grid_clb 271.104 501.600 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_6__1_ grid_clb 330.336 24.480 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_6__2_ grid_clb 330.336 92.640 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_6__3_ grid_clb 330.336 160.800 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_6__4_ grid_clb 330.336 228.960 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_6__5_ grid_clb 330.336 297.120 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_6__6_ grid_clb 330.336 365.280 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_6__7_ grid_clb 330.336 433.440 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_6__8_ grid_clb 330.336 501.600 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_7__1_ grid_clb 389.568 24.480 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_7__2_ grid_clb 389.568 92.640 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_7__3_ grid_clb 389.568 160.800 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_7__4_ grid_clb 389.568 228.960 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_7__5_ grid_clb 389.568 297.120 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_7__6_ grid_clb 389.568 365.280 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_7__7_ grid_clb 389.568 433.440 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_7__8_ grid_clb 389.568 501.600 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_8__1_ grid_clb 448.800 24.480 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_8__2_ grid_clb 448.800 92.640 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_8__3_ grid_clb 448.800 160.800 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_8__4_ grid_clb 448.800 228.960 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_8__5_ grid_clb 448.800 297.120 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_8__6_ grid_clb 448.800 365.280 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_8__7_ grid_clb 448.800 433.440 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + grid_clb_8__8_ grid_clb 448.800 501.600 rect 4 0.000 0.000 0.000 60.960 43.872 60.960 43.872 0.000 + sb_0__0_ sb_0__0_ 1.920 0.960 cross 4 0.000 0.000 0.000 23.520 32.256 23.520 32.256 0.000 + sb_0__1_ sb_0__1_ 1.920 85.440 cross 4 0.000 0.000 0.000 7.200 32.256 7.200 32.256 0.000 + sb_0__2_ sb_0__1_ 1.920 153.600 cross 4 0.000 0.000 0.000 7.200 32.256 7.200 32.256 0.000 + sb_0__3_ sb_0__1_ 1.920 221.760 cross 4 0.000 0.000 0.000 7.200 32.256 7.200 32.256 0.000 + sb_0__4_ sb_0__1_ 1.920 289.920 cross 4 0.000 0.000 0.000 7.200 32.256 7.200 32.256 0.000 + sb_0__5_ sb_0__1_ 1.920 358.080 cross 4 0.000 0.000 0.000 7.200 32.256 7.200 32.256 0.000 + sb_0__6_ sb_0__1_ 1.920 426.240 cross 4 0.000 0.000 0.000 7.200 32.256 7.200 32.256 0.000 + sb_0__7_ sb_0__1_ 1.920 494.400 cross 4 0.000 0.000 0.000 7.200 32.256 7.200 32.256 0.000 + sb_0__8_ sb_0__8_ 1.920 562.560 cross 4 0.000 0.000 0.000 24.960 32.256 24.960 32.256 0.000 + sb_1__0_ sb_1__0_ 78.048 0.960 cross 4 0.000 0.000 0.000 23.520 15.360 23.520 15.360 0.000 + sb_2__0_ sb_1__0_ 137.280 0.960 cross 4 0.000 0.000 0.000 23.520 15.360 23.520 15.360 0.000 + sb_3__0_ sb_1__0_ 196.512 0.960 cross 4 0.000 0.000 0.000 23.520 15.360 23.520 15.360 0.000 + sb_4__0_ sb_1__0_ 255.744 0.960 cross 4 0.000 0.000 0.000 23.520 15.360 23.520 15.360 0.000 + sb_5__0_ sb_1__0_ 314.976 0.960 cross 4 0.000 0.000 0.000 23.520 15.360 23.520 15.360 0.000 + sb_6__0_ sb_1__0_ 374.208 0.960 cross 4 0.000 0.000 0.000 23.520 15.360 23.520 15.360 0.000 + sb_7__0_ sb_1__0_ 433.440 0.960 cross 4 0.000 0.000 0.000 23.520 15.360 23.520 15.360 0.000 + sb_1__1_ sb_1__1_ 78.048 85.440 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_1__2_ sb_1__1_ 78.048 153.600 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_1__3_ sb_1__1_ 78.048 221.760 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_1__4_ sb_1__1_ 78.048 289.920 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_1__5_ sb_1__1_ 78.048 358.080 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_1__6_ sb_1__1_ 78.048 426.240 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_1__7_ sb_1__1_ 78.048 494.400 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_2__1_ sb_1__1_ 137.280 85.440 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_2__2_ sb_1__1_ 137.280 153.600 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_2__3_ sb_1__1_ 137.280 221.760 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_2__4_ sb_1__1_ 137.280 289.920 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_2__5_ sb_1__1_ 137.280 358.080 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_2__6_ sb_1__1_ 137.280 426.240 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_2__7_ sb_1__1_ 137.280 494.400 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_3__1_ sb_1__1_ 196.512 85.440 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_3__2_ sb_1__1_ 196.512 153.600 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_3__3_ sb_1__1_ 196.512 221.760 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_3__4_ sb_1__1_ 196.512 289.920 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_3__5_ sb_1__1_ 196.512 358.080 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_3__6_ sb_1__1_ 196.512 426.240 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_3__7_ sb_1__1_ 196.512 494.400 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_4__1_ sb_1__1_ 255.744 85.440 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_4__2_ sb_1__1_ 255.744 153.600 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_4__3_ sb_1__1_ 255.744 221.760 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_4__4_ sb_1__1_ 255.744 289.920 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_4__5_ sb_1__1_ 255.744 358.080 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_4__6_ sb_1__1_ 255.744 426.240 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_4__7_ sb_1__1_ 255.744 494.400 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_5__1_ sb_1__1_ 314.976 85.440 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_5__2_ sb_1__1_ 314.976 153.600 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_5__3_ sb_1__1_ 314.976 221.760 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_5__4_ sb_1__1_ 314.976 289.920 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_5__5_ sb_1__1_ 314.976 358.080 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_5__6_ sb_1__1_ 314.976 426.240 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_5__7_ sb_1__1_ 314.976 494.400 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_6__1_ sb_1__1_ 374.208 85.440 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_6__2_ sb_1__1_ 374.208 153.600 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_6__3_ sb_1__1_ 374.208 221.760 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_6__4_ sb_1__1_ 374.208 289.920 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_6__5_ sb_1__1_ 374.208 358.080 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_6__6_ sb_1__1_ 374.208 426.240 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_6__7_ sb_1__1_ 374.208 494.400 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_7__1_ sb_1__1_ 433.440 85.440 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_7__2_ sb_1__1_ 433.440 153.600 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_7__3_ sb_1__1_ 433.440 221.760 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_7__4_ sb_1__1_ 433.440 289.920 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_7__5_ sb_1__1_ 433.440 358.080 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_7__6_ sb_1__1_ 433.440 426.240 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_7__7_ sb_1__1_ 433.440 494.400 cross 4 0.000 0.000 0.000 7.200 15.360 7.200 15.360 0.000 + sb_1__8_ sb_1__8_ 78.048 562.560 cross 4 0.000 0.000 0.000 24.960 15.360 24.960 15.360 0.000 + sb_2__8_ sb_1__8_ 137.280 562.560 cross 4 0.000 0.000 0.000 24.960 15.360 24.960 15.360 0.000 + sb_3__8_ sb_1__8_ 196.512 562.560 cross 4 0.000 0.000 0.000 24.960 15.360 24.960 15.360 0.000 + sb_4__8_ sb_1__8_ 255.744 562.560 cross 4 0.000 0.000 0.000 24.960 15.360 24.960 15.360 0.000 + sb_5__8_ sb_1__8_ 314.976 562.560 cross 4 0.000 0.000 0.000 24.960 15.360 24.960 15.360 0.000 + sb_6__8_ sb_1__8_ 374.208 562.560 cross 4 0.000 0.000 0.000 24.960 15.360 24.960 15.360 0.000 + sb_7__8_ sb_1__8_ 433.440 562.560 cross 4 0.000 0.000 0.000 24.960 15.360 24.960 15.360 0.000 + sb_8__0_ sb_8__0_ 492.672 0.960 cross 4 0.000 0.000 0.000 23.520 32.256 23.520 32.256 0.000 + sb_8__1_ sb_8__1_ 492.672 85.440 cross 4 0.000 0.000 0.000 7.200 32.256 7.200 32.256 0.000 + sb_8__2_ sb_8__1_ 492.672 153.600 cross 4 0.000 0.000 0.000 7.200 32.256 7.200 32.256 0.000 + sb_8__3_ sb_8__1_ 492.672 221.760 cross 4 0.000 0.000 0.000 7.200 32.256 7.200 32.256 0.000 + sb_8__4_ sb_8__1_ 492.672 289.920 cross 4 0.000 0.000 0.000 7.200 32.256 7.200 32.256 0.000 + sb_8__5_ sb_8__1_ 492.672 358.080 cross 4 0.000 0.000 0.000 7.200 32.256 7.200 32.256 0.000 + sb_8__6_ sb_8__1_ 492.672 426.240 cross 4 0.000 0.000 0.000 7.200 32.256 7.200 32.256 0.000 + sb_8__7_ sb_8__1_ 492.672 494.400 cross 4 0.000 0.000 0.000 7.200 32.256 7.200 32.256 0.000 + sb_8__8_ sb_8__8_ 492.672 562.560 cross 4 0.000 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[cbx_1__1_] + + + cbx_6__2_ + [cbx_1__1_] + + + cbx_6__3_ + [cbx_1__1_] + + + cbx_6__4_ + [cbx_1__1_] + + + cbx_6__5_ + [cbx_1__1_] + + + cbx_6__6_ + [cbx_1__1_] + + + cbx_6__7_ + [cbx_1__1_] + + + cbx_7__1_ + [cbx_1__1_] + + + cbx_7__2_ + [cbx_1__1_] + + + cbx_7__3_ + [cbx_1__1_] + + + cbx_7__4_ + [cbx_1__1_] + + + cbx_7__5_ + [cbx_1__1_] + + + cbx_7__6_ + [cbx_1__1_] + + + cbx_7__7_ + [cbx_1__1_] + + + cbx_8__1_ + [cbx_1__1_] + + + cbx_8__2_ + [cbx_1__1_] + + + cbx_8__3_ + [cbx_1__1_] + + + cbx_8__4_ + [cbx_1__1_] + + + cbx_8__5_ + [cbx_1__1_] + + + cbx_8__6_ + [cbx_1__1_] + + + cbx_8__7_ + [cbx_1__1_] + + + cby_1__1_ + [cby_1__1_] + + + cby_1__2_ + [cby_1__1_] + + + cby_1__3_ + [cby_1__1_] + + + cby_1__4_ + [cby_1__1_] + + + cby_1__5_ + [cby_1__1_] + + + cby_1__6_ + [cby_1__1_] + + + cby_1__7_ + [cby_1__1_] + + + cby_1__8_ + [cby_1__1_] + + + cby_2__1_ + [cby_1__1_] + + + cby_2__2_ + [cby_1__1_] + + + cby_2__3_ + [cby_1__1_] + + + cby_2__4_ + [cby_1__1_] + + + cby_2__5_ + [cby_1__1_] + + + cby_2__6_ + [cby_1__1_] + + + cby_2__7_ + [cby_1__1_] + + + cby_2__8_ + [cby_1__1_] + + + cby_3__1_ + [cby_1__1_] + + + cby_3__2_ + [cby_1__1_] + + + cby_3__3_ + [cby_1__1_] + + + cby_3__4_ + [cby_1__1_] + + + cby_3__5_ + [cby_1__1_] + + + cby_3__6_ + [cby_1__1_] + + + cby_3__7_ + [cby_1__1_] + + + cby_3__8_ + [cby_1__1_] + + + cby_4__1_ + [cby_1__1_] + + + cby_4__2_ + [cby_1__1_] + + + cby_4__3_ + [cby_1__1_] + + + cby_4__4_ + [cby_1__1_] + + + cby_4__5_ + [cby_1__1_] + + + cby_4__6_ + [cby_1__1_] + + + cby_4__7_ + [cby_1__1_] + + + cby_4__8_ + [cby_1__1_] + + + cby_5__1_ + [cby_1__1_] + + + cby_5__2_ + [cby_1__1_] + + + cby_5__3_ + [cby_1__1_] + + + cby_5__4_ + [cby_1__1_] + + + cby_5__5_ + [cby_1__1_] + + + cby_5__6_ + [cby_1__1_] + + + cby_5__7_ + [cby_1__1_] + + + cby_5__8_ + [cby_1__1_] + + + cby_6__1_ + [cby_1__1_] + + + cby_6__2_ + [cby_1__1_] + + + cby_6__3_ + [cby_1__1_] + + + cby_6__4_ + [cby_1__1_] + + + cby_6__5_ + [cby_1__1_] + + + cby_6__6_ + [cby_1__1_] + + + cby_6__7_ + [cby_1__1_] + + + cby_6__8_ + [cby_1__1_] + + + cby_7__1_ + [cby_1__1_] + + + cby_7__2_ + [cby_1__1_] + + + cby_7__3_ + [cby_1__1_] + + + cby_7__4_ + [cby_1__1_] + + + cby_7__5_ + [cby_1__1_] + + + cby_7__6_ + [cby_1__1_] + + + cby_7__7_ + [cby_1__1_] + + + cby_7__8_ + [cby_1__1_] + + + cby_0__1_ + [cby_0__1_] + + + cby_0__2_ + [cby_0__1_] + + + cby_0__3_ + [cby_0__1_] + + + cby_0__4_ + [cby_0__1_] + + + cby_0__5_ + [cby_0__1_] + + + cby_0__6_ + [cby_0__1_] + + + cby_0__7_ + [cby_0__1_] + + + cby_0__8_ + [cby_0__1_] + + + cbx_1__8_ + [cbx_1__8_] + + + cbx_2__8_ + [cbx_1__8_] + + + cbx_3__8_ + [cbx_1__8_] + + + cbx_4__8_ + [cbx_1__8_] + + + cbx_5__8_ + [cbx_1__8_] + + + cbx_6__8_ + [cbx_1__8_] + + + cbx_7__8_ + [cbx_1__8_] + + + cbx_8__8_ + [cbx_1__8_] + + + cby_8__8_ + [cby_8__1_] + + + cby_8__7_ + [cby_8__1_] + + + cby_8__6_ + [cby_8__1_] + + + cby_8__5_ + [cby_8__1_] + + + cby_8__4_ + [cby_8__1_] + + + cby_8__3_ + [cby_8__1_] + + + cby_8__2_ + [cby_8__1_] + + + cby_8__1_ + [cby_8__1_] + + + cbx_8__0_ + [cbx_1__0_] + + + cbx_7__0_ + [cbx_1__0_] + + + cbx_6__0_ + [cbx_1__0_] + + + cbx_5__0_ + [cbx_1__0_] + + + cbx_4__0_ + [cbx_1__0_] + + + cbx_3__0_ + [cbx_1__0_] + + + cbx_2__0_ + [cbx_1__0_] + + + cbx_1__0_ + [cbx_1__0_] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_raw_floorplan.svg b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_raw_floorplan.svg new file mode 100644 index 0000000..e0de727 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_raw_floorplan.svg @@ -0,0 +1,1594 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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grid_clb_6__8_ + [grid_clb] + + + grid_clb_7__1_ + [grid_clb] + + + grid_clb_7__2_ + [grid_clb] + + + grid_clb_7__3_ + [grid_clb] + + + grid_clb_7__4_ + [grid_clb] + + + grid_clb_7__5_ + [grid_clb] + + + grid_clb_7__6_ + [grid_clb] + + + grid_clb_7__7_ + [grid_clb] + + + grid_clb_7__8_ + [grid_clb] + + + grid_clb_8__1_ + [grid_clb] + + + grid_clb_8__2_ + [grid_clb] + + + grid_clb_8__3_ + [grid_clb] + + + grid_clb_8__4_ + [grid_clb] + + + grid_clb_8__5_ + [grid_clb] + + + grid_clb_8__6_ + [grid_clb] + + + grid_clb_8__7_ + [grid_clb] + + + grid_clb_8__8_ + [grid_clb] + + + sb_0__0_ + [sb_0__0_] + + + sb_0__1_ + [sb_0__1_] + + + sb_0__2_ + [sb_0__1_] + + + sb_0__3_ + [sb_0__1_] + + + sb_0__4_ + [sb_0__1_] + + + sb_0__5_ + [sb_0__1_] + + + sb_0__6_ + [sb_0__1_] + + + sb_0__7_ + [sb_0__1_] + + + sb_0__8_ + [sb_0__8_] + + + sb_1__0_ + [sb_1__0_] + + + sb_2__0_ + [sb_1__0_] + + + sb_3__0_ + [sb_1__0_] + + + sb_4__0_ + [sb_1__0_] + + + sb_5__0_ + [sb_1__0_] + + + sb_6__0_ + [sb_1__0_] + + + sb_7__0_ + [sb_1__0_] + + + sb_1__1_ + [sb_1__1_] + + + sb_1__2_ + [sb_1__1_] + + + sb_1__3_ + [sb_1__1_] + + + sb_1__4_ + [sb_1__1_] + + + sb_1__5_ + [sb_1__1_] + + + sb_1__6_ + [sb_1__1_] + + + sb_1__7_ + [sb_1__1_] + + + sb_2__1_ + [sb_1__1_] + + + sb_2__2_ + [sb_1__1_] + + + sb_2__3_ + [sb_1__1_] + + + sb_2__4_ + [sb_1__1_] + + + sb_2__5_ + [sb_1__1_] + + + sb_2__6_ + [sb_1__1_] + + + sb_2__7_ + [sb_1__1_] + + + sb_3__1_ + [sb_1__1_] + + + sb_3__2_ + [sb_1__1_] + + + sb_3__3_ + [sb_1__1_] + + + sb_3__4_ + [sb_1__1_] + + + sb_3__5_ + [sb_1__1_] + + + sb_3__6_ + [sb_1__1_] + + + sb_3__7_ + [sb_1__1_] + + + sb_4__1_ + [sb_1__1_] + + + sb_4__2_ + [sb_1__1_] + + + sb_4__3_ + [sb_1__1_] + + + sb_4__4_ + [sb_1__1_] + + + sb_4__5_ + [sb_1__1_] + + + sb_4__6_ + [sb_1__1_] + + + sb_4__7_ + [sb_1__1_] + + + sb_5__1_ + [sb_1__1_] + + + sb_5__2_ + [sb_1__1_] + + + sb_5__3_ + [sb_1__1_] + + + sb_5__4_ + [sb_1__1_] + + + sb_5__5_ + [sb_1__1_] + + + sb_5__6_ + [sb_1__1_] + + + sb_5__7_ + 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sb_0__1_ + cby_0__2_ + sb_0__2_ + cby_0__3_ + sb_0__3_ + cby_0__4_ + sb_0__4_ + cby_0__5_ + sb_0__5_ + cby_0__6_ + sb_0__6_ + cby_0__7_ + sb_0__7_ + cby_0__8_ + sb_0__8_ + io_bottom_1__0_ + cbx_1__0_ + clb_1__1_ + cbx_1__1_ + clb_1__2_ + cbx_1__2_ + clb_1__3_ + cbx_1__3_ + clb_1__4_ + cbx_1__4_ + clb_1__5_ + cbx_1__5_ + clb_1__6_ + cbx_1__6_ + clb_1__7_ + cbx_1__7_ + clb_1__8_ + cbx_1__8_ + io_top_1__9_ + sb_1__0_ + cby_1__1_ + sb_1__1_ + cby_1__2_ + sb_1__2_ + cby_1__3_ + sb_1__3_ + cby_1__4_ + sb_1__4_ + cby_1__5_ + sb_1__5_ + cby_1__6_ + sb_1__6_ + cby_1__7_ + sb_1__7_ + cby_1__8_ + sb_1__8_ + io_bottom_2__0_ + cbx_2__0_ + clb_2__1_ + cbx_2__1_ + clb_2__2_ + cbx_2__2_ + clb_2__3_ + cbx_2__3_ + clb_2__4_ + cbx_2__4_ + clb_2__5_ + cbx_2__5_ + clb_2__6_ + cbx_2__6_ + clb_2__7_ + cbx_2__7_ + clb_2__8_ + cbx_2__8_ + io_top_2__9_ + sb_2__0_ + cby_2__1_ + sb_2__1_ + cby_2__2_ + sb_2__2_ + cby_2__3_ + sb_2__3_ + cby_2__4_ + sb_2__4_ + cby_2__5_ + sb_2__5_ + cby_2__6_ + sb_2__6_ + cby_2__7_ + sb_2__7_ + cby_2__8_ + sb_2__8_ + io_bottom_3__0_ + cbx_3__0_ + clb_3__1_ + cbx_3__1_ + clb_3__2_ + cbx_3__2_ + clb_3__3_ + cbx_3__3_ + clb_3__4_ + cbx_3__4_ + clb_3__5_ + cbx_3__5_ + clb_3__6_ + cbx_3__6_ + clb_3__7_ + cbx_3__7_ + clb_3__8_ + cbx_3__8_ + io_top_3__9_ + sb_3__0_ + cby_3__1_ + sb_3__1_ + cby_3__2_ + sb_3__2_ + cby_3__3_ + sb_3__3_ + cby_3__4_ + sb_3__4_ + cby_3__5_ + sb_3__5_ + cby_3__6_ + sb_3__6_ + cby_3__7_ + sb_3__7_ + cby_3__8_ + sb_3__8_ + io_bottom_4__0_ + cbx_4__0_ + clb_4__1_ + cbx_4__1_ + clb_4__2_ + cbx_4__2_ + clb_4__3_ + cbx_4__3_ + clb_4__4_ + cbx_4__4_ + clb_4__5_ + cbx_4__5_ + clb_4__6_ + cbx_4__6_ + clb_4__7_ + cbx_4__7_ + clb_4__8_ + cbx_4__8_ + io_top_4__9_ + sb_4__0_ + cby_4__1_ + sb_4__1_ + cby_4__2_ + sb_4__2_ + cby_4__3_ + sb_4__3_ + cby_4__4_ + sb_4__4_ + cby_4__5_ + sb_4__5_ + cby_4__6_ + sb_4__6_ + cby_4__7_ + sb_4__7_ + cby_4__8_ + sb_4__8_ + io_bottom_5__0_ + cbx_5__0_ + clb_5__1_ + cbx_5__1_ + clb_5__2_ + cbx_5__2_ + clb_5__3_ + cbx_5__3_ + clb_5__4_ + cbx_5__4_ + clb_5__5_ + cbx_5__5_ + clb_5__6_ + cbx_5__6_ + clb_5__7_ + cbx_5__7_ + clb_5__8_ + cbx_5__8_ + io_top_5__9_ + sb_5__0_ + cby_5__1_ + sb_5__1_ + cby_5__2_ + sb_5__2_ + cby_5__3_ + sb_5__3_ + cby_5__4_ + sb_5__4_ + cby_5__5_ + sb_5__5_ + cby_5__6_ + sb_5__6_ + cby_5__7_ + sb_5__7_ + cby_5__8_ + sb_5__8_ + io_bottom_6__0_ + cbx_6__0_ + clb_6__1_ + cbx_6__1_ + clb_6__2_ + cbx_6__2_ + clb_6__3_ + cbx_6__3_ + clb_6__4_ + cbx_6__4_ + clb_6__5_ + cbx_6__5_ + clb_6__6_ + cbx_6__6_ + clb_6__7_ + cbx_6__7_ + clb_6__8_ + cbx_6__8_ + io_top_6__9_ + sb_6__0_ + cby_6__1_ + sb_6__1_ + cby_6__2_ + sb_6__2_ + cby_6__3_ + sb_6__3_ + cby_6__4_ + sb_6__4_ + cby_6__5_ + sb_6__5_ + cby_6__6_ + sb_6__6_ + cby_6__7_ + sb_6__7_ + cby_6__8_ + sb_6__8_ + io_bottom_7__0_ + cbx_7__0_ + clb_7__1_ + cbx_7__1_ + clb_7__2_ + cbx_7__2_ + clb_7__3_ + cbx_7__3_ + clb_7__4_ + cbx_7__4_ + clb_7__5_ + cbx_7__5_ + clb_7__6_ + cbx_7__6_ + clb_7__7_ + cbx_7__7_ + clb_7__8_ + cbx_7__8_ + io_top_7__9_ + sb_7__0_ + cby_7__1_ + sb_7__1_ + cby_7__2_ + sb_7__2_ + cby_7__3_ + sb_7__3_ + cby_7__4_ + sb_7__4_ + cby_7__5_ + sb_7__5_ + cby_7__6_ + sb_7__6_ + cby_7__7_ + sb_7__7_ + cby_7__8_ + sb_7__8_ + io_bottom_8__0_ + cbx_8__0_ + clb_8__1_ + cbx_8__1_ + clb_8__2_ + cbx_8__2_ + clb_8__3_ + cbx_8__3_ + clb_8__4_ + cbx_8__4_ + clb_8__5_ + cbx_8__5_ + clb_8__6_ + cbx_8__6_ + clb_8__7_ + cbx_8__7_ + clb_8__8_ + cbx_8__8_ + io_top_8__9_ + sb_8__0_ + cby_8__1_ + sb_8__1_ + cby_8__2_ + sb_8__2_ + cby_8__3_ + sb_8__3_ + cby_8__4_ + sb_8__4_ + cby_8__5_ + sb_8__5_ + cby_8__6_ + sb_8__6_ + cby_8__7_ + sb_8__7_ + cby_8__8_ + sb_8__8_ + io_right_9__1_ + io_right_9__2_ + io_right_9__3_ + io_right_9__4_ + io_right_9__5_ + io_right_9__6_ + io_right_9__7_ + io_right_9__8_ + + + diff --git a/SOFA_A/FPGA88_SOFA_A/scripts/generate_fabric_key.py b/SOFA_A/FPGA88_SOFA_A/scripts/generate_fabric_key.py new file mode 100644 index 0000000..287f751 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/scripts/generate_fabric_key.py @@ -0,0 +1,53 @@ +""" +""" +import argparse +import logging +import os +import pickle +from glob import glob + +import spydrnet as sdn +from spydrnet_physical.util import FabricKeyGenCCFF, FPGAGridGen + +logger = logging.getLogger("spydrnet_logs") + + +def formatter(prog): + ''' + Formatting string + ''' + return argparse.HelpFormatter(prog, max_help_position=60) + + +PROJ_NAME = os.environ["PROJ_NAME"] +RELEASE_DIR = os.environ["RELEASE_DIRECTORY"] +FABRIC_KEY_PATTERN = os.environ["FABRIC_KEY_PATTERN"] +TASK_DIR_NAME = os.environ.get("TASK_DIR_NAME") +LAYOUT = os.environ["LAYOUT"] +TASK_DIR_NAME = os.environ["TASK_DIR_NAME"] +SVG_DIR = f"{RELEASE_DIR}/SVG" +PICKLE_DIR = f"{RELEASE_DIR}/pickle" + + +def main(): + """ + Main method to execute function + """ + # Parse architecture file and get layout block + + # Load the existing grid from generate shapes + fpga = pickle.load( + open(f"{PICKLE_DIR}/{PROJ_NAME}_fpgagridgen.pickle", "rb")) + + fabric_key = FabricKeyGenCCFF(fpga) + fabric_key.create_fabric_key(FABRIC_KEY_PATTERN) + + filename = os.path.join(SVG_DIR, f"{PROJ_NAME}_CCFF_Chain.svg") + fabric_key.render_svg(filename=filename) + fabric_filename = os.path.join( + TASK_DIR_NAME, "flow_inputs", "fabric_key.xml") + fabric_key.save_fabric_key(filename=fabric_filename) + + +if __name__ == "__main__": + main() diff --git a/SOFA_A/FPGA88_SOFA_A/shapes.yaml b/SOFA_A/FPGA88_SOFA_A/shapes.yaml new file mode 100644 index 0000000..7e78b77 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/shapes.yaml @@ -0,0 +1,18 @@ +bottom_cbx_h: 49 +bottom_cbx_w: 457 +cbx11_h: 15 +cbx11_w: 457 +cby11_h: 127 +cby11_w: 160 +clb_h: 127 +clb_w: 457 +grid_bottom_height: 179 +grid_left_width: 352 +grid_right_width: 352 +grid_top_height: 147 +left_cby_h: 127 +left_cby_w: 336 +right_cby_h: 127 +right_cby_w: 336 +top_cbx_h: 52 +top_cbx_w: 457 diff --git a/SOFA_A/Makefile b/SOFA_A/Makefile deleted file mode 100644 index 58c5c72..0000000 --- a/SOFA_A/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -########################################################################################## -########################################################################################## - -SHELL=bash -PYTHON_EXEC=python3.8 -RERUN = 0 -PROJ_NAME=SOFA_A -TB = top -OPTIONS = - -.SILENT: -.ONESHELL: - -.PHONY: runOpenFPGA - -generate_netlist: - echo "Generating OpenFPGA netlist" - source $${OPENFPGA_PATH}/openfpga.sh - cp ${PROJ_NAME}_task/config/task_generation.conf ${PROJ_NAME}_task/config/task.conf - rerun-task ${PROJ_NAME}_task - mkdir -p ${PROJ_NAME}_verilog - cp -r ${PROJ_NAME}_task/latest/*/*/*/SRC/* ${PROJ_NAME}_verilog - -runOpenFPGA: - SECONDS=0 - source config.sh - # ===================== Check Tools ===================== - which python3.8 > /dev/null - if [ $$? -eq 1 ]; then - echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit; - fi - - # =================== Clean Previous Run ================================= - rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME} - (cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf) - - # ===================== Generate Netlist ================================= - (currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir && - run-task $${TASK_DIR_NAME} --remove_run_dir all - run-task $${TASK_DIR_NAME} ${OPTIONS}) - - if [ $$? -eq 1 ]; then - echo "X X X X X X Failed to generate netlist X X X X X X"; exit; - fi - - duration=$$SECONDS - date > runOpenFPGA - echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA - -clean: - rm -rf runOpenFPGA \ No newline at end of file diff --git a/SOFA_A/SOFA_A_task/BENCHMARK b/SOFA_A/SOFA_A_task/BENCHMARK deleted file mode 120000 index 9fed94a..0000000 --- a/SOFA_A/SOFA_A_task/BENCHMARK +++ /dev/null @@ -1 +0,0 @@ -../../BENCHMARK \ No newline at end of file diff --git a/SOFA_A/SOFA_A_verilog/fpga_top.v b/SOFA_A/SOFA_A_verilog/fpga_top.v deleted file mode 100644 index cbdff84..0000000 --- a/SOFA_A/SOFA_A_verilog/fpga_top.v +++ /dev/null @@ -1,580 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Top-level Verilog module for FPGA -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Default net type ----- -`default_nettype none - -// ----- Verilog module for fpga_top ----- -module fpga_top(clk, - Reset, - IO_ISOL_N, - pReset, - prog_clk, - Test_en, - gfpga_pad_EMBEDDED_IO_HD_SOC_IN, - gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, - gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, - ccff_head, - ccff_tail); -//----- GLOBAL PORTS ----- -input [0:0] clk; -//----- GLOBAL PORTS ----- -input [0:0] Reset; -//----- GLOBAL PORTS ----- -input [0:0] IO_ISOL_N; -//----- GLOBAL PORTS ----- -input [0:0] pReset; -//----- GLOBAL PORTS ----- -input [0:0] prog_clk; -//----- GLOBAL PORTS ----- -input [0:0] Test_en; -//----- GPIN PORTS ----- -input [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; -//----- GPOUT PORTS ----- -output [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; -//----- GPOUT PORTS ----- -output [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; -//----- INPUT PORTS ----- -input [0:0] ccff_head; -//----- OUTPUT PORTS ----- -output [0:0] ccff_tail; - -//----- BEGIN wire-connection ports ----- -//----- END wire-connection ports ----- - - -//----- BEGIN Registered ports ----- -//----- END Registered ports ----- - - -wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; -wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; -wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; -wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; -wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_; -wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_; -wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_; -wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_; -wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_; -wire [0:0] cbx_1__0__0_ccff_tail; -wire [0:10] cbx_1__0__0_chanx_left_out; -wire [0:10] cbx_1__0__0_chanx_right_out; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; -wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; -wire [0:0] cbx_1__1__0_ccff_tail; -wire [0:10] cbx_1__1__0_chanx_left_out; -wire [0:10] cbx_1__1__0_chanx_right_out; -wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; -wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; -wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; -wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; -wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_; -wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_; -wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_; -wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_; -wire [0:0] cby_0__1__0_ccff_tail; -wire [0:10] cby_0__1__0_chany_bottom_out; -wire [0:10] cby_0__1__0_chany_top_out; -wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; -wire [0:0] cby_1__1__0_ccff_tail; -wire [0:10] cby_1__1__0_chany_bottom_out; -wire [0:10] cby_1__1__0_chany_top_out; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; -wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; -wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; -wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; -wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; -wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; -wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_; -wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_; -wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_; -wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_; -wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_; -wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_; -wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_; -wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_; -wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_; -wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_; -wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_; -wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_; -wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_; -wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_; -wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_; -wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_; -wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_; -wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_; -wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_; -wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_; -wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_; -wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_sc_out_0_; -wire [0:0] grid_clb_1__1__undriven_right_width_0_height_0_subtile_0__pin_O_15_; -wire [0:0] grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_cin_0_; -wire [0:0] grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_; -wire [0:0] grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_sc_in_0_; -wire [0:0] grid_io_bottom_bottom_0_ccff_tail; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_8__pin_inpad_0_; -wire [0:0] grid_io_left_left_0_ccff_tail; -wire [0:0] grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_; -wire [0:0] grid_io_right_right_0_ccff_tail; -wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_; -wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_; -wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_; -wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_; -wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_; -wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_; -wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_; -wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_; -wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_; -wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_; -wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_; -wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_; -wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_; -wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_; -wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_; -wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_; -wire [0:0] grid_io_top_top_0_ccff_tail; -wire [0:0] sb_0__0__0_ccff_tail; -wire [0:10] sb_0__0__0_chanx_right_out; -wire [0:10] sb_0__0__0_chany_top_out; -wire [0:0] sb_0__1__0_ccff_tail; -wire [0:10] sb_0__1__0_chanx_right_out; -wire [0:10] sb_0__1__0_chany_bottom_out; -wire [0:0] sb_1__0__0_ccff_tail; -wire [0:10] sb_1__0__0_chanx_left_out; -wire [0:10] sb_1__0__0_chany_top_out; -wire [0:0] sb_1__1__0_ccff_tail; -wire [0:10] sb_1__1__0_chanx_left_out; -wire [0:10] sb_1__1__0_chany_bottom_out; - -// ----- BEGIN Local short connections ----- -// ----- END Local short connections ----- -// ----- BEGIN Local output short connections ----- -// ----- END Local output short connections ----- - - grid_io_top_top grid_io_top_top_1__2_ ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:7]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:7]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:7]), - .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), - .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), - .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), - .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), - .bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_), - .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), - .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), - .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__1__0_ccff_tail), - .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), - .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), - .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), - .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), - .bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_), - .bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_), - .bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), - .bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_tail(grid_io_top_top_0_ccff_tail)); - - grid_io_right_right grid_io_right_right_2__1_ ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8:15]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8:15]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8:15]), - .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), - .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), - .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), - .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), - .left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_), - .left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_), - .left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_), - .left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(grid_io_bottom_bottom_0_ccff_tail), - .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), - .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), - .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), - .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), - .left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_), - .left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_), - .left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_), - .left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_tail(grid_io_right_right_0_ccff_tail)); - - grid_io_bottom_bottom grid_io_bottom_bottom_1__0_ ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16:24]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16:24]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16:24]), - .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), - .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), - .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), - .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), - .top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_), - .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), - .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), - .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .top_width_0_height_0_subtile_8__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_), - .ccff_head(ccff_head), - .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), - .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), - .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), - .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), - .top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_), - .top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), - .top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), - .top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .top_width_0_height_0_subtile_8__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_8__pin_inpad_0_), - .ccff_tail(grid_io_bottom_bottom_0_ccff_tail)); - - grid_io_left_left grid_io_left_left_0__1_ ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[25]), - .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), - .ccff_head(cby_0__1__0_ccff_tail), - .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), - .ccff_tail(grid_io_left_left_0_ccff_tail)); - - grid_clb grid_clb_1__1_ ( - .pReset(pReset), - .prog_clk(prog_clk), - .Test_en(Test_en), - .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), - .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), - .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), - .top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), - .top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), - .top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), - .top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), - .top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), - .top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), - .top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), - .top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), - .top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), - .top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), - .top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), - .top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), - .top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), - .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_), - .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_sc_in_0_), - .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_cin_0_), - .right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), - .right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), - .right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), - .right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), - .right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), - .right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), - .right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), - .right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), - .right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), - .right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), - .right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), - .right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), - .right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), - .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), - .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), - .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), - .left_width_0_height_0_subtile_0__pin_reset_0_(Reset), - .left_width_0_height_0_subtile_0__pin_clk_0_(clk), - .ccff_head(cby_1__1__0_ccff_tail), - .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_), - .top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_), - .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), - .top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_), - .top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_), - .top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_), - .top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_), - .top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_), - .right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_), - .right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_), - .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_), - .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_), - .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_), - .right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_), - .right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_), - .right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_1__1__undriven_right_width_0_height_0_subtile_0__pin_O_15_), - .bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_), - .bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_sc_out_0_), - .bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_), - .ccff_tail(ccff_tail)); - - sb_0__0_ sb_0__0_ ( - .pReset(pReset), - .prog_clk(prog_clk), - .chany_top_in(cby_0__1__0_chany_bottom_out[0:10]), - .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), - .chanx_right_in(cbx_1__0__0_chanx_left_out[0:10]), - .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), - .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), - .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), - .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), - .right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_), - .right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), - .right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), - .right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .right_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_8__pin_inpad_0_), - .ccff_head(sb_0__1__0_ccff_tail), - .chany_top_out(sb_0__0__0_chany_top_out[0:10]), - .chanx_right_out(sb_0__0__0_chanx_right_out[0:10]), - .ccff_tail(sb_0__0__0_ccff_tail)); - - sb_0__1_ sb_0__1_ ( - .pReset(pReset), - .prog_clk(prog_clk), - .chanx_right_in(cbx_1__1__0_chanx_left_out[0:10]), - .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), - .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), - .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), - .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), - .right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_), - .right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_), - .right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), - .right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), - .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_), - .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_), - .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), - .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_), - .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_), - .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_), - .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_), - .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_), - .chany_bottom_in(cby_0__1__0_chany_top_out[0:10]), - .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), - .ccff_head(grid_io_top_top_0_ccff_tail), - .chanx_right_out(sb_0__1__0_chanx_right_out[0:10]), - .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:10]), - .ccff_tail(sb_0__1__0_ccff_tail)); - - sb_1__0_ sb_1__0_ ( - .pReset(pReset), - .prog_clk(prog_clk), - .chany_top_in(cby_1__1__0_chany_bottom_out[0:10]), - .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_), - .top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_), - .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_), - .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_), - .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_), - .top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_), - .top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_), - .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), - .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), - .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), - .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), - .top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_), - .top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_), - .top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_), - .top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_), - .chanx_left_in(cbx_1__0__0_chanx_right_out[0:10]), - .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), - .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), - .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), - .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), - .left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_), - .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), - .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), - .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .left_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_8__pin_inpad_0_), - .ccff_head(grid_io_left_left_0_ccff_tail), - .chany_top_out(sb_1__0__0_chany_top_out[0:10]), - .chanx_left_out(sb_1__0__0_chanx_left_out[0:10]), - .ccff_tail(sb_1__0__0_ccff_tail)); - - sb_1__1_ sb_1__1_ ( - .pReset(pReset), - .prog_clk(prog_clk), - .chany_bottom_in(cby_1__1__0_chany_top_out[0:10]), - .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), - .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), - .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), - .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), - .bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_), - .bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_), - .bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_), - .bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_), - .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_), - .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_), - .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_), - .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_), - .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_), - .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_), - .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_), - .chanx_left_in(cbx_1__1__0_chanx_right_out[0:10]), - .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), - .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), - .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), - .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), - .left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_), - .left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_), - .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), - .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), - .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_), - .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_), - .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), - .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_), - .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_), - .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_), - .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_), - .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_), - .ccff_head(grid_io_right_right_0_ccff_tail), - .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:10]), - .chanx_left_out(sb_1__1__0_chanx_left_out[0:10]), - .ccff_tail(sb_1__1__0_ccff_tail)); - - cbx_1__0_ cbx_1__0_ ( - .pReset(pReset), - .prog_clk(prog_clk), - .chanx_left_in(sb_0__0__0_chanx_right_out[0:10]), - .chanx_right_in(sb_1__0__0_chanx_left_out[0:10]), - .ccff_head(sb_1__0__0_ccff_tail), - .chanx_left_out(cbx_1__0__0_chanx_left_out[0:10]), - .chanx_right_out(cbx_1__0__0_chanx_right_out[0:10]), - .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), - .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), - .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), - .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), - .bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_), - .bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), - .bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), - .bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_), - .ccff_tail(cbx_1__0__0_ccff_tail)); - - cbx_1__1_ cbx_1__1_ ( - .pReset(pReset), - .prog_clk(prog_clk), - .chanx_left_in(sb_0__1__0_chanx_right_out[0:10]), - .chanx_right_in(sb_1__1__0_chanx_left_out[0:10]), - .ccff_head(sb_1__1__0_ccff_tail), - .chanx_left_out(cbx_1__1__0_chanx_left_out[0:10]), - .chanx_right_out(cbx_1__1__0_chanx_right_out[0:10]), - .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), - .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), - .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), - .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), - .top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_), - .top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), - .top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), - .top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_), - .bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_), - .ccff_tail(cbx_1__1__0_ccff_tail)); - - cby_0__1_ cby_0__1_ ( - .pReset(pReset), - .prog_clk(prog_clk), - .chany_bottom_in(sb_0__0__0_chany_top_out[0:10]), - .chany_top_in(sb_0__1__0_chany_bottom_out[0:10]), - .ccff_head(sb_0__0__0_ccff_tail), - .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:10]), - .chany_top_out(cby_0__1__0_chany_top_out[0:10]), - .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), - .ccff_tail(cby_0__1__0_ccff_tail)); - - cby_1__1_ cby_1__1_ ( - .pReset(pReset), - .prog_clk(prog_clk), - .chany_bottom_in(sb_1__0__0_chany_top_out[0:10]), - .chany_top_in(sb_1__1__0_chany_bottom_out[0:10]), - .ccff_head(cbx_1__0__0_ccff_tail), - .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:10]), - .chany_top_out(cby_1__1__0_chany_top_out[0:10]), - .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), - .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), - .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), - .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), - .right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_), - .right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_), - .right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_), - .right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_), - .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_), - .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_), - .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_), - .left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_), - .left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_), - .left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_), - .left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_), - .left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_), - .left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_), - .left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_), - .left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_), - .left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_), - .left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_), - .left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_), - .left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_), - .left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_), - .ccff_tail(cby_1__1__0_ccff_tail)); - -endmodule -// ----- END Verilog module for fpga_top ----- - -//----- Default net type ----- -`default_nettype none - - - - diff --git a/SOFA_A/SOFA_A_verilog/lb/grid_io_left_left.v b/SOFA_A/SOFA_A_verilog/lb/grid_io_left_left.v deleted file mode 100644 index b3a4161..0000000 --- a/SOFA_A/SOFA_A_verilog/lb/grid_io_left_left.v +++ /dev/null @@ -1,82 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Verilog modules for physical tile: io_left] -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ----- BEGIN Grid Verilog module: grid_io_left_left ----- -//----- Default net type ----- -`default_nettype none - -// ----- Verilog module for grid_io_left_left ----- -module grid_io_left_left(IO_ISOL_N, - pReset, - prog_clk, - gfpga_pad_EMBEDDED_IO_HD_SOC_IN, - gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, - gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, - right_width_0_height_0_subtile_0__pin_outpad_0_, - ccff_head, - right_width_0_height_0_subtile_0__pin_inpad_0_, - ccff_tail); -//----- GLOBAL PORTS ----- -input [0:0] IO_ISOL_N; -//----- GLOBAL PORTS ----- -input [0:0] pReset; -//----- GLOBAL PORTS ----- -input [0:0] prog_clk; -//----- GPIN PORTS ----- -input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; -//----- GPOUT PORTS ----- -output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; -//----- GPOUT PORTS ----- -output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; -//----- INPUT PORTS ----- -input [0:0] right_width_0_height_0_subtile_0__pin_outpad_0_; -//----- INPUT PORTS ----- -input [0:0] ccff_head; -//----- OUTPUT PORTS ----- -output [0:0] right_width_0_height_0_subtile_0__pin_inpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] ccff_tail; - -//----- BEGIN wire-connection ports ----- -//----- END wire-connection ports ----- - - -//----- BEGIN Registered ports ----- -//----- END Registered ports ----- - - - -// ----- BEGIN Local short connections ----- -// ----- END Local short connections ----- -// ----- BEGIN Local output short connections ----- -// ----- END Local output short connections ----- - - logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .IO_ISOL_N(IO_ISOL_N), - .pReset(pReset), - .prog_clk(prog_clk), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), - .io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_), - .ccff_head(ccff_head), - .io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_), - .ccff_tail(ccff_tail)); - -endmodule -// ----- END Verilog module for grid_io_left_left ----- - -//----- Default net type ----- -`default_nettype none - - - -// ----- END Grid Verilog module: grid_io_left_left ----- - diff --git a/SOFA_A/SOFA_A_verilog/routing/cbx_1__0_.v b/SOFA_A/SOFA_A_verilog/routing/cbx_1__0_.v deleted file mode 100644 index a0e7791..0000000 --- a/SOFA_A/SOFA_A_verilog/routing/cbx_1__0_.v +++ /dev/null @@ -1,320 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Verilog modules for Unique Connection Blocks[1][0] -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Default net type ----- -`default_nettype none - -// ----- Verilog module for cbx_1__0_ ----- -module cbx_1__0_(pReset, - prog_clk, - chanx_left_in, - chanx_right_in, - ccff_head, - chanx_left_out, - chanx_right_out, - bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_, - bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_, - bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_, - bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_, - bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_, - bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_, - bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_, - bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_, - bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_, - ccff_tail); -//----- GLOBAL PORTS ----- -input [0:0] pReset; -//----- GLOBAL PORTS ----- -input [0:0] prog_clk; -//----- INPUT PORTS ----- -input [0:10] chanx_left_in; -//----- INPUT PORTS ----- -input [0:10] chanx_right_in; -//----- INPUT PORTS ----- -input [0:0] ccff_head; -//----- OUTPUT PORTS ----- -output [0:10] chanx_left_out; -//----- OUTPUT PORTS ----- -output [0:10] chanx_right_out; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] ccff_tail; - -//----- BEGIN wire-connection ports ----- -//----- END wire-connection ports ----- - - -//----- BEGIN Registered ports ----- -//----- END Registered ports ----- - - -wire [0:3] mux_top_ipin_0_undriven_sram_inv; -wire [0:3] mux_top_ipin_1_undriven_sram_inv; -wire [0:3] mux_top_ipin_2_undriven_sram_inv; -wire [0:3] mux_top_ipin_3_undriven_sram_inv; -wire [0:3] mux_top_ipin_4_undriven_sram_inv; -wire [0:3] mux_top_ipin_5_undriven_sram_inv; -wire [0:3] mux_top_ipin_6_undriven_sram_inv; -wire [0:3] mux_top_ipin_7_undriven_sram_inv; -wire [0:3] mux_top_ipin_8_undriven_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:3] mux_tree_tapbuf_size10_2_sram; -wire [0:3] mux_tree_tapbuf_size10_3_sram; -wire [0:3] mux_tree_tapbuf_size10_4_sram; -wire [0:3] mux_tree_tapbuf_size10_5_sram; -wire [0:3] mux_tree_tapbuf_size10_6_sram; -wire [0:3] mux_tree_tapbuf_size10_7_sram; -wire [0:3] mux_tree_tapbuf_size10_8_sram; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; - -// ----- BEGIN Local short connections ----- -// ----- Local connection due to Wire 0 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[0] = chanx_left_in[0]; -// ----- Local connection due to Wire 1 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[1] = chanx_left_in[1]; -// ----- Local connection due to Wire 2 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[2] = chanx_left_in[2]; -// ----- Local connection due to Wire 3 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[3] = chanx_left_in[3]; -// ----- Local connection due to Wire 4 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[4] = chanx_left_in[4]; -// ----- Local connection due to Wire 5 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[5] = chanx_left_in[5]; -// ----- Local connection due to Wire 6 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[6] = chanx_left_in[6]; -// ----- Local connection due to Wire 7 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[7] = chanx_left_in[7]; -// ----- Local connection due to Wire 8 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[8] = chanx_left_in[8]; -// ----- Local connection due to Wire 9 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[9] = chanx_left_in[9]; -// ----- Local connection due to Wire 10 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[10] = chanx_left_in[10]; -// ----- Local connection due to Wire 11 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[0] = chanx_right_in[0]; -// ----- Local connection due to Wire 12 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[1] = chanx_right_in[1]; -// ----- Local connection due to Wire 13 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[2] = chanx_right_in[2]; -// ----- Local connection due to Wire 14 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[3] = chanx_right_in[3]; -// ----- Local connection due to Wire 15 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[4] = chanx_right_in[4]; -// ----- Local connection due to Wire 16 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[5] = chanx_right_in[5]; -// ----- Local connection due to Wire 17 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[6] = chanx_right_in[6]; -// ----- Local connection due to Wire 18 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[7] = chanx_right_in[7]; -// ----- Local connection due to Wire 19 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[8] = chanx_right_in[8]; -// ----- Local connection due to Wire 20 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[9] = chanx_right_in[9]; -// ----- Local connection due to Wire 21 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[10] = chanx_right_in[10]; -// ----- END Local short connections ----- -// ----- BEGIN Local output short connections ----- -// ----- END Local output short connections ----- - - mux_tree_tapbuf_size10 mux_top_ipin_0 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[10], chanx_right_in[10]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_1 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7]}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_2 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8]}), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_3 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9]}), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_4 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[10], chanx_right_in[10]}), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_5 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_6 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[8], chanx_right_in[8]}), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_7 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_8 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[10], chanx_right_in[10]}), - .sram(mux_tree_tapbuf_size10_8_sram[0:3]), - .sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_)); - - mux_tree_tapbuf_size10_mem mem_top_ipin_0 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(ccff_head), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_1 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_2 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_3 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_4 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_6 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_7 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail), - .ccff_tail(ccff_tail), - .mem_out(mux_tree_tapbuf_size10_8_sram[0:3])); - -endmodule -// ----- END Verilog module for cbx_1__0_ ----- - -//----- Default net type ----- -`default_nettype none - - - - diff --git a/SOFA_A/SOFA_A_verilog/routing/cbx_1__1_.v b/SOFA_A/SOFA_A_verilog/routing/cbx_1__1_.v deleted file mode 100644 index d320c6a..0000000 --- a/SOFA_A/SOFA_A_verilog/routing/cbx_1__1_.v +++ /dev/null @@ -1,605 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Verilog modules for Unique Connection Blocks[1][1] -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Default net type ----- -`default_nettype none - -// ----- Verilog module for cbx_1__1_ ----- -module cbx_1__1_(pReset, - prog_clk, - chanx_left_in, - chanx_right_in, - ccff_head, - chanx_left_out, - chanx_right_out, - top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_, - top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_, - top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_, - top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_, - top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_, - top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_, - top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_, - top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_, - bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_, - ccff_tail); -//----- GLOBAL PORTS ----- -input [0:0] pReset; -//----- GLOBAL PORTS ----- -input [0:0] prog_clk; -//----- INPUT PORTS ----- -input [0:10] chanx_left_in; -//----- INPUT PORTS ----- -input [0:10] chanx_right_in; -//----- INPUT PORTS ----- -input [0:0] ccff_head; -//----- OUTPUT PORTS ----- -output [0:10] chanx_left_out; -//----- OUTPUT PORTS ----- -output [0:10] chanx_right_out; -//----- OUTPUT PORTS ----- -output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_; -//----- OUTPUT PORTS ----- -output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_; -//----- OUTPUT PORTS ----- -output [0:0] ccff_tail; - -//----- BEGIN wire-connection ports ----- -//----- END wire-connection ports ----- - - -//----- BEGIN Registered ports ----- -//----- END Registered ports ----- - - -wire [0:3] mux_bottom_ipin_0_undriven_sram_inv; -wire [0:3] mux_bottom_ipin_1_undriven_sram_inv; -wire [0:3] mux_bottom_ipin_2_undriven_sram_inv; -wire [0:3] mux_bottom_ipin_3_undriven_sram_inv; -wire [0:3] mux_bottom_ipin_4_undriven_sram_inv; -wire [0:3] mux_bottom_ipin_5_undriven_sram_inv; -wire [0:3] mux_bottom_ipin_6_undriven_sram_inv; -wire [0:3] mux_bottom_ipin_7_undriven_sram_inv; -wire [0:3] mux_top_ipin_0_undriven_sram_inv; -wire [0:3] mux_top_ipin_10_undriven_sram_inv; -wire [0:2] mux_top_ipin_11_undriven_sram_inv; -wire [0:3] mux_top_ipin_12_undriven_sram_inv; -wire [0:2] mux_top_ipin_13_undriven_sram_inv; -wire [0:3] mux_top_ipin_14_undriven_sram_inv; -wire [0:2] mux_top_ipin_15_undriven_sram_inv; -wire [0:2] mux_top_ipin_1_undriven_sram_inv; -wire [0:3] mux_top_ipin_2_undriven_sram_inv; -wire [0:2] mux_top_ipin_3_undriven_sram_inv; -wire [0:3] mux_top_ipin_4_undriven_sram_inv; -wire [0:2] mux_top_ipin_5_undriven_sram_inv; -wire [0:3] mux_top_ipin_6_undriven_sram_inv; -wire [0:2] mux_top_ipin_7_undriven_sram_inv; -wire [0:3] mux_top_ipin_8_undriven_sram_inv; -wire [0:2] mux_top_ipin_9_undriven_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_10_sram; -wire [0:3] mux_tree_tapbuf_size10_11_sram; -wire [0:3] mux_tree_tapbuf_size10_12_sram; -wire [0:3] mux_tree_tapbuf_size10_13_sram; -wire [0:3] mux_tree_tapbuf_size10_14_sram; -wire [0:3] mux_tree_tapbuf_size10_15_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:3] mux_tree_tapbuf_size10_2_sram; -wire [0:3] mux_tree_tapbuf_size10_3_sram; -wire [0:3] mux_tree_tapbuf_size10_4_sram; -wire [0:3] mux_tree_tapbuf_size10_5_sram; -wire [0:3] mux_tree_tapbuf_size10_6_sram; -wire [0:3] mux_tree_tapbuf_size10_7_sram; -wire [0:3] mux_tree_tapbuf_size10_8_sram; -wire [0:3] mux_tree_tapbuf_size10_9_sram; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_12_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_13_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_14_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_15_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_2_sram; -wire [0:2] mux_tree_tapbuf_size6_3_sram; -wire [0:2] mux_tree_tapbuf_size6_4_sram; -wire [0:2] mux_tree_tapbuf_size6_5_sram; -wire [0:2] mux_tree_tapbuf_size6_6_sram; -wire [0:2] mux_tree_tapbuf_size6_7_sram; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; - -// ----- BEGIN Local short connections ----- -// ----- Local connection due to Wire 0 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[0] = chanx_left_in[0]; -// ----- Local connection due to Wire 1 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[1] = chanx_left_in[1]; -// ----- Local connection due to Wire 2 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[2] = chanx_left_in[2]; -// ----- Local connection due to Wire 3 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[3] = chanx_left_in[3]; -// ----- Local connection due to Wire 4 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[4] = chanx_left_in[4]; -// ----- Local connection due to Wire 5 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[5] = chanx_left_in[5]; -// ----- Local connection due to Wire 6 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[6] = chanx_left_in[6]; -// ----- Local connection due to Wire 7 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[7] = chanx_left_in[7]; -// ----- Local connection due to Wire 8 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[8] = chanx_left_in[8]; -// ----- Local connection due to Wire 9 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[9] = chanx_left_in[9]; -// ----- Local connection due to Wire 10 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_right_out[10] = chanx_left_in[10]; -// ----- Local connection due to Wire 11 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[0] = chanx_right_in[0]; -// ----- Local connection due to Wire 12 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[1] = chanx_right_in[1]; -// ----- Local connection due to Wire 13 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[2] = chanx_right_in[2]; -// ----- Local connection due to Wire 14 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[3] = chanx_right_in[3]; -// ----- Local connection due to Wire 15 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[4] = chanx_right_in[4]; -// ----- Local connection due to Wire 16 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[5] = chanx_right_in[5]; -// ----- Local connection due to Wire 17 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[6] = chanx_right_in[6]; -// ----- Local connection due to Wire 18 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[7] = chanx_right_in[7]; -// ----- Local connection due to Wire 19 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[8] = chanx_right_in[8]; -// ----- Local connection due to Wire 20 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[9] = chanx_right_in[9]; -// ----- Local connection due to Wire 21 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chanx_left_out[10] = chanx_right_in[10]; -// ----- END Local short connections ----- -// ----- BEGIN Local output short connections ----- -// ----- END Local output short connections ----- - - mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[10], chanx_right_in[10]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_bottom_ipin_0_undriven_sram_inv[0:3]), - .out(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_bottom_ipin_1 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7]}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_bottom_ipin_1_undriven_sram_inv[0:3]), - .out(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_bottom_ipin_2 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8]}), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_bottom_ipin_2_undriven_sram_inv[0:3]), - .out(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_bottom_ipin_3 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9]}), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_bottom_ipin_3_undriven_sram_inv[0:3]), - .out(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_bottom_ipin_4 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[10], chanx_right_in[10]}), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_bottom_ipin_4_undriven_sram_inv[0:3]), - .out(top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_bottom_ipin_5 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_bottom_ipin_5_undriven_sram_inv[0:3]), - .out(top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_bottom_ipin_6 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[8], chanx_right_in[8]}), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_bottom_ipin_6_undriven_sram_inv[0:3]), - .out(top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_bottom_ipin_7 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_bottom_ipin_7_undriven_sram_inv[0:3]), - .out(top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_0 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[10], chanx_right_in[10]}), - .sram(mux_tree_tapbuf_size10_8_sram[0:3]), - .sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_2 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7]}), - .sram(mux_tree_tapbuf_size10_9_sram[0:3]), - .sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_4 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9]}), - .sram(mux_tree_tapbuf_size10_10_sram[0:3]), - .sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_6 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}), - .sram(mux_tree_tapbuf_size10_11_sram[0:3]), - .sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_8 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}), - .sram(mux_tree_tapbuf_size10_12_sram[0:3]), - .sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_10 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[10], chanx_right_in[10]}), - .sram(mux_tree_tapbuf_size10_13_sram[0:3]), - .sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_12 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8]}), - .sram(mux_tree_tapbuf_size10_14_sram[0:3]), - .sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_)); - - mux_tree_tapbuf_size10 mux_top_ipin_14 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[10], chanx_right_in[10]}), - .sram(mux_tree_tapbuf_size10_15_sram[0:3]), - .sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_)); - - mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(ccff_head), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_bottom_ipin_1 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_bottom_ipin_2 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_bottom_ipin_3 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_bottom_ipin_4 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_bottom_ipin_5 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_bottom_ipin_6 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_bottom_ipin_7 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_0 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_8_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_2 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_9_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_4 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_10_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_6 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_11_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_12_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_12_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_10 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_13_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_13_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_12 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_14_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_14_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_top_ipin_14 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_15_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_15_sram[0:3])); - - mux_tree_tapbuf_size6 mux_top_ipin_1 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_top_ipin_1_undriven_sram_inv[0:2]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_)); - - mux_tree_tapbuf_size6 mux_top_ipin_3 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_top_ipin_3_undriven_sram_inv[0:2]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_)); - - mux_tree_tapbuf_size6 mux_top_ipin_5 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[6], chanx_right_in[6]}), - .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_top_ipin_5_undriven_sram_inv[0:2]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_)); - - mux_tree_tapbuf_size6 mux_top_ipin_7 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[8], chanx_right_in[8]}), - .sram(mux_tree_tapbuf_size6_3_sram[0:2]), - .sram_inv(mux_top_ipin_7_undriven_sram_inv[0:2]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_)); - - mux_tree_tapbuf_size6 mux_top_ipin_9 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[10], chanx_right_in[10]}), - .sram(mux_tree_tapbuf_size6_4_sram[0:2]), - .sram_inv(mux_top_ipin_9_undriven_sram_inv[0:2]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_)); - - mux_tree_tapbuf_size6 mux_top_ipin_11 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3]}), - .sram(mux_tree_tapbuf_size6_5_sram[0:2]), - .sram_inv(mux_top_ipin_11_undriven_sram_inv[0:2]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_)); - - mux_tree_tapbuf_size6 mux_top_ipin_13 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[5], chanx_right_in[5]}), - .sram(mux_tree_tapbuf_size6_6_sram[0:2]), - .sram_inv(mux_top_ipin_13_undriven_sram_inv[0:2]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_)); - - mux_tree_tapbuf_size6 mux_top_ipin_15 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7]}), - .sram(mux_tree_tapbuf_size6_7_sram[0:2]), - .sram_inv(mux_top_ipin_15_undriven_sram_inv[0:2]), - .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_)); - - mux_tree_tapbuf_size6_mem mem_top_ipin_1 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2])); - - mux_tree_tapbuf_size6_mem mem_top_ipin_3 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2])); - - mux_tree_tapbuf_size6_mem mem_top_ipin_5 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2])); - - mux_tree_tapbuf_size6_mem mem_top_ipin_7 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), - .mem_out(mux_tree_tapbuf_size6_3_sram[0:2])); - - mux_tree_tapbuf_size6_mem mem_top_ipin_9 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_12_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), - .mem_out(mux_tree_tapbuf_size6_4_sram[0:2])); - - mux_tree_tapbuf_size6_mem mem_top_ipin_11 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_13_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), - .mem_out(mux_tree_tapbuf_size6_5_sram[0:2])); - - mux_tree_tapbuf_size6_mem mem_top_ipin_13 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_14_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), - .mem_out(mux_tree_tapbuf_size6_6_sram[0:2])); - - mux_tree_tapbuf_size6_mem mem_top_ipin_15 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_15_ccff_tail), - .ccff_tail(ccff_tail), - .mem_out(mux_tree_tapbuf_size6_7_sram[0:2])); - -endmodule -// ----- END Verilog module for cbx_1__1_ ----- - -//----- Default net type ----- -`default_nettype none - - - - diff --git a/SOFA_A/SOFA_A_verilog/routing/cby_0__1_.v b/SOFA_A/SOFA_A_verilog/routing/cby_0__1_.v deleted file mode 100644 index 2d240ac..0000000 --- a/SOFA_A/SOFA_A_verilog/routing/cby_0__1_.v +++ /dev/null @@ -1,168 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Verilog modules for Unique Connection Blocks[0][1] -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Default net type ----- -`default_nettype none - -// ----- Verilog module for cby_0__1_ ----- -module cby_0__1_(pReset, - prog_clk, - chany_bottom_in, - chany_top_in, - ccff_head, - chany_bottom_out, - chany_top_out, - left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_, - ccff_tail); -//----- GLOBAL PORTS ----- -input [0:0] pReset; -//----- GLOBAL PORTS ----- -input [0:0] prog_clk; -//----- INPUT PORTS ----- -input [0:10] chany_bottom_in; -//----- INPUT PORTS ----- -input [0:10] chany_top_in; -//----- INPUT PORTS ----- -input [0:0] ccff_head; -//----- OUTPUT PORTS ----- -output [0:10] chany_bottom_out; -//----- OUTPUT PORTS ----- -output [0:10] chany_top_out; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] ccff_tail; - -//----- BEGIN wire-connection ports ----- -//----- END wire-connection ports ----- - - -//----- BEGIN Registered ports ----- -//----- END Registered ports ----- - - -wire [0:3] mux_right_ipin_0_undriven_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_0_sram; - -// ----- BEGIN Local short connections ----- -// ----- Local connection due to Wire 0 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[0] = chany_bottom_in[0]; -// ----- Local connection due to Wire 1 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[1] = chany_bottom_in[1]; -// ----- Local connection due to Wire 2 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[2] = chany_bottom_in[2]; -// ----- Local connection due to Wire 3 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[3] = chany_bottom_in[3]; -// ----- Local connection due to Wire 4 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[4] = chany_bottom_in[4]; -// ----- Local connection due to Wire 5 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[5] = chany_bottom_in[5]; -// ----- Local connection due to Wire 6 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[6] = chany_bottom_in[6]; -// ----- Local connection due to Wire 7 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[7] = chany_bottom_in[7]; -// ----- Local connection due to Wire 8 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[8] = chany_bottom_in[8]; -// ----- Local connection due to Wire 9 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[9] = chany_bottom_in[9]; -// ----- Local connection due to Wire 10 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[10] = chany_bottom_in[10]; -// ----- Local connection due to Wire 11 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[0] = chany_top_in[0]; -// ----- Local connection due to Wire 12 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[1] = chany_top_in[1]; -// ----- Local connection due to Wire 13 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[2] = chany_top_in[2]; -// ----- Local connection due to Wire 14 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[3] = chany_top_in[3]; -// ----- Local connection due to Wire 15 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[4] = chany_top_in[4]; -// ----- Local connection due to Wire 16 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[5] = chany_top_in[5]; -// ----- Local connection due to Wire 17 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[6] = chany_top_in[6]; -// ----- Local connection due to Wire 18 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[7] = chany_top_in[7]; -// ----- Local connection due to Wire 19 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[8] = chany_top_in[8]; -// ----- Local connection due to Wire 20 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[9] = chany_top_in[9]; -// ----- Local connection due to Wire 21 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[10] = chany_top_in[10]; -// ----- END Local short connections ----- -// ----- BEGIN Local output short connections ----- -// ----- END Local output short connections ----- - - mux_tree_tapbuf_size10 mux_right_ipin_0 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[10], chany_top_in[10]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_)); - - mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(ccff_head), - .ccff_tail(ccff_tail), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3])); - -endmodule -// ----- END Verilog module for cby_0__1_ ----- - -//----- Default net type ----- -`default_nettype none - - - - diff --git a/SOFA_A/SOFA_A_verilog/routing/cby_1__1_.v b/SOFA_A/SOFA_A_verilog/routing/cby_1__1_.v deleted file mode 100644 index 3ae44b5..0000000 --- a/SOFA_A/SOFA_A_verilog/routing/cby_1__1_.v +++ /dev/null @@ -1,605 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Verilog modules for Unique Connection Blocks[1][1] -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Default net type ----- -`default_nettype none - -// ----- Verilog module for cby_1__1_ ----- -module cby_1__1_(pReset, - prog_clk, - chany_bottom_in, - chany_top_in, - ccff_head, - chany_bottom_out, - chany_top_out, - right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_, - right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_, - right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_, - right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_, - right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_, - right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_, - right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_, - right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_, - left_grid_right_width_0_height_0_subtile_0__pin_I4_0_, - left_grid_right_width_0_height_0_subtile_0__pin_I4_1_, - left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_, - left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_, - left_grid_right_width_0_height_0_subtile_0__pin_I5_0_, - left_grid_right_width_0_height_0_subtile_0__pin_I5_1_, - left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_, - left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_, - left_grid_right_width_0_height_0_subtile_0__pin_I6_0_, - left_grid_right_width_0_height_0_subtile_0__pin_I6_1_, - left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_, - left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_, - left_grid_right_width_0_height_0_subtile_0__pin_I7_0_, - left_grid_right_width_0_height_0_subtile_0__pin_I7_1_, - left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_, - left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_, - ccff_tail); -//----- GLOBAL PORTS ----- -input [0:0] pReset; -//----- GLOBAL PORTS ----- -input [0:0] prog_clk; -//----- INPUT PORTS ----- -input [0:10] chany_bottom_in; -//----- INPUT PORTS ----- -input [0:10] chany_top_in; -//----- INPUT PORTS ----- -input [0:0] ccff_head; -//----- OUTPUT PORTS ----- -output [0:10] chany_bottom_out; -//----- OUTPUT PORTS ----- -output [0:10] chany_top_out; -//----- OUTPUT PORTS ----- -output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4_0_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4_1_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5_0_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5_1_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6_0_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6_1_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7_0_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7_1_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_; -//----- OUTPUT PORTS ----- -output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_; -//----- OUTPUT PORTS ----- -output [0:0] ccff_tail; - -//----- BEGIN wire-connection ports ----- -//----- END wire-connection ports ----- - - -//----- BEGIN Registered ports ----- -//----- END Registered ports ----- - - -wire [0:3] mux_left_ipin_0_undriven_sram_inv; -wire [0:3] mux_left_ipin_1_undriven_sram_inv; -wire [0:3] mux_left_ipin_2_undriven_sram_inv; -wire [0:3] mux_left_ipin_3_undriven_sram_inv; -wire [0:3] mux_left_ipin_4_undriven_sram_inv; -wire [0:3] mux_left_ipin_5_undriven_sram_inv; -wire [0:3] mux_left_ipin_6_undriven_sram_inv; -wire [0:3] mux_left_ipin_7_undriven_sram_inv; -wire [0:3] mux_right_ipin_0_undriven_sram_inv; -wire [0:3] mux_right_ipin_10_undriven_sram_inv; -wire [0:2] mux_right_ipin_11_undriven_sram_inv; -wire [0:3] mux_right_ipin_12_undriven_sram_inv; -wire [0:2] mux_right_ipin_13_undriven_sram_inv; -wire [0:3] mux_right_ipin_14_undriven_sram_inv; -wire [0:2] mux_right_ipin_15_undriven_sram_inv; -wire [0:2] mux_right_ipin_1_undriven_sram_inv; -wire [0:3] mux_right_ipin_2_undriven_sram_inv; -wire [0:2] mux_right_ipin_3_undriven_sram_inv; -wire [0:3] mux_right_ipin_4_undriven_sram_inv; -wire [0:2] mux_right_ipin_5_undriven_sram_inv; -wire [0:3] mux_right_ipin_6_undriven_sram_inv; -wire [0:2] mux_right_ipin_7_undriven_sram_inv; -wire [0:3] mux_right_ipin_8_undriven_sram_inv; -wire [0:2] mux_right_ipin_9_undriven_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_10_sram; -wire [0:3] mux_tree_tapbuf_size10_11_sram; -wire [0:3] mux_tree_tapbuf_size10_12_sram; -wire [0:3] mux_tree_tapbuf_size10_13_sram; -wire [0:3] mux_tree_tapbuf_size10_14_sram; -wire [0:3] mux_tree_tapbuf_size10_15_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:3] mux_tree_tapbuf_size10_2_sram; -wire [0:3] mux_tree_tapbuf_size10_3_sram; -wire [0:3] mux_tree_tapbuf_size10_4_sram; -wire [0:3] mux_tree_tapbuf_size10_5_sram; -wire [0:3] mux_tree_tapbuf_size10_6_sram; -wire [0:3] mux_tree_tapbuf_size10_7_sram; -wire [0:3] mux_tree_tapbuf_size10_8_sram; -wire [0:3] mux_tree_tapbuf_size10_9_sram; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_12_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_13_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_14_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_15_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_2_sram; -wire [0:2] mux_tree_tapbuf_size6_3_sram; -wire [0:2] mux_tree_tapbuf_size6_4_sram; -wire [0:2] mux_tree_tapbuf_size6_5_sram; -wire [0:2] mux_tree_tapbuf_size6_6_sram; -wire [0:2] mux_tree_tapbuf_size6_7_sram; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; - -// ----- BEGIN Local short connections ----- -// ----- Local connection due to Wire 0 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[0] = chany_bottom_in[0]; -// ----- Local connection due to Wire 1 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[1] = chany_bottom_in[1]; -// ----- Local connection due to Wire 2 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[2] = chany_bottom_in[2]; -// ----- Local connection due to Wire 3 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[3] = chany_bottom_in[3]; -// ----- Local connection due to Wire 4 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[4] = chany_bottom_in[4]; -// ----- Local connection due to Wire 5 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[5] = chany_bottom_in[5]; -// ----- Local connection due to Wire 6 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[6] = chany_bottom_in[6]; -// ----- Local connection due to Wire 7 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[7] = chany_bottom_in[7]; -// ----- Local connection due to Wire 8 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[8] = chany_bottom_in[8]; -// ----- Local connection due to Wire 9 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[9] = chany_bottom_in[9]; -// ----- Local connection due to Wire 10 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[10] = chany_bottom_in[10]; -// ----- Local connection due to Wire 11 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[0] = chany_top_in[0]; -// ----- Local connection due to Wire 12 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[1] = chany_top_in[1]; -// ----- Local connection due to Wire 13 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[2] = chany_top_in[2]; -// ----- Local connection due to Wire 14 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[3] = chany_top_in[3]; -// ----- Local connection due to Wire 15 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[4] = chany_top_in[4]; -// ----- Local connection due to Wire 16 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[5] = chany_top_in[5]; -// ----- Local connection due to Wire 17 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[6] = chany_top_in[6]; -// ----- Local connection due to Wire 18 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[7] = chany_top_in[7]; -// ----- Local connection due to Wire 19 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[8] = chany_top_in[8]; -// ----- Local connection due to Wire 20 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[9] = chany_top_in[9]; -// ----- Local connection due to Wire 21 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[10] = chany_top_in[10]; -// ----- END Local short connections ----- -// ----- BEGIN Local output short connections ----- -// ----- END Local output short connections ----- - - mux_tree_tapbuf_size10 mux_left_ipin_0 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[10], chany_top_in[10]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_left_ipin_0_undriven_sram_inv[0:3]), - .out(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_left_ipin_1 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7]}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_left_ipin_1_undriven_sram_inv[0:3]), - .out(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_left_ipin_2 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8]}), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_left_ipin_2_undriven_sram_inv[0:3]), - .out(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_left_ipin_3 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9]}), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_left_ipin_3_undriven_sram_inv[0:3]), - .out(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_left_ipin_4 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[10], chany_top_in[10]}), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_left_ipin_4_undriven_sram_inv[0:3]), - .out(right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_left_ipin_5 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[7], chany_top_in[7]}), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_left_ipin_5_undriven_sram_inv[0:3]), - .out(right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_left_ipin_6 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[8], chany_top_in[8]}), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_left_ipin_6_undriven_sram_inv[0:3]), - .out(right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_left_ipin_7 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[9], chany_top_in[9]}), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_left_ipin_7_undriven_sram_inv[0:3]), - .out(right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_)); - - mux_tree_tapbuf_size10 mux_right_ipin_0 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[10], chany_top_in[10]}), - .sram(mux_tree_tapbuf_size10_8_sram[0:3]), - .sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_)); - - mux_tree_tapbuf_size10 mux_right_ipin_2 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7]}), - .sram(mux_tree_tapbuf_size10_9_sram[0:3]), - .sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_)); - - mux_tree_tapbuf_size10 mux_right_ipin_4 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9]}), - .sram(mux_tree_tapbuf_size10_10_sram[0:3]), - .sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_)); - - mux_tree_tapbuf_size10 mux_right_ipin_6 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[7], chany_top_in[7]}), - .sram(mux_tree_tapbuf_size10_11_sram[0:3]), - .sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_)); - - mux_tree_tapbuf_size10 mux_right_ipin_8 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[9], chany_top_in[9]}), - .sram(mux_tree_tapbuf_size10_12_sram[0:3]), - .sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_)); - - mux_tree_tapbuf_size10 mux_right_ipin_10 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[10], chany_top_in[10]}), - .sram(mux_tree_tapbuf_size10_13_sram[0:3]), - .sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_)); - - mux_tree_tapbuf_size10 mux_right_ipin_12 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8]}), - .sram(mux_tree_tapbuf_size10_14_sram[0:3]), - .sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_)); - - mux_tree_tapbuf_size10 mux_right_ipin_14 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[10], chany_top_in[10]}), - .sram(mux_tree_tapbuf_size10_15_sram[0:3]), - .sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_)); - - mux_tree_tapbuf_size10_mem mem_left_ipin_0 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(ccff_head), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_left_ipin_1 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_left_ipin_2 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_left_ipin_3 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_left_ipin_4 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_left_ipin_5 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_left_ipin_6 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_left_ipin_7 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_8_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_right_ipin_2 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_9_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_right_ipin_4 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_10_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_right_ipin_6 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_11_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_12_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_12_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_right_ipin_10 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_13_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_13_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_right_ipin_12 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_14_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_14_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_right_ipin_14 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_15_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_15_sram[0:3])); - - mux_tree_tapbuf_size6 mux_right_ipin_1 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_right_ipin_1_undriven_sram_inv[0:2]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_)); - - mux_tree_tapbuf_size6 mux_right_ipin_3 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_right_ipin_3_undriven_sram_inv[0:2]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_)); - - mux_tree_tapbuf_size6 mux_right_ipin_5 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}), - .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_right_ipin_5_undriven_sram_inv[0:2]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_)); - - mux_tree_tapbuf_size6 mux_right_ipin_7 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[8], chany_top_in[8]}), - .sram(mux_tree_tapbuf_size6_3_sram[0:2]), - .sram_inv(mux_right_ipin_7_undriven_sram_inv[0:2]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_)); - - mux_tree_tapbuf_size6 mux_right_ipin_9 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[10], chany_top_in[10]}), - .sram(mux_tree_tapbuf_size6_4_sram[0:2]), - .sram_inv(mux_right_ipin_9_undriven_sram_inv[0:2]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_)); - - mux_tree_tapbuf_size6 mux_right_ipin_11 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3]}), - .sram(mux_tree_tapbuf_size6_5_sram[0:2]), - .sram_inv(mux_right_ipin_11_undriven_sram_inv[0:2]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_)); - - mux_tree_tapbuf_size6 mux_right_ipin_13 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[5], chany_top_in[5]}), - .sram(mux_tree_tapbuf_size6_6_sram[0:2]), - .sram_inv(mux_right_ipin_13_undriven_sram_inv[0:2]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_)); - - mux_tree_tapbuf_size6 mux_right_ipin_15 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7]}), - .sram(mux_tree_tapbuf_size6_7_sram[0:2]), - .sram_inv(mux_right_ipin_15_undriven_sram_inv[0:2]), - .out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_)); - - mux_tree_tapbuf_size6_mem mem_right_ipin_1 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2])); - - mux_tree_tapbuf_size6_mem mem_right_ipin_3 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2])); - - mux_tree_tapbuf_size6_mem mem_right_ipin_5 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2])); - - mux_tree_tapbuf_size6_mem mem_right_ipin_7 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), - .mem_out(mux_tree_tapbuf_size6_3_sram[0:2])); - - mux_tree_tapbuf_size6_mem mem_right_ipin_9 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_12_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), - .mem_out(mux_tree_tapbuf_size6_4_sram[0:2])); - - mux_tree_tapbuf_size6_mem mem_right_ipin_11 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_13_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), - .mem_out(mux_tree_tapbuf_size6_5_sram[0:2])); - - mux_tree_tapbuf_size6_mem mem_right_ipin_13 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_14_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), - .mem_out(mux_tree_tapbuf_size6_6_sram[0:2])); - - mux_tree_tapbuf_size6_mem mem_right_ipin_15 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_15_ccff_tail), - .ccff_tail(ccff_tail), - .mem_out(mux_tree_tapbuf_size6_7_sram[0:2])); - -endmodule -// ----- END Verilog module for cby_1__1_ ----- - -//----- Default net type ----- -`default_nettype none - - - - diff --git a/SOFA_A/SOFA_A_verilog/routing/sb_0__0_.v b/SOFA_A/SOFA_A_verilog/routing/sb_0__0_.v deleted file mode 100644 index 8cce511..0000000 --- a/SOFA_A/SOFA_A_verilog/routing/sb_0__0_.v +++ /dev/null @@ -1,346 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Verilog modules for Unique Switch Blocks[0][0] -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Default net type ----- -`default_nettype none - -// ----- Verilog module for sb_0__0_ ----- -module sb_0__0_(pReset, - prog_clk, - chany_top_in, - top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, - chanx_right_in, - right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, - right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, - right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, - right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, - right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, - right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, - right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, - right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, - right_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_, - ccff_head, - chany_top_out, - chanx_right_out, - ccff_tail); -//----- GLOBAL PORTS ----- -input [0:0] pReset; -//----- GLOBAL PORTS ----- -input [0:0] prog_clk; -//----- INPUT PORTS ----- -input [0:10] chany_top_in; -//----- INPUT PORTS ----- -input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:10] chanx_right_in; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] ccff_head; -//----- OUTPUT PORTS ----- -output [0:10] chany_top_out; -//----- OUTPUT PORTS ----- -output [0:10] chanx_right_out; -//----- OUTPUT PORTS ----- -output [0:0] ccff_tail; - -//----- BEGIN wire-connection ports ----- -//----- END wire-connection ports ----- - - -//----- BEGIN Registered ports ----- -//----- END Registered ports ----- - - -wire [0:3] mux_right_track_0_undriven_sram_inv; -wire [0:1] mux_right_track_10_undriven_sram_inv; -wire [0:1] mux_right_track_12_undriven_sram_inv; -wire [0:1] mux_right_track_14_undriven_sram_inv; -wire [0:1] mux_right_track_16_undriven_sram_inv; -wire [0:1] mux_right_track_18_undriven_sram_inv; -wire [0:1] mux_right_track_20_undriven_sram_inv; -wire [0:3] mux_right_track_2_undriven_sram_inv; -wire [0:1] mux_right_track_4_undriven_sram_inv; -wire [0:1] mux_right_track_6_undriven_sram_inv; -wire [0:1] mux_right_track_8_undriven_sram_inv; -wire [0:1] mux_top_track_0_undriven_sram_inv; -wire [0:1] mux_top_track_2_undriven_sram_inv; -wire [0:1] mux_top_track_4_undriven_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_10_sram; -wire [0:1] mux_tree_tapbuf_size2_11_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:1] mux_tree_tapbuf_size2_5_sram; -wire [0:1] mux_tree_tapbuf_size2_6_sram; -wire [0:1] mux_tree_tapbuf_size2_7_sram; -wire [0:1] mux_tree_tapbuf_size2_8_sram; -wire [0:1] mux_tree_tapbuf_size2_9_sram; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; - -// ----- BEGIN Local short connections ----- -// ----- Local connection due to Wire 12 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[10] = chanx_right_in[0]; -// ----- Local connection due to Wire 16 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[3] = chanx_right_in[4]; -// ----- Local connection due to Wire 17 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[4] = chanx_right_in[5]; -// ----- Local connection due to Wire 18 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[5] = chanx_right_in[6]; -// ----- Local connection due to Wire 19 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[6] = chanx_right_in[7]; -// ----- Local connection due to Wire 20 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[7] = chanx_right_in[8]; -// ----- Local connection due to Wire 21 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[8] = chanx_right_in[9]; -// ----- Local connection due to Wire 22 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_top_out[9] = chanx_right_in[10]; -// ----- END Local short connections ----- -// ----- BEGIN Local output short connections ----- -// ----- END Local output short connections ----- - - mux_tree_tapbuf_size2 mux_top_track_0 ( - .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[1]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_top_track_0_undriven_sram_inv[0:1]), - .out(chany_top_out[0])); - - mux_tree_tapbuf_size2 mux_top_track_2 ( - .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[2]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_top_track_2_undriven_sram_inv[0:1]), - .out(chany_top_out[1])); - - mux_tree_tapbuf_size2 mux_top_track_4 ( - .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[3]}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_top_track_4_undriven_sram_inv[0:1]), - .out(chany_top_out[2])); - - mux_tree_tapbuf_size2 mux_right_track_4 ( - .in({chany_top_in[1], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_right_track_4_undriven_sram_inv[0:1]), - .out(chanx_right_out[2])); - - mux_tree_tapbuf_size2 mux_right_track_6 ( - .in({chany_top_in[2], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_right_track_6_undriven_sram_inv[0:1]), - .out(chanx_right_out[3])); - - mux_tree_tapbuf_size2 mux_right_track_8 ( - .in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_right_track_8_undriven_sram_inv[0:1]), - .out(chanx_right_out[4])); - - mux_tree_tapbuf_size2 mux_right_track_10 ( - .in({chany_top_in[4], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_right_track_10_undriven_sram_inv[0:1]), - .out(chanx_right_out[5])); - - mux_tree_tapbuf_size2 mux_right_track_12 ( - .in({chany_top_in[5], right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_right_track_12_undriven_sram_inv[0:1]), - .out(chanx_right_out[6])); - - mux_tree_tapbuf_size2 mux_right_track_14 ( - .in({chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_right_track_14_undriven_sram_inv[0:1]), - .out(chanx_right_out[7])); - - mux_tree_tapbuf_size2 mux_right_track_16 ( - .in({chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_right_track_16_undriven_sram_inv[0:1]), - .out(chanx_right_out[8])); - - mux_tree_tapbuf_size2 mux_right_track_18 ( - .in({chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_right_track_18_undriven_sram_inv[0:1]), - .out(chanx_right_out[9])); - - mux_tree_tapbuf_size2 mux_right_track_20 ( - .in({chany_top_in[9], right_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_right_track_20_undriven_sram_inv[0:1]), - .out(chanx_right_out[10])); - - mux_tree_tapbuf_size2_mem mem_top_track_0 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(ccff_head), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_2 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_4 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_right_track_4 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_right_track_6 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_right_track_8 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_right_track_10 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_right_track_12 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_right_track_14 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_right_track_16 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_right_track_18 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_right_track_20 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), - .ccff_tail(ccff_tail), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1])); - - mux_tree_tapbuf_size10 mux_right_track_0 ( - .in({chany_top_in[10], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_right_track_0_undriven_sram_inv[0:3]), - .out(chanx_right_out[0])); - - mux_tree_tapbuf_size10 mux_right_track_2 ( - .in({chany_top_in[0], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_right_track_2_undriven_sram_inv[0:3]), - .out(chanx_right_out[1])); - - mux_tree_tapbuf_size10_mem mem_right_track_0 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_right_track_2 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3])); - -endmodule -// ----- END Verilog module for sb_0__0_ ----- - -//----- Default net type ----- -`default_nettype none - - - diff --git a/SOFA_A/SOFA_A_verilog/routing/sb_0__1_.v b/SOFA_A/SOFA_A_verilog/routing/sb_0__1_.v deleted file mode 100644 index 987018d..0000000 --- a/SOFA_A/SOFA_A_verilog/routing/sb_0__1_.v +++ /dev/null @@ -1,367 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Verilog modules for Unique Switch Blocks[0][1] -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Default net type ----- -`default_nettype none - -// ----- Verilog module for sb_0__1_ ----- -module sb_0__1_(pReset, - prog_clk, - chanx_right_in, - right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, - right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, - right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, - right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, - right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, - right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, - right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, - right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, - right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, - right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, - right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, - right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, - right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, - right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, - right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, - right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, - chany_bottom_in, - bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, - ccff_head, - chanx_right_out, - chany_bottom_out, - ccff_tail); -//----- GLOBAL PORTS ----- -input [0:0] pReset; -//----- GLOBAL PORTS ----- -input [0:0] prog_clk; -//----- INPUT PORTS ----- -input [0:10] chanx_right_in; -//----- INPUT PORTS ----- -input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; -//----- INPUT PORTS ----- -input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; -//----- INPUT PORTS ----- -input [0:10] chany_bottom_in; -//----- INPUT PORTS ----- -input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] ccff_head; -//----- OUTPUT PORTS ----- -output [0:10] chanx_right_out; -//----- OUTPUT PORTS ----- -output [0:10] chany_bottom_out; -//----- OUTPUT PORTS ----- -output [0:0] ccff_tail; - -//----- BEGIN wire-connection ports ----- -//----- END wire-connection ports ----- - - -//----- BEGIN Registered ports ----- -//----- END Registered ports ----- - - -wire [0:1] mux_bottom_track_1_undriven_sram_inv; -wire [0:1] mux_bottom_track_3_undriven_sram_inv; -wire [0:1] mux_bottom_track_5_undriven_sram_inv; -wire [0:4] mux_right_track_0_undriven_sram_inv; -wire [0:1] mux_right_track_10_undriven_sram_inv; -wire [0:1] mux_right_track_12_undriven_sram_inv; -wire [0:1] mux_right_track_14_undriven_sram_inv; -wire [0:1] mux_right_track_16_undriven_sram_inv; -wire [0:1] mux_right_track_18_undriven_sram_inv; -wire [0:1] mux_right_track_20_undriven_sram_inv; -wire [0:4] mux_right_track_2_undriven_sram_inv; -wire [0:1] mux_right_track_4_undriven_sram_inv; -wire [0:1] mux_right_track_6_undriven_sram_inv; -wire [0:1] mux_right_track_8_undriven_sram_inv; -wire [0:4] mux_tree_tapbuf_size17_0_sram; -wire [0:4] mux_tree_tapbuf_size17_1_sram; -wire [0:0] mux_tree_tapbuf_size17_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size17_mem_1_ccff_tail; -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_2_sram; -wire [0:1] mux_tree_tapbuf_size3_3_sram; -wire [0:1] mux_tree_tapbuf_size3_4_sram; -wire [0:1] mux_tree_tapbuf_size3_5_sram; -wire [0:1] mux_tree_tapbuf_size3_6_sram; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; - -// ----- BEGIN Local short connections ----- -// ----- Local connection due to Wire 0 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[9] = chanx_right_in[0]; -// ----- Local connection due to Wire 1 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[8] = chanx_right_in[1]; -// ----- Local connection due to Wire 2 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[7] = chanx_right_in[2]; -// ----- Local connection due to Wire 3 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[6] = chanx_right_in[3]; -// ----- Local connection due to Wire 4 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[5] = chanx_right_in[4]; -// ----- Local connection due to Wire 5 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[4] = chanx_right_in[5]; -// ----- Local connection due to Wire 6 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[3] = chanx_right_in[6]; -// ----- Local connection due to Wire 10 ----- -// ----- Net source id 0 ----- -// ----- Net sink id 0 ----- - assign chany_bottom_out[10] = chanx_right_in[10]; -// ----- END Local short connections ----- -// ----- BEGIN Local output short connections ----- -// ----- END Local output short connections ----- - - mux_tree_tapbuf_size17 mux_right_track_0 ( - .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[9]}), - .sram(mux_tree_tapbuf_size17_0_sram[0:4]), - .sram_inv(mux_right_track_0_undriven_sram_inv[0:4]), - .out(chanx_right_out[0])); - - mux_tree_tapbuf_size17 mux_right_track_2 ( - .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[8]}), - .sram(mux_tree_tapbuf_size17_1_sram[0:4]), - .sram_inv(mux_right_track_2_undriven_sram_inv[0:4]), - .out(chanx_right_out[1])); - - mux_tree_tapbuf_size17_mem mem_right_track_0 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(ccff_head), - .ccff_tail(mux_tree_tapbuf_size17_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size17_0_sram[0:4])); - - mux_tree_tapbuf_size17_mem mem_right_track_2 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size17_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size17_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size17_1_sram[0:4])); - - mux_tree_tapbuf_size3 mux_right_track_4 ( - .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[7]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_right_track_4_undriven_sram_inv[0:1]), - .out(chanx_right_out[2])); - - mux_tree_tapbuf_size3 mux_right_track_6 ( - .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[6]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_right_track_6_undriven_sram_inv[0:1]), - .out(chanx_right_out[3])); - - mux_tree_tapbuf_size3 mux_right_track_8 ( - .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[5]}), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_right_track_8_undriven_sram_inv[0:1]), - .out(chanx_right_out[4])); - - mux_tree_tapbuf_size3 mux_right_track_10 ( - .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[4]}), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_right_track_10_undriven_sram_inv[0:1]), - .out(chanx_right_out[5])); - - mux_tree_tapbuf_size3 mux_right_track_12 ( - .in({right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[3]}), - .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_right_track_12_undriven_sram_inv[0:1]), - .out(chanx_right_out[6])); - - mux_tree_tapbuf_size3 mux_right_track_14 ( - .in({right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[2]}), - .sram(mux_tree_tapbuf_size3_5_sram[0:1]), - .sram_inv(mux_right_track_14_undriven_sram_inv[0:1]), - .out(chanx_right_out[7])); - - mux_tree_tapbuf_size3 mux_right_track_16 ( - .in({right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[1]}), - .sram(mux_tree_tapbuf_size3_6_sram[0:1]), - .sram_inv(mux_right_track_16_undriven_sram_inv[0:1]), - .out(chanx_right_out[8])); - - mux_tree_tapbuf_size3_mem mem_right_track_4 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size17_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_right_track_6 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_right_track_8 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_right_track_10 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_right_track_12 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_right_track_14 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_5_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_right_track_16 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_6_sram[0:1])); - - mux_tree_tapbuf_size2 mux_right_track_18 ( - .in({right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[0]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_right_track_18_undriven_sram_inv[0:1]), - .out(chanx_right_out[9])); - - mux_tree_tapbuf_size2 mux_right_track_20 ( - .in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[10]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_right_track_20_undriven_sram_inv[0:1]), - .out(chanx_right_out[10])); - - mux_tree_tapbuf_size2 mux_bottom_track_1 ( - .in({chanx_right_in[9], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:1]), - .out(chany_bottom_out[0])); - - mux_tree_tapbuf_size2 mux_bottom_track_3 ( - .in({chanx_right_in[8], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:1]), - .out(chany_bottom_out[1])); - - mux_tree_tapbuf_size2 mux_bottom_track_5 ( - .in({chanx_right_in[7], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:1]), - .out(chany_bottom_out[2])); - - mux_tree_tapbuf_size2_mem mem_right_track_18 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_right_track_20 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_1 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_3 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_5 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), - .ccff_tail(ccff_tail), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1])); - -endmodule -// ----- END Verilog module for sb_0__1_ ----- - -//----- Default net type ----- -`default_nettype none - - - diff --git a/SOFA_A/SOFA_A_verilog/routing/sb_1__0_.v b/SOFA_A/SOFA_A_verilog/routing/sb_1__0_.v deleted file mode 100644 index 64c7f0c..0000000 --- a/SOFA_A/SOFA_A_verilog/routing/sb_1__0_.v +++ /dev/null @@ -1,484 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Verilog modules for Unique Switch Blocks[1][0] -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Default net type ----- -`default_nettype none - -// ----- Verilog module for sb_1__0_ ----- -module sb_1__0_(pReset, - prog_clk, - chany_top_in, - top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, - top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, - top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, - top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, - top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, - top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, - top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, - top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, - top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, - top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, - top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, - top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, - top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, - top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, - top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, - chanx_left_in, - left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, - left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, - left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, - left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, - left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, - left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, - left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, - left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, - left_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_, - ccff_head, - chany_top_out, - chanx_left_out, - ccff_tail); -//----- GLOBAL PORTS ----- -input [0:0] pReset; -//----- GLOBAL PORTS ----- -input [0:0] prog_clk; -//----- INPUT PORTS ----- -input [0:10] chany_top_in; -//----- INPUT PORTS ----- -input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; -//----- INPUT PORTS ----- -input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; -//----- INPUT PORTS ----- -input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; -//----- INPUT PORTS ----- -input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; -//----- INPUT PORTS ----- -input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; -//----- INPUT PORTS ----- -input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; -//----- INPUT PORTS ----- -input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; -//----- INPUT PORTS ----- -input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:10] chanx_left_in; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] ccff_head; -//----- OUTPUT PORTS ----- -output [0:10] chany_top_out; -//----- OUTPUT PORTS ----- -output [0:10] chanx_left_out; -//----- OUTPUT PORTS ----- -output [0:0] ccff_tail; - -//----- BEGIN wire-connection ports ----- -//----- END wire-connection ports ----- - - -//----- BEGIN Registered ports ----- -//----- END Registered ports ----- - - -wire [0:1] mux_left_track_11_undriven_sram_inv; -wire [0:1] mux_left_track_13_undriven_sram_inv; -wire [0:1] mux_left_track_15_undriven_sram_inv; -wire [0:1] mux_left_track_17_undriven_sram_inv; -wire [0:1] mux_left_track_19_undriven_sram_inv; -wire [0:3] mux_left_track_1_undriven_sram_inv; -wire [0:1] mux_left_track_21_undriven_sram_inv; -wire [0:3] mux_left_track_3_undriven_sram_inv; -wire [0:1] mux_left_track_5_undriven_sram_inv; -wire [0:1] mux_left_track_7_undriven_sram_inv; -wire [0:1] mux_left_track_9_undriven_sram_inv; -wire [0:4] mux_top_track_0_undriven_sram_inv; -wire [0:1] mux_top_track_10_undriven_sram_inv; -wire [0:1] mux_top_track_12_undriven_sram_inv; -wire [0:1] mux_top_track_14_undriven_sram_inv; -wire [0:1] mux_top_track_16_undriven_sram_inv; -wire [0:1] mux_top_track_18_undriven_sram_inv; -wire [0:1] mux_top_track_20_undriven_sram_inv; -wire [0:4] mux_top_track_2_undriven_sram_inv; -wire [0:1] mux_top_track_4_undriven_sram_inv; -wire [0:1] mux_top_track_6_undriven_sram_inv; -wire [0:1] mux_top_track_8_undriven_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; -wire [0:4] mux_tree_tapbuf_size16_0_sram; -wire [0:4] mux_tree_tapbuf_size16_1_sram; -wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail; -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_10_sram; -wire [0:1] mux_tree_tapbuf_size2_11_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:1] mux_tree_tapbuf_size2_5_sram; -wire [0:1] mux_tree_tapbuf_size2_6_sram; -wire [0:1] mux_tree_tapbuf_size2_7_sram; -wire [0:1] mux_tree_tapbuf_size2_8_sram; -wire [0:1] mux_tree_tapbuf_size2_9_sram; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_2_sram; -wire [0:1] mux_tree_tapbuf_size3_3_sram; -wire [0:1] mux_tree_tapbuf_size3_4_sram; -wire [0:1] mux_tree_tapbuf_size3_5_sram; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; - -// ----- BEGIN Local short connections ----- -// ----- END Local short connections ----- -// ----- BEGIN Local output short connections ----- -// ----- END Local output short connections ----- - - mux_tree_tapbuf_size16 mux_top_track_0 ( - .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[0]}), - .sram(mux_tree_tapbuf_size16_0_sram[0:4]), - .sram_inv(mux_top_track_0_undriven_sram_inv[0:4]), - .out(chany_top_out[0])); - - mux_tree_tapbuf_size16 mux_top_track_2 ( - .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size16_1_sram[0:4]), - .sram_inv(mux_top_track_2_undriven_sram_inv[0:4]), - .out(chany_top_out[1])); - - mux_tree_tapbuf_size16_mem mem_top_track_0 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(ccff_head), - .ccff_tail(mux_tree_tapbuf_size16_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size16_0_sram[0:4])); - - mux_tree_tapbuf_size16_mem mem_top_track_2 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size16_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size16_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size16_1_sram[0:4])); - - mux_tree_tapbuf_size3 mux_top_track_4 ( - .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[9]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_top_track_4_undriven_sram_inv[0:1]), - .out(chany_top_out[2])); - - mux_tree_tapbuf_size3 mux_top_track_6 ( - .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[8]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_top_track_6_undriven_sram_inv[0:1]), - .out(chany_top_out[3])); - - mux_tree_tapbuf_size3 mux_top_track_8 ( - .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[7]}), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_top_track_8_undriven_sram_inv[0:1]), - .out(chany_top_out[4])); - - mux_tree_tapbuf_size3 mux_top_track_10 ( - .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[6]}), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_top_track_10_undriven_sram_inv[0:1]), - .out(chany_top_out[5])); - - mux_tree_tapbuf_size3 mux_top_track_12 ( - .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[5]}), - .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_top_track_12_undriven_sram_inv[0:1]), - .out(chany_top_out[6])); - - mux_tree_tapbuf_size3 mux_top_track_14 ( - .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[4]}), - .sram(mux_tree_tapbuf_size3_5_sram[0:1]), - .sram_inv(mux_top_track_14_undriven_sram_inv[0:1]), - .out(chany_top_out[7])); - - mux_tree_tapbuf_size3_mem mem_top_track_4 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size16_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_6 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_8 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_10 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_12 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_14 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_5_sram[0:1])); - - mux_tree_tapbuf_size2 mux_top_track_16 ( - .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[3]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_top_track_16_undriven_sram_inv[0:1]), - .out(chany_top_out[8])); - - mux_tree_tapbuf_size2 mux_top_track_18 ( - .in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[2]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_top_track_18_undriven_sram_inv[0:1]), - .out(chany_top_out[9])); - - mux_tree_tapbuf_size2 mux_top_track_20 ( - .in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[1]}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_top_track_20_undriven_sram_inv[0:1]), - .out(chany_top_out[10])); - - mux_tree_tapbuf_size2 mux_left_track_5 ( - .in({chany_top_in[9], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_left_track_5_undriven_sram_inv[0:1]), - .out(chanx_left_out[2])); - - mux_tree_tapbuf_size2 mux_left_track_7 ( - .in({chany_top_in[8], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_left_track_7_undriven_sram_inv[0:1]), - .out(chanx_left_out[3])); - - mux_tree_tapbuf_size2 mux_left_track_9 ( - .in({chany_top_in[7], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_left_track_9_undriven_sram_inv[0:1]), - .out(chanx_left_out[4])); - - mux_tree_tapbuf_size2 mux_left_track_11 ( - .in({chany_top_in[6], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_left_track_11_undriven_sram_inv[0:1]), - .out(chanx_left_out[5])); - - mux_tree_tapbuf_size2 mux_left_track_13 ( - .in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_left_track_13_undriven_sram_inv[0:1]), - .out(chanx_left_out[6])); - - mux_tree_tapbuf_size2 mux_left_track_15 ( - .in({chany_top_in[4], left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_left_track_15_undriven_sram_inv[0:1]), - .out(chanx_left_out[7])); - - mux_tree_tapbuf_size2 mux_left_track_17 ( - .in({chany_top_in[3], left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_left_track_17_undriven_sram_inv[0:1]), - .out(chanx_left_out[8])); - - mux_tree_tapbuf_size2 mux_left_track_19 ( - .in({chany_top_in[2], left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_left_track_19_undriven_sram_inv[0:1]), - .out(chanx_left_out[9])); - - mux_tree_tapbuf_size2 mux_left_track_21 ( - .in({chany_top_in[1], left_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_left_track_21_undriven_sram_inv[0:1]), - .out(chanx_left_out[10])); - - mux_tree_tapbuf_size2_mem mem_top_track_16 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_18 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_20 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_5 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_7 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_9 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_11 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_13 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_15 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_17 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_19 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_21 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail), - .ccff_tail(ccff_tail), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1])); - - mux_tree_tapbuf_size10 mux_left_track_1 ( - .in({chany_top_in[0], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_left_track_1_undriven_sram_inv[0:3]), - .out(chanx_left_out[0])); - - mux_tree_tapbuf_size10 mux_left_track_3 ( - .in({chany_top_in[10], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_left_track_3_undriven_sram_inv[0:3]), - .out(chanx_left_out[1])); - - mux_tree_tapbuf_size10_mem mem_left_track_1 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3])); - - mux_tree_tapbuf_size10_mem mem_left_track_3 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3])); - -endmodule -// ----- END Verilog module for sb_1__0_ ----- - -//----- Default net type ----- -`default_nettype none - - - diff --git a/SOFA_A/SOFA_A_verilog/routing/sb_1__1_.v b/SOFA_A/SOFA_A_verilog/routing/sb_1__1_.v deleted file mode 100644 index 6546aae..0000000 --- a/SOFA_A/SOFA_A_verilog/routing/sb_1__1_.v +++ /dev/null @@ -1,505 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Verilog modules for Unique Switch Blocks[1][1] -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Default net type ----- -`default_nettype none - -// ----- Verilog module for sb_1__1_ ----- -module sb_1__1_(pReset, - prog_clk, - chany_bottom_in, - bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, - bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, - bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, - bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, - bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, - bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, - bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, - bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, - bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, - bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, - bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, - bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, - bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, - bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, - bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, - chanx_left_in, - left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, - left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, - left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, - left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, - left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, - left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, - left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, - left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, - left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, - left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, - left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, - left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, - left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, - left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, - left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, - left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, - ccff_head, - chany_bottom_out, - chanx_left_out, - ccff_tail); -//----- GLOBAL PORTS ----- -input [0:0] pReset; -//----- GLOBAL PORTS ----- -input [0:0] prog_clk; -//----- INPUT PORTS ----- -input [0:10] chany_bottom_in; -//----- INPUT PORTS ----- -input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_; -//----- INPUT PORTS ----- -input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_; -//----- INPUT PORTS ----- -input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_; -//----- INPUT PORTS ----- -input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_; -//----- INPUT PORTS ----- -input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_; -//----- INPUT PORTS ----- -input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_; -//----- INPUT PORTS ----- -input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_; -//----- INPUT PORTS ----- -input [0:10] chanx_left_in; -//----- INPUT PORTS ----- -input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_; -//----- INPUT PORTS ----- -input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_; -//----- INPUT PORTS ----- -input [0:0] ccff_head; -//----- OUTPUT PORTS ----- -output [0:10] chany_bottom_out; -//----- OUTPUT PORTS ----- -output [0:10] chanx_left_out; -//----- OUTPUT PORTS ----- -output [0:0] ccff_tail; - -//----- BEGIN wire-connection ports ----- -//----- END wire-connection ports ----- - - -//----- BEGIN Registered ports ----- -//----- END Registered ports ----- - - -wire [0:1] mux_bottom_track_11_undriven_sram_inv; -wire [0:1] mux_bottom_track_13_undriven_sram_inv; -wire [0:1] mux_bottom_track_15_undriven_sram_inv; -wire [0:1] mux_bottom_track_17_undriven_sram_inv; -wire [0:1] mux_bottom_track_19_undriven_sram_inv; -wire [0:4] mux_bottom_track_1_undriven_sram_inv; -wire [0:1] mux_bottom_track_21_undriven_sram_inv; -wire [0:4] mux_bottom_track_3_undriven_sram_inv; -wire [0:1] mux_bottom_track_5_undriven_sram_inv; -wire [0:1] mux_bottom_track_7_undriven_sram_inv; -wire [0:1] mux_bottom_track_9_undriven_sram_inv; -wire [0:1] mux_left_track_11_undriven_sram_inv; -wire [0:1] mux_left_track_13_undriven_sram_inv; -wire [0:1] mux_left_track_15_undriven_sram_inv; -wire [0:1] mux_left_track_17_undriven_sram_inv; -wire [0:1] mux_left_track_19_undriven_sram_inv; -wire [0:4] mux_left_track_1_undriven_sram_inv; -wire [0:1] mux_left_track_21_undriven_sram_inv; -wire [0:4] mux_left_track_3_undriven_sram_inv; -wire [0:1] mux_left_track_5_undriven_sram_inv; -wire [0:1] mux_left_track_7_undriven_sram_inv; -wire [0:1] mux_left_track_9_undriven_sram_inv; -wire [0:4] mux_tree_tapbuf_size16_0_sram; -wire [0:4] mux_tree_tapbuf_size16_1_sram; -wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail; -wire [0:4] mux_tree_tapbuf_size17_0_sram; -wire [0:4] mux_tree_tapbuf_size17_1_sram; -wire [0:0] mux_tree_tapbuf_size17_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size17_mem_1_ccff_tail; -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_10_sram; -wire [0:1] mux_tree_tapbuf_size3_11_sram; -wire [0:1] mux_tree_tapbuf_size3_12_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_2_sram; -wire [0:1] mux_tree_tapbuf_size3_3_sram; -wire [0:1] mux_tree_tapbuf_size3_4_sram; -wire [0:1] mux_tree_tapbuf_size3_5_sram; -wire [0:1] mux_tree_tapbuf_size3_6_sram; -wire [0:1] mux_tree_tapbuf_size3_7_sram; -wire [0:1] mux_tree_tapbuf_size3_8_sram; -wire [0:1] mux_tree_tapbuf_size3_9_sram; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail; - -// ----- BEGIN Local short connections ----- -// ----- END Local short connections ----- -// ----- BEGIN Local output short connections ----- -// ----- END Local output short connections ----- - - mux_tree_tapbuf_size16 mux_bottom_track_1 ( - .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[1]}), - .sram(mux_tree_tapbuf_size16_0_sram[0:4]), - .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:4]), - .out(chany_bottom_out[0])); - - mux_tree_tapbuf_size16 mux_bottom_track_3 ( - .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[2]}), - .sram(mux_tree_tapbuf_size16_1_sram[0:4]), - .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:4]), - .out(chany_bottom_out[1])); - - mux_tree_tapbuf_size16_mem mem_bottom_track_1 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(ccff_head), - .ccff_tail(mux_tree_tapbuf_size16_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size16_0_sram[0:4])); - - mux_tree_tapbuf_size16_mem mem_bottom_track_3 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size16_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size16_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size16_1_sram[0:4])); - - mux_tree_tapbuf_size3 mux_bottom_track_5 ( - .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[3]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:1]), - .out(chany_bottom_out[2])); - - mux_tree_tapbuf_size3 mux_bottom_track_7 ( - .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[4]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_bottom_track_7_undriven_sram_inv[0:1]), - .out(chany_bottom_out[3])); - - mux_tree_tapbuf_size3 mux_bottom_track_9 ( - .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[5]}), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:1]), - .out(chany_bottom_out[4])); - - mux_tree_tapbuf_size3 mux_bottom_track_11 ( - .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[6]}), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_bottom_track_11_undriven_sram_inv[0:1]), - .out(chany_bottom_out[5])); - - mux_tree_tapbuf_size3 mux_bottom_track_13 ( - .in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[7]}), - .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]), - .out(chany_bottom_out[6])); - - mux_tree_tapbuf_size3 mux_bottom_track_15 ( - .in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[8]}), - .sram(mux_tree_tapbuf_size3_5_sram[0:1]), - .sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]), - .out(chany_bottom_out[7])); - - mux_tree_tapbuf_size3 mux_left_track_5 ( - .in({chany_bottom_in[1], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_}), - .sram(mux_tree_tapbuf_size3_6_sram[0:1]), - .sram_inv(mux_left_track_5_undriven_sram_inv[0:1]), - .out(chanx_left_out[2])); - - mux_tree_tapbuf_size3 mux_left_track_7 ( - .in({chany_bottom_in[2], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), - .sram(mux_tree_tapbuf_size3_7_sram[0:1]), - .sram_inv(mux_left_track_7_undriven_sram_inv[0:1]), - .out(chanx_left_out[3])); - - mux_tree_tapbuf_size3 mux_left_track_9 ( - .in({chany_bottom_in[3], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_}), - .sram(mux_tree_tapbuf_size3_8_sram[0:1]), - .sram_inv(mux_left_track_9_undriven_sram_inv[0:1]), - .out(chanx_left_out[4])); - - mux_tree_tapbuf_size3 mux_left_track_11 ( - .in({chany_bottom_in[4], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_}), - .sram(mux_tree_tapbuf_size3_9_sram[0:1]), - .sram_inv(mux_left_track_11_undriven_sram_inv[0:1]), - .out(chanx_left_out[5])); - - mux_tree_tapbuf_size3 mux_left_track_13 ( - .in({chany_bottom_in[5], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_}), - .sram(mux_tree_tapbuf_size3_10_sram[0:1]), - .sram_inv(mux_left_track_13_undriven_sram_inv[0:1]), - .out(chanx_left_out[6])); - - mux_tree_tapbuf_size3 mux_left_track_15 ( - .in({chany_bottom_in[6], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_}), - .sram(mux_tree_tapbuf_size3_11_sram[0:1]), - .sram_inv(mux_left_track_15_undriven_sram_inv[0:1]), - .out(chanx_left_out[7])); - - mux_tree_tapbuf_size3 mux_left_track_17 ( - .in({chany_bottom_in[7], left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), - .sram(mux_tree_tapbuf_size3_12_sram[0:1]), - .sram_inv(mux_left_track_17_undriven_sram_inv[0:1]), - .out(chanx_left_out[8])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_5 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size16_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_7 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_9 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_11 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_13 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_15 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_5_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_left_track_5 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size17_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_6_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_left_track_7 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_7_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_left_track_9 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_8_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_left_track_11 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_9_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_left_track_13 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_10_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_left_track_15 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_11_sram[0:1])); - - mux_tree_tapbuf_size3_mem mem_left_track_17 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail), - .mem_out(mux_tree_tapbuf_size3_12_sram[0:1])); - - mux_tree_tapbuf_size2 mux_bottom_track_17 ( - .in({bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[9]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]), - .out(chany_bottom_out[8])); - - mux_tree_tapbuf_size2 mux_bottom_track_19 ( - .in({bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]), - .out(chany_bottom_out[9])); - - mux_tree_tapbuf_size2 mux_bottom_track_21 ( - .in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[0]}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]), - .out(chany_bottom_out[10])); - - mux_tree_tapbuf_size2 mux_left_track_19 ( - .in({chany_bottom_in[8], left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_left_track_19_undriven_sram_inv[0:1]), - .out(chanx_left_out[9])); - - mux_tree_tapbuf_size2 mux_left_track_21 ( - .in({chany_bottom_in[9], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_left_track_21_undriven_sram_inv[0:1]), - .out(chanx_left_out[10])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_17 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_19 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_21 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_19 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_21 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), - .ccff_tail(ccff_tail), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1])); - - mux_tree_tapbuf_size17 mux_left_track_1 ( - .in({chany_bottom_in[10], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), - .sram(mux_tree_tapbuf_size17_0_sram[0:4]), - .sram_inv(mux_left_track_1_undriven_sram_inv[0:4]), - .out(chanx_left_out[0])); - - mux_tree_tapbuf_size17 mux_left_track_3 ( - .in({chany_bottom_in[0], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_}), - .sram(mux_tree_tapbuf_size17_1_sram[0:4]), - .sram_inv(mux_left_track_3_undriven_sram_inv[0:4]), - .out(chanx_left_out[1])); - - mux_tree_tapbuf_size17_mem mem_left_track_1 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size17_mem_0_ccff_tail), - .mem_out(mux_tree_tapbuf_size17_0_sram[0:4])); - - mux_tree_tapbuf_size17_mem mem_left_track_3 ( - .pReset(pReset), - .prog_clk(prog_clk), - .ccff_head(mux_tree_tapbuf_size17_mem_0_ccff_tail), - .ccff_tail(mux_tree_tapbuf_size17_mem_1_ccff_tail), - .mem_out(mux_tree_tapbuf_size17_1_sram[0:4])); - -endmodule -// ----- END Verilog module for sb_1__1_ ----- - -//----- Default net type ----- -`default_nettype none - - - diff --git a/SOFA_A/SOFA_A_verilog/top_autocheck_top_tb.v b/SOFA_A/SOFA_A_verilog/top_autocheck_top_tb.v deleted file mode 100644 index 55f1bb0..0000000 --- a/SOFA_A/SOFA_A_verilog/top_autocheck_top_tb.v +++ /dev/null @@ -1,6608 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: FPGA Verilog full testbench for top-level netlist of design: top -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Default net type ----- -`default_nettype none - -module top_autocheck_top_tb; -// ----- Local wires for global ports of FPGA fabric ----- -wire [0:0] clk; -wire [0:0] Reset; -wire [0:0] IO_ISOL_N; -wire [0:0] pReset; -wire [0:0] prog_clk; -wire [0:0] Test_en; - -// ----- Local wires for I/Os of FPGA fabric ----- - -wire [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; - -wire [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; -wire [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; - -reg [0:0] __config_done__; -wire [0:0] __prog_clock__; -reg [0:0] __prog_clock___reg__; -wire [0:0] __op_clock__; -reg [0:0] __op_clock___reg__; -reg [0:0] __prog_reset__; -reg [0:0] __prog_set_; -reg [0:0] __greset__; -reg [0:0] __gset__; -// ---- Configuration-chain head ----- -reg [0:0] ccff_head; -// ---- Configuration-chain tail ----- -wire [0:0] ccff_tail; -// ----- Shared inputs ------- - reg [0:0] a_shared_input; - reg [0:0] b_shared_input; - -// ----- FPGA fabric outputs ------- - wire [0:0] c_fpga; - -// ----- Benchmark outputs ------- - wire [0:0] c_benchmark; - -// ----- Output vectors checking flags ------- - reg [0:0] c_flag; - -// ----- Error counter: Deposit an error for config_done signal is not raised at the beginning ----- - integer nb_error= 1; -// ----- Number of clock cycles in configuration phase: 651 ----- -// ----- Begin configuration done signal generation ----- -initial - begin - __config_done__[0] = 1'b0; - end - -// ----- End configuration done signal generation ----- - -// ----- Begin raw programming clock signal generation ----- -initial - begin - __prog_clock___reg__[0] = 1'b0; - end -always - begin - #5 __prog_clock___reg__[0] = ~__prog_clock___reg__[0]; - end - -// ----- End raw programming clock signal generation ----- - -// ----- Actual programming clock is triggered only when __config_done__ and __prog_reset__ are disabled ----- - assign __prog_clock__[0] = __prog_clock___reg__[0] & (~__config_done__[0]) & (~__prog_reset__[0]); - -// ----- Begin raw operating clock signal generation ----- -initial - begin - __op_clock___reg__[0] = 1'b0; - end -always wait(~__greset__) - begin - #6.660000324 __op_clock___reg__[0] = ~__op_clock___reg__[0]; - end - -// ----- End raw operating clock signal generation ----- -// ----- Actual operating clock is triggered only when __config_done__ is enabled ----- - assign __op_clock__[0] = __op_clock___reg__[0] & __config_done__[0]; - -// ----- Begin programming reset signal generation ----- -initial - begin - __prog_reset__[0] = 1'b1; - #10 __prog_reset__[0] = 1'b0; - end - -// ----- End programming reset signal generation ----- - -// ----- Begin programming set signal generation ----- -initial - begin - __prog_set_[0] = 1'b1; - #10 __prog_set_[0] = 1'b0; - end - -// ----- End programming set signal generation ----- - -// ----- Begin operating reset signal generation ----- -// ----- Reset signal is enabled until the first clock cycle in operation phase ----- -initial - begin - __greset__[0] = 1'b1; - wait(__config_done__) - #13.32000065 __greset__[0] = 1'b1; - #26.6400013 __greset__[0] = 1'b0; - end - -// ----- End operating reset signal generation ----- -// ----- Begin operating set signal generation: always disabled ----- -initial - begin - __gset__[0] = 1'b0; - end - -// ----- End operating set signal generation: always disabled ----- - -// ----- Begin connecting global ports of FPGA fabric to stimuli ----- - assign prog_clk[0] = __prog_clock__[0]; - assign clk[0] = __op_clock__[0]; - assign pReset[0] = ~__prog_reset__[0]; - assign Reset[0] = ~__greset__[0]; - assign Test_en[0] = 1'b0; - assign IO_ISOL_N[0] = 1'b1; -// ----- End connecting global ports of FPGA fabric to stimuli ----- -// ----- FPGA top-level module to be capsulated ----- - fpga_top FPGA_DUT ( - .clk(clk[0]), - .Reset(Reset[0]), - .IO_ISOL_N(IO_ISOL_N[0]), - .pReset(pReset[0]), - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:25]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:25]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:25]), - .ccff_head(ccff_head[0]), - .ccff_tail(ccff_tail[0])); - -// ----- Link BLIF Benchmark I/Os to FPGA I/Os ----- -// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] ----- - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = a_shared_input[0]; - -// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ----- - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = b_shared_input[0]; - -// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24] ----- - assign c_fpga[0] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24]; - -// ----- Wire unused FPGA I/Os to constants ----- - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = 1'b0; - - -// ----- Reference Benchmark Instanication ------- - top REF_DUT( - .a(a_shared_input), - .b(b_shared_input), - .c(c_benchmark) - ); -// ----- End reference Benchmark Instanication ------- - -// ----- Begin bitstream loading during configuration phase ----- -`define BITSTREAM_LENGTH 650 -`define BITSTREAM_WIDTH 1 -// ----- Virtual memory to store the bitstream from external file ----- -reg [0:`BITSTREAM_WIDTH - 1] bit_mem[0:`BITSTREAM_LENGTH - 1]; -reg [$clog2(`BITSTREAM_LENGTH):0] bit_index; -// ----- Registers used for fast configuration logic ----- -reg [$clog2(`BITSTREAM_LENGTH):0] ibit; -reg [0:0] skip_bits; -// ----- Preload bitstream file to a virtual memory ----- -initial begin - $readmemb("fabric_bitstream.bit", bit_mem); -// ----- Configuration chain default input ----- - ccff_head[0] <= 1'b0; - bit_index <= 0; - skip_bits[0] <= 1'b0; - for (ibit = 0; ibit < `BITSTREAM_LENGTH + 1; ibit = ibit + 1) begin - if (1'b0 == bit_mem[ibit]) begin - if (1'b1 == skip_bits[0]) begin - bit_index <= bit_index + 1; - end - end else begin - skip_bits[0] <= 1'b0; - end - end -end -// ----- 'else if' condition is required by Modelsim to synthesis the Verilog correctly ----- -always @(negedge __prog_clock___reg__[0]) begin - if (bit_index >= `BITSTREAM_LENGTH) begin - __config_done__[0] <= 1'b1; - end else if (bit_index >= 0 && bit_index < `BITSTREAM_LENGTH) begin - ccff_head[0] <= bit_mem[bit_index]; - bit_index <= bit_index + 1; - end -end -// ----- End bitstream loading during configuration phase ----- - -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_lut4_0_in_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_fabric_out_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_0_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mux_ff_1_D_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_top_track_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_top_track_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_top_track_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_top_track_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_top_track_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_top_track_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_top_track_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_top_track_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_top_track_4.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_top_track_4.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_top_track_4.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_top_track_4.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_4.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_4.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_4.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_4.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_6.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_6.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_6.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_6.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_8.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_8.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_8.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_8.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_10.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_10.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_10.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_10.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_12.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_12.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_12.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_12.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_14.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_14.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_14.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_14.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_16.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_16.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_16.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_16.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_18.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_18.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_18.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_18.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_20.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_20.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_20.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_20.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_0.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__0_.mux_right_track_2.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l2_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l3_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l3_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l3_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l3_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l4_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l4_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l5_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_0.mux_l5_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l2_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l3_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l3_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l3_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l3_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l4_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l4_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l5_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_2.mux_l5_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_4.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_4.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_4.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_4.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_4.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_4.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_6.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_6.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_6.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_6.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_6.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_6.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_8.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_8.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_8.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_8.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_8.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_8.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_10.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_10.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_10.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_10.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_10.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_10.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_12.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_12.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_12.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_12.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_12.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_12.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_14.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_14.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_14.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_14.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_14.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_14.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_16.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_16.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_16.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_16.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_16.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_16.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_18.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_18.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_18.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_18.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_20.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_20.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_20.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_right_track_20.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_bottom_track_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_bottom_track_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_bottom_track_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_bottom_track_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_bottom_track_3.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_bottom_track_3.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_bottom_track_3.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_bottom_track_3.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_bottom_track_5.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_bottom_track_5.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_0__1_.mux_bottom_track_5.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_0__1_.mux_bottom_track_5.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l2_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l3_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l3_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l3_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l3_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l4_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l4_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l5_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_0.mux_l5_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l2_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l3_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l3_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l3_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l3_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l4_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l4_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l5_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_2.mux_l5_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_4.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_4.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_4.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_4.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_4.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_4.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_6.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_6.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_6.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_6.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_6.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_6.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_8.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_8.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_8.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_8.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_8.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_8.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_10.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_10.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_10.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_10.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_10.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_10.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_12.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_12.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_12.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_12.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_12.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_12.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_14.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_14.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_14.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_14.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_14.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_14.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_16.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_16.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_16.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_16.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_18.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_18.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_18.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_18.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_20.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_20.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_20.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_top_track_20.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_5.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_5.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_5.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_5.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_7.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_7.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_7.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_7.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_9.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_9.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_9.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_9.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_11.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_11.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_11.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_11.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_13.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_13.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_13.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_13.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_15.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_15.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_15.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_15.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_17.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_17.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_17.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_17.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_19.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_19.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_19.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_19.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_21.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_21.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_21.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_21.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_1.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__0_.mux_left_track_3.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l2_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l3_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l3_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l3_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l3_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l4_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l4_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l5_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_1.mux_l5_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l2_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l3_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l3_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l3_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l3_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l4_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l4_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l5_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_3.mux_l5_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_5.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_5.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_5.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_5.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_5.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_5.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_7.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_7.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_7.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_7.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_7.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_7.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_9.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_9.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_9.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_9.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_9.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_9.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_11.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_11.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_11.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_11.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_11.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_11.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_13.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_13.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_13.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_13.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_13.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_13.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_15.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_15.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_15.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_15.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_15.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_15.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_5.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_5.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_5.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_5.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_5.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_5.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_7.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_7.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_7.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_7.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_7.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_7.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_9.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_9.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_9.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_9.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_9.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_9.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_11.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_11.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_11.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_11.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_11.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_11.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_13.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_13.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_13.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_13.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_13.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_13.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_15.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_15.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_15.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_15.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_15.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_15.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_17.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_17.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_17.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_17.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_17.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_17.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_17.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_17.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_17.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_17.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_19.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_19.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_19.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_19.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_21.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_21.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_21.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_bottom_track_21.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_19.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_19.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_19.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_19.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_21.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_21.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_21.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_21.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l2_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l3_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l3_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l3_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l3_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l4_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l4_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l5_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_1.mux_l5_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_4_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_4_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_5_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_5_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_6_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_6_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_7_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l2_in_7_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l3_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l3_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l3_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l3_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l4_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l4_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l5_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.sb_1__1_.mux_left_track_3.mux_l5_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_0.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_1.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_2.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_3.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_4.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_5.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_6.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_7.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__0_.mux_top_ipin_8.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_0.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_1.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_2.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_3.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_4.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_5.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_6.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_bottom_ipin_7.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_0.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_2.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_4.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_6.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_8.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_10.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_12.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_14.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_1.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_1.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_1.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_1.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_1.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_1.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_1.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_1.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_3.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_3.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_3.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_3.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_3.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_3.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_3.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_3.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_3.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_3.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_3.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_3.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_5.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_5.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_5.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_5.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_5.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_5.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_5.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_5.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_5.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_5.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_5.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_5.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_7.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_7.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_7.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_7.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_7.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_7.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_7.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_7.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_7.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_7.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_7.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_7.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_9.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_9.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_9.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_9.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_9.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_9.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_9.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_9.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_9.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_9.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_9.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_9.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_11.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_11.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_11.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_11.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_11.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_11.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_11.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_11.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_11.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_11.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_11.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_11.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_13.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_13.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_13.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_13.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_13.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_13.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_13.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_13.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_13.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_13.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_13.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_13.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_15.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_15.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_15.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_15.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_15.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_15.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_15.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_15.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_15.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_15.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_15.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cbx_1__1_.mux_top_ipin_15.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_0__1_.mux_right_ipin_0.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_0.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_1.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_2.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_3.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_4.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_5.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_6.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_left_ipin_7.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_0.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_2.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_4.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_6.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_8.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_10.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_12.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l2_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l2_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l2_in_3_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l2_in_3_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l3_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l3_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l4_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_14.mux_l4_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_1.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_1.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_1.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_1.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_1.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_1.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_1.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_1.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_1.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_1.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_1.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_1.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_3.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_3.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_3.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_3.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_3.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_3.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_3.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_3.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_3.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_3.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_3.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_3.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_5.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_5.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_5.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_5.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_5.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_5.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_5.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_5.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_5.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_5.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_5.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_5.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_7.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_7.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_7.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_7.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_7.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_7.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_7.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_7.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_7.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_7.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_7.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_7.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_9.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_9.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_9.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_9.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_9.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_9.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_9.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_9.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_9.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_9.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_9.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_9.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_11.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_11.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_11.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_11.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_11.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_11.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_11.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_11.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_11.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_11.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_11.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_11.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_13.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_13.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_13.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_13.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_13.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_13.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_13.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_13.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_13.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_13.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_13.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_13.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_15.mux_l1_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_15.mux_l1_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_15.mux_l1_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_15.mux_l1_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_15.mux_l1_in_2_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_15.mux_l1_in_2_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_15.mux_l2_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_15.mux_l2_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_15.mux_l2_in_1_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_15.mux_l2_in_1_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ------ BEGIN driver initialization ----- - initial begin - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_15.mux_l3_in_0_.A1, $random % 2 ? 1'b1 : 1'b0); - $deposit(FPGA_DUT.cby_1__1_.mux_right_ipin_15.mux_l3_in_0_.A0, $random % 2 ? 1'b1 : 1'b0); - end -// ------ END driver initialization ----- -// ----- Begin reset signal generation ----- -// ----- Input Initialization ------- - initial begin - a_shared_input <= 1'b0; - b_shared_input <= 1'b0; - - c_flag[0] <= 1'b0; - end - -// ----- Input Stimulus ------- - always@(negedge __op_clock__[0]) begin - a_shared_input <= $random; - b_shared_input <= $random; - end - -// ----- Begin checking output vectors ------- -// ----- Skip the first falling edge of clock, it is for initialization ------- - reg [0:0] sim_start; - - always@(negedge __op_clock__[0]) begin - if (1'b1 == sim_start[0]) begin - sim_start[0] <= ~sim_start[0]; - end else -if (1'b1 == __config_done__) begin - if(!(c_fpga === c_benchmark) && !(c_benchmark === 1'bx)) begin - c_flag <= 1'b1; - end else begin - c_flag<= 1'b0; - end - end - end - - always@(posedge c_flag) begin - if(c_flag) begin - nb_error = nb_error + 1; - $display("Mismatch on c_fpga at time = %t", $realtime); - end - end - - -// ----- Configuration done must be raised in the end ------- - always@(posedge __config_done__[0]) begin - nb_error = nb_error - 1; - end - -// ----- Begin output waveform to VCD file------- - initial begin - $dumpfile("top_formal.vcd"); - $dumpvars(1, top_autocheck_top_tb); - end -// ----- END output waveform to VCD file ------- - -initial begin - sim_start[0] <= 1'b1; - $timeformat(-9, 2, "ns", 20); - $display("Simulation start"); -// ----- Can be changed by the user for his/her need ------- - #6584 - if(nb_error == 0) begin - $display("Simulation Succeed"); - end else begin - $display("Simulation Failed with %d error(s)", nb_error); - end - $finish; -end - -endmodule -// ----- END Verilog module for top_autocheck_top_tb ----- - -//----- Default net type ----- -`default_nettype none - diff --git a/SOFA_A/SOFA_A_verilog/top_formal_random_top_tb.v b/SOFA_A/SOFA_A_verilog/top_formal_random_top_tb.v deleted file mode 100644 index 5432170..0000000 --- a/SOFA_A/SOFA_A_verilog/top_formal_random_top_tb.v +++ /dev/null @@ -1,127 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: FPGA Verilog Testbench for Formal Top-level netlist of Design: top -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Default net type ----- -`default_nettype none - -module top_top_formal_verification_random_tb; -// ----- Default clock port is added here since benchmark does not contain one ------- - reg [0:0] clk; - -// ----- Shared inputs ------- - reg [0:0] a; - reg [0:0] b; - -// ----- FPGA fabric outputs ------- - wire [0:0] c_gfpga; - -// ----- Benchmark outputs ------- - wire [0:0] c_bench; - -// ----- Output vectors checking flags ------- - reg [0:0] c_flag; - -// ----- Error counter ------- - integer nb_error= 0; - -// ----- FPGA fabric instanciation ------- - top_top_formal_verification FPGA_DUT( - .a(a), - .b(b), - .c(c_gfpga) - ); -// ----- End FPGA Fabric Instanication ------- - -// ----- Reference Benchmark Instanication ------- - top REF_DUT( - .a(a), - .b(b), - .c(c_bench) - ); -// ----- End reference Benchmark Instanication ------- - -// ----- Clock 'clk' Initialization ------- - initial begin - clk[0] <= 1'b0; - while(1) begin - #6.660000324 - clk[0] <= !clk[0]; - end - end - -// ----- Begin reset signal generation ----- -// ----- End reset signal generation ----- - -// ----- Input Initialization ------- - initial begin - a <= 1'b0; - b <= 1'b0; - - c_flag[0] <= 1'b0; - end - -// ----- Input Stimulus ------- - always@(negedge clk[0]) begin - a <= $random; - b <= $random; - end - -// ----- Begin checking output vectors ------- -// ----- Skip the first falling edge of clock, it is for initialization ------- - reg [0:0] sim_start; - - always@(negedge clk[0]) begin - if (1'b1 == sim_start[0]) begin - sim_start[0] <= ~sim_start[0]; - end else -begin - if(!(c_gfpga === c_bench) && !(c_bench === 1'bx)) begin - c_flag <= 1'b1; - end else begin - c_flag<= 1'b0; - end - end - end - - always@(posedge c_flag) begin - if(c_flag) begin - nb_error = nb_error + 1; - $display("Mismatch on c_gfpga at time = %t", $realtime); - end - end - - -// ----- Begin output waveform to VCD file------- - initial begin - $dumpfile("top_formal.vcd"); - $dumpvars(1, top_top_formal_verification_random_tb); - end -// ----- END output waveform to VCD file ------- - -initial begin - sim_start[0] <= 1'b1; - $timeformat(-9, 2, "ns", 20); - $display("Simulation start"); -// ----- Can be changed by the user for his/her need ------- - #26.6400013 - if(nb_error == 0) begin - $display("Simulation Succeed"); - end else begin - $display("Simulation Failed with %d error(s)", nb_error); - end - $finish; -end - -endmodule -// ----- END Verilog module for top_top_formal_verification_random_tb ----- - -//----- Default net type ----- -`default_nettype none - diff --git a/SOFA_A/SOFA_A_verilog/top_include_netlists.v b/SOFA_A/SOFA_A_verilog/top_include_netlists.v deleted file mode 100644 index b3a9940..0000000 --- a/SOFA_A/SOFA_A_verilog/top_include_netlists.v +++ /dev/null @@ -1,17 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include fabric top-level netlists ----- -`include "./SRC/fabric_netlists.v" - -`include "top_output_verilog.v" - -`include "./SRC/top_top_formal_verification.v" -`include "./SRC/top_formal_random_top_tb.v" diff --git a/SOFA_A/SOFA_A_verilog/top_top_formal_verification.v b/SOFA_A/SOFA_A_verilog/top_top_formal_verification.v deleted file mode 100644 index 98a2b03..0000000 --- a/SOFA_A/SOFA_A_verilog/top_top_formal_verification.v +++ /dev/null @@ -1,315 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Verilog netlist for pre-configured FPGA fabric by design: top -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Feb 19 10:53:27 2023 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Default net type ----- -`default_nettype none - -module top_top_formal_verification ( -input [0:0] a, -input [0:0] b, -output [0:0] c); - -// ----- Local wires for FPGA fabric ----- -wire [0:0] clk_fm; -wire [0:0] Reset_fm; -wire [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm; -wire [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_fm; -wire [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_fm; -wire [0:0] ccff_head_fm; -wire [0:0] ccff_tail_fm; -wire [0:0] IO_ISOL_N_fm; -wire [0:0] pReset_fm; -wire [0:0] prog_clk_fm; -wire [0:0] Test_en_fm; - -// ----- FPGA top-level module to be capsulated ----- - fpga_top U0_formal_verification ( - .clk(clk_fm[0]), - .Reset(Reset_fm[0]), - .IO_ISOL_N(IO_ISOL_N_fm[0]), - .pReset(pReset_fm[0]), - .prog_clk(prog_clk_fm[0]), - .Test_en(Test_en_fm[0]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[0:25]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_fm[0:25]), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_fm[0:25]), - .ccff_head(ccff_head_fm[0]), - .ccff_tail(ccff_tail_fm[0])); - -// ----- Begin Connect Global ports of FPGA top module ----- - assign Test_en_fm[0] = 1'b0; - assign prog_clk_fm[0] = 1'b0; - assign pReset_fm[0] = 1'b1; - assign IO_ISOL_N_fm[0] = 1'b1; - assign clk_fm[0] = 1'b0; - assign Reset_fm[0] = 1'b1; -// ----- End Connect Global ports of FPGA top module ----- - -// ----- Link BLIF Benchmark I/Os to FPGA I/Os ----- -// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[18] ----- - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[18] = a[0]; - -// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[3] ----- - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[3] = b[0]; - -// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_fm[24] ----- - assign c[0] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_fm[24]; - -// ----- Wire unused FPGA I/Os to constants ----- - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[0] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[1] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[2] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[4] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[5] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[6] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[7] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[8] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[9] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[10] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[11] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[12] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[13] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[14] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[15] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[16] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[17] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[19] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[20] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[21] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[22] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[23] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[24] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN_fm[25] = 1'b0; - - -// ----- Begin load bitstream to configuration memories ----- -// ----- Begin assign bitstream to configuration memories ----- -initial begin - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = {17{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = {17{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = {17{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = {17{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = {17{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = {17{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = {17{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0:16] = 17'b00000000110000001; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_lut4_0_in_2.mem_out[0:1] = 2'b01; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = 2'b01; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_top_top_1__2_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_right_right_2__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__8.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b0; - force U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.mem_out[0] = 1'b1; - force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:3] = 4'b0011; - force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_8.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_12.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:4] = {5{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:4] = 5'b00111; - force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_right_track_8.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:4] = 5'b01000; - force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:4] = {5{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_left_track_1.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_left_track_7.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_left_track_13.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_left_track_15.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_left_track_17.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_left_track_19.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_left_track_21.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:4] = 5'b01000; - force U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_out[0:4] = 5'b00100; - force U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_left_track_1.mem_out[0:4] = {5{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_out[0:4] = {5{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_left_track_13.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_left_track_15.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_left_track_19.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_left_track_21.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__0_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__0_.mem_top_ipin_8.mem_out[0:3] = 4'b0100; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_3.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_5.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_7.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_8.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_9.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_10.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_11.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_12.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_13.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_14.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_15.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_3.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_4.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_5.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_6.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_7.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_8.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_9.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_out[0:2] = 3'b011; - force U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_out[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_out[0:2] = {3{1'b0}}; -end -// ----- End assign bitstream to configuration memories ----- -// ----- End load bitstream to configuration memories ----- -endmodule -// ----- END Verilog module for top_top_formal_verification ----- - -//----- Default net type ----- -`default_nettype none - diff --git a/SOFA_A/config.sh b/SOFA_A/config.sh deleted file mode 100644 index 521023a..0000000 --- a/SOFA_A/config.sh +++ /dev/null @@ -1,51 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# = = = = = = = = = = = = = = Variables Sections = = = = = = = = = = = = = = = -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -export PROJ_NAME=FPGA1212_QLSOFA_HD # Project Name -export FPGA_SIZE_X=12 # Grid X Size -export FPGA_SIZE_Y=12 # Grid Y Size -# Design Style [hier/flat], mostly hier -export DESIGN_STYLE=hier -export TECHNOLOGY="skywater" - -# Complete Chip (fpga_top) or eFPGA (fpga_core) -export DESIGN_NAME=fpga_core - -# Pin Information Source Automatic or Sheet -export PIN_MAP=Automatic -export PIN_MAP_CSV_SPREADSHEET_LINK="" # Required only if PIN_MAP==Sheet - -# Core Dimension, requires if DESIGN_NAME=fpga_core -# if DESIGN_NAME=fpga_top its Optional if defined it overrides the -# Calculated DIE_DIMENSION -export DIE_DIMENSION=3200 - -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Derived Or Fixed Variables -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -export OPENFPGA_ENGINE_PATH=${OPENFPGA_PATH} -export TASK_DIR_NAME=${PROJ_NAME}_task -export VERILOG_PROJ_DIR=${PROJ_NAME}_Verilog -export SPY_HACK_FILE=${TASK_DIR_NAME}/spy_hack.txt -export POST_OPENFPGA_SCRIPT=./PostOpenFPGAScript.sh -export RESTRUCT_NETLIST=../utils/RestructureNetlistSkywater.py -export POST_GENERATION_SCRIPT=./generate_scandef_and_case_analysis.sh - -export TAPEOUT_DIRECTORY=/research/ece/lnis/USERS/DARPA_ERI/Tapeout/SOFA -export TAPEOUT_SCRIPT= -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Restructure Netlist Varaibles -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# export RESTRUCTURE_skipClockRestructure="" -# export RESTRUCTURE_Skeleton="" - -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# PNR RELATED FLOW -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -export INIT_DESIGN_INPUT="ASCII" - -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Extra variables availble during flow (suuffix FLOWVAR_) -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -export FLOWVAR_STANDARD_CELLS="sc_hd" diff --git a/openfpga-physical/Makefile b/openfpga-physical/Makefile index 5b4f357..04c3678 100644 --- a/openfpga-physical/Makefile +++ b/openfpga-physical/Makefile @@ -226,7 +226,7 @@ netlist_cleanup: run_openfpga # ===================== Copy Custom Modules ================================= # ============================================================================ if test -f "$${CUSTOM_MODULES_LIST}"; then - cat $${CUSTOM_MODULES_LIST} | while read line; do + cat $${CUSTOM_MODULES_LIST} | grep -v '^#' | while read line; do cp $$line $${VERILOG_PROJ_DIR}/SRCOriginal/CustomModules/; echo "[ Info] Copied custom module $$line" done