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[Sync] Updated sync file list

This commit is contained in:
Ganesh Gore 2020-12-14 15:29:41 -07:00
parent 06e220d7e4
commit 3f8a9ee1fe
6 changed files with 20 additions and 8 deletions
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3
.github/workflows/perform_precheck.sh vendored
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@ -44,8 +44,7 @@ mv ./gds/caravel_merged.gds ./gds/caravel.gds
# rm -f gds/caravel.old.gds # rm -f gds/caravel.old.gds
# = = = = = = = = = = = = = Perform Open MPW Checks = = = = = = = = = = = = = = # = = = = = = = = = = = = = Perform Open MPW Checks = = = = = = = = = = = = = =
if [[ ! -n "$SKIP_PRECHECK" ]]; then if [[ "$SKIP_PRECHECK" != 1 ]]; then
echo $SKIP_PRECHECK
echo "[Info] Running MPW Prechecker" echo "[Info] Running MPW Prechecker"
cd /usr/local/bin cd /usr/local/bin
python3 open_mpw_prechecker.py \ python3 open_mpw_prechecker.py \

11
.github/workflows/sync_repo.sh vendored
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@ -5,10 +5,13 @@
# Working directory in github workspace # Working directory in github workspace
# Original repo is places SOFA-Chips # Original repo is places SOFA-Chips
# for conditional file copy use PROJ_SUFFIX (example SOFA_HD) # for conditional file copy use PROJ_SUFFIX (example SOFA_HD)
COPY_FILE="./SOFA-Chips/SynRepoConfig/sync_files_${PROJ_SUFFIX,,}.csv"
tail -n +2 ./SOFA-Chips/SynRepoConfig/sync_files.csv | while IFS=, read -r srcLoc dstLoc; do echo "[Info] Using file for rsync $COPY_FILE"
Copying "./SOFA-Chips/$srcLoc --> ${DEST_DIR}/$dstLoc" tail -n +2 $COPY_FILE | while IFS=, read -r srcLoc dstLoc; do
rsync -avp ./SOFA-Chips/$srcLoc ${DEST_DIR}/$dstLoc srcLoc=$(echo $(eval "echo $srcLoc"))
dstLoc=$(echo $(eval "echo $dstLoc"))
echo "Copying ./SOFA-Chips/$srcLoc --> ${DEST_DIR}/$dstLoc"
rsync -ap ./SOFA-Chips/$srcLoc ${DEST_DIR}/$dstLoc
done done
cd ${DEST_DIR} cd ${DEST_DIR}

2
SynRepoConfig/sync_files.csv
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@ -1,2 +0,0 @@
SrcLoc, DestLoc
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/,OpenFPGA_task
1 SrcLoc DestLoc
2 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/ OpenFPGA_task

4
SynRepoConfig/sync_files_qlsofa_hd.csv Normal file
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@ -0,0 +1,4 @@
SrcLoc, DestLoc
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/,OpenFPGA_task
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
1 SrcLoc, DestLoc
2 FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/,OpenFPGA_task
3 FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
4 FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v

4
SynRepoConfig/sync_files_sofa_chd.csv Normal file
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@ -0,0 +1,4 @@
SrcLoc, DestLoc
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/,OpenFPGA_task
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
1 SrcLoc, DestLoc
2 FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/,OpenFPGA_task
3 FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
4 FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v

4
SynRepoConfig/sync_files_sofa_hd.csv Normal file
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@ -0,0 +1,4 @@
SrcLoc, DestLoc
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/,OpenFPGA_task
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
1 SrcLoc, DestLoc
2 FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/,OpenFPGA_task
3 FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
4 FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v