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add 4 global clocks

This commit is contained in:
Tarachand Pagarani 2021-01-14 02:28:07 -08:00
parent 40ddcdff67
commit 3f5409eee2
2 changed files with 3 additions and 3 deletions
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2
ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
View File

@ -229,7 +229,7 @@
</direct_connection>
<tile_annotations>
<global_port name="clk" is_clock="true" default_val="0">
<tile name="clb" port="clk" x="-1" y="-1"/>
<tile name="clb" port="clk[0:3]" x="-1" y="-1"/>
</global_port>
<global_port name="Reset" is_reset="true" default_val="1">
<tile name="clb" port="reset" x="-1" y="-1"/>

4
ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -134,7 +134,7 @@
<output name="sc_out" num_pins="1"/>
<output name="cout" num_pins="1"/>
<output name="cout_copy" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<clock name="clk" num_pins="4"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="reg_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="reg_out" fc_type="frac" fc_val="0"/>
@ -344,7 +344,7 @@
<output name="sc_out" num_pins="1"/>
<output name="cout" num_pins="1"/>
<output name="cout_copy" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<clock name="clk" num_pins="4"/>
<!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered