From 3f5409eee25ee49b2e43a68d8ab4eb7819166fa1 Mon Sep 17 00:00:00 2001
From: Tarachand Pagarani <tpagarani@quicklogic.com>
Date: Thu, 14 Jan 2021 02:28:07 -0800
Subject: [PATCH] add 4 global clocks

---
 ...r_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml | 2 +-
 ...der_register_scan_chain_nonLR_caravel_io_skywater130nm.xml | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
index 08baa4d..aee247d 100644
--- a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -229,7 +229,7 @@
   </direct_connection>
   <tile_annotations>
       <global_port name="clk" is_clock="true" default_val="0">
-          <tile name="clb" port="clk" x="-1" y="-1"/>
+          <tile name="clb" port="clk[0:3]" x="-1" y="-1"/>
       </global_port>
       <global_port name="Reset" is_reset="true" default_val="1">
           <tile name="clb" port="reset" x="-1" y="-1"/>
diff --git a/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index 767b5a2..86c2f16 100644
--- a/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -134,7 +134,7 @@
       <output name="sc_out" num_pins="1"/>
       <output name="cout" num_pins="1"/>
       <output name="cout_copy" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
+      <clock name="clk" num_pins="4"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
         <fc_override port_name="reg_in" fc_type="frac" fc_val="0"/>
         <fc_override port_name="reg_out" fc_type="frac" fc_val="0"/>
@@ -344,7 +344,7 @@
       <output name="sc_out" num_pins="1"/>
       <output name="cout" num_pins="1"/>
       <output name="cout_copy" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
+      <clock name="clk" num_pins="4"/>
       <!-- Describe fracturable logic element.  
              Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
              The outputs of the fracturable logic element can be optionally registered