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Merge branch 'master' into arch_exploration

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Andrew Pond 2021-04-06 08:08:01 -06:00 committed by GitHub
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93
.github/workflows/build.yml vendored
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@ -1,93 +0,0 @@
name: linux_build
# Run CI on
# - each push
# - each pull request
# - scheduled weekly
on:
push:
branches-ignore:
- ganesh_dev
pull_request:
schedule:
- cron: '0 0 * * 0 ' # weekly
# Environment variables
env:
# Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
BUILD_TYPE: Release
MAKEFLAGS: "-j8"
# Multiple job to tests
jobs:
# Test the compilation compatibility
linux_build:
name: ${{ matrix.config.name }}
runs-on: ${{ matrix.config.os }}
# Branch on different OS and settings
strategy:
fail-fast: false
matrix:
config:
- {
name: "Quick Test: GCC-8 (Ubuntu 18.04)",
artifact: "OpenFPGA-basic-tests-ubuntu-18.04-gcc8-build.7z",
os: ubuntu-18.04,
cc: "gcc-8", cxx: "g++-8",
reg_script: "quick_test.sh"
}
# Define the steps to run the build job
steps:
- name: Checkout Skywater-OpenFPGA repo
uses: actions/checkout@v2
- name: Checkout OpenFPGA repo
uses: actions/checkout@v2
with:
repository: lnis-uofu/OpenFPGA
path: OpenFPGA
submodules: true
- name: Install dependency
run: source ./.github/workflows/install_dependency.sh
- name: Checkout CMake version
run: cmake --version
- name: Checkout iVerilog version
run: |
iverilog -V
vvp -V
- name: Create CMake build environment
# Some projects don't allow in-source building, so create a separate build directory
# We'll use this as our working directory for all subsequent commands
run: cmake -E make_directory ${{runner.workspace}}/OpenFPGA/build
- name: Configure CMake
# Use a bash shell so we can use the same syntax for environment variable
# access regardless of the host operating system
shell: bash
working-directory: ${{runner.workspace}}/OpenFPGA/build
# Note the current convention is to use the -S and -B options here to specify source
# and build directories, but this is only available with CMake 3.13 and higher.
# The CMake binaries on the Github Actions machines are (as of this writing) 3.12
run: |
export CC=${{ matrix.config.cc }}
export CXX=${{ matrix.config.cxx }}
cmake $GITHUB_WORKSPACE/OpenFPGA -DCMAKE_BUILD_TYPE=$BUILD_TYPE
- name: Build
working-directory: ${{runner.workspace}}/OpenFPGA/build
shell: bash
# Execute the build. You can specify a specific target with "--target <NAME>"
run: |
cmake --build . --config $BUILD_TYPE
- name: ${{matrix.config.name}}
if: contains(matrix.config.name, 'Quick Test')
shell: bash
# Execute the test.
run: source ./.github/workflows/${{matrix.config.reg_script}}

50
.github/workflows/buildDocker.yml vendored Normal file
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@ -0,0 +1,50 @@
# ##############################################################################
# TODO: Add verification task after the netlist modification
################################################################################
name: Arch XML Regression
# Run CI on push on each branch
on:
push:
pull_request:
jobs:
generate_netlist:
name: Arch development
runs-on: ubuntu-18.04
container: ghcr.io/lnis-uofu/openfpga-master:latest
strategy:
fail-fast: false
matrix:
config:
- name: "FPGA1212_QLSOFA_HD"
- name: "FPGA1212_SOFA_CHD"
- name: "FPGA1212_SOFA_HD"
steps:
- name: Runner workspace path
run: |
echo "Cleaning up previous run"
rm -rf "${{ github.workspace }}"
mkdir -p "${{ github.workspace }}"
- name: Checkout OpenFPGA-ArcticPro3 repo
uses: actions/checkout@v2
- name: Detect changes
uses: technote-space/get-diff-action@v4
with:
PATTERNS: |
${{ matrix.config.name }}_PNR/*_task/**
- name: Running benchmark
shell: bash
if: ${{ env.GIT_DIFF || (github.event_name == 'pull_request' && github.ref == 'refs/heads/master') }}
run: |
${PYTHON_EXEC} -m pip install -r requirements.txt
cat ${{ matrix.config.name }}_PNR/${{ matrix.config.name }}_task/config/task_simulation.conf
cd ${{ matrix.config.name }}_PNR && make clean runOpenFPGA
- name: Upload artifact
uses: actions/upload-artifact@v2
if: ${{ failure() }}
with:
name: failed_${{matrix.config.name}}_regression_log
retention-days: 1
path: "${{ matrix.config.name }}_PNR/*_task/latest/*.log"

8
.github/workflows/perform_precheck.sh vendored
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@ -8,6 +8,13 @@ cd ./${DEST_DIR}
echo "[Info] Running in directory ${PWD}"
cp ../SOFA-Chips/${SCAN_DIRECTORY}/fpga_top_icv_in_design.gds.gz ./gds/
if test -f "./gds/fpga_top_icv_in_design.gds.gz.sha1"; then
sha1sum --status -c ./gds/fpga_top_icv_in_design.gds.gz.sha1
status=$?
[ $status -eq 0 ] && echo "SHA1 matched GDS is already merged ... skipping drc" && exit
fi
fpga_top_sha1=$(sha1sum ./gds/fpga_top_icv_in_design.gds.gz)
make uncompress
echo "[Info] All files are uncompressed"
@ -80,3 +87,4 @@ if [[ 0 -eq $(git cat-file -e $CARAVEL_COMPARE_COMMIT) ]]; then
/usr/local/workspace/${DEST_DIR}/checks/compare_caravel.txt
echo "[Info] Create compare_caravel.txt"
fi
echo $fpga_top_sha1 > ./gds/fpga_top_icv_in_design.gds.gz.sha1

4
.gitignore vendored
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@ -11,3 +11,7 @@
**/SRC**/*_tb.v
**/SDC/**/*.sdc
!**/SDC/**/disable_configure_ports.sdc
*/runOpenFPGA
**/*_task/latest
**/*_task/run**
**/*_task/config/task.conf

8
ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
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@ -18,9 +18,9 @@ LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT3_DELAY: 2.31e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9
LUT4_DELAY: 2.6e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9
LUT3_DELAY: 0.86e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
LUT4_DELAY: 1.14e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
REGIN_TO_FF0_DELAY: 0.58e-9
FF0_TO_FF1_DELAY: 0.56e-9

32
ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
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@ -1,7 +1,7 @@
L1_SB_MUX_DELAY: 1.44e-9
L2_SB_MUX_DELAY: 1.44e-9
L4_SB_MUX_DELAY: 1.44e-9
CB_MUX_DELAY: 1.38e-9
L1_SB_MUX_DELAY: 0.81e-9
L2_SB_MUX_DELAY: 0.81e-9
L4_SB_MUX_DELAY: 0.81e-9
CB_MUX_DELAY: 0.57e-9
L1_WIRE_R: 100
L1_WIRE_C: 1e-12
L2_WIRE_R: 100
@ -12,15 +12,15 @@ INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT3_DELAY: 2.31e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9
LUT4_DELAY: 2.6e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9
REGIN_TO_FF0_DELAY: 1.12e-9
FF0_TO_FF1_DELAY: 0.56e-9
LUT_OUT0_TO_FF_D_DELAY: 0.32e-9
LUT_OUT1_TO_FF_D_DELAY: 0.16e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.65e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.48e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.47e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.37e-9
LUT3_DELAY: 0.86e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 0.65e-9
LUT4_DELAY: 1.20e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 0.66e-9
REGIN_TO_FF0_DELAY: 0.15e-9
FF0_TO_FF1_DELAY: 0.16e-9

8
ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
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@ -18,9 +18,9 @@ LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT3_DELAY: 2.31e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9
LUT4_DELAY: 2.6e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9
LUT3_DELAY: 0.92e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
LUT4_DELAY: 1.21e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
REGIN_TO_FF0_DELAY: 1.12e-9
FF0_TO_FF1_DELAY: 0.56e-9

26
DOC/source/conf.py
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@ -23,16 +23,16 @@ import sphinx_rtd_theme
#html_theme = "sphinx_rtd_theme"
#html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
# Import sphinxcontrib.bibtex
have_sphinxcontrib_bibtex = True
try:
import sphinxcontrib.bibtex
except ImportError:
have_sphinxcontrib_bibtex = False
# For bibtex support
import sphinxcontrib.bibtex
# For embedded youtube
import sphinxcontrib.yt
# For converting SVG to PNG using rsvg
import sphinxcontrib.rsvgconverter
# -- Project information -----------------------------------------------------
project = u'Skywater-OpenFPGA Chips'
project = u'SOFA eFPGAs'
copyright = u'2020, Xifan Tang'
author = u'Xifan Tang'
@ -57,6 +57,8 @@ extensions = [
'sphinx.ext.graphviz',
'sphinxcontrib.bibtex',
'sphinx.ext.autosectionlabel',
'sphinxcontrib.yt',
'sphinxcontrib.rsvgconverter',
]
# Add any paths that contain templates here, relative to this directory.
@ -129,7 +131,7 @@ html_theme = 'sphinx_rtd_theme'
# -- Options for HTMLHelp output ---------------------------------------------
# Output file base name for HTML help builder.
htmlhelp_basename = 'OpenFPGAdoc'
htmlhelp_basename = 'SOFAdoc'
# -- Options for LaTeX output ------------------------------------------------
@ -156,7 +158,7 @@ latex_elements = {
# (source start file, target name, title,
# author, documentclass [howto, manual, or own class]).
latex_documents = [
(master_doc, 'OpenFPGA.tex', u'OpenFPGA Documentation',
(master_doc, 'SOFA.tex', u'SOFA Documentation',
u'Xifan Tang', 'manual'),
]
@ -166,7 +168,7 @@ latex_documents = [
# One entry per manual page. List of tuples
# (source start file, name, description, authors, manual section).
man_pages = [
(master_doc, 'openfpga', u'OpenFPGA Documentation',
(master_doc, 'sofa', u'SOFA Documentation',
[author], 1)
]
@ -177,8 +179,8 @@ man_pages = [
# (source start file, target name, title, author,
# dir menu entry, description, category)
texinfo_documents = [
(master_doc, 'Skywater-OpenFPGA', u'Skywater-OpenFPGA Documentation',
author, 'Skywater-OpenFPGA', 'Open-source FPGA chips built with Skywater PDK and OpenFPGA.',
(master_doc, 'SOFA', u'SOFA Documentation',
author, 'SOFA', 'Open-source FPGA chips built with Skywater PDK and OpenFPGA.',
'Miscellaneous'),
]

11
DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg
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@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
<svg xmlns:xl="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" xmlns:dc="http://purl.org/dc/elements/1.1/" version="1.1" viewBox="130.62533 187.22044 463.9655 252.71838" width="463.9655" height="252.71838">
<svg version="1.1" xmlns:xl="http://www.w3.org/1999/xlink" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns="http://www.w3.org/2000/svg" viewBox="130.62533 187.22044 463.9655 252.71838" width="463.9655" height="252.71838">
<defs>
<font-face font-family="Times New Roman" font-size="15" panose-1="2 2 8 3 7 5 5 2 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="0" x-height="456.54297" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-weight="700">
<font-face-src>
@ -23,8 +23,8 @@
</font-face-src>
</font-face>
</defs>
<metadata> Produced by OmniGraffle 7.18.4\n2021-04-02 20:35:25 +0000</metadata>
<g id="schematic_timing" stroke-dasharray="none" fill-opacity="1" stroke-opacity="1" fill="none" stroke="none">
<metadata> Produced by OmniGraffle 7.18.4\n2021-04-03 20:07:23 +0000</metadata>
<g id="schematic_timing" stroke="none" stroke-opacity="1" stroke-dasharray="none" fill="none" fill-opacity="1">
<title>schematic_timing</title>
<g id="schematic_timing_图层_1">
<title>图层 1</title>
@ -392,6 +392,11 @@
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">A</tspan>
</text>
</g>
<g id="Graphic_266">
<text transform="translate(223.72933 316.22945)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">B</tspan>
</text>
</g>
</g>
</g>
</svg>

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28
DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst
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@ -8,12 +8,12 @@ Timing Annotation
Configurable Logic Block
^^^^^^^^^^^^^^^^^^^^^^^^
The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`.
The path delays in :numref:`fig_qlsofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`.
.. _fig_qlsofa_hd_fle_arch_timing:
.. figure:: ./figures/qlsofa_hd_fle_arch_timing.svg
:scale: 30%
:width: 80%
:alt: Schematic of a logic element used in QLSOFA HD FPGA
Schematic of a logic element used in QLSOFA HD FPGA
@ -25,25 +25,27 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`
+-------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+=========================+==============================+
| in0 -> LUT3_out[0] [1]_ | 2.31 |
| in0 -> LUT3_out[0] | 0.85 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[0] [1]_ | 2.31 |
| in1 -> LUT3_out[0] | 0.57 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[0] [1]_ | 2.31 |
| in2 -> B | 0.60 |
+-------------------------+------------------------------+
| in0 -> LUT3_out[1] [1]_ | 2.31 |
| B -> LUT3_out[0] | 0.32 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[1] [1]_ | 2.31 |
| in0 -> LUT3_out[1] | 0.90 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[1] [1]_ | 2.31 |
| in1 -> LUT3_out[1] | 0.62 |
+-------------------------+------------------------------+
| in0 -> LUT4_out [1]_ | 2.60 |
| B -> LUT3_out[1] | 0.33 |
+-------------------------+------------------------------+
| in1 -> LUT4_out [1]_ | 2.60 |
| in0 -> LUT4_out | 1.17 |
+-------------------------+------------------------------+
| in2 -> LUT4_out [1]_ | 2.60 |
| in1 -> LUT4_out | 0.89 |
+-------------------------+------------------------------+
| in3 -> LUT4_out [1]_ | 2.60 |
| in2 -> LUT4_out | 1.21 |
+-------------------------+------------------------------+
| in3 -> LUT4_out | 0.79 |
+-------------------------+------------------------------+
| LUT3_out[0] -> A | 0.56 |
+-------------------------+------------------------------+
@ -66,8 +68,6 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`
| FF[0] -> FF[1] | 0.56 |
+-------------------------+------------------------------+
.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques.
.. _qlsofa_hd_timing_io:
I/O Block

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DOC/source/datasheet/sofa_chd/custom_cells/cell_eval/SKY130_UUOPENFPGA_CC_HD_INVMUX2_1.pdf Normal file
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DOC/source/datasheet/sofa_chd/custom_cells/custom_cells.rst Normal file
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@ -0,0 +1,133 @@
=========================================================
Skywater Custom Multiplexer Cells
=========================================================
Background
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Traditionally, larger multiplexers are built using trees of smaller multiplexers as illustrated below:
.. image:: figures/mux_tree.png
:align: center
:alt: Traditional Multiplexer Tree
Multiplexers trees lead to large power and timing constraints that limit FPGA performance. FPGA fabrics use complementary pass gate logic (CPL) to replace multiplexer trees with single level inverted transmission gate derived multiplexers, as illustrated below:
.. image:: figures/fpga_mux.png
:height: 300px
:width: 800px
:align: center
:alt: Single Level FPGA Multiplexer
Single level multiplexers are controlled through configuration SRAM cells which enable high impedance connections throughout the multiplexer hierarchy, thereby removing the need for hierarchical designs of multiplexers. Therefore, the CPL multiplexers enable increased performance and reduced power consumption throughout FPGA fabrics. Standard cells required for CPL multiplexers are not commonly included in PDKs, thereby requiring the need for custom cell creation to enable FPGA multiplexer hierarchies. The remainder of this document is dedicated to the architecture and performance evaluation of our *sky130_uuopenfpga_cc_hd_invmux2_1*/*sky130_uuopenfpga_cc_hd_invmux3_1* custom cells generated using the Skywater 130nm PDK. A comparison is achieved by generating 4-to-1 multiplexer and 6-to-1 multiplexers made from our cells and standard cells provided within the Skywater 130nm PDK.
.. INVMUX2_1
SKY130_UUOPENFPGA_CC_HD_INVMUX2_1
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- Usage: 2-Input Transmission Gate Multiplexer with Unity Drive Strength Inverter Input
-Pins:
- Q1/Q2 - Inverter Input
- S0/S1 - NMOS Select Input
- S0B/S1B - PMOS Select Input
- Schematic:
.. image:: figures/sky130_fd_sc_hd_mux2_1\ schematic.png
:height: 350px
:width: 500px
:align: center
:alt: Sky130_uuopenfpga_cc_hd_invmux2_1 Schematic
- Layout:\
.. image:: figures/sky130_fd_sc_hd_mux2_1\ gds.png
:height: 400px
:width: 800px
:align: center
:alt: Sky130_uuopenfpga_cc_hd_invmux2_1 Layout
- Comparison: To demonstrate the performance gains using CPL multiplexers, we built a 4-1 single level multiplexer using our custom *sky130_uuopenfpga_cc_hd_invmux2_1* cell along with a 4-to-1 multiplexer using the *sky130_fd_sc_hd__mux2_1* as the root cell of the multiplexer tree.
The *sky130_fd_sc_hd_mux2_1* multiplexer is built using a static CMOS structure with a single select input, whereas our cell uses a fractured select hierarchy. To perform the comparisons we have tabulated values in regards to power, area, and timing for the 4-to-1 multiplexer tree using Cadence ADE XL.
- Power:
- sky130_uuopenfpga_cc_hd_invmux2_1: 2.37 μW
- sky130_fd_sc_hd__mux2_1: 3.03 μW
Our custom multiplexer provides a 22\% reduction in power consumption.
- Area:
- sky130_uuopenfpga_cc_hd_invmux2_1: 33.78 μA\ :sup:`2`
- sky130_fd_sc_hd__mux2_1: 33.78 μA\ :sup:`2`
Our multiplexer implementation requires equal area neglecting interconnect overhead.
- Timing:
- sky130_uuopenfpga_cc_hd_invmux2_1: 211.1 ps
- sky130_fd_sc_hd__mux2_1: 304.3 ps
Our custom multiplexer provides over a 31\% reduction in propagation delay.
`SKY130_UUOPENFPGA_CC_HD_INVMUX2_1 Cell Characterization`_
.. _`SKY130_UUOPENFPGA_CC_HD_INVMUX2_1 Cell Characterization`: https://github.com/lnis-uofu/SOFA/blob/master/DOC/source/datasheet/sofa_chd/custom_cells/cell_eval/SKY130_UUOPENFPGA_CC_HD_INVMUX2_1.pdf
.. INVMUX2_1
.. INVMUX3_1
SKY130_UUOPENFPGA_CC_HD_INVMUX3_1
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- Usage: 3-Input Transmission Gate Multiplexer with Unity Drive Strength Inverter Input
- Pins:
- Q2/Q3 - Inverted Input
- S0/S1/S2 - NMOS Select Input
- S0B/S1B/S2B - PMOS Select Input
- Schematic:
.. image:: figures/sky130_fd_sc_hd_mux3_1\ schematic.png
:height: 550px
:width: 500px
:align: center
:alt: Sky130_uuopenfpga_cc_hd_invmux3_1 Schematic
- Layout:
.. image:: figures/sky130_fd_sc_hd_mux3_1\ gds.png
:height: 350px
:width: 1100px
:align: center
:alt: Sky130_uuopenfpga_cc_hd_invmux3_1 Layout
- Comparison: To demonstrate the performance gains using CPL multiplexers, we built a 6-1 single level multiplexer using our custom *sky130_uuopenfpga_cc_hd_invmux3_1* cell along with a 6-to-1 multiplexer using the *sky130_fd_sc_hd__mux4/2_1* as the root cells of the multiplexer tree.
To perform the comparisons we have tabulated values in regards to power, area, and timing for the 4-to-1 multiplexer tree using Cadence ADE XL.
- Power:
- sky130_uuopenfpga_cc_hd_invmux3_1: 2.96 μW
- sky130_fd_sc_hd__mux2_1: 3.31 μW
Our custom multiplexer provides a 10.5\% reduction in power consumption.
- Area:
- sky130_uuopenfpga_cc_hd_invmux3_1: 61.31 μA\ :sup:`2`
- sky130_fd_sc_hd__mux2_1: 48.80 μA\ :sup:`2`
The Skywater multiplexer provides a 20\% reduction in area.
- Timing:
- sky130_uuopenfpga_cc_hd_invmux3_1: 272.6 ps
- sky130_fd_sc_hd__mux2_1: 374.2 ps
Our custom multiplexer provides over a 27\% reduction in propagation delay.
`SKY130_UUOPENFPGA_CC_HD_INVMUX3_1 Cell Characterization`_
.. _`SKY130_UUOPENFPGA_CC_HD_INVMUX3_1 Cell Characterization`: https://github.com/lnis-uofu/SOFA/blob/master/DOC/source/datasheet/sofa_chd/custom_cells/cell_eval/SKY130_UUOPENFPGA_CC_HD_INVMUX3_1.pdf
.. INVMUX3_1

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DOC/source/datasheet/sofa_chd/custom_cells/index.rst Normal file
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@ -0,0 +1,10 @@
.. _custom_cells:
Custom Cells
Custom Cells
--------
.. toctree::
:maxdepth: 2
custom_cells

11
DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg
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@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
<svg xmlns:xl="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" xmlns:dc="http://purl.org/dc/elements/1.1/" version="1.1" viewBox="130.62533 187.22044 463.9655 252.71838" width="463.9655" height="252.71838">
<svg version="1.1" xmlns:xl="http://www.w3.org/1999/xlink" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns="http://www.w3.org/2000/svg" viewBox="130.62533 187.22044 463.9655 252.71838" width="463.9655" height="252.71838">
<defs>
<font-face font-family="Times New Roman" font-size="15" panose-1="2 2 8 3 7 5 5 2 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="0" x-height="456.54297" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-weight="700">
<font-face-src>
@ -23,8 +23,8 @@
</font-face-src>
</font-face>
</defs>
<metadata> Produced by OmniGraffle 7.18.4\n2021-04-02 20:35:25 +0000</metadata>
<g id="schematic_timing" stroke-dasharray="none" fill-opacity="1" stroke-opacity="1" fill="none" stroke="none">
<metadata> Produced by OmniGraffle 7.18.4\n2021-04-03 20:07:23 +0000</metadata>
<g id="schematic_timing" stroke="none" stroke-opacity="1" stroke-dasharray="none" fill="none" fill-opacity="1">
<title>schematic_timing</title>
<g id="schematic_timing_图层_1">
<title>图层 1</title>
@ -392,6 +392,11 @@
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">A</tspan>
</text>
</g>
<g id="Graphic_266">
<text transform="translate(223.72933 316.22945)" fill="#ff2600">
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">B</tspan>
</text>
</g>
</g>
</g>
</svg>

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2
DOC/source/datasheet/sofa_chd/index.rst
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@ -16,3 +16,5 @@ SOFA CHD
sofa_chd_circuit_design
sofa_chd_timing
custom_cells/index

53
DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst
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@ -13,7 +13,7 @@ The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref:
.. _fig_sofa_chd_fle_arch_timing:
.. figure:: ./figures/sofa_chd_fle_arch_timing.svg
:scale: 30%
:width: 80%
:alt: Schematic of a logic element used in SOFA CHD FPGA
Schematic of a logic element used in SOFA CHD FPGA
@ -25,48 +25,49 @@ The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref:
+-------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+=========================+==============================+
| in0 -> LUT3_out[0] [1]_ | 2.31 |
| in0 -> LUT3_out[0] | 0.86 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[0] [1]_ | 2.31 |
| in1 -> LUT3_out[0] | 0.58 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[0] [1]_ | 2.31 |
| in2 -> B | 0.16 |
+-------------------------+------------------------------+
| in0 -> LUT3_out[1] [1]_ | 2.31 |
| B -> LUT3_out[0] | 0.32 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[1] [1]_ | 2.31 |
| in0 -> LUT3_out[1] | 0.91 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[1] [1]_ | 2.31 |
| in1 -> LUT3_out[1] | 0.63 |
+-------------------------+------------------------------+
| in0 -> LUT4_out [1]_ | 2.60 |
| B -> LUT3_out[1] | 0.34 |
+-------------------------+------------------------------+
| in1 -> LUT4_out [1]_ | 2.60 |
| in0 -> LUT4_out | 1.20 |
+-------------------------+------------------------------+
| in2 -> LUT4_out [1]_ | 2.60 |
| in1 -> LUT4_out | 0.92 |
+-------------------------+------------------------------+
| in3 -> LUT4_out [1]_ | 2.60 |
| in2 -> LUT4_out | 0.78 |
+-------------------------+------------------------------+
| LUT3_out[0] -> A | 0.56 |
| in3 -> LUT4_out | 0.52 |
+-------------------------+------------------------------+
| LUT4_out[0] -> A | 0.58 |
| LUT3_out[0] -> A | 0.17 |
+-------------------------+------------------------------+
| A -> out[0] | 0.88 |
| LUT4_out[0] -> A | 0.18 |
+-------------------------+------------------------------+
| A -> FF[0] | 0.56 |
| A -> out[0] | 0.48 |
+-------------------------+------------------------------+
| FF[0] -> out[0] | 0.88 |
| A -> FF[0] | 0.15 |
+-------------------------+------------------------------+
| LUT3_out[1] -> out[1] | 0.89 |
| FF[0] -> out[0] | 0.48 |
+-------------------------+------------------------------+
| LUT3_out[1] -> FF[1] | 0.56 |
| LUT3_out[1] -> out[1] | 0.47 |
+-------------------------+------------------------------+
| FF[1] -> out[1] | 0.89 |
| LUT3_out[1] -> FF[1] | 0.16 |
+-------------------------+------------------------------+
| regin -> FF[0] | 0.58 |
| FF[1] -> out[1] | 0.37 |
+-------------------------+------------------------------+
| FF[0] -> FF[1] | 0.56 |
| regin -> FF[0] | 0.15 |
+-------------------------+------------------------------+
| FF[0] -> FF[1] | 0.16 |
+-------------------------+------------------------------+
.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques.
.. _sofa_chd_timing_io:
@ -89,12 +90,12 @@ The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`tab
+---------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+===========================+==============================+
| A -> B | 1.44 |
| A -> B | 0.81 |
+---------------------------+------------------------------+
| A -> C | 1.44 |
| A -> C | 0.81 |
+---------------------------+------------------------------+
| A -> D | 1.44 |
| A -> D | 0.81 |
+---------------------------+------------------------------+
| B -> E | 1.38 |
| B -> E | 0.57 |
+---------------------------+------------------------------+

24
DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst
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@ -13,7 +13,7 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`
.. _fig_sofa_hd_fle_arch_timing:
.. figure:: ./figures/sofa_hd_fle_arch_timing.svg
:scale: 30%
:width: 80%
:alt: Schematic of a logic element used in SOFA HD FPGA
Schematic of a logic element used in SOFA HD FPGA
@ -25,25 +25,25 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`
+-------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+=========================+==============================+
| in0 -> LUT3_out[0] [1]_ | 2.31 |
| in0 -> LUT3_out[0] | 0.85 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[0] [1]_ | 2.31 |
| in1 -> LUT3_out[0] | 0.57 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[0] [1]_ | 2.31 |
| in2 -> LUT3_out[0] | 0.30 |
+-------------------------+------------------------------+
| in0 -> LUT3_out[1] [1]_ | 2.31 |
| in0 -> LUT3_out[1] | 0.86 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[1] [1]_ | 2.31 |
| in1 -> LUT3_out[1] | 0.59 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[1] [1]_ | 2.31 |
| in2 -> LUT3_out[1] | 0.31 |
+-------------------------+------------------------------+
| in0 -> LUT4_out [1]_ | 2.60 |
| in0 -> LUT4_out | 1.14 |
+-------------------------+------------------------------+
| in1 -> LUT4_out [1]_ | 2.60 |
| in1 -> LUT4_out | 0.86 |
+-------------------------+------------------------------+
| in2 -> LUT4_out [1]_ | 2.60 |
| in2 -> LUT4_out | 0.58 |
+-------------------------+------------------------------+
| in3 -> LUT4_out [1]_ | 2.60 |
| in3 -> LUT4_out | 0.51 |
+-------------------------+------------------------------+
| LUT3_out[0] -> A | 0.56 |
+-------------------------+------------------------------+
@ -66,8 +66,6 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`
| FF[0] -> FF[1] | 0.56 |
+-------------------------+------------------------------+
.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques.
.. _sofa_hd_timing_io:
I/O Block

1
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/BENCHMARK Symbolic link
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@ -0,0 +1 @@
../../BENCHMARK

169
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/vpr_arch.xml
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@ -1,5 +1,5 @@
<!--
Low-cost homogeneous FPGA Architecture.
Low-cost homogeneous FPGA Architecture for QLSOFA_HD.
- Skywater 130 nm technology
- General purpose logic block:
@ -214,21 +214,6 @@
</fixed_layout>
</layout>
<device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
lined up with Stratix IV.
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
by 2.5x when looking up in Jeff's tables.
The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
@ -242,41 +227,25 @@
<connection_block input_switch_name="ipin_cblock"/>
</device>
<switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L1_mux" R="0" Cin="0" Cout="0" Tdel="${L1_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="0" Cin="0" Cout="0" Tdel="${L2_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="0" Cin="0" Cout="0" Tdel="${L4_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
<switch type="mux" name="ipin_cblock" R="0" Cout="0" Cin="0" Tdel="${CB_MUX_DELAY}" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist>
<segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="${L1_WIRE_R}" Cmetal="${L1_WIRE_C}">
<mux name="L1_mux"/>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="${L2_WIRE_R}" Cmetal="${L2_WIRE_C}">
<mux name="L2_mux"/>
<sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1</cb>
</segment>
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="${L4_WIRE_R}" Cmetal="${L4_WIRE_C}">
<mux name="L4_mux"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
@ -306,10 +275,10 @@
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
<delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
<delay_constant max="${INPAD_DELAY}" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
@ -325,7 +294,7 @@
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
<delay_constant max="${INPAD_DELAY}" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
@ -335,7 +304,7 @@
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
<delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
@ -440,10 +409,10 @@
<input name="reset" num_pins="1"/>
<output name="Q" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_setup value="66e-12" port="ff.DI" clock="clk"/>
<T_setup value="66e-12" port="ff.reset" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.DI" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.reset" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
@ -456,22 +425,22 @@
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<complete name="complete2" input="fabric.reset" output="ff[1:0].reset"/>
<mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
<delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
</mux>
<mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
<delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
<delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
<delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
</mux>
<mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
<delay_constant max="${LUT_OUT0_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux>
<mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
<delay_constant max="${LUT_OUT1_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux>
</interconnect>
</pb_type>
@ -504,18 +473,10 @@
<input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
-->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
235e-12
235e-12
235e-12
${LUT3_DELAY}
${LUT3_DELAY}
${LUT3_DELAY}
</delay_matrix>
</pb_type>
<!-- Define the flip-flop -->
@ -523,8 +484,8 @@
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
@ -535,8 +496,8 @@
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
<delay_constant max="${LUT3_OUT_TO_FLE_OUT_DELAY}" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux>
</interconnect>
</pb_type>
@ -566,20 +527,11 @@
<input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
397e-12
-->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12
261e-12
261e-12
261e-12
${LUT4_DELAY}
${LUT4_DELAY}
${LUT4_DELAY}
${LUT4_DELAY}
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
@ -587,20 +539,21 @@
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut4.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
<delay_constant max="${LUT4_OUT_TO_FLE_OUT_DELAY}" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff.Q" out_port="ble4.out"/>
</mux>
</interconnect>
</pb_type>
@ -622,15 +575,23 @@
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D"/>
<direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D">
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="shift_reg.reg_in" out_port="ff[0].D"/>
</direct>
<direct name="direct2" input="ff[0].Q" output="ff[1].D">
<delay_constant max="${FF0_TO_FF1_DELAY}" in_port="ff[0].Q" out_port="ff[1].D"/>
</direct>
<direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]"/>
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]"/>
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]">
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="shift_reg.ff_out[0:0]"/>
</direct>
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]">
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="shift_reg.ff_out[1:1]"/>
</direct>
<complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
</interconnect>
</pb_type>
@ -652,52 +613,36 @@
I[0] should be connected to in[0]
-->
<direct name="direct_fle0" input="clb.I0[0:1]" output="fle[0:0].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle0i" input="clb.I0i[0:1]" output="fle[0:0].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle1" input="clb.I1[0:1]" output="fle[1:1].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle1i" input="clb.I1i[0:1]" output="fle[1:1].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle2" input="clb.I2[0:1]" output="fle[2:2].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle2i" input="clb.I2i[0:1]" output="fle[2:2].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle3" input="clb.I3[0:1]" output="fle[3:3].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle3i" input="clb.I3i[0:1]" output="fle[3:3].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle4" input="clb.I4[0:1]" output="fle[4:4].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle4i" input="clb.I4i[0:1]" output="fle[4:4].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle5" input="clb.I5[0:1]" output="fle[5:5].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle5i" input="clb.I5i[0:1]" output="fle[5:5].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle6" input="clb.I6[0:1]" output="fle[6:6].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle6i" input="clb.I6i[0:1]" output="fle[6:6].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle7" input="clb.I7[0:1]" output="fle[7:7].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle7i" input="clb.I7i[0:1]" output="fle[7:7].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<complete name="clks" input="clb.clk" output="fle[7:0].clk">
</complete>
@ -713,7 +658,7 @@
<!-- Shift register chain links -->
<direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
<delay_constant max="0" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
<!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
</direct>
<direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
@ -725,7 +670,7 @@
<!-- Scan chain links -->
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
<delay_constant max="0" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
</direct>
<direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
</direct>
@ -734,7 +679,7 @@
<!-- Carry chain links -->
<direct name="carry_chain_in" input="clb.cin" output="fle[0:0].cin">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
<delay_constant max="0" in_port="clb.cin" out_port="fle[0:0].cin"/>
</direct>
<direct name="carry_chain_out" input="fle[7:7].cout" output="clb.cout">
</direct>

45
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task_simulation.conf
View File

@ -8,26 +8,47 @@
[GENERAL]
run_engine=openfpga_shell
power_analysis = false
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=60
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif
bench0=${PATH:TASK_DIR}/BENCHMARK/and2/and2.v
bench1=${PATH:TASK_DIR}/BENCHMARK/and2_latch/and2_latch.v
bench2=${PATH:TASK_DIR}/BENCHMARK/bin2bcd/bin2bcd.v
bench3=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
bench4=${PATH:TASK_DIR}/BENCHMARK/routing_test/routing_test.v
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5=${PATH:TASK_DIR}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${PATH:TASK_DIR}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${PATH:TASK_DIR}/BENCHMARK/and2_or2/and2_or2.v
[SYNTHESIS_PARAM]
bench0_top = top
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v
bench0_top = and2
bench1_top = and2_latch
bench2_top = bin2bcd
bench3_top = counter
bench4_top = routing_test
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5_top = rs_decoder_top
bench6_top = top_module
bench7_top = and2_or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
vpr_fpga_verilog_formal_verification_top_netlist=
#end_flow_with_test=

27
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/design_variables.yml
View File

@ -1 +1,26 @@
DELAY_VALUE: 12
L1_SB_MUX_DELAY: 1.44e-9
L2_SB_MUX_DELAY: 1.44e-9
L4_SB_MUX_DELAY: 1.44e-9
CB_MUX_DELAY: 1.38e-9
L1_WIRE_R: 100
L1_WIRE_C: 1e-12
L2_WIRE_R: 100
L2_WIRE_C: 1e-12
L4_WIRE_R: 100
L4_WIRE_C: 1e-12
INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT3_DELAY: 0.92e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
LUT4_DELAY: 1.21e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
REGIN_TO_FF0_DELAY: 1.12e-9
FF0_TO_FF1_DELAY: 0.56e-9

14
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_fabric.openfpga
View File

@ -36,9 +36,19 @@ write_fabric_bitstream --format xml --file fabric_bitstream.xml
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --verbose
write_fabric_verilog \
--file ./SRC \
--explicit_port_mapping \
--include_timing \
--verbose
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
write_verilog_testbench \
--file ./SRC \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--print_top_testbench \
--print_preconfig_top_testbench \
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
--explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

45
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga
View File

@ -1,6 +1,12 @@
# Run VPR for the 'and' design
# This script is designed to generate Verilog testbenches
# with a fixed device layout
# It will only output netlists to be used by verification tools
# including
# - Verilog testbenches, used by ModelSim
# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
#
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --route_chan_width 200
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
@ -24,11 +30,7 @@ lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE}
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
@ -37,28 +39,29 @@ repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_fabric_bitstream
build_architecture_bitstream --verbose --write_file arch_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream
write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
write_fabric_bitstream --format xml --file fabric_bitstream.xml
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
write_verilog_testbench --file ./SRC \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--print_top_testbench \
--print_preconfig_top_testbench \
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
--explicit_port_mapping
# Exclude signal initialization since it does not help simulator converge
# due to the lack of reset pins for flip-flops
#--include_signal_init
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis

40
FPGA1212_QLSOFA_HD_PNR/Makefile Normal file
View File

@ -0,0 +1,40 @@
##########################################################################################
##########################################################################################
SHELL=bash
PYTHON_EXEC=python3.8
RERUN = 0
TB = top
OPTIONS =
.SILENT:
.ONESHELL:
runOpenFPGA:
SECONDS=0
source config.sh
# ===================== Check Tools =====================
which python3.8 > /dev/null
if [ $$? -eq 1 ]; then
echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
fi
# =================== Clean Previous Run =================================
rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf)
# ===================== Generate Netlist =================================
(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
run-task $${TASK_DIR_NAME} --remove_run_dir all
run-task $${TASK_DIR_NAME} ${OPTIONS})
if [ $$? -eq 1 ]; then
echo "X X X X X X Failed to generate netlist X X X X X X"; exit;
fi
duration=$$SECONDS
date > runOpenFPGA
echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA
clean:
rm -rf runOpenFPGA

1
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/BENCHMARK Symbolic link
View File

@ -0,0 +1 @@
../../BENCHMARK

4
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/arch/openfpga_arch.xml
View File

@ -288,10 +288,10 @@
</direct_connection>
<tile_annotations>
<global_port name="clk" is_clock="true" default_val="0">
<tile name=="clb" port="clk" x="-1" y="-1"/>
<tile name="clb" port="clk" x="-1" y="-1"/>
</global_port>
<global_port name="Reset" is_reset="true" default_val="1">
<tile name=="clb" port="reset" x="-1" y="-1"/>
<tile name="clb" port="reset" x="-1" y="-1"/>
</global_port>
</tile_annotations>
<pb_type_annotations>

179
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/arch/vpr_arch.xml
View File

@ -1,5 +1,5 @@
<!--
Low-cost homogeneous FPGA Architecture.
Low-cost homogeneous FPGA Architecture for SOFA_CHD.
- Skywater 130 nm technology
- General purpose logic block:
@ -202,23 +202,18 @@
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</fixed_layout>
<fixed_layout name="16x16" width="18" height="18">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<row type="io_top" starty="H-1" priority="100"/>
<row type="io_bottom" starty="0" priority="100"/>
<col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</fixed_layout>
</layout>
<device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
lined up with Stratix IV.
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
by 2.5x when looking up in Jeff's tables.
The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
@ -232,41 +227,25 @@
<connection_block input_switch_name="ipin_cblock"/>
</device>
<switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L1_mux" R="0" Cin="0" Cout="0" Tdel="${L1_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="0" Cin="0" Cout="0" Tdel="${L2_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="0" Cin="0" Cout="0" Tdel="${L4_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
<switch type="mux" name="ipin_cblock" R="0" Cout="0" Cin="0" Tdel="${CB_MUX_DELAY}" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist>
<segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="${L1_WIRE_R}" Cmetal="${L1_WIRE_C}">
<mux name="L1_mux"/>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="${L2_WIRE_R}" Cmetal="${L2_WIRE_C}">
<mux name="L2_mux"/>
<sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1</cb>
</segment>
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="${L4_WIRE_R}" Cmetal="${L4_WIRE_C}">
<mux name="L4_mux"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
@ -296,10 +275,10 @@
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
<delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
<delay_constant max="${INPAD_DELAY}" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
@ -315,7 +294,7 @@
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
<delay_constant max="${INPAD_DELAY}" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
@ -325,7 +304,7 @@
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
<delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
@ -430,10 +409,10 @@
<input name="reset" num_pins="1"/>
<output name="Q" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_setup value="66e-12" port="ff.DI" clock="clk"/>
<T_setup value="66e-12" port="ff.reset" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.DI" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.reset" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
@ -446,22 +425,22 @@
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<complete name="complete2" input="fabric.reset" output="ff[1:0].reset"/>
<mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
<delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
</mux>
<mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
<delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
<delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
<delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
</mux>
<mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
<delay_constant max="${LUT_OUT0_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux>
<mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
<delay_constant max="${LUT_OUT1_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux>
</interconnect>
</pb_type>
@ -494,18 +473,10 @@
<input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
-->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
235e-12
235e-12
235e-12
${LUT3_DELAY}
${LUT3_DELAY}
${LUT3_DELAY}
</delay_matrix>
</pb_type>
<!-- Define the flip-flop -->
@ -513,8 +484,8 @@
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
@ -525,8 +496,8 @@
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
<delay_constant max="${LUT3_OUT_TO_FLE_OUT_DELAY}" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux>
</interconnect>
</pb_type>
@ -556,20 +527,11 @@
<input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
397e-12
-->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12
261e-12
261e-12
261e-12
${LUT4_DELAY}
${LUT4_DELAY}
${LUT4_DELAY}
${LUT4_DELAY}
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
@ -577,20 +539,21 @@
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut4.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
<delay_constant max="${LUT4_OUT_TO_FLE_OUT_DELAY}" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff.Q" out_port="ble4.out"/>
</mux>
</interconnect>
</pb_type>
@ -612,15 +575,23 @@
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D"/>
<direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D">
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="shift_reg.reg_in" out_port="ff[0].D"/>
</direct>
<direct name="direct2" input="ff[0].Q" output="ff[1].D">
<delay_constant max="${FF0_TO_FF1_DELAY}" in_port="ff[0].Q" out_port="ff[1].D"/>
</direct>
<direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]"/>
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]"/>
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]">
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="shift_reg.ff_out[0:0]"/>
</direct>
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]">
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="shift_reg.ff_out[1:1]"/>
</direct>
<complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
</interconnect>
</pb_type>
@ -642,52 +613,36 @@
I[0] should be connected to in[0]
-->
<direct name="direct_fle0" input="clb.I0[0:1]" output="fle[0:0].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle0i" input="clb.I0i[0:1]" output="fle[0:0].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle1" input="clb.I1[0:1]" output="fle[1:1].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle1i" input="clb.I1i[0:1]" output="fle[1:1].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle2" input="clb.I2[0:1]" output="fle[2:2].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle2i" input="clb.I2i[0:1]" output="fle[2:2].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle3" input="clb.I3[0:1]" output="fle[3:3].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle3i" input="clb.I3i[0:1]" output="fle[3:3].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle4" input="clb.I4[0:1]" output="fle[4:4].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle4i" input="clb.I4i[0:1]" output="fle[4:4].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle5" input="clb.I5[0:1]" output="fle[5:5].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle5i" input="clb.I5i[0:1]" output="fle[5:5].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle6" input="clb.I6[0:1]" output="fle[6:6].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle6i" input="clb.I6i[0:1]" output="fle[6:6].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle7" input="clb.I7[0:1]" output="fle[7:7].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle7i" input="clb.I7i[0:1]" output="fle[7:7].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<complete name="clks" input="clb.clk" output="fle[7:0].clk">
</complete>
@ -703,7 +658,7 @@
<!-- Shift register chain links -->
<direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
<delay_constant max="0" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
<!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
</direct>
<direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
@ -715,7 +670,7 @@
<!-- Scan chain links -->
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
<delay_constant max="0" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
</direct>
<direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
</direct>
@ -724,7 +679,7 @@
<!-- Carry chain links -->
<direct name="carry_chain_in" input="clb.cin" output="fle[0:0].cin">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
<delay_constant max="0" in_port="clb.cin" out_port="fle[0:0].cin"/>
</direct>
<direct name="carry_chain_out" input="fle[7:7].cout" output="clb.cout">
</direct>

45
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task_simulation.conf
View File

@ -8,26 +8,47 @@
[GENERAL]
run_engine=openfpga_shell
power_analysis = false
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=60
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif
bench0=${PATH:TASK_DIR}/BENCHMARK/and2/and2.v
bench1=${PATH:TASK_DIR}/BENCHMARK/and2_latch/and2_latch.v
bench2=${PATH:TASK_DIR}/BENCHMARK/bin2bcd/bin2bcd.v
bench3=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
bench4=${PATH:TASK_DIR}/BENCHMARK/routing_test/routing_test.v
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5=${PATH:TASK_DIR}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${PATH:TASK_DIR}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${PATH:TASK_DIR}/BENCHMARK/and2_or2/and2_or2.v
[SYNTHESIS_PARAM]
bench0_top = top
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v
bench0_top = and2
bench1_top = and2_latch
bench2_top = bin2bcd
bench3_top = counter
bench4_top = routing_test
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5_top = rs_decoder_top
bench6_top = top_module
bench7_top = and2_or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
vpr_fpga_verilog_formal_verification_top_netlist=
#end_flow_with_test=

27
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/design_variables.yml
View File

@ -1 +1,26 @@
DELAY_VALUE: 12
L1_SB_MUX_DELAY: 0.81e-9
L2_SB_MUX_DELAY: 0.81e-9
L4_SB_MUX_DELAY: 0.81e-9
CB_MUX_DELAY: 0.57e-9
L1_WIRE_R: 100
L1_WIRE_C: 1e-12
L2_WIRE_R: 100
L2_WIRE_C: 1e-12
L4_WIRE_R: 100
L4_WIRE_C: 1e-12
INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 0.32e-9
LUT_OUT1_TO_FF_D_DELAY: 0.16e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.65e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.48e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.47e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.37e-9
LUT3_DELAY: 0.86e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 0.65e-9
LUT4_DELAY: 1.20e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 0.66e-9
REGIN_TO_FF0_DELAY: 0.15e-9
FF0_TO_FF1_DELAY: 0.16e-9

14
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_fabric.openfpga
View File

@ -36,9 +36,19 @@ write_fabric_bitstream --format xml --file fabric_bitstream.xml
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --verbose
write_fabric_verilog \
--file ./SRC \
--explicit_port_mapping \
--include_timing \
--verbose
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
write_verilog_testbench \
--file ./SRC \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--print_top_testbench \
--print_preconfig_top_testbench \
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
--explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

45
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga
View File

@ -1,6 +1,12 @@
# Run VPR for the 'and' design
# This script is designed to generate Verilog testbenches
# with a fixed device layout
# It will only output netlists to be used by verification tools
# including
# - Verilog testbenches, used by ModelSim
# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
#
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --route_chan_width 200
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
@ -24,11 +30,7 @@ lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE}
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
@ -37,28 +39,29 @@ repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_fabric_bitstream
build_architecture_bitstream --verbose --write_file arch_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream
write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
write_fabric_bitstream --format xml --file fabric_bitstream.xml
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
write_verilog_testbench --file ./SRC \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--print_top_testbench \
--print_preconfig_top_testbench \
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
--explicit_port_mapping
# Exclude signal initialization since it does not help simulator converge
# due to the lack of reset pins for flip-flops
#--include_signal_init
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis

40
FPGA1212_SOFA_CHD_PNR/Makefile Normal file
View File

@ -0,0 +1,40 @@
##########################################################################################
##########################################################################################
SHELL=bash
PYTHON_EXEC=python3.8
RERUN = 0
TB = top
OPTIONS =
.SILENT:
.ONESHELL:
runOpenFPGA:
SECONDS=0
source config.sh
# ===================== Check Tools =====================
which python3.8 > /dev/null
if [ $$? -eq 1 ]; then
echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
fi
# =================== Clean Previous Run =================================
rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf)
# ===================== Generate Netlist =================================
(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
run-task $${TASK_DIR_NAME} --remove_run_dir all
run-task $${TASK_DIR_NAME} ${OPTIONS})
if [ $$? -eq 1 ]; then
echo "X X X X X X Failed to generate netlist X X X X X X"; exit;
fi
duration=$$SECONDS
date > runOpenFPGA
echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA
clean:
rm -rf runOpenFPGA

1
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/BENCHMARK Symbolic link
View File

@ -0,0 +1 @@
../../BENCHMARK

48
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/arch/efpga_12x12_sim_openfpga.xml Normal file
View File

@ -0,0 +1,48 @@
<!-- Simulation Setting for OpenFPGA framework
This file will use
- a fixed operating clock frequency
- a fixed programming clock frequency
Note: all the numbers are tuned to STA results from physical layouts
-->
<openfpga_simulation_setting>
<clock_setting>
<!-- Use 50MHz as the Caravel SoC can operate at 50MHz
As the FPGA core does not share the clock with Caravel SoC
the actual clock frequency could be higher
-->
<operating frequency="50e6" num_cycles="auto" slack="0.2"/>
<!-- Use 50MHz as the Caravel SoC can operate at 50MHz
As the FPGA core does not share the clock with Caravel SoC
the actual programming clock frequency could be higher
-->
<programming frequency="50e6"/>
</clock_setting>
<simulator_option>
<operating_condition temperature="25"/>
<output_log verbose="false" captab="false"/>
<accuracy type="abs" value="1e-13"/>
<runtime fast_simulation="true"/>
</simulator_option>
<monte_carlo num_simulation_points="2"/>
<measurement_setting>
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
</slew>
<delay>
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
</measurement_setting>
<stimulus>
<clock>
<rise slew_type="abs" slew_time="20e-12" />
<fall slew_type="abs" slew_time="20e-12" />
</clock>
<input>
<rise slew_type="abs" slew_time="25e-12" />
<fall slew_type="abs" slew_time="25e-12" />
</input>
</stimulus>
</openfpga_simulation_setting>

2
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/arch/openfpga_arch.xml
View File

@ -217,7 +217,7 @@
</direct_connection>
<tile_annotations>
<global_port name="clk" is_clock="true" default_val="0">
<tile name=="clb" port="clk" x="-1" y="-1"/>
<tile name="clb" port="clk" x="-1" y="-1"/>
</global_port>
</tile_annotations>
<pb_type_annotations>

190
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/arch/vpr_arch.xml
View File

@ -1,5 +1,5 @@
<!--
Low-cost homogeneous FPGA Architecture.
Low-cost homogeneous FPGA Architecture: SOFA HD
- Skywater 130 nm technology
- General purpose logic block:
@ -11,6 +11,8 @@
- 80% L = 4, fc_in = 0.15, Fc_out = 0.10
- 100 routing tracks per channel
- Timing is loaded through an external yml file, so that we can model multiple corners
Authors: Xifan Tang
-->
<architecture>
@ -186,21 +188,6 @@
</fixed_layout>
</layout>
<device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
lined up with Stratix IV.
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
by 2.5x when looking up in Jeff's tables.
The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
@ -214,41 +201,32 @@
<connection_block input_switch_name="ipin_cblock"/>
</device>
<switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!-- Give uniform delays for all the MUXes driving different length of wires
TODO: Can be more accurate once the report timing strategies are elaborated
-->
<switch type="mux" name="L1_mux" R="0" Cin="0" Cout="0" Tdel="${L1_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="0" Cin="0" Cout="0" Tdel="${L2_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="0" Cin="0" Cout="0" Tdel="${L4_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
<switch type="mux" name="ipin_cblock" R="0" Cout="0." Cin="0" Tdel="${CB_MUX_DELAY}" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist>
<segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!--- The wire delay is around 0.1ns in post PnR netlist.
Create a pair of RC value so that R * C = 0.1ns
This is o.k. because other RC values are all zero
-->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="${L1_WIRE_R}" Cmetal="${L1_WIRE_C}">
<mux name="L1_mux"/>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="${L2_WIRE_R}" Cmetal="${L2_WIRE_C}">
<mux name="L2_mux"/>
<sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1</cb>
</segment>
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="${L4_WIRE_R}" Cmetal="${L4_WIRE_C}">
<mux name="L4_mux"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
@ -277,18 +255,17 @@
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
<delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
<delay_constant max="${INPAD_DELAY}" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them.
The Embedded I/O timing is 0.11ns
FIXME: the timing may include the GPIO timing!!!
-->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1">
@ -296,7 +273,7 @@
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
<delay_constant max="${INPAD_DELAY}" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
@ -306,7 +283,7 @@
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
<delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
@ -386,9 +363,9 @@
<input name="DI" num_pins="1"/>
<output name="Q" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_setup value="66e-12" port="ff.DI" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.DI" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
@ -398,22 +375,22 @@
<direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
<delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
</mux>
<mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
<delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
<delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
<delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
</mux>
<mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
<delay_constant max="${LUT_OUT0_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux>
<mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
<delay_constant max="${LUT_OUT1_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux>
</interconnect>
</pb_type>
@ -443,18 +420,10 @@
<input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
-->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
235e-12
235e-12
235e-12
${LUT3_DELAY}
${LUT3_DELAY}
${LUT3_DELAY}
</delay_matrix>
</pb_type>
<!-- Define the flip-flop -->
@ -462,20 +431,22 @@
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
<!-- Consider the delay of the MUX between LUT3 and FF -->
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
</direct>
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
<!-- Combine the delay of LUT4/LUT3 output MUX and fabric output mux -->
<delay_constant max="${LUT3_OUT_TO_FLE_OUT_DELAY}" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux>
</interconnect>
</pb_type>
@ -505,20 +476,11 @@
<input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
397e-12
-->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12
261e-12
261e-12
261e-12
${LUT4_DELAY}
${LUT4_DELAY}
${LUT4_DELAY}
${LUT4_DELAY}
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
@ -526,20 +488,22 @@
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
<!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut4.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
<!-- Combine the delay of LUT4/LUT3 output MUX and fabric output mux -->
<delay_constant max="${LUT4_OUT_TO_FLE_OUT_DELAY}" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff.Q" out_port="ble4.out"/>
</mux>
</interconnect>
</pb_type>
@ -561,15 +525,27 @@
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D"/>
<direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D">
<!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${REGIN_TO_FF0_DELAY}" in_port="shift_reg.reg_in" out_port="ff[0].D"/>
</direct>
<direct name="direct2" input="ff[0].Q" output="ff[1].D">
<!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${FF0_TO_FF1_DELAY}" in_port="ff[0].Q" out_port="ff[1].D"/>
</direct>
<direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]"/>
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]"/>
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]">
<!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="shift_reg.ff_out[0:0]"/>
</direct>
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]">
<!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="shift_reg.ff_out[1:1]"/>
</direct>
<complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
</interconnect>
</pb_type>
@ -591,52 +567,36 @@
I[0] should be connected to in[0]
-->
<direct name="direct_fle0" input="clb.I0[0:2]" output="fle[0:0].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle1" input="clb.I1[0:2]" output="fle[1:1].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle2" input="clb.I2[0:2]" output="fle[2:2].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle3" input="clb.I3[0:2]" output="fle[3:3].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle4" input="clb.I4[0:2]" output="fle[4:4].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle5" input="clb.I5[0:2]" output="fle[5:5].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle6" input="clb.I6[0:2]" output="fle[6:6].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle7" input="clb.I7[0:2]" output="fle[7:7].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<complete name="clks" input="clb.clk" output="fle[7:0].clk">
</complete>
@ -650,7 +610,7 @@
<!-- Shift register chain links -->
<direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
<delay_constant max="0e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
<!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
</direct>
<direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
@ -662,7 +622,7 @@
<!-- Scan chain links -->
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
<delay_constant max="0e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
</direct>
<direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
</direct>

47
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/config/task_simulation.conf
View File

@ -8,26 +8,47 @@
[GENERAL]
run_engine=openfpga_shell
power_analysis = false
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:TASK_DIR}/arch/efpga_12x12_sim_openfpga.xml
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=40
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif
bench0=${PATH:TASK_DIR}/BENCHMARK/and2/and2.v
bench1=${PATH:TASK_DIR}/BENCHMARK/and2_latch/and2_latch.v
bench2=${PATH:TASK_DIR}/BENCHMARK/bin2bcd/bin2bcd.v
bench3=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
bench4=${PATH:TASK_DIR}/BENCHMARK/routing_test/routing_test.v
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5=${PATH:TASK_DIR}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${PATH:TASK_DIR}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${PATH:TASK_DIR}/BENCHMARK/and2_or2/and2_or2.v
[SYNTHESIS_PARAM]
bench0_top = top
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v
bench0_top = and2
bench1_top = and2_latch
bench2_top = bin2bcd
bench3_top = counter
bench4_top = routing_test
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5_top = rs_decoder_top
bench6_top = top_module
bench7_top = and2_or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
vpr_fpga_verilog_formal_verification_top_netlist=
#end_flow_with_test=

27
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/design_variables.yml
View File

@ -1 +1,26 @@
DELAY_VALUE: 12
L1_SB_MUX_DELAY: 1.61e-9
L2_SB_MUX_DELAY: 1.61e-9
L4_SB_MUX_DELAY: 1.61e-9
CB_MUX_DELAY: 1.38e-9
L1_WIRE_R: 100
L1_WIRE_C: 1e-12
L2_WIRE_R: 100
L2_WIRE_C: 1e-12
L4_WIRE_R: 100
L4_WIRE_C: 1e-12
INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT3_DELAY: 0.86e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
LUT4_DELAY: 1.14e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
REGIN_TO_FF0_DELAY: 0.58e-9
FF0_TO_FF1_DELAY: 0.56e-9

14
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_fabric.openfpga
View File

@ -36,9 +36,19 @@ write_fabric_bitstream --format xml --file fabric_bitstream.xml
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose
write_fabric_verilog \
--file ./SRC \
--explicit_port_mapping \
--include_timing \
--verbose
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
write_verilog_testbench \
--file ./SRC \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--print_top_testbench \
--print_preconfig_top_testbench \
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
--explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

45
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga
View File

@ -1,6 +1,12 @@
# Run VPR for the 'and' design
# This script is designed to generate Verilog testbenches
# with a fixed device layout
# It will only output netlists to be used by verification tools
# including
# - Verilog testbenches, used by ModelSim
# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
#
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --route_chan_width 200
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
@ -24,11 +30,7 @@ lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE}
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
@ -37,28 +39,29 @@ repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_fabric_bitstream
build_architecture_bitstream --verbose --write_file arch_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream
write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
write_fabric_bitstream --format xml --file fabric_bitstream.xml
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
write_verilog_testbench --file ./SRC \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--print_top_testbench \
--print_preconfig_top_testbench \
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
--explicit_port_mapping
# Exclude signal initialization since it does not help simulator converge
# due to the lack of reset pins for flip-flops
#--include_signal_init
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis

42
FPGA1212_SOFA_HD_PNR/Makefile Normal file
View File

@ -0,0 +1,42 @@
##########################################################################################
##########################################################################################
SHELL=bash
PYTHON_EXEC=python3.8
RERUN = 0
TB = top
OPTIONS =
TASK_FILENAME ?= task_simulation.conf
.SILENT:
.ONESHELL:
runOpenFPGA:
SECONDS=0
source config.sh
# ===================== Check Tools =====================
which python3.8 > /dev/null
if [ $$? -eq 1 ]; then
echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
fi
echo "Running ${TASK_FILENAME} task"
# =================== Clean Previous Run =================================
rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && ln -s ${TASK_FILENAME} task.conf)
# ===================== Generate Netlist =================================
(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
run-task $${TASK_DIR_NAME} --remove_run_dir all
run-task $${TASK_DIR_NAME} ${OPTIONS})
if [ $$? -eq 1 ]; then
echo "X X X X X X Failed to generate netlist X X X X X X"; exit;
fi
duration=$$SECONDS
date > runOpenFPGA
echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA
clean:
rm -rf runOpenFPGA

2
FPGA1212_SOFA_HD_PNR/config.sh
View File

@ -2,7 +2,7 @@
# = = = = = = = = = = = = = = Variables Sections = = = = = = = = = = = = = = =
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
export PROJ_NAME=FPGA1212_SOFA_HD_PNR # Project Name
export PROJ_NAME=FPGA1212_SOFA_HD # Project Name
export FPGA_SIZE_X=12 # Grid X Size
export FPGA_SIZE_Y=12 # Grid Y Size
# Design Style [hier/flat], mostly hier

60
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info
View File

@ -1,60 +0,0 @@
commit 520e54d7abecebf75310bb901ce702532148d686
Merge: 4a53640c 056b7c0c
Author: Laboratory for Nano Integrated Systems (LNIS) <40280375+LNIS-Projects@users.noreply.github.com>
Date: Fri Nov 6 13:25:29 2020 -0700
Merge pull request #118 from LNIS-Projects/dev
Remove the restrictions on requiring two outputs for configurable memory circuits
commit 056b7c0c7997d2d12473f2fc4b7915e25ff74820
Author: tangxifan <tangxifan@gmail.com>
Date: Fri Nov 6 12:22:22 2020 -0700
[Doc] Update documentation about CCFF circuit model examples
commit 70734abc35347dbc27113200908858c9a66e9945
Author: tangxifan <tangxifan@gmail.com>
Date: Fri Nov 6 11:20:13 2020 -0700
[Arch] Remove QN from stdcell arch
commit 1a79a556467ae8d9d4d791b94462e168e15635ca
Author: tangxifan <tangxifan@gmail.com>
Date: Fri Nov 6 11:19:19 2020 -0700
[HDL] Add DFF cell with reset but only 1 output
commit 0a273ffab65b1f503d6e63da59c93644375dc3b1
Author: tangxifan <tangxifan@gmail.com>
Date: Fri Nov 6 11:16:46 2020 -0700
[Tool] Bug fix in the tight requirements on CCFF circuit model
On branch master
Your branch is up to date with 'origin/master'.
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openfpga/openfpga
openfpga_flow/tasks/FPGA1212_FC_HD_SKY_task
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openfpga_flow/tasks/FPGA128128_FLAT_task
openfpga_flow/tasks/FPGA1616_FLAT_task
openfpga_flow/tasks/FPGA22_FLAT_task
openfpga_flow/tasks/FPGA22_FRAME_task
openfpga_flow/tasks/FPGA22_HIER_SKY_SC_MS_task
openfpga_flow/tasks/FPGA22_HIER_SKY_task
openfpga_flow/tasks/FPGA22_HIER_task
openfpga_flow/tasks/FPGA22_MB_task
openfpga_flow/tasks/FPGA22_MODULAR_task
openfpga_flow/tasks/FPGA22_SPY_task
openfpga_flow/tasks/FPGA3232_FLAT_task
openfpga_flow/tasks/FPGA44_FLAT_task
openfpga_flow/tasks/FPGA6464_FLAT_task
openfpga_flow/tasks/FPGA66_FLAT_task
openfpga_flow/tasks/FPGA88_FLAT_task
openfpga_flow/tasks/routing_test/
openfpga_flow/tasks/skywater_openfpga_task
vpr/vpr
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1
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/InstancesMap.txt
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@ -1 +0,0 @@
{"grid_clb": ["grid_clb_1__1_", "grid_clb_1__2_", "grid_clb_2__1_", "grid_clb_2__2_"], "grid_io_top": ["grid_io_top_1__3_", "grid_io_top_2__3_"], "grid_io_right": ["grid_io_right_3__1_", "grid_io_right_3__2_"], "grid_io_bottom": ["grid_io_bottom_1__0_", "grid_io_bottom_2__0_"], "grid_io_left": ["grid_io_left_0__1_", "grid_io_left_0__2_"], "sb_0__0_": ["sb_0__0_"], "sb_0__1_": ["sb_0__1_"], "sb_0__2_": ["sb_0__2_"], "sb_1__0_": ["sb_1__0_"], "sb_1__1_": ["sb_1__1_"], "sb_1__2_": ["sb_1__2_"], "sb_2__0_": ["sb_2__0_"], "sb_2__1_": ["sb_2__1_"], "sb_2__2_": ["sb_2__2_"], "cbx_1__0_": ["cbx_1__0_", "cbx_2__0_"], "cbx_1__1_": ["cbx_1__1_", "cbx_2__1_"], "cbx_1__2_": ["cbx_1__2_", "cbx_2__2_"], "cby_0__1_": ["cby_0__1_", "cby_0__2_"], "cby_1__1_": ["cby_1__1_", "cby_1__2_"], "cby_2__1_": ["cby_2__1_", "cby_2__2_"], "direct_interc": ["direct_interc_0_", "direct_interc_1_", "direct_interc_2_", "direct_interc_3_", "direct_interc_4_", "direct_interc_5_"]}

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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
`define INITIAL_SIMULATION 1
`define AUTOCHECKED_SIMULATION 1
`define ENABLE_FORMAL_VERIFICATION 1
`define FORMAL_SIMULATION 1

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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
`include "./SRC/fpga_defines.v"
//
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v"
//
`include "./SRC/sub_module/inv_buf_passgate.v"
`include "./SRC/sub_module/arch_encoder.v"
`include "./SRC/sub_module/local_encoder.v"
`include "./SRC/sub_module/muxes.v"
`include "./SRC/sub_module/luts.v"
`include "./SRC/sub_module/wires.v"
`include "./SRC/sub_module/memories.v"
//
`include "./SRC/lb/logical_tile_io_mode_physical__iopad.v"
`include "./SRC/lb/logical_tile_io_mode_io_.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle.v"
`include "./SRC/lb/logical_tile_clb_mode_clb_.v"
`include "./SRC/lb/grid_io_top_top.v"
`include "./SRC/lb/grid_io_right_right.v"
`include "./SRC/lb/grid_io_bottom_bottom.v"
`include "./SRC/lb/grid_io_left_left.v"
`include "./SRC/lb/grid_clb.v"
//
`include "./SRC/routing/sb_0__0_.v"
`include "./SRC/routing/sb_0__1_.v"
`include "./SRC/routing/sb_0__2_.v"
`include "./SRC/routing/sb_1__0_.v"
`include "./SRC/routing/sb_1__1_.v"
`include "./SRC/routing/sb_1__2_.v"
`include "./SRC/routing/sb_2__0_.v"
`include "./SRC/routing/sb_2__1_.v"
`include "./SRC/routing/sb_2__2_.v"
`include "./SRC/routing/cbx_1__0_.v"
`include "./SRC/routing/cbx_1__1_.v"
`include "./SRC/routing/cbx_1__2_.v"
`include "./SRC/routing/cby_0__1_.v"
`include "./SRC/routing/cby_1__1_.v"
`include "./SRC/routing/cby_2__1_.v"
//
`include "./SRC/fpga_top.v"

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FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v
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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
`define ENABLE_TIMING 1
`define ENABLE_SIGNAL_INITIALIZATION 1
`define ICARUS_SIMULATOR 1

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FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v
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module grid_clb
( prog_clk, Test_en, clk, top_width_0_height_0__pin_0_, top_width_0_height_0__pin_1_, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_3_, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_5_, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_7_, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_9_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_11_, top_width_0_height_0__pin_12_, top_width_0_height_0__pin_13_, top_width_0_height_0__pin_14_, top_width_0_height_0__pin_15_, top_width_0_height_0__pin_32_, top_width_0_height_0__pin_33_, right_width_0_height_0__pin_16_, right_width_0_height_0__pin_17_, right_width_0_height_0__pin_18_, right_width_0_height_0__pin_19_, right_width_0_height_0__pin_20_, right_width_0_height_0__pin_21_, right_width_0_height_0__pin_22_, right_width_0_height_0__pin_23_, right_width_0_height_0__pin_24_, right_width_0_height_0__pin_25_, right_width_0_height_0__pin_26_, right_width_0_height_0__pin_27_, right_width_0_height_0__pin_28_, right_width_0_height_0__pin_29_, right_width_0_height_0__pin_30_, right_width_0_height_0__pin_31_, left_width_0_height_0__pin_52_, ccff_head, top_width_0_height_0__pin_34_upper, top_width_0_height_0__pin_34_lower, top_width_0_height_0__pin_35_upper, top_width_0_height_0__pin_35_lower, top_width_0_height_0__pin_36_upper, top_width_0_height_0__pin_36_lower, top_width_0_height_0__pin_37_upper, top_width_0_height_0__pin_37_lower, top_width_0_height_0__pin_38_upper, top_width_0_height_0__pin_38_lower, top_width_0_height_0__pin_39_upper, top_width_0_height_0__pin_39_lower, top_width_0_height_0__pin_40_upper, top_width_0_height_0__pin_40_lower, top_width_0_height_0__pin_41_upper, top_width_0_height_0__pin_41_lower, right_width_0_height_0__pin_42_upper, right_width_0_height_0__pin_42_lower, right_width_0_height_0__pin_43_upper, right_width_0_height_0__pin_43_lower, right_width_0_height_0__pin_44_upper, right_width_0_height_0__pin_44_lower, right_width_0_height_0__pin_45_upper, right_width_0_height_0__pin_45_lower, right_width_0_height_0__pin_46_upper, right_width_0_height_0__pin_46_lower, right_width_0_height_0__pin_47_upper, right_width_0_height_0__pin_47_lower, right_width_0_height_0__pin_48_upper, right_width_0_height_0__pin_48_lower, right_width_0_height_0__pin_49_upper, right_width_0_height_0__pin_49_lower, bottom_width_0_height_0__pin_50_, bottom_width_0_height_0__pin_51_, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:0] Test_en;
input [0:0] clk;
input [0:0] top_width_0_height_0__pin_0_;
input [0:0] top_width_0_height_0__pin_1_;
input [0:0] top_width_0_height_0__pin_2_;
input [0:0] top_width_0_height_0__pin_3_;
input [0:0] top_width_0_height_0__pin_4_;
input [0:0] top_width_0_height_0__pin_5_;
input [0:0] top_width_0_height_0__pin_6_;
input [0:0] top_width_0_height_0__pin_7_;
input [0:0] top_width_0_height_0__pin_8_;
input [0:0] top_width_0_height_0__pin_9_;
input [0:0] top_width_0_height_0__pin_10_;
input [0:0] top_width_0_height_0__pin_11_;
input [0:0] top_width_0_height_0__pin_12_;
input [0:0] top_width_0_height_0__pin_13_;
input [0:0] top_width_0_height_0__pin_14_;
input [0:0] top_width_0_height_0__pin_15_;
input [0:0] top_width_0_height_0__pin_32_;
input [0:0] top_width_0_height_0__pin_33_;
input [0:0] right_width_0_height_0__pin_16_;
input [0:0] right_width_0_height_0__pin_17_;
input [0:0] right_width_0_height_0__pin_18_;
input [0:0] right_width_0_height_0__pin_19_;
input [0:0] right_width_0_height_0__pin_20_;
input [0:0] right_width_0_height_0__pin_21_;
input [0:0] right_width_0_height_0__pin_22_;
input [0:0] right_width_0_height_0__pin_23_;
input [0:0] right_width_0_height_0__pin_24_;
input [0:0] right_width_0_height_0__pin_25_;
input [0:0] right_width_0_height_0__pin_26_;
input [0:0] right_width_0_height_0__pin_27_;
input [0:0] right_width_0_height_0__pin_28_;
input [0:0] right_width_0_height_0__pin_29_;
input [0:0] right_width_0_height_0__pin_30_;
input [0:0] right_width_0_height_0__pin_31_;
input [0:0] left_width_0_height_0__pin_52_;
input [0:0] ccff_head;
output [0:0] top_width_0_height_0__pin_34_upper;
output [0:0] top_width_0_height_0__pin_34_lower;
output [0:0] top_width_0_height_0__pin_35_upper;
output [0:0] top_width_0_height_0__pin_35_lower;
output [0:0] top_width_0_height_0__pin_36_upper;
output [0:0] top_width_0_height_0__pin_36_lower;
output [0:0] top_width_0_height_0__pin_37_upper;
output [0:0] top_width_0_height_0__pin_37_lower;
output [0:0] top_width_0_height_0__pin_38_upper;
output [0:0] top_width_0_height_0__pin_38_lower;
output [0:0] top_width_0_height_0__pin_39_upper;
output [0:0] top_width_0_height_0__pin_39_lower;
output [0:0] top_width_0_height_0__pin_40_upper;
output [0:0] top_width_0_height_0__pin_40_lower;
output [0:0] top_width_0_height_0__pin_41_upper;
output [0:0] top_width_0_height_0__pin_41_lower;
output [0:0] right_width_0_height_0__pin_42_upper;
output [0:0] right_width_0_height_0__pin_42_lower;
output [0:0] right_width_0_height_0__pin_43_upper;
output [0:0] right_width_0_height_0__pin_43_lower;
output [0:0] right_width_0_height_0__pin_44_upper;
output [0:0] right_width_0_height_0__pin_44_lower;
output [0:0] right_width_0_height_0__pin_45_upper;
output [0:0] right_width_0_height_0__pin_45_lower;
output [0:0] right_width_0_height_0__pin_46_upper;
output [0:0] right_width_0_height_0__pin_46_lower;
output [0:0] right_width_0_height_0__pin_47_upper;
output [0:0] right_width_0_height_0__pin_47_lower;
output [0:0] right_width_0_height_0__pin_48_upper;
output [0:0] right_width_0_height_0__pin_48_lower;
output [0:0] right_width_0_height_0__pin_49_upper;
output [0:0] right_width_0_height_0__pin_49_lower;
output [0:0] bottom_width_0_height_0__pin_50_;
output [0:0] bottom_width_0_height_0__pin_51_;
output [0:0] ccff_tail;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
assign top_width_0_height_0__pin_34_lower[0] = top_width_0_height_0__pin_34_upper[0];
assign top_width_0_height_0__pin_35_lower[0] = top_width_0_height_0__pin_35_upper[0];
assign top_width_0_height_0__pin_36_lower[0] = top_width_0_height_0__pin_36_upper[0];
assign top_width_0_height_0__pin_37_lower[0] = top_width_0_height_0__pin_37_upper[0];
assign top_width_0_height_0__pin_38_lower[0] = top_width_0_height_0__pin_38_upper[0];
assign top_width_0_height_0__pin_39_lower[0] = top_width_0_height_0__pin_39_upper[0];
assign top_width_0_height_0__pin_40_lower[0] = top_width_0_height_0__pin_40_upper[0];
assign top_width_0_height_0__pin_41_lower[0] = top_width_0_height_0__pin_41_upper[0];
assign right_width_0_height_0__pin_42_lower[0] = right_width_0_height_0__pin_42_upper[0];
assign right_width_0_height_0__pin_43_lower[0] = right_width_0_height_0__pin_43_upper[0];
assign right_width_0_height_0__pin_44_lower[0] = right_width_0_height_0__pin_44_upper[0];
assign right_width_0_height_0__pin_45_lower[0] = right_width_0_height_0__pin_45_upper[0];
assign right_width_0_height_0__pin_46_lower[0] = right_width_0_height_0__pin_46_upper[0];
assign right_width_0_height_0__pin_47_lower[0] = right_width_0_height_0__pin_47_upper[0];
assign right_width_0_height_0__pin_48_lower[0] = right_width_0_height_0__pin_48_upper[0];
assign right_width_0_height_0__pin_49_lower[0] = right_width_0_height_0__pin_49_upper[0];
assign SC_IN_TOP = SC_IN_BOT;
assign SC_OUT_TOP = SC_OUT_BOT;
logical_tile_clb_mode_clb_
logical_tile_clb_mode_clb__0
(
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
.clb_I0({ top_width_0_height_0__pin_0_[0], top_width_0_height_0__pin_1_[0], top_width_0_height_0__pin_2_[0] }),
.clb_I0i(top_width_0_height_0__pin_3_[0]),
.clb_I1({ top_width_0_height_0__pin_4_[0], top_width_0_height_0__pin_5_[0], top_width_0_height_0__pin_6_[0] }),
.clb_I1i(top_width_0_height_0__pin_7_[0]),
.clb_I2({ top_width_0_height_0__pin_8_[0], top_width_0_height_0__pin_9_[0], top_width_0_height_0__pin_10_[0] }),
.clb_I2i(top_width_0_height_0__pin_11_[0]),
.clb_I3({ top_width_0_height_0__pin_12_[0], top_width_0_height_0__pin_13_[0], top_width_0_height_0__pin_14_[0] }),
.clb_I3i(top_width_0_height_0__pin_15_[0]),
.clb_I4({ right_width_0_height_0__pin_16_[0], right_width_0_height_0__pin_17_[0], right_width_0_height_0__pin_18_[0] }),
.clb_I4i(right_width_0_height_0__pin_19_[0]),
.clb_I5({ right_width_0_height_0__pin_20_[0], right_width_0_height_0__pin_21_[0], right_width_0_height_0__pin_22_[0] }),
.clb_I5i(right_width_0_height_0__pin_23_[0]),
.clb_I6({ right_width_0_height_0__pin_24_[0], right_width_0_height_0__pin_25_[0], right_width_0_height_0__pin_26_[0] }),
.clb_I6i(right_width_0_height_0__pin_27_[0]),
.clb_I7({ right_width_0_height_0__pin_28_[0], right_width_0_height_0__pin_29_[0], right_width_0_height_0__pin_30_[0] }),
.clb_I7i(right_width_0_height_0__pin_31_[0]),
.clb_regin(top_width_0_height_0__pin_32_[0]),
.clb_sc_in(SC_IN_TOP),
.clb_clk(left_width_0_height_0__pin_52_[0]),
.ccff_head(ccff_head[0]),
.clb_O({ top_width_0_height_0__pin_34_upper[0], top_width_0_height_0__pin_35_upper[0], top_width_0_height_0__pin_36_upper[0], top_width_0_height_0__pin_37_upper[0], top_width_0_height_0__pin_38_upper[0], top_width_0_height_0__pin_39_upper[0], top_width_0_height_0__pin_40_upper[0], top_width_0_height_0__pin_41_upper[0], right_width_0_height_0__pin_42_upper[0], right_width_0_height_0__pin_43_upper[0], right_width_0_height_0__pin_44_upper[0], right_width_0_height_0__pin_45_upper[0], right_width_0_height_0__pin_46_upper[0], right_width_0_height_0__pin_47_upper[0], right_width_0_height_0__pin_48_upper[0], right_width_0_height_0__pin_49_upper[0] }),
.clb_regout(bottom_width_0_height_0__pin_50_[0]),
.clb_sc_out(SC_OUT_BOT),
.ccff_tail(ccff_tail[0])
);
endmodule

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FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v
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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module logical_tile_clb_mode_clb_(prog_clk,
Test_en,
clk,
clb_I0,
clb_I0i,
clb_I1,
clb_I1i,
clb_I2,
clb_I2i,
clb_I3,
clb_I3i,
clb_I4,
clb_I4i,
clb_I5,
clb_I5i,
clb_I6,
clb_I6i,
clb_I7,
clb_I7i,
clb_regin,
clb_sc_in,
clb_clk,
ccff_head,
clb_O,
clb_regout,
clb_sc_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:0] Test_en;
//
input [0:0] clk;
//
input [0:2] clb_I0;
//
input [0:0] clb_I0i;
//
input [0:2] clb_I1;
//
input [0:0] clb_I1i;
//
input [0:2] clb_I2;
//
input [0:0] clb_I2i;
//
input [0:2] clb_I3;
//
input [0:0] clb_I3i;
//
input [0:2] clb_I4;
//
input [0:0] clb_I4i;
//
input [0:2] clb_I5;
//
input [0:0] clb_I5i;
//
input [0:2] clb_I6;
//
input [0:0] clb_I6i;
//
input [0:2] clb_I7;
//
input [0:0] clb_I7i;
//
input [0:0] clb_regin;
//
input [0:0] clb_sc_in;
//
input [0:0] clb_clk;
//
input [0:0] ccff_head;
//
output [0:15] clb_O;
//
output [0:0] clb_regout;
//
output [0:0] clb_sc_out;
//
output [0:0] ccff_tail;
//
wire [0:2] clb_I0;
wire [0:0] clb_I0i;
wire [0:2] clb_I1;
wire [0:0] clb_I1i;
wire [0:2] clb_I2;
wire [0:0] clb_I2i;
wire [0:2] clb_I3;
wire [0:0] clb_I3i;
wire [0:2] clb_I4;
wire [0:0] clb_I4i;
wire [0:2] clb_I5;
wire [0:0] clb_I5i;
wire [0:2] clb_I6;
wire [0:0] clb_I6i;
wire [0:2] clb_I7;
wire [0:0] clb_I7i;
wire [0:0] clb_regin;
wire [0:0] clb_sc_in;
wire [0:0] clb_clk;
wire [0:15] clb_O;
wire [0:0] clb_regout;
wire [0:0] clb_sc_out;
//
//
//
wire [0:0] direct_interc_18_out;
wire [0:0] direct_interc_19_out;
wire [0:0] direct_interc_20_out;
wire [0:0] direct_interc_21_out;
wire [0:0] direct_interc_22_out;
wire [0:0] direct_interc_23_out;
wire [0:0] direct_interc_24_out;
wire [0:0] direct_interc_25_out;
wire [0:0] direct_interc_26_out;
wire [0:0] direct_interc_27_out;
wire [0:0] direct_interc_28_out;
wire [0:0] direct_interc_29_out;
wire [0:0] direct_interc_30_out;
wire [0:0] direct_interc_31_out;
wire [0:0] direct_interc_32_out;
wire [0:0] direct_interc_33_out;
wire [0:0] direct_interc_34_out;
wire [0:0] direct_interc_35_out;
wire [0:0] direct_interc_36_out;
wire [0:0] direct_interc_37_out;
wire [0:0] direct_interc_38_out;
wire [0:0] direct_interc_39_out;
wire [0:0] direct_interc_40_out;
wire [0:0] direct_interc_41_out;
wire [0:0] direct_interc_42_out;
wire [0:0] direct_interc_43_out;
wire [0:0] direct_interc_44_out;
wire [0:0] direct_interc_45_out;
wire [0:0] direct_interc_46_out;
wire [0:0] direct_interc_47_out;
wire [0:0] direct_interc_48_out;
wire [0:0] direct_interc_49_out;
wire [0:0] direct_interc_50_out;
wire [0:0] direct_interc_51_out;
wire [0:0] direct_interc_52_out;
wire [0:0] direct_interc_53_out;
wire [0:0] direct_interc_54_out;
wire [0:0] direct_interc_55_out;
wire [0:0] direct_interc_56_out;
wire [0:0] direct_interc_57_out;
wire [0:0] direct_interc_58_out;
wire [0:0] direct_interc_59_out;
wire [0:0] direct_interc_60_out;
wire [0:0] direct_interc_61_out;
wire [0:0] direct_interc_62_out;
wire [0:0] direct_interc_63_out;
wire [0:0] direct_interc_64_out;
wire [0:0] direct_interc_65_out;
wire [0:0] direct_interc_66_out;
wire [0:0] direct_interc_67_out;
wire [0:0] direct_interc_68_out;
wire [0:0] direct_interc_69_out;
wire [0:0] direct_interc_70_out;
wire [0:0] direct_interc_71_out;
wire [0:0] direct_interc_72_out;
wire [0:0] direct_interc_73_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_0_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_1_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_2_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_4_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_5_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_6_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out;
wire [0:1] logical_tile_clb_mode_default__fle_7_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_7_fle_regout;
wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
//
//
//
//
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
.fle_in({direct_interc_18_out[0], direct_interc_19_out[0], direct_interc_20_out[0], direct_interc_21_out[0]}),
.fle_regin(direct_interc_22_out[0]),
.fle_sc_in(direct_interc_23_out[0]),
.fle_clk(direct_interc_24_out[0]),
.ccff_head(ccff_head[0]),
.fle_out(logical_tile_clb_mode_default__fle_0_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_0_fle_regout[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
.fle_in({direct_interc_25_out[0], direct_interc_26_out[0], direct_interc_27_out[0], direct_interc_28_out[0]}),
.fle_regin(direct_interc_29_out[0]),
.fle_sc_in(direct_interc_30_out[0]),
.fle_clk(direct_interc_31_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_1_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_1_fle_regout[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
.fle_in({direct_interc_32_out[0], direct_interc_33_out[0], direct_interc_34_out[0], direct_interc_35_out[0]}),
.fle_regin(direct_interc_36_out[0]),
.fle_sc_in(direct_interc_37_out[0]),
.fle_clk(direct_interc_38_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_2_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_2_fle_regout[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
.fle_in({direct_interc_39_out[0], direct_interc_40_out[0], direct_interc_41_out[0], direct_interc_42_out[0]}),
.fle_regin(direct_interc_43_out[0]),
.fle_sc_in(direct_interc_44_out[0]),
.fle_clk(direct_interc_45_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_3_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_3_fle_regout[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
.fle_in({direct_interc_46_out[0], direct_interc_47_out[0], direct_interc_48_out[0], direct_interc_49_out[0]}),
.fle_regin(direct_interc_50_out[0]),
.fle_sc_in(direct_interc_51_out[0]),
.fle_clk(direct_interc_52_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_4_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_4_fle_regout[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
.fle_in({direct_interc_53_out[0], direct_interc_54_out[0], direct_interc_55_out[0], direct_interc_56_out[0]}),
.fle_regin(direct_interc_57_out[0]),
.fle_sc_in(direct_interc_58_out[0]),
.fle_clk(direct_interc_59_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_5_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_5_fle_regout[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
.fle_in({direct_interc_60_out[0], direct_interc_61_out[0], direct_interc_62_out[0], direct_interc_63_out[0]}),
.fle_regin(direct_interc_64_out[0]),
.fle_sc_in(direct_interc_65_out[0]),
.fle_clk(direct_interc_66_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_6_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_6_fle_regout[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
.fle_in({direct_interc_67_out[0], direct_interc_68_out[0], direct_interc_69_out[0], direct_interc_70_out[0]}),
.fle_regin(direct_interc_71_out[0]),
.fle_sc_in(direct_interc_72_out[0]),
.fle_clk(direct_interc_73_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_7_fle_out[0:1]),
.fle_regout(logical_tile_clb_mode_default__fle_7_fle_regout[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]),
.ccff_tail(ccff_tail[0]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_0_fle_out[1]),
.out(clb_O[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_0_fle_out[0]),
.out(clb_O[1]));
direct_interc direct_interc_2_ (
.in(logical_tile_clb_mode_default__fle_1_fle_out[1]),
.out(clb_O[2]));
direct_interc direct_interc_3_ (
.in(logical_tile_clb_mode_default__fle_1_fle_out[0]),
.out(clb_O[3]));
direct_interc direct_interc_4_ (
.in(logical_tile_clb_mode_default__fle_2_fle_out[1]),
.out(clb_O[4]));
direct_interc direct_interc_5_ (
.in(logical_tile_clb_mode_default__fle_2_fle_out[0]),
.out(clb_O[5]));
direct_interc direct_interc_6_ (
.in(logical_tile_clb_mode_default__fle_3_fle_out[1]),
.out(clb_O[6]));
direct_interc direct_interc_7_ (
.in(logical_tile_clb_mode_default__fle_3_fle_out[0]),
.out(clb_O[7]));
direct_interc direct_interc_8_ (
.in(logical_tile_clb_mode_default__fle_4_fle_out[1]),
.out(clb_O[8]));
direct_interc direct_interc_9_ (
.in(logical_tile_clb_mode_default__fle_4_fle_out[0]),
.out(clb_O[9]));
direct_interc direct_interc_10_ (
.in(logical_tile_clb_mode_default__fle_5_fle_out[1]),
.out(clb_O[10]));
direct_interc direct_interc_11_ (
.in(logical_tile_clb_mode_default__fle_5_fle_out[0]),
.out(clb_O[11]));
direct_interc direct_interc_12_ (
.in(logical_tile_clb_mode_default__fle_6_fle_out[1]),
.out(clb_O[12]));
direct_interc direct_interc_13_ (
.in(logical_tile_clb_mode_default__fle_6_fle_out[0]),
.out(clb_O[13]));
direct_interc direct_interc_14_ (
.in(logical_tile_clb_mode_default__fle_7_fle_out[1]),
.out(clb_O[14]));
direct_interc direct_interc_15_ (
.in(logical_tile_clb_mode_default__fle_7_fle_out[0]),
.out(clb_O[15]));
direct_interc direct_interc_16_ (
.in(logical_tile_clb_mode_default__fle_7_fle_regout[0]),
.out(clb_regout[0]));
direct_interc direct_interc_17_ (
.in(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]),
.out(clb_sc_out[0]));
direct_interc direct_interc_18_ (
.in(clb_I0[0]),
.out(direct_interc_18_out[0]));
direct_interc direct_interc_19_ (
.in(clb_I0[1]),
.out(direct_interc_19_out[0]));
direct_interc direct_interc_20_ (
.in(clb_I0[2]),
.out(direct_interc_20_out[0]));
direct_interc direct_interc_21_ (
.in(clb_I0i[0]),
.out(direct_interc_21_out[0]));
direct_interc direct_interc_22_ (
.in(clb_regin[0]),
.out(direct_interc_22_out[0]));
direct_interc direct_interc_23_ (
.in(clb_sc_in[0]),
.out(direct_interc_23_out[0]));
direct_interc direct_interc_24_ (
.in(clb_clk[0]),
.out(direct_interc_24_out[0]));
direct_interc direct_interc_25_ (
.in(clb_I1[0]),
.out(direct_interc_25_out[0]));
direct_interc direct_interc_26_ (
.in(clb_I1[1]),
.out(direct_interc_26_out[0]));
direct_interc direct_interc_27_ (
.in(clb_I1[2]),
.out(direct_interc_27_out[0]));
direct_interc direct_interc_28_ (
.in(clb_I1i[0]),
.out(direct_interc_28_out[0]));
direct_interc direct_interc_29_ (
.in(logical_tile_clb_mode_default__fle_0_fle_regout[0]),
.out(direct_interc_29_out[0]));
direct_interc direct_interc_30_ (
.in(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]),
.out(direct_interc_30_out[0]));
direct_interc direct_interc_31_ (
.in(clb_clk[0]),
.out(direct_interc_31_out[0]));
direct_interc direct_interc_32_ (
.in(clb_I2[0]),
.out(direct_interc_32_out[0]));
direct_interc direct_interc_33_ (
.in(clb_I2[1]),
.out(direct_interc_33_out[0]));
direct_interc direct_interc_34_ (
.in(clb_I2[2]),
.out(direct_interc_34_out[0]));
direct_interc direct_interc_35_ (
.in(clb_I2i[0]),
.out(direct_interc_35_out[0]));
direct_interc direct_interc_36_ (
.in(logical_tile_clb_mode_default__fle_1_fle_regout[0]),
.out(direct_interc_36_out[0]));
direct_interc direct_interc_37_ (
.in(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]),
.out(direct_interc_37_out[0]));
direct_interc direct_interc_38_ (
.in(clb_clk[0]),
.out(direct_interc_38_out[0]));
direct_interc direct_interc_39_ (
.in(clb_I3[0]),
.out(direct_interc_39_out[0]));
direct_interc direct_interc_40_ (
.in(clb_I3[1]),
.out(direct_interc_40_out[0]));
direct_interc direct_interc_41_ (
.in(clb_I3[2]),
.out(direct_interc_41_out[0]));
direct_interc direct_interc_42_ (
.in(clb_I3i[0]),
.out(direct_interc_42_out[0]));
direct_interc direct_interc_43_ (
.in(logical_tile_clb_mode_default__fle_2_fle_regout[0]),
.out(direct_interc_43_out[0]));
direct_interc direct_interc_44_ (
.in(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]),
.out(direct_interc_44_out[0]));
direct_interc direct_interc_45_ (
.in(clb_clk[0]),
.out(direct_interc_45_out[0]));
direct_interc direct_interc_46_ (
.in(clb_I4[0]),
.out(direct_interc_46_out[0]));
direct_interc direct_interc_47_ (
.in(clb_I4[1]),
.out(direct_interc_47_out[0]));
direct_interc direct_interc_48_ (
.in(clb_I4[2]),
.out(direct_interc_48_out[0]));
direct_interc direct_interc_49_ (
.in(clb_I4i[0]),
.out(direct_interc_49_out[0]));
direct_interc direct_interc_50_ (
.in(logical_tile_clb_mode_default__fle_3_fle_regout[0]),
.out(direct_interc_50_out[0]));
direct_interc direct_interc_51_ (
.in(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]),
.out(direct_interc_51_out[0]));
direct_interc direct_interc_52_ (
.in(clb_clk[0]),
.out(direct_interc_52_out[0]));
direct_interc direct_interc_53_ (
.in(clb_I5[0]),
.out(direct_interc_53_out[0]));
direct_interc direct_interc_54_ (
.in(clb_I5[1]),
.out(direct_interc_54_out[0]));
direct_interc direct_interc_55_ (
.in(clb_I5[2]),
.out(direct_interc_55_out[0]));
direct_interc direct_interc_56_ (
.in(clb_I5i[0]),
.out(direct_interc_56_out[0]));
direct_interc direct_interc_57_ (
.in(logical_tile_clb_mode_default__fle_4_fle_regout[0]),
.out(direct_interc_57_out[0]));
direct_interc direct_interc_58_ (
.in(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]),
.out(direct_interc_58_out[0]));
direct_interc direct_interc_59_ (
.in(clb_clk[0]),
.out(direct_interc_59_out[0]));
direct_interc direct_interc_60_ (
.in(clb_I6[0]),
.out(direct_interc_60_out[0]));
direct_interc direct_interc_61_ (
.in(clb_I6[1]),
.out(direct_interc_61_out[0]));
direct_interc direct_interc_62_ (
.in(clb_I6[2]),
.out(direct_interc_62_out[0]));
direct_interc direct_interc_63_ (
.in(clb_I6i[0]),
.out(direct_interc_63_out[0]));
direct_interc direct_interc_64_ (
.in(logical_tile_clb_mode_default__fle_5_fle_regout[0]),
.out(direct_interc_64_out[0]));
direct_interc direct_interc_65_ (
.in(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]),
.out(direct_interc_65_out[0]));
direct_interc direct_interc_66_ (
.in(clb_clk[0]),
.out(direct_interc_66_out[0]));
direct_interc direct_interc_67_ (
.in(clb_I7[0]),
.out(direct_interc_67_out[0]));
direct_interc direct_interc_68_ (
.in(clb_I7[1]),
.out(direct_interc_68_out[0]));
direct_interc direct_interc_69_ (
.in(clb_I7[2]),
.out(direct_interc_69_out[0]));
direct_interc direct_interc_70_ (
.in(clb_I7i[0]),
.out(direct_interc_70_out[0]));
direct_interc direct_interc_71_ (
.in(logical_tile_clb_mode_default__fle_6_fle_regout[0]),
.out(direct_interc_71_out[0]));
direct_interc direct_interc_72_ (
.in(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]),
.out(direct_interc_72_out[0]));
direct_interc direct_interc_73_ (
.in(clb_clk[0]),
.out(direct_interc_73_out[0]));
endmodule
//
//

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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module logical_tile_clb_mode_default__fle(prog_clk,
Test_en,
clk,
fle_in,
fle_regin,
fle_sc_in,
fle_clk,
ccff_head,
fle_out,
fle_regout,
fle_sc_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:0] Test_en;
//
input [0:0] clk;
//
input [0:3] fle_in;
//
input [0:0] fle_regin;
//
input [0:0] fle_sc_in;
//
input [0:0] fle_clk;
//
input [0:0] ccff_head;
//
output [0:1] fle_out;
//
output [0:0] fle_regout;
//
output [0:0] fle_sc_out;
//
output [0:0] ccff_tail;
//
wire [0:3] fle_in;
wire [0:0] fle_regin;
wire [0:0] fle_sc_in;
wire [0:0] fle_clk;
wire [0:1] fle_out;
wire [0:0] fle_regout;
wire [0:0] fle_sc_out;
//
//
//
wire [0:0] direct_interc_10_out;
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
wire [0:0] direct_interc_6_out;
wire [0:0] direct_interc_7_out;
wire [0:0] direct_interc_8_out;
wire [0:0] direct_interc_9_out;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out;
//
//
//
//
logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
.fabric_in({direct_interc_4_out[0], direct_interc_5_out[0], direct_interc_6_out[0], direct_interc_7_out[0]}),
.fabric_regin(direct_interc_8_out[0]),
.fabric_sc_in(direct_interc_9_out[0]),
.fabric_clk(direct_interc_10_out[0]),
.ccff_head(ccff_head[0]),
.fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0:1]),
.fabric_regout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout[0]),
.fabric_sc_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]),
.ccff_tail(ccff_tail[0]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0]),
.out(fle_out[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[1]),
.out(fle_out[1]));
direct_interc direct_interc_2_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout[0]),
.out(fle_regout[0]));
direct_interc direct_interc_3_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]),
.out(fle_sc_out[0]));
direct_interc direct_interc_4_ (
.in(fle_in[0]),
.out(direct_interc_4_out[0]));
direct_interc direct_interc_5_ (
.in(fle_in[1]),
.out(direct_interc_5_out[0]));
direct_interc direct_interc_6_ (
.in(fle_in[2]),
.out(direct_interc_6_out[0]));
direct_interc direct_interc_7_ (
.in(fle_in[3]),
.out(direct_interc_7_out[0]));
direct_interc direct_interc_8_ (
.in(fle_regin[0]),
.out(direct_interc_8_out[0]));
direct_interc direct_interc_9_ (
.in(fle_sc_in[0]),
.out(direct_interc_9_out[0]));
direct_interc direct_interc_10_ (
.in(fle_clk[0]),
.out(direct_interc_10_out[0]));
endmodule
//
//

200
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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module logical_tile_clb_mode_default__fle_mode_physical__fabric(prog_clk,
Test_en,
clk,
fabric_in,
fabric_regin,
fabric_sc_in,
fabric_clk,
ccff_head,
fabric_out,
fabric_regout,
fabric_sc_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:0] Test_en;
//
input [0:0] clk;
//
input [0:3] fabric_in;
//
input [0:0] fabric_regin;
//
input [0:0] fabric_sc_in;
//
input [0:0] fabric_clk;
//
input [0:0] ccff_head;
//
output [0:1] fabric_out;
//
output [0:0] fabric_regout;
//
output [0:0] fabric_sc_out;
//
output [0:0] ccff_tail;
//
wire [0:3] fabric_in;
wire [0:0] fabric_regin;
wire [0:0] fabric_sc_in;
wire [0:0] fabric_clk;
wire [0:1] fabric_out;
wire [0:0] fabric_regout;
wire [0:0] fabric_sc_out;
//
//
//
wire [0:0] direct_interc_10_out;
wire [0:0] direct_interc_2_out;
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
wire [0:0] direct_interc_6_out;
wire [0:0] direct_interc_7_out;
wire [0:0] direct_interc_8_out;
wire [0:0] direct_interc_9_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out;
wire [0:1] mux_fabric_out_0_undriven_sram_inv;
wire [0:1] mux_fabric_out_1_undriven_sram_inv;
wire [0:1] mux_ff_0_D_0_undriven_sram_inv;
wire [0:1] mux_tree_size2_0_sram;
wire [0:1] mux_tree_size2_1_sram;
wire [0:0] mux_tree_size2_2_out;
wire [0:1] mux_tree_size2_2_sram;
wire [0:0] mux_tree_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_size2_mem_1_ccff_tail;
//
//
//
//
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
.prog_clk(prog_clk[0]),
.frac_logic_in({direct_interc_2_out[0], direct_interc_3_out[0], direct_interc_4_out[0], direct_interc_5_out[0]}),
.ccff_head(ccff_head[0]),
.frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0:1]),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]));
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
.Test_en(Test_en[0]),
.clk(clk[0]),
.ff_D(mux_tree_size2_2_out[0]),
.ff_DI(direct_interc_6_out[0]),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
.ff_clk(direct_interc_7_out[0]));
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
.Test_en(Test_en[0]),
.clk(clk[0]),
.ff_D(direct_interc_8_out[0]),
.ff_DI(direct_interc_9_out[0]),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
.ff_clk(direct_interc_10_out[0]));
mux_tree_size2 mux_fabric_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}),
.sram(mux_tree_size2_0_sram[0:1]),
.sram_inv(mux_fabric_out_0_undriven_sram_inv[0:1]),
.out(fabric_out[0]));
mux_tree_size2 mux_fabric_out_1 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}),
.sram(mux_tree_size2_1_sram[0:1]),
.sram_inv(mux_fabric_out_1_undriven_sram_inv[0:1]),
.out(fabric_out[1]));
mux_tree_size2 mux_ff_0_D_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_regin[0]}),
.sram(mux_tree_size2_2_sram[0:1]),
.sram_inv(mux_ff_0_D_0_undriven_sram_inv[0:1]),
.out(mux_tree_size2_2_out[0]));
mux_tree_size2_mem mem_fabric_out_0 (
.prog_clk(prog_clk[0]),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]),
.ccff_tail(mux_tree_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_size2_0_sram[0:1]));
mux_tree_size2_mem mem_fabric_out_1 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_size2_1_sram[0:1]));
mux_tree_size2_mem mem_ff_0_D_0 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_size2_mem_1_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_size2_2_sram[0:1]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
.out(fabric_regout[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
.out(fabric_sc_out[0]));
direct_interc direct_interc_2_ (
.in(fabric_in[0]),
.out(direct_interc_2_out[0]));
direct_interc direct_interc_3_ (
.in(fabric_in[1]),
.out(direct_interc_3_out[0]));
direct_interc direct_interc_4_ (
.in(fabric_in[2]),
.out(direct_interc_4_out[0]));
direct_interc direct_interc_5_ (
.in(fabric_in[3]),
.out(direct_interc_5_out[0]));
direct_interc direct_interc_6_ (
.in(fabric_sc_in[0]),
.out(direct_interc_6_out[0]));
direct_interc direct_interc_7_ (
.in(fabric_clk[0]),
.out(direct_interc_7_out[0]));
direct_interc direct_interc_8_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]),
.out(direct_interc_8_out[0]));
direct_interc direct_interc_9_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
.out(direct_interc_9_out[0]));
direct_interc direct_interc_10_ (
.in(fabric_clk[0]),
.out(direct_interc_10_out[0]));
endmodule
//
//

59
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@ -1,59 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff(Test_en,
clk,
ff_D,
ff_DI,
ff_Q,
ff_clk);
//
input [0:0] Test_en;
//
input [0:0] clk;
//
input [0:0] ff_D;
//
input [0:0] ff_DI;
//
output [0:0] ff_Q;
//
input [0:0] ff_clk;
//
wire [0:0] ff_D;
wire [0:0] ff_DI;
wire [0:0] ff_Q;
wire [0:0] ff_clk;
//
//
//
//
//
//
//
sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ (
.SCE(Test_en[0]),
.CLK(clk[0]),
.D(ff_D[0]),
.SCD(ff_DI[0]),
.Q(ff_Q[0]));
endmodule
//

98
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@ -1,98 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic(prog_clk,
frac_logic_in,
ccff_head,
frac_logic_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:3] frac_logic_in;
//
input [0:0] ccff_head;
//
output [0:1] frac_logic_out;
//
output [0:0] ccff_tail;
//
wire [0:3] frac_logic_in;
wire [0:1] frac_logic_out;
//
//
//
wire [0:0] direct_interc_1_out;
wire [0:0] direct_interc_2_out;
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out;
wire [0:1] mux_frac_logic_out_0_undriven_sram_inv;
wire [0:1] mux_tree_size2_0_sram;
//
//
//
//
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
.prog_clk(prog_clk[0]),
.frac_lut4_in({direct_interc_1_out[0], direct_interc_2_out[0], direct_interc_3_out[0], direct_interc_4_out[0]}),
.ccff_head(ccff_head[0]),
.frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0:1]),
.frac_lut4_lut4_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail[0]));
mux_tree_size2 mux_frac_logic_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}),
.sram(mux_tree_size2_0_sram[0:1]),
.sram_inv(mux_frac_logic_out_0_undriven_sram_inv[0:1]),
.out(frac_logic_out[0]));
mux_tree_size2_mem mem_frac_logic_out_0 (
.prog_clk(prog_clk[0]),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_size2_0_sram[0:1]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]),
.out(frac_logic_out[1]));
direct_interc direct_interc_1_ (
.in(frac_logic_in[0]),
.out(direct_interc_1_out[0]));
direct_interc direct_interc_2_ (
.in(frac_logic_in[1]),
.out(direct_interc_2_out[0]));
direct_interc direct_interc_3_ (
.in(frac_logic_in[2]),
.out(direct_interc_3_out[0]));
direct_interc direct_interc_4_ (
.in(frac_logic_in[3]),
.out(direct_interc_4_out[0]));
endmodule
//
//

70
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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4(prog_clk,
frac_lut4_in,
ccff_head,
frac_lut4_lut3_out,
frac_lut4_lut4_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:3] frac_lut4_in;
//
input [0:0] ccff_head;
//
output [0:1] frac_lut4_lut3_out;
//
output [0:0] frac_lut4_lut4_out;
//
output [0:0] ccff_tail;
//
wire [0:3] frac_lut4_in;
wire [0:1] frac_lut4_lut3_out;
wire [0:0] frac_lut4_lut4_out;
//
//
//
wire [0:0] frac_lut4_0__undriven_mode_inv;
wire [0:15] frac_lut4_0__undriven_sram_inv;
wire [0:0] frac_lut4_0_mode;
wire [0:15] frac_lut4_0_sram;
//
//
//
//
frac_lut4 frac_lut4_0_ (
.in(frac_lut4_in[0:3]),
.sram(frac_lut4_0_sram[0:15]),
.sram_inv(frac_lut4_0__undriven_sram_inv[0:15]),
.mode(frac_lut4_0_mode[0]),
.mode_inv(frac_lut4_0__undriven_mode_inv[0]),
.lut3_out(frac_lut4_lut3_out[0:1]),
.lut4_out(frac_lut4_lut4_out[0]));
frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem (
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0]),
.mem_out({frac_lut4_0_sram[0:15], frac_lut4_0_mode[0]}));
endmodule
//

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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module logical_tile_io_mode_io_(prog_clk,
gfpga_pad_EMBEDDED_IO_SOC_IN,
gfpga_pad_EMBEDDED_IO_SOC_OUT,
gfpga_pad_EMBEDDED_IO_SOC_DIR,
io_outpad,
ccff_head,
io_inpad,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
//
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
//
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
//
input [0:0] io_outpad;
//
input [0:0] ccff_head;
//
output [0:0] io_inpad;
//
output [0:0] ccff_tail;
//
wire [0:0] io_outpad;
wire [0:0] io_inpad;
//
//
//
wire [0:0] direct_interc_1_out;
wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad;
//
//
//
//
logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.iopad_outpad(direct_interc_1_out[0]),
.ccff_head(ccff_head[0]),
.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]),
.ccff_tail(ccff_tail[0]));
direct_interc direct_interc_0_ (
.in(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]),
.out(io_inpad[0]));
direct_interc direct_interc_1_ (
.in(io_outpad[0]),
.out(direct_interc_1_out[0]));
endmodule
//
//

71
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v
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@ -1,71 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module logical_tile_io_mode_physical__iopad(prog_clk,
gfpga_pad_EMBEDDED_IO_SOC_IN,
gfpga_pad_EMBEDDED_IO_SOC_OUT,
gfpga_pad_EMBEDDED_IO_SOC_DIR,
iopad_outpad,
ccff_head,
iopad_inpad,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
//
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
//
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
//
input [0:0] iopad_outpad;
//
input [0:0] ccff_head;
//
output [0:0] iopad_inpad;
//
output [0:0] ccff_tail;
//
wire [0:0] iopad_outpad;
wire [0:0] iopad_inpad;
//
//
//
wire [0:0] EMBEDDED_IO_0_en;
//
//
//
//
EMBEDDED_IO EMBEDDED_IO_0_ (
.SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.FPGA_OUT(iopad_outpad[0]),
.FPGA_DIR(EMBEDDED_IO_0_en[0]),
.FPGA_IN(iopad_inpad[0]));
EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem (
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(EMBEDDED_IO_0_en[0]));
endmodule
//

321
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@ -1,321 +0,0 @@
module cbx_1__0_
( prog_clk, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, bottom_grid_pin_0_, bottom_grid_pin_2_, bottom_grid_pin_4_, bottom_grid_pin_6_, bottom_grid_pin_8_, bottom_grid_pin_10_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, top_width_0_height_0__pin_0_, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_1_upper, top_width_0_height_0__pin_1_lower, top_width_0_height_0__pin_3_upper, top_width_0_height_0__pin_3_lower, top_width_0_height_0__pin_5_upper, top_width_0_height_0__pin_5_lower, top_width_0_height_0__pin_7_upper, top_width_0_height_0__pin_7_lower, top_width_0_height_0__pin_9_upper, top_width_0_height_0__pin_9_lower, top_width_0_height_0__pin_11_upper, top_width_0_height_0__pin_11_lower, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:19] chanx_left_in;
input [0:19] chanx_right_in;
input [0:0] ccff_head;
output [0:19] chanx_left_out;
output [0:19] chanx_right_out;
output [0:0] bottom_grid_pin_0_;
output [0:0] bottom_grid_pin_2_;
output [0:0] bottom_grid_pin_4_;
output [0:0] bottom_grid_pin_6_;
output [0:0] bottom_grid_pin_8_;
output [0:0] bottom_grid_pin_10_;
output [0:0] ccff_tail;
input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN;
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT;
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR;
input [0:0] top_width_0_height_0__pin_0_;
input [0:0] top_width_0_height_0__pin_2_;
input [0:0] top_width_0_height_0__pin_4_;
input [0:0] top_width_0_height_0__pin_6_;
input [0:0] top_width_0_height_0__pin_8_;
input [0:0] top_width_0_height_0__pin_10_;
output [0:0] top_width_0_height_0__pin_1_upper;
output [0:0] top_width_0_height_0__pin_1_lower;
output [0:0] top_width_0_height_0__pin_3_upper;
output [0:0] top_width_0_height_0__pin_3_lower;
output [0:0] top_width_0_height_0__pin_5_upper;
output [0:0] top_width_0_height_0__pin_5_lower;
output [0:0] top_width_0_height_0__pin_7_upper;
output [0:0] top_width_0_height_0__pin_7_lower;
output [0:0] top_width_0_height_0__pin_9_upper;
output [0:0] top_width_0_height_0__pin_9_lower;
output [0:0] top_width_0_height_0__pin_11_upper;
output [0:0] top_width_0_height_0__pin_11_lower;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire ccff_tail_mid;
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
assign chanx_right_out[0] = chanx_left_in[0];
assign chanx_right_out[1] = chanx_left_in[1];
assign chanx_right_out[2] = chanx_left_in[2];
assign chanx_right_out[3] = chanx_left_in[3];
assign chanx_right_out[4] = chanx_left_in[4];
assign chanx_right_out[5] = chanx_left_in[5];
assign chanx_right_out[6] = chanx_left_in[6];
assign chanx_right_out[7] = chanx_left_in[7];
assign chanx_right_out[8] = chanx_left_in[8];
assign chanx_right_out[9] = chanx_left_in[9];
assign chanx_right_out[10] = chanx_left_in[10];
assign chanx_right_out[11] = chanx_left_in[11];
assign chanx_right_out[12] = chanx_left_in[12];
assign chanx_right_out[13] = chanx_left_in[13];
assign chanx_right_out[14] = chanx_left_in[14];
assign chanx_right_out[15] = chanx_left_in[15];
assign chanx_right_out[16] = chanx_left_in[16];
assign chanx_right_out[17] = chanx_left_in[17];
assign chanx_right_out[18] = chanx_left_in[18];
assign chanx_right_out[19] = chanx_left_in[19];
assign chanx_left_out[0] = chanx_right_in[0];
assign chanx_left_out[1] = chanx_right_in[1];
assign chanx_left_out[2] = chanx_right_in[2];
assign chanx_left_out[3] = chanx_right_in[3];
assign chanx_left_out[4] = chanx_right_in[4];
assign chanx_left_out[5] = chanx_right_in[5];
assign chanx_left_out[6] = chanx_right_in[6];
assign chanx_left_out[7] = chanx_right_in[7];
assign chanx_left_out[8] = chanx_right_in[8];
assign chanx_left_out[9] = chanx_right_in[9];
assign chanx_left_out[10] = chanx_right_in[10];
assign chanx_left_out[11] = chanx_right_in[11];
assign chanx_left_out[12] = chanx_right_in[12];
assign chanx_left_out[13] = chanx_right_in[13];
assign chanx_left_out[14] = chanx_right_in[14];
assign chanx_left_out[15] = chanx_right_in[15];
assign chanx_left_out[16] = chanx_right_in[16];
assign chanx_left_out[17] = chanx_right_in[17];
assign chanx_left_out[18] = chanx_right_in[18];
assign chanx_left_out[19] = chanx_right_in[19];
assign top_width_0_height_0__pin_1_lower[0] = top_width_0_height_0__pin_1_upper[0];
assign top_width_0_height_0__pin_3_lower[0] = top_width_0_height_0__pin_3_upper[0];
assign top_width_0_height_0__pin_5_lower[0] = top_width_0_height_0__pin_5_upper[0];
assign top_width_0_height_0__pin_7_lower[0] = top_width_0_height_0__pin_7_upper[0];
assign top_width_0_height_0__pin_9_lower[0] = top_width_0_height_0__pin_9_upper[0];
assign top_width_0_height_0__pin_11_lower[0] = top_width_0_height_0__pin_11_upper[0];
assign SC_IN_TOP = SC_IN_BOT;
assign SC_OUT_TOP = SC_OUT_BOT;
mux_tree_tapbuf_size10
mux_top_ipin_0
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_0_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_1
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_2_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_2
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_4_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_3
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_6_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_4
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_8_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_5
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_10_[0])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__0
(
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.io_outpad(top_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(top_width_0_height_0__pin_1_upper[0]),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail[0])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__1
(
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]),
.io_outpad(top_width_0_height_0__pin_2_[0]),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_3_upper[0]),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail[0])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__2
(
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]),
.io_outpad(top_width_0_height_0__pin_4_[0]),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_5_upper[0]),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail[0])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__3
(
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]),
.io_outpad(top_width_0_height_0__pin_6_[0]),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_7_upper[0]),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail[0])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__4
(
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4]),
.io_outpad(top_width_0_height_0__pin_8_[0]),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_9_upper[0]),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail[0])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__5
(
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[5]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[5]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[5]),
.io_outpad(top_width_0_height_0__pin_10_[0]),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_11_upper[0]),
.ccff_tail(ccff_tail[0])
);
endmodule

444
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@ -1,444 +0,0 @@
module cbx_1__1_
( prog_clk, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:19] chanx_left_in;
input [0:19] chanx_right_in;
input [0:0] ccff_head;
output [0:19] chanx_left_out;
output [0:19] chanx_right_out;
output [0:0] bottom_grid_pin_0_;
output [0:0] bottom_grid_pin_1_;
output [0:0] bottom_grid_pin_2_;
output [0:0] bottom_grid_pin_3_;
output [0:0] bottom_grid_pin_4_;
output [0:0] bottom_grid_pin_5_;
output [0:0] bottom_grid_pin_6_;
output [0:0] bottom_grid_pin_7_;
output [0:0] bottom_grid_pin_8_;
output [0:0] bottom_grid_pin_9_;
output [0:0] bottom_grid_pin_10_;
output [0:0] bottom_grid_pin_11_;
output [0:0] bottom_grid_pin_12_;
output [0:0] bottom_grid_pin_13_;
output [0:0] bottom_grid_pin_14_;
output [0:0] bottom_grid_pin_15_;
output [0:0] ccff_tail;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_10_undriven_sram_inv;
wire [0:3] mux_top_ipin_11_undriven_sram_inv;
wire [0:3] mux_top_ipin_12_undriven_sram_inv;
wire [0:3] mux_top_ipin_13_undriven_sram_inv;
wire [0:3] mux_top_ipin_14_undriven_sram_inv;
wire [0:3] mux_top_ipin_15_undriven_sram_inv;
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
wire [0:3] mux_top_ipin_6_undriven_sram_inv;
wire [0:3] mux_top_ipin_7_undriven_sram_inv;
wire [0:3] mux_top_ipin_8_undriven_sram_inv;
wire [0:3] mux_top_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
assign chanx_right_out[0] = chanx_left_in[0];
assign chanx_right_out[1] = chanx_left_in[1];
assign chanx_right_out[2] = chanx_left_in[2];
assign chanx_right_out[3] = chanx_left_in[3];
assign chanx_right_out[4] = chanx_left_in[4];
assign chanx_right_out[5] = chanx_left_in[5];
assign chanx_right_out[6] = chanx_left_in[6];
assign chanx_right_out[7] = chanx_left_in[7];
assign chanx_right_out[8] = chanx_left_in[8];
assign chanx_right_out[9] = chanx_left_in[9];
assign chanx_right_out[10] = chanx_left_in[10];
assign chanx_right_out[11] = chanx_left_in[11];
assign chanx_right_out[12] = chanx_left_in[12];
assign chanx_right_out[13] = chanx_left_in[13];
assign chanx_right_out[14] = chanx_left_in[14];
assign chanx_right_out[15] = chanx_left_in[15];
assign chanx_right_out[16] = chanx_left_in[16];
assign chanx_right_out[17] = chanx_left_in[17];
assign chanx_right_out[18] = chanx_left_in[18];
assign chanx_right_out[19] = chanx_left_in[19];
assign chanx_left_out[0] = chanx_right_in[0];
assign chanx_left_out[1] = chanx_right_in[1];
assign chanx_left_out[2] = chanx_right_in[2];
assign chanx_left_out[3] = chanx_right_in[3];
assign chanx_left_out[4] = chanx_right_in[4];
assign chanx_left_out[5] = chanx_right_in[5];
assign chanx_left_out[6] = chanx_right_in[6];
assign chanx_left_out[7] = chanx_right_in[7];
assign chanx_left_out[8] = chanx_right_in[8];
assign chanx_left_out[9] = chanx_right_in[9];
assign chanx_left_out[10] = chanx_right_in[10];
assign chanx_left_out[11] = chanx_right_in[11];
assign chanx_left_out[12] = chanx_right_in[12];
assign chanx_left_out[13] = chanx_right_in[13];
assign chanx_left_out[14] = chanx_right_in[14];
assign chanx_left_out[15] = chanx_right_in[15];
assign chanx_left_out[16] = chanx_right_in[16];
assign chanx_left_out[17] = chanx_right_in[17];
assign chanx_left_out[18] = chanx_right_in[18];
assign chanx_left_out[19] = chanx_right_in[19];
assign SC_IN_TOP = SC_IN_BOT;
assign SC_OUT_TOP = SC_OUT_BOT;
mux_tree_tapbuf_size10
mux_top_ipin_0
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_0_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_3
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_3_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_4
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_4_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_7
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_7_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_8
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_8_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_11
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_11_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_12
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_12_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_15
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_15_[0])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
mux_tree_tapbuf_size8
mux_top_ipin_1
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_1_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_2
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_2_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_5
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_5_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_6
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_6_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_9
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_9_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_10
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_10_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_13
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_13_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_14
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_14_[0])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);
endmodule

490
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v
View File

@ -1,490 +0,0 @@
module cbx_1__2_
( prog_clk, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, top_grid_pin_0_, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, bottom_width_0_height_0__pin_0_, bottom_width_0_height_0__pin_1_upper, bottom_width_0_height_0__pin_1_lower, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:19] chanx_left_in;
input [0:19] chanx_right_in;
input [0:0] ccff_head;
output [0:19] chanx_left_out;
output [0:19] chanx_right_out;
output [0:0] top_grid_pin_0_;
output [0:0] bottom_grid_pin_0_;
output [0:0] bottom_grid_pin_1_;
output [0:0] bottom_grid_pin_2_;
output [0:0] bottom_grid_pin_3_;
output [0:0] bottom_grid_pin_4_;
output [0:0] bottom_grid_pin_5_;
output [0:0] bottom_grid_pin_6_;
output [0:0] bottom_grid_pin_7_;
output [0:0] bottom_grid_pin_8_;
output [0:0] bottom_grid_pin_9_;
output [0:0] bottom_grid_pin_10_;
output [0:0] bottom_grid_pin_11_;
output [0:0] bottom_grid_pin_12_;
output [0:0] bottom_grid_pin_13_;
output [0:0] bottom_grid_pin_14_;
output [0:0] bottom_grid_pin_15_;
output [0:0] ccff_tail;
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
input [0:0] bottom_width_0_height_0__pin_0_;
output [0:0] bottom_width_0_height_0__pin_1_upper;
output [0:0] bottom_width_0_height_0__pin_1_lower;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:3] mux_bottom_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_10_undriven_sram_inv;
wire [0:3] mux_top_ipin_11_undriven_sram_inv;
wire [0:3] mux_top_ipin_12_undriven_sram_inv;
wire [0:3] mux_top_ipin_13_undriven_sram_inv;
wire [0:3] mux_top_ipin_14_undriven_sram_inv;
wire [0:3] mux_top_ipin_15_undriven_sram_inv;
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
wire [0:3] mux_top_ipin_6_undriven_sram_inv;
wire [0:3] mux_top_ipin_7_undriven_sram_inv;
wire [0:3] mux_top_ipin_8_undriven_sram_inv;
wire [0:3] mux_top_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
wire ccff_tail_mid;
assign chanx_right_out[0] = chanx_left_in[0];
assign chanx_right_out[1] = chanx_left_in[1];
assign chanx_right_out[2] = chanx_left_in[2];
assign chanx_right_out[3] = chanx_left_in[3];
assign chanx_right_out[4] = chanx_left_in[4];
assign chanx_right_out[5] = chanx_left_in[5];
assign chanx_right_out[6] = chanx_left_in[6];
assign chanx_right_out[7] = chanx_left_in[7];
assign chanx_right_out[8] = chanx_left_in[8];
assign chanx_right_out[9] = chanx_left_in[9];
assign chanx_right_out[10] = chanx_left_in[10];
assign chanx_right_out[11] = chanx_left_in[11];
assign chanx_right_out[12] = chanx_left_in[12];
assign chanx_right_out[13] = chanx_left_in[13];
assign chanx_right_out[14] = chanx_left_in[14];
assign chanx_right_out[15] = chanx_left_in[15];
assign chanx_right_out[16] = chanx_left_in[16];
assign chanx_right_out[17] = chanx_left_in[17];
assign chanx_right_out[18] = chanx_left_in[18];
assign chanx_right_out[19] = chanx_left_in[19];
assign chanx_left_out[0] = chanx_right_in[0];
assign chanx_left_out[1] = chanx_right_in[1];
assign chanx_left_out[2] = chanx_right_in[2];
assign chanx_left_out[3] = chanx_right_in[3];
assign chanx_left_out[4] = chanx_right_in[4];
assign chanx_left_out[5] = chanx_right_in[5];
assign chanx_left_out[6] = chanx_right_in[6];
assign chanx_left_out[7] = chanx_right_in[7];
assign chanx_left_out[8] = chanx_right_in[8];
assign chanx_left_out[9] = chanx_right_in[9];
assign chanx_left_out[10] = chanx_right_in[10];
assign chanx_left_out[11] = chanx_right_in[11];
assign chanx_left_out[12] = chanx_right_in[12];
assign chanx_left_out[13] = chanx_right_in[13];
assign chanx_left_out[14] = chanx_right_in[14];
assign chanx_left_out[15] = chanx_right_in[15];
assign chanx_left_out[16] = chanx_right_in[16];
assign chanx_left_out[17] = chanx_right_in[17];
assign chanx_left_out[18] = chanx_right_in[18];
assign chanx_left_out[19] = chanx_right_in[19];
assign bottom_width_0_height_0__pin_1_lower[0] = bottom_width_0_height_0__pin_1_upper[0];
assign SC_IN_TOP = SC_IN_BOT;
assign SC_OUT_TOP = SC_OUT_BOT;
mux_tree_tapbuf_size10
mux_bottom_ipin_0
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_bottom_ipin_0_undriven_sram_inv[0:3]),
.out(top_grid_pin_0_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_0
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_0_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_3
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_3_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_4
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_4_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_7
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_7_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_8
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_8_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_11
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_11_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_12
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_12_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_15
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_15_[0])
);
mux_tree_tapbuf_size10_mem
mem_bottom_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3])
);
mux_tree_tapbuf_size8
mux_top_ipin_1
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_1_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_2
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_2_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_5
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_5_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_6
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_6_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_9
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_9_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_10
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_10_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_13
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_13_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_14
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_14_[0])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__0
(
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.io_outpad(bottom_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(bottom_width_0_height_0__pin_1_upper[0]),
.ccff_tail(ccff_tail[0])
);
endmodule

100
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v
View File

@ -1,100 +0,0 @@
module cby_0__1_
( prog_clk, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_0_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, right_width_0_height_0__pin_0_, right_width_0_height_0__pin_1_upper, right_width_0_height_0__pin_1_lower );
input [0:0] prog_clk;
input [0:19] chany_bottom_in;
input [0:19] chany_top_in;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chany_top_out;
output [0:0] left_grid_pin_0_;
output [0:0] ccff_tail;
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
input [0:0] right_width_0_height_0__pin_0_;
output [0:0] right_width_0_height_0__pin_1_upper;
output [0:0] right_width_0_height_0__pin_1_lower;
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire ccff_tail_mid;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
assign chany_top_out[2] = chany_bottom_in[2];
assign chany_top_out[3] = chany_bottom_in[3];
assign chany_top_out[4] = chany_bottom_in[4];
assign chany_top_out[5] = chany_bottom_in[5];
assign chany_top_out[6] = chany_bottom_in[6];
assign chany_top_out[7] = chany_bottom_in[7];
assign chany_top_out[8] = chany_bottom_in[8];
assign chany_top_out[9] = chany_bottom_in[9];
assign chany_top_out[10] = chany_bottom_in[10];
assign chany_top_out[11] = chany_bottom_in[11];
assign chany_top_out[12] = chany_bottom_in[12];
assign chany_top_out[13] = chany_bottom_in[13];
assign chany_top_out[14] = chany_bottom_in[14];
assign chany_top_out[15] = chany_bottom_in[15];
assign chany_top_out[16] = chany_bottom_in[16];
assign chany_top_out[17] = chany_bottom_in[17];
assign chany_top_out[18] = chany_bottom_in[18];
assign chany_top_out[19] = chany_bottom_in[19];
assign chany_bottom_out[0] = chany_top_in[0];
assign chany_bottom_out[1] = chany_top_in[1];
assign chany_bottom_out[2] = chany_top_in[2];
assign chany_bottom_out[3] = chany_top_in[3];
assign chany_bottom_out[4] = chany_top_in[4];
assign chany_bottom_out[5] = chany_top_in[5];
assign chany_bottom_out[6] = chany_top_in[6];
assign chany_bottom_out[7] = chany_top_in[7];
assign chany_bottom_out[8] = chany_top_in[8];
assign chany_bottom_out[9] = chany_top_in[9];
assign chany_bottom_out[10] = chany_top_in[10];
assign chany_bottom_out[11] = chany_top_in[11];
assign chany_bottom_out[12] = chany_top_in[12];
assign chany_bottom_out[13] = chany_top_in[13];
assign chany_bottom_out[14] = chany_top_in[14];
assign chany_bottom_out[15] = chany_top_in[15];
assign chany_bottom_out[16] = chany_top_in[16];
assign chany_bottom_out[17] = chany_top_in[17];
assign chany_bottom_out[18] = chany_top_in[18];
assign chany_bottom_out[19] = chany_top_in[19];
assign right_width_0_height_0__pin_1_lower[0] = right_width_0_height_0__pin_1_upper[0];
mux_tree_tapbuf_size10
mux_right_ipin_0
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_pin_0_[0])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__0
(
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.io_outpad(right_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(right_width_0_height_0__pin_1_upper[0]),
.ccff_tail(ccff_tail[0])
);
endmodule

438
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v
View File

@ -1,438 +0,0 @@
module cby_1__1_
( prog_clk, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail );
input [0:0] prog_clk;
input [0:19] chany_bottom_in;
input [0:19] chany_top_in;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chany_top_out;
output [0:0] left_grid_pin_16_;
output [0:0] left_grid_pin_17_;
output [0:0] left_grid_pin_18_;
output [0:0] left_grid_pin_19_;
output [0:0] left_grid_pin_20_;
output [0:0] left_grid_pin_21_;
output [0:0] left_grid_pin_22_;
output [0:0] left_grid_pin_23_;
output [0:0] left_grid_pin_24_;
output [0:0] left_grid_pin_25_;
output [0:0] left_grid_pin_26_;
output [0:0] left_grid_pin_27_;
output [0:0] left_grid_pin_28_;
output [0:0] left_grid_pin_29_;
output [0:0] left_grid_pin_30_;
output [0:0] left_grid_pin_31_;
output [0:0] ccff_tail;
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_right_ipin_10_undriven_sram_inv;
wire [0:3] mux_right_ipin_11_undriven_sram_inv;
wire [0:3] mux_right_ipin_12_undriven_sram_inv;
wire [0:3] mux_right_ipin_13_undriven_sram_inv;
wire [0:3] mux_right_ipin_14_undriven_sram_inv;
wire [0:3] mux_right_ipin_15_undriven_sram_inv;
wire [0:3] mux_right_ipin_1_undriven_sram_inv;
wire [0:3] mux_right_ipin_2_undriven_sram_inv;
wire [0:3] mux_right_ipin_3_undriven_sram_inv;
wire [0:3] mux_right_ipin_4_undriven_sram_inv;
wire [0:3] mux_right_ipin_5_undriven_sram_inv;
wire [0:3] mux_right_ipin_6_undriven_sram_inv;
wire [0:3] mux_right_ipin_7_undriven_sram_inv;
wire [0:3] mux_right_ipin_8_undriven_sram_inv;
wire [0:3] mux_right_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
assign chany_top_out[2] = chany_bottom_in[2];
assign chany_top_out[3] = chany_bottom_in[3];
assign chany_top_out[4] = chany_bottom_in[4];
assign chany_top_out[5] = chany_bottom_in[5];
assign chany_top_out[6] = chany_bottom_in[6];
assign chany_top_out[7] = chany_bottom_in[7];
assign chany_top_out[8] = chany_bottom_in[8];
assign chany_top_out[9] = chany_bottom_in[9];
assign chany_top_out[10] = chany_bottom_in[10];
assign chany_top_out[11] = chany_bottom_in[11];
assign chany_top_out[12] = chany_bottom_in[12];
assign chany_top_out[13] = chany_bottom_in[13];
assign chany_top_out[14] = chany_bottom_in[14];
assign chany_top_out[15] = chany_bottom_in[15];
assign chany_top_out[16] = chany_bottom_in[16];
assign chany_top_out[17] = chany_bottom_in[17];
assign chany_top_out[18] = chany_bottom_in[18];
assign chany_top_out[19] = chany_bottom_in[19];
assign chany_bottom_out[0] = chany_top_in[0];
assign chany_bottom_out[1] = chany_top_in[1];
assign chany_bottom_out[2] = chany_top_in[2];
assign chany_bottom_out[3] = chany_top_in[3];
assign chany_bottom_out[4] = chany_top_in[4];
assign chany_bottom_out[5] = chany_top_in[5];
assign chany_bottom_out[6] = chany_top_in[6];
assign chany_bottom_out[7] = chany_top_in[7];
assign chany_bottom_out[8] = chany_top_in[8];
assign chany_bottom_out[9] = chany_top_in[9];
assign chany_bottom_out[10] = chany_top_in[10];
assign chany_bottom_out[11] = chany_top_in[11];
assign chany_bottom_out[12] = chany_top_in[12];
assign chany_bottom_out[13] = chany_top_in[13];
assign chany_bottom_out[14] = chany_top_in[14];
assign chany_bottom_out[15] = chany_top_in[15];
assign chany_bottom_out[16] = chany_top_in[16];
assign chany_bottom_out[17] = chany_top_in[17];
assign chany_bottom_out[18] = chany_top_in[18];
assign chany_bottom_out[19] = chany_top_in[19];
mux_tree_tapbuf_size10
mux_right_ipin_0
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_pin_16_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_3
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]),
.out(left_grid_pin_19_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_4
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]),
.out(left_grid_pin_20_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_7
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]),
.out(left_grid_pin_23_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_8
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]),
.out(left_grid_pin_24_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_11
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]),
.out(left_grid_pin_27_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_12
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]),
.out(left_grid_pin_28_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_15
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]),
.out(left_grid_pin_31_[0])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
mux_tree_tapbuf_size8
mux_right_ipin_1
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]),
.out(left_grid_pin_17_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_2
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]),
.out(left_grid_pin_18_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_5
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]),
.out(left_grid_pin_21_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_6
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]),
.out(left_grid_pin_22_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_9
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]),
.out(left_grid_pin_25_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_10
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]),
.out(left_grid_pin_26_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_13
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]),
.out(left_grid_pin_29_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_14
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]),
.out(left_grid_pin_30_[0])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);
endmodule

484
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v
View File

@ -1,484 +0,0 @@
module cby_2__1_
( prog_clk, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, right_grid_pin_0_, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, left_width_0_height_0__pin_0_, left_width_0_height_0__pin_1_upper, left_width_0_height_0__pin_1_lower );
input [0:0] prog_clk;
input [0:19] chany_bottom_in;
input [0:19] chany_top_in;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chany_top_out;
output [0:0] right_grid_pin_0_;
output [0:0] left_grid_pin_16_;
output [0:0] left_grid_pin_17_;
output [0:0] left_grid_pin_18_;
output [0:0] left_grid_pin_19_;
output [0:0] left_grid_pin_20_;
output [0:0] left_grid_pin_21_;
output [0:0] left_grid_pin_22_;
output [0:0] left_grid_pin_23_;
output [0:0] left_grid_pin_24_;
output [0:0] left_grid_pin_25_;
output [0:0] left_grid_pin_26_;
output [0:0] left_grid_pin_27_;
output [0:0] left_grid_pin_28_;
output [0:0] left_grid_pin_29_;
output [0:0] left_grid_pin_30_;
output [0:0] left_grid_pin_31_;
output [0:0] ccff_tail;
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
input [0:0] left_width_0_height_0__pin_0_;
output [0:0] left_width_0_height_0__pin_1_upper;
output [0:0] left_width_0_height_0__pin_1_lower;
wire [0:3] mux_left_ipin_0_undriven_sram_inv;
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_right_ipin_10_undriven_sram_inv;
wire [0:3] mux_right_ipin_11_undriven_sram_inv;
wire [0:3] mux_right_ipin_12_undriven_sram_inv;
wire [0:3] mux_right_ipin_13_undriven_sram_inv;
wire [0:3] mux_right_ipin_14_undriven_sram_inv;
wire [0:3] mux_right_ipin_15_undriven_sram_inv;
wire [0:3] mux_right_ipin_1_undriven_sram_inv;
wire [0:3] mux_right_ipin_2_undriven_sram_inv;
wire [0:3] mux_right_ipin_3_undriven_sram_inv;
wire [0:3] mux_right_ipin_4_undriven_sram_inv;
wire [0:3] mux_right_ipin_5_undriven_sram_inv;
wire [0:3] mux_right_ipin_6_undriven_sram_inv;
wire [0:3] mux_right_ipin_7_undriven_sram_inv;
wire [0:3] mux_right_ipin_8_undriven_sram_inv;
wire [0:3] mux_right_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
wire ccff_tail_mid;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
assign chany_top_out[2] = chany_bottom_in[2];
assign chany_top_out[3] = chany_bottom_in[3];
assign chany_top_out[4] = chany_bottom_in[4];
assign chany_top_out[5] = chany_bottom_in[5];
assign chany_top_out[6] = chany_bottom_in[6];
assign chany_top_out[7] = chany_bottom_in[7];
assign chany_top_out[8] = chany_bottom_in[8];
assign chany_top_out[9] = chany_bottom_in[9];
assign chany_top_out[10] = chany_bottom_in[10];
assign chany_top_out[11] = chany_bottom_in[11];
assign chany_top_out[12] = chany_bottom_in[12];
assign chany_top_out[13] = chany_bottom_in[13];
assign chany_top_out[14] = chany_bottom_in[14];
assign chany_top_out[15] = chany_bottom_in[15];
assign chany_top_out[16] = chany_bottom_in[16];
assign chany_top_out[17] = chany_bottom_in[17];
assign chany_top_out[18] = chany_bottom_in[18];
assign chany_top_out[19] = chany_bottom_in[19];
assign chany_bottom_out[0] = chany_top_in[0];
assign chany_bottom_out[1] = chany_top_in[1];
assign chany_bottom_out[2] = chany_top_in[2];
assign chany_bottom_out[3] = chany_top_in[3];
assign chany_bottom_out[4] = chany_top_in[4];
assign chany_bottom_out[5] = chany_top_in[5];
assign chany_bottom_out[6] = chany_top_in[6];
assign chany_bottom_out[7] = chany_top_in[7];
assign chany_bottom_out[8] = chany_top_in[8];
assign chany_bottom_out[9] = chany_top_in[9];
assign chany_bottom_out[10] = chany_top_in[10];
assign chany_bottom_out[11] = chany_top_in[11];
assign chany_bottom_out[12] = chany_top_in[12];
assign chany_bottom_out[13] = chany_top_in[13];
assign chany_bottom_out[14] = chany_top_in[14];
assign chany_bottom_out[15] = chany_top_in[15];
assign chany_bottom_out[16] = chany_top_in[16];
assign chany_bottom_out[17] = chany_top_in[17];
assign chany_bottom_out[18] = chany_top_in[18];
assign chany_bottom_out[19] = chany_top_in[19];
assign left_width_0_height_0__pin_1_lower[0] = left_width_0_height_0__pin_1_upper[0];
mux_tree_tapbuf_size10
mux_left_ipin_0
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_left_ipin_0_undriven_sram_inv[0:3]),
.out(right_grid_pin_0_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_0
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_pin_16_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_3
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]),
.out(left_grid_pin_19_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_4
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]),
.out(left_grid_pin_20_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_7
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]),
.out(left_grid_pin_23_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_8
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]),
.out(left_grid_pin_24_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_11
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]),
.out(left_grid_pin_27_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_12
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]),
.out(left_grid_pin_28_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_15
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]),
.out(left_grid_pin_31_[0])
);
mux_tree_tapbuf_size10_mem
mem_left_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3])
);
mux_tree_tapbuf_size8
mux_right_ipin_1
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]),
.out(left_grid_pin_17_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_2
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]),
.out(left_grid_pin_18_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_5
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]),
.out(left_grid_pin_21_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_6
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]),
.out(left_grid_pin_22_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_9
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]),
.out(left_grid_pin_25_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_10
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]),
.out(left_grid_pin_26_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_13
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]),
.out(left_grid_pin_29_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_14
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]),
.out(left_grid_pin_30_[0])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__0
(
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.io_outpad(left_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(left_width_0_height_0__pin_1_upper[0]),
.ccff_tail(ccff_tail[0])
);
endmodule

501
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v
View File

@ -1,501 +0,0 @@
module sb_0__0_
( prog_clk, chany_top_in, top_left_grid_pin_1_, chanx_right_in, right_bottom_grid_pin_1_, right_bottom_grid_pin_3_, right_bottom_grid_pin_5_, right_bottom_grid_pin_7_, right_bottom_grid_pin_9_, right_bottom_grid_pin_11_, ccff_head, chany_top_out, chanx_right_out, ccff_tail );
input [0:0] prog_clk;
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_1_;
input [0:19] chanx_right_in;
input [0:0] right_bottom_grid_pin_1_;
input [0:0] right_bottom_grid_pin_3_;
input [0:0] right_bottom_grid_pin_5_;
input [0:0] right_bottom_grid_pin_7_;
input [0:0] right_bottom_grid_pin_9_;
input [0:0] right_bottom_grid_pin_11_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_right_out;
output [0:0] ccff_tail;
wire [0:2] mux_right_track_0_undriven_sram_inv;
wire [0:1] mux_right_track_10_undriven_sram_inv;
wire [0:1] mux_right_track_12_undriven_sram_inv;
wire [0:1] mux_right_track_14_undriven_sram_inv;
wire [0:1] mux_right_track_16_undriven_sram_inv;
wire [0:1] mux_right_track_18_undriven_sram_inv;
wire [0:1] mux_right_track_24_undriven_sram_inv;
wire [0:1] mux_right_track_26_undriven_sram_inv;
wire [0:1] mux_right_track_28_undriven_sram_inv;
wire [0:2] mux_right_track_2_undriven_sram_inv;
wire [0:1] mux_right_track_30_undriven_sram_inv;
wire [0:1] mux_right_track_32_undriven_sram_inv;
wire [0:1] mux_right_track_34_undriven_sram_inv;
wire [0:2] mux_right_track_4_undriven_sram_inv;
wire [0:2] mux_right_track_6_undriven_sram_inv;
wire [0:1] mux_right_track_8_undriven_sram_inv;
wire [0:1] mux_top_track_0_undriven_sram_inv;
wire [0:1] mux_top_track_24_undriven_sram_inv;
wire [0:1] mux_top_track_4_undriven_sram_inv;
wire [0:1] mux_top_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
assign chanx_right_out[10] = chany_top_in[9];
assign chanx_right_out[11] = chany_top_in[10];
assign chanx_right_out[18] = chany_top_in[17];
assign chanx_right_out[19] = chany_top_in[18];
assign chany_top_out[19] = chanx_right_in[0];
assign chany_top_out[1] = chanx_right_in[2];
assign chany_top_out[3] = chanx_right_in[4];
assign chany_top_out[5] = chanx_right_in[6];
assign chany_top_out[6] = chanx_right_in[7];
assign chany_top_out[7] = chanx_right_in[8];
assign chany_top_out[8] = chanx_right_in[9];
assign chany_top_out[9] = chanx_right_in[10];
assign chany_top_out[10] = chanx_right_in[11];
assign chany_top_out[11] = chanx_right_in[12];
assign chany_top_out[13] = chanx_right_in[14];
assign chany_top_out[14] = chanx_right_in[15];
assign chany_top_out[15] = chanx_right_in[16];
assign chany_top_out[16] = chanx_right_in[17];
assign chany_top_out[17] = chanx_right_in[18];
assign chany_top_out[18] = chanx_right_in[19];
mux_tree_tapbuf_size2
mux_top_track_0
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[1] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:1]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size2
mux_top_track_4
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[3] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:1]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size2
mux_top_track_8
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[5] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:1]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size2
mux_top_track_24
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:1]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size2
mux_right_track_8
(
.in({ chany_top_in[3], right_bottom_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:1]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size2
mux_right_track_10
(
.in({ chany_top_in[4], right_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_right_track_10_undriven_sram_inv[0:1]),
.out(chanx_right_out[5])
);
mux_tree_tapbuf_size2
mux_right_track_12
(
.in({ chany_top_in[5], right_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_right_track_12_undriven_sram_inv[0:1]),
.out(chanx_right_out[6])
);
mux_tree_tapbuf_size2
mux_right_track_14
(
.in({ chany_top_in[6], right_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_right_track_14_undriven_sram_inv[0:1]),
.out(chanx_right_out[7])
);
mux_tree_tapbuf_size2
mux_right_track_16
(
.in({ chany_top_in[7], right_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size2
mux_right_track_18
(
.in({ chany_top_in[8], right_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
.out(chanx_right_out[9])
);
mux_tree_tapbuf_size2
mux_right_track_24
(
.in({ chany_top_in[11], right_bottom_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:1]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size2
mux_right_track_26
(
.in({ chany_top_in[12], right_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_right_track_26_undriven_sram_inv[0:1]),
.out(chanx_right_out[13])
);
mux_tree_tapbuf_size2
mux_right_track_28
(
.in({ chany_top_in[13], right_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_right_track_28_undriven_sram_inv[0:1]),
.out(chanx_right_out[14])
);
mux_tree_tapbuf_size2
mux_right_track_30
(
.in({ chany_top_in[14], right_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_right_track_30_undriven_sram_inv[0:1]),
.out(chanx_right_out[15])
);
mux_tree_tapbuf_size2
mux_right_track_32
(
.in({ chany_top_in[15], right_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:1]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size2
mux_right_track_34
(
.in({ chany_top_in[16], right_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_right_track_34_undriven_sram_inv[0:1]),
.out(chanx_right_out[17])
);
mux_tree_tapbuf_size2_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_26
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_28
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_30
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_34
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
mux_tree_tapbuf_size4
mux_right_track_0
(
.in({ chany_top_in[19], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:2]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size4
mux_right_track_2
(
.in({ chany_top_in[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:2]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size4
mux_right_track_4
(
.in({ chany_top_in[1], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:2]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size4
mux_right_track_6
(
.in({ chany_top_in[2], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_right_track_6_undriven_sram_inv[0:2]),
.out(chanx_right_out[3])
);
mux_tree_tapbuf_size4_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2])
);
endmodule

812
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v
View File

@ -1,812 +0,0 @@
module sb_0__1_
( prog_clk, chany_top_in, top_left_grid_pin_1_, chanx_right_in, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chany_top_out, chanx_right_out, chany_bottom_out, ccff_tail );
input [0:0] prog_clk;
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_1_;
input [0:19] chanx_right_in;
input [0:0] right_bottom_grid_pin_34_;
input [0:0] right_bottom_grid_pin_35_;
input [0:0] right_bottom_grid_pin_36_;
input [0:0] right_bottom_grid_pin_37_;
input [0:0] right_bottom_grid_pin_38_;
input [0:0] right_bottom_grid_pin_39_;
input [0:0] right_bottom_grid_pin_40_;
input [0:0] right_bottom_grid_pin_41_;
input [0:19] chany_bottom_in;
input [0:0] bottom_left_grid_pin_1_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_right_out;
output [0:19] chany_bottom_out;
output [0:0] ccff_tail;
wire [0:2] mux_bottom_track_17_undriven_sram_inv;
wire [0:2] mux_bottom_track_1_undriven_sram_inv;
wire [0:2] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_33_undriven_sram_inv;
wire [0:2] mux_bottom_track_3_undriven_sram_inv;
wire [0:2] mux_bottom_track_5_undriven_sram_inv;
wire [0:2] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_right_track_0_undriven_sram_inv;
wire [0:2] mux_right_track_10_undriven_sram_inv;
wire [0:2] mux_right_track_12_undriven_sram_inv;
wire [0:2] mux_right_track_14_undriven_sram_inv;
wire [0:1] mux_right_track_16_undriven_sram_inv;
wire [0:1] mux_right_track_18_undriven_sram_inv;
wire [0:1] mux_right_track_20_undriven_sram_inv;
wire [0:1] mux_right_track_22_undriven_sram_inv;
wire [0:2] mux_right_track_24_undriven_sram_inv;
wire [0:1] mux_right_track_26_undriven_sram_inv;
wire [0:1] mux_right_track_28_undriven_sram_inv;
wire [0:2] mux_right_track_2_undriven_sram_inv;
wire [0:1] mux_right_track_30_undriven_sram_inv;
wire [0:1] mux_right_track_32_undriven_sram_inv;
wire [0:1] mux_right_track_34_undriven_sram_inv;
wire [0:1] mux_right_track_36_undriven_sram_inv;
wire [0:2] mux_right_track_4_undriven_sram_inv;
wire [0:2] mux_right_track_6_undriven_sram_inv;
wire [0:2] mux_right_track_8_undriven_sram_inv;
wire [0:2] mux_top_track_0_undriven_sram_inv;
wire [0:2] mux_top_track_16_undriven_sram_inv;
wire [0:2] mux_top_track_24_undriven_sram_inv;
wire [0:2] mux_top_track_2_undriven_sram_inv;
wire [0:2] mux_top_track_32_undriven_sram_inv;
wire [0:2] mux_top_track_4_undriven_sram_inv;
wire [0:2] mux_top_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_4_sram;
wire [0:2] mux_tree_tapbuf_size4_5_sram;
wire [0:2] mux_tree_tapbuf_size4_6_sram;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:2] mux_tree_tapbuf_size5_2_sram;
wire [0:2] mux_tree_tapbuf_size5_3_sram;
wire [0:2] mux_tree_tapbuf_size5_4_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:2] mux_tree_tapbuf_size6_4_sram;
wire [0:2] mux_tree_tapbuf_size6_5_sram;
wire [0:2] mux_tree_tapbuf_size6_6_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
assign chany_bottom_out[3] = chany_top_in[2];
assign chany_bottom_out[5] = chany_top_in[4];
assign chany_bottom_out[6] = chany_top_in[5];
assign chany_bottom_out[7] = chany_top_in[6];
assign chany_bottom_out[9] = chany_top_in[8];
assign chany_bottom_out[10] = chany_top_in[9];
assign chany_bottom_out[11] = chany_top_in[10];
assign chany_bottom_out[13] = chany_top_in[12];
assign chany_bottom_out[14] = chany_top_in[13];
assign chany_bottom_out[15] = chany_top_in[14];
assign chany_bottom_out[17] = chany_top_in[16];
assign chany_bottom_out[18] = chany_top_in[17];
assign chany_bottom_out[19] = chany_top_in[18];
assign chanx_right_out[19] = right_bottom_grid_pin_41_[0];
assign chany_top_out[3] = chany_bottom_in[2];
assign chany_top_out[5] = chany_bottom_in[4];
assign chany_top_out[6] = chany_bottom_in[5];
assign chany_top_out[7] = chany_bottom_in[6];
assign chany_top_out[9] = chany_bottom_in[8];
assign chany_top_out[10] = chany_bottom_in[9];
assign chany_top_out[11] = chany_bottom_in[10];
assign chany_top_out[13] = chany_bottom_in[12];
assign chany_top_out[14] = chany_bottom_in[13];
assign chany_top_out[15] = chany_bottom_in[14];
assign chany_top_out[17] = chany_bottom_in[16];
assign chany_top_out[18] = chany_bottom_in[17];
assign chany_top_out[19] = chany_bottom_in[18];
mux_tree_tapbuf_size6
mux_top_track_0
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15], chany_bottom_in[2], chany_bottom_in[12] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:2]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size6
mux_top_track_4
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], chany_bottom_in[5], chany_bottom_in[14] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:2]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size6
mux_top_track_8
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18], chany_bottom_in[6], chany_bottom_in[16] }),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:2]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size6
mux_right_track_0
(
.in({ chany_top_in[2], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[2] }),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:2]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size6
mux_bottom_track_1
(
.in({ chany_top_in[2], chany_top_in[12], chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size6_4_sram[0:2]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size6
mux_bottom_track_5
(
.in({ chany_top_in[5], chany_top_in[14], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size6_5_sram[0:2]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size6
mux_bottom_track_9
(
.in({ chany_top_in[6], chany_top_in[16], chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size6_6_sram[0:2]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:2]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size6_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_4_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_5_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_6_sram[0:2])
);
mux_tree_tapbuf_size5
mux_top_track_2
(
.in({ chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], chany_bottom_in[4], chany_bottom_in[13] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:2]),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size5
mux_top_track_16
(
.in({ chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], chany_bottom_in[8], chany_bottom_in[17] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:2]),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size5
mux_bottom_track_3
(
.in({ chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size5_2_sram[0:2]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]),
.out(chany_bottom_out[1])
);
mux_tree_tapbuf_size5
mux_bottom_track_17
(
.in({ chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size5_3_sram[0:2]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:2]),
.out(chany_bottom_out[8])
);
mux_tree_tapbuf_size5
mux_bottom_track_25
(
.in({ chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[7], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size5_4_sram[0:2]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size5_mem
mem_top_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_top_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_bottom_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_2_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_bottom_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_3_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_4_sram[0:2])
);
mux_tree_tapbuf_size4
mux_top_track_24
(
.in({ chanx_right_in[6], chanx_right_in[13], chany_bottom_in[9], chany_bottom_in[18] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:2]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size4
mux_top_track_32
(
.in({ chanx_right_in[0], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[10] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_top_track_32_undriven_sram_inv[0:2]),
.out(chany_top_out[16])
);
mux_tree_tapbuf_size4
mux_right_track_8
(
.in({ chany_top_in[7:8], right_bottom_grid_pin_34_[0], chany_bottom_in[8] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:2]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size4
mux_right_track_10
(
.in({ chany_top_in[9], chany_top_in[11], right_bottom_grid_pin_35_[0], chany_bottom_in[9] }),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_right_track_10_undriven_sram_inv[0:2]),
.out(chanx_right_out[5])
);
mux_tree_tapbuf_size4
mux_right_track_12
(
.in({ chany_top_in[10], chany_top_in[15], right_bottom_grid_pin_36_[0], chany_bottom_in[10] }),
.sram(mux_tree_tapbuf_size4_4_sram[0:2]),
.sram_inv(mux_right_track_12_undriven_sram_inv[0:2]),
.out(chanx_right_out[6])
);
mux_tree_tapbuf_size4
mux_right_track_14
(
.in({ chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_37_[0], chany_bottom_in[12] }),
.sram(mux_tree_tapbuf_size4_5_sram[0:2]),
.sram_inv(mux_right_track_14_undriven_sram_inv[0:2]),
.out(chanx_right_out[7])
);
mux_tree_tapbuf_size4
mux_right_track_24
(
.in({ chany_top_in[18], right_bottom_grid_pin_34_[0], chany_bottom_in[18:19] }),
.sram(mux_tree_tapbuf_size4_6_sram[0:2]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:2]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size4_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_top_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_4_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_5_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_6_sram[0:2])
);
mux_tree_tapbuf_size7
mux_right_track_2
(
.in({ chany_top_in[0], chany_top_in[4], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[4] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:2]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size7
mux_right_track_4
(
.in({ chany_top_in[1], chany_top_in[5], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[5] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:2]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size7
mux_right_track_6
(
.in({ chany_top_in[3], chany_top_in[6], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_right_track_6_undriven_sram_inv[0:2]),
.out(chanx_right_out[3])
);
mux_tree_tapbuf_size7_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
mux_tree_tapbuf_size3
mux_right_track_16
(
.in({ chany_top_in[13], right_bottom_grid_pin_38_[0], chany_bottom_in[13] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size3
mux_right_track_18
(
.in({ chany_top_in[14], right_bottom_grid_pin_39_[0], chany_bottom_in[14] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
.out(chanx_right_out[9])
);
mux_tree_tapbuf_size3
mux_right_track_20
(
.in({ chany_top_in[16], right_bottom_grid_pin_40_[0], chany_bottom_in[16] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_right_track_20_undriven_sram_inv[0:1]),
.out(chanx_right_out[10])
);
mux_tree_tapbuf_size3
mux_right_track_22
(
.in({ chany_top_in[17], right_bottom_grid_pin_41_[0], chany_bottom_in[17] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_right_track_22_undriven_sram_inv[0:1]),
.out(chanx_right_out[11])
);
mux_tree_tapbuf_size3
mux_bottom_track_33
(
.in({ chany_top_in[10], chanx_right_in[6], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_bottom_track_33_undriven_sram_inv[0:1]),
.out(chany_bottom_out[16])
);
mux_tree_tapbuf_size3_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_right_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_right_track_20
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_right_track_22
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
mux_tree_tapbuf_size2
mux_right_track_26
(
.in({ right_bottom_grid_pin_35_[0], chany_bottom_in[15] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_right_track_26_undriven_sram_inv[0:1]),
.out(chanx_right_out[13])
);
mux_tree_tapbuf_size2
mux_right_track_28
(
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_right_track_28_undriven_sram_inv[0:1]),
.out(chanx_right_out[14])
);
mux_tree_tapbuf_size2
mux_right_track_30
(
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[7] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_right_track_30_undriven_sram_inv[0:1]),
.out(chanx_right_out[15])
);
mux_tree_tapbuf_size2
mux_right_track_32
(
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[3] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:1]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size2
mux_right_track_34
(
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[1] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_right_track_34_undriven_sram_inv[0:1]),
.out(chanx_right_out[17])
);
mux_tree_tapbuf_size2
mux_right_track_36
(
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[0] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_right_track_36_undriven_sram_inv[0:1]),
.out(chanx_right_out[18])
);
mux_tree_tapbuf_size2_mem
mem_right_track_26
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_28
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_30
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_34
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_36
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
endmodule

598
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v
View File

@ -1,598 +0,0 @@
module sb_0__2_
( prog_clk, chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chanx_right_out, chany_bottom_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:19] chanx_right_in;
input [0:0] right_top_grid_pin_1_;
input [0:0] right_bottom_grid_pin_34_;
input [0:0] right_bottom_grid_pin_35_;
input [0:0] right_bottom_grid_pin_36_;
input [0:0] right_bottom_grid_pin_37_;
input [0:0] right_bottom_grid_pin_38_;
input [0:0] right_bottom_grid_pin_39_;
input [0:0] right_bottom_grid_pin_40_;
input [0:0] right_bottom_grid_pin_41_;
input [0:19] chany_bottom_in;
input [0:0] bottom_left_grid_pin_1_;
input [0:0] ccff_head;
output [0:19] chanx_right_out;
output [0:19] chany_bottom_out;
output [0:0] ccff_tail;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:1] mux_bottom_track_1_undriven_sram_inv;
wire [0:1] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_5_undriven_sram_inv;
wire [0:1] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_right_track_0_undriven_sram_inv;
wire [0:1] mux_right_track_10_undriven_sram_inv;
wire [0:1] mux_right_track_12_undriven_sram_inv;
wire [0:1] mux_right_track_14_undriven_sram_inv;
wire [0:1] mux_right_track_16_undriven_sram_inv;
wire [0:1] mux_right_track_18_undriven_sram_inv;
wire [0:1] mux_right_track_20_undriven_sram_inv;
wire [0:1] mux_right_track_22_undriven_sram_inv;
wire [0:1] mux_right_track_24_undriven_sram_inv;
wire [0:1] mux_right_track_26_undriven_sram_inv;
wire [0:1] mux_right_track_28_undriven_sram_inv;
wire [0:2] mux_right_track_2_undriven_sram_inv;
wire [0:1] mux_right_track_30_undriven_sram_inv;
wire [0:1] mux_right_track_32_undriven_sram_inv;
wire [0:1] mux_right_track_34_undriven_sram_inv;
wire [0:1] mux_right_track_36_undriven_sram_inv;
wire [0:1] mux_right_track_38_undriven_sram_inv;
wire [0:2] mux_right_track_4_undriven_sram_inv;
wire [0:2] mux_right_track_6_undriven_sram_inv;
wire [0:1] mux_right_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
assign chany_bottom_out[18] = chanx_right_in[0];
assign chany_bottom_out[17] = chanx_right_in[1];
assign chany_bottom_out[16] = chanx_right_in[2];
assign chany_bottom_out[15] = chanx_right_in[3];
assign chany_bottom_out[14] = chanx_right_in[4];
assign chany_bottom_out[13] = chanx_right_in[5];
assign chany_bottom_out[11] = chanx_right_in[7];
assign chany_bottom_out[10] = chanx_right_in[8];
assign chany_bottom_out[9] = chanx_right_in[9];
assign chany_bottom_out[8] = chanx_right_in[10];
assign chany_bottom_out[7] = chanx_right_in[11];
assign chany_bottom_out[6] = chanx_right_in[12];
assign chany_bottom_out[5] = chanx_right_in[13];
assign chany_bottom_out[3] = chanx_right_in[15];
assign chany_bottom_out[1] = chanx_right_in[17];
assign chany_bottom_out[19] = chanx_right_in[19];
assign SC_IN_TOP = SC_IN_BOT;
assign SC_OUT_TOP = SC_OUT_BOT;
mux_tree_tapbuf_size6
mux_right_track_0
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[18] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:2]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size6
mux_right_track_4
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[16] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:2]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size6_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size5
mux_right_track_2
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[17] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:2]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size5
mux_right_track_6
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[15] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_right_track_6_undriven_sram_inv[0:2]),
.out(chanx_right_out[3])
);
mux_tree_tapbuf_size5_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_right_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
mux_tree_tapbuf_size3
mux_right_track_8
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[14] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:1]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size3
mux_right_track_24
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:1]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size3_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size2
mux_right_track_10
(
.in({ right_bottom_grid_pin_34_[0], chany_bottom_in[13] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_right_track_10_undriven_sram_inv[0:1]),
.out(chanx_right_out[5])
);
mux_tree_tapbuf_size2
mux_right_track_12
(
.in({ right_bottom_grid_pin_35_[0], chany_bottom_in[12] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_right_track_12_undriven_sram_inv[0:1]),
.out(chanx_right_out[6])
);
mux_tree_tapbuf_size2
mux_right_track_14
(
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_right_track_14_undriven_sram_inv[0:1]),
.out(chanx_right_out[7])
);
mux_tree_tapbuf_size2
mux_right_track_16
(
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[10] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size2
mux_right_track_18
(
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[9] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
.out(chanx_right_out[9])
);
mux_tree_tapbuf_size2
mux_right_track_20
(
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[8] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_right_track_20_undriven_sram_inv[0:1]),
.out(chanx_right_out[10])
);
mux_tree_tapbuf_size2
mux_right_track_22
(
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[7] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_right_track_22_undriven_sram_inv[0:1]),
.out(chanx_right_out[11])
);
mux_tree_tapbuf_size2
mux_right_track_26
(
.in({ right_bottom_grid_pin_34_[0], chany_bottom_in[5] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_right_track_26_undriven_sram_inv[0:1]),
.out(chanx_right_out[13])
);
mux_tree_tapbuf_size2
mux_right_track_28
(
.in({ right_bottom_grid_pin_35_[0], chany_bottom_in[4] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_right_track_28_undriven_sram_inv[0:1]),
.out(chanx_right_out[14])
);
mux_tree_tapbuf_size2
mux_right_track_30
(
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[3] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_right_track_30_undriven_sram_inv[0:1]),
.out(chanx_right_out[15])
);
mux_tree_tapbuf_size2
mux_right_track_32
(
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[2] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:1]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size2
mux_right_track_34
(
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[1] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_right_track_34_undriven_sram_inv[0:1]),
.out(chanx_right_out[17])
);
mux_tree_tapbuf_size2
mux_right_track_36
(
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_right_track_36_undriven_sram_inv[0:1]),
.out(chanx_right_out[18])
);
mux_tree_tapbuf_size2
mux_right_track_38
(
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[19] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_right_track_38_undriven_sram_inv[0:1]),
.out(chanx_right_out[19])
);
mux_tree_tapbuf_size2
mux_bottom_track_1
(
.in({ chanx_right_in[18], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:1]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size2
mux_bottom_track_5
(
.in({ chanx_right_in[16], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:1]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size2
mux_bottom_track_9
(
.in({ chanx_right_in[14], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:1]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size2
mux_bottom_track_25
(
.in({ chanx_right_in[6], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:1]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size2_mem
mem_right_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_20
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_22
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_26
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_28
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_30
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_34
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_36
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_38
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1])
);
endmodule

718
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v
View File

@ -1,718 +0,0 @@
module sb_1__0_
( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, chanx_right_in, right_bottom_grid_pin_1_, right_bottom_grid_pin_3_, right_bottom_grid_pin_5_, right_bottom_grid_pin_7_, right_bottom_grid_pin_9_, right_bottom_grid_pin_11_, chanx_left_in, left_bottom_grid_pin_1_, left_bottom_grid_pin_3_, left_bottom_grid_pin_5_, left_bottom_grid_pin_7_, left_bottom_grid_pin_9_, left_bottom_grid_pin_11_, ccff_head, chany_top_out, chanx_right_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_42_;
input [0:0] top_left_grid_pin_43_;
input [0:0] top_left_grid_pin_44_;
input [0:0] top_left_grid_pin_45_;
input [0:0] top_left_grid_pin_46_;
input [0:0] top_left_grid_pin_47_;
input [0:0] top_left_grid_pin_48_;
input [0:0] top_left_grid_pin_49_;
input [0:19] chanx_right_in;
input [0:0] right_bottom_grid_pin_1_;
input [0:0] right_bottom_grid_pin_3_;
input [0:0] right_bottom_grid_pin_5_;
input [0:0] right_bottom_grid_pin_7_;
input [0:0] right_bottom_grid_pin_9_;
input [0:0] right_bottom_grid_pin_11_;
input [0:19] chanx_left_in;
input [0:0] left_bottom_grid_pin_1_;
input [0:0] left_bottom_grid_pin_3_;
input [0:0] left_bottom_grid_pin_5_;
input [0:0] left_bottom_grid_pin_7_;
input [0:0] left_bottom_grid_pin_9_;
input [0:0] left_bottom_grid_pin_11_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_right_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:2] mux_left_track_17_undriven_sram_inv;
wire [0:3] mux_left_track_1_undriven_sram_inv;
wire [0:2] mux_left_track_25_undriven_sram_inv;
wire [0:2] mux_left_track_33_undriven_sram_inv;
wire [0:2] mux_left_track_3_undriven_sram_inv;
wire [0:3] mux_left_track_5_undriven_sram_inv;
wire [0:2] mux_left_track_9_undriven_sram_inv;
wire [0:2] mux_right_track_0_undriven_sram_inv;
wire [0:2] mux_right_track_16_undriven_sram_inv;
wire [0:2] mux_right_track_24_undriven_sram_inv;
wire [0:3] mux_right_track_2_undriven_sram_inv;
wire [0:2] mux_right_track_32_undriven_sram_inv;
wire [0:3] mux_right_track_4_undriven_sram_inv;
wire [0:2] mux_right_track_8_undriven_sram_inv;
wire [0:3] mux_top_track_0_undriven_sram_inv;
wire [0:2] mux_top_track_10_undriven_sram_inv;
wire [0:1] mux_top_track_12_undriven_sram_inv;
wire [0:1] mux_top_track_14_undriven_sram_inv;
wire [0:1] mux_top_track_16_undriven_sram_inv;
wire [0:1] mux_top_track_18_undriven_sram_inv;
wire [0:1] mux_top_track_20_undriven_sram_inv;
wire [0:1] mux_top_track_22_undriven_sram_inv;
wire [0:1] mux_top_track_24_undriven_sram_inv;
wire [0:2] mux_top_track_2_undriven_sram_inv;
wire [0:1] mux_top_track_38_undriven_sram_inv;
wire [0:2] mux_top_track_4_undriven_sram_inv;
wire [0:2] mux_top_track_6_undriven_sram_inv;
wire [0:2] mux_top_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size11_0_sram;
wire [0:3] mux_tree_tapbuf_size11_1_sram;
wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_5_sram;
wire [0:1] mux_tree_tapbuf_size3_6_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_3_sram;
wire [0:2] mux_tree_tapbuf_size7_4_sram;
wire [0:2] mux_tree_tapbuf_size7_5_sram;
wire [0:2] mux_tree_tapbuf_size7_6_sram;
wire [0:2] mux_tree_tapbuf_size7_7_sram;
wire [0:2] mux_tree_tapbuf_size7_8_sram;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
assign chany_top_out[13] = top_left_grid_pin_43_[0];
assign chanx_left_out[3] = chanx_right_in[2];
assign chanx_left_out[5] = chanx_right_in[4];
assign chanx_left_out[6] = chanx_right_in[5];
assign chanx_left_out[7] = chanx_right_in[6];
assign chanx_left_out[9] = chanx_right_in[8];
assign chanx_left_out[10] = chanx_right_in[9];
assign chanx_left_out[11] = chanx_right_in[10];
assign chanx_left_out[13] = chanx_right_in[12];
assign chanx_left_out[14] = chanx_right_in[13];
assign chanx_left_out[15] = chanx_right_in[14];
assign chanx_left_out[17] = chanx_right_in[16];
assign chanx_left_out[18] = chanx_right_in[17];
assign chanx_left_out[19] = chanx_right_in[18];
assign chanx_right_out[3] = chanx_left_in[2];
assign chany_top_out[18] = chanx_left_in[3];
assign chanx_right_out[5] = chanx_left_in[4];
assign chanx_right_out[6] = chanx_left_in[5];
assign chanx_right_out[7] = chanx_left_in[6];
assign chany_top_out[17] = chanx_left_in[7];
assign chanx_right_out[9] = chanx_left_in[8];
assign chanx_right_out[10] = chanx_left_in[9];
assign chanx_right_out[11] = chanx_left_in[10];
assign chany_top_out[16] = chanx_left_in[11];
assign chanx_right_out[13] = chanx_left_in[12];
assign chanx_right_out[14] = chanx_left_in[13];
assign chanx_right_out[15] = chanx_left_in[14];
assign chany_top_out[15] = chanx_left_in[15];
assign chanx_right_out[17] = chanx_left_in[16];
assign chanx_right_out[18] = chanx_left_in[17];
assign chanx_right_out[19] = chanx_left_in[18];
assign chany_top_out[14] = chanx_left_in[19];
assign SC_IN_TOP = SC_IN_BOT;
assign SC_OUT_TOP = SC_OUT_BOT;
mux_tree_tapbuf_size8
mux_top_track_0
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[1:2], chanx_left_in[0], chanx_left_in[2] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:3]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size8
mux_right_track_2
(
.in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0], chanx_left_in[4], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:3]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size8
mux_left_track_1
(
.in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], chanx_right_in[2], chanx_right_in[12], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:3]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size8_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size7
mux_top_track_2
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[3:4], chanx_left_in[4] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:2]),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size7
mux_top_track_4
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[5], chanx_right_in[7], chanx_left_in[5] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:2]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size7
mux_top_track_6
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[6], chanx_right_in[11], chanx_left_in[6] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_top_track_6_undriven_sram_inv[0:2]),
.out(chany_top_out[3])
);
mux_tree_tapbuf_size7
mux_right_track_0
(
.in({ chany_top_in[6], chany_top_in[13], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0], chanx_left_in[2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size7_3_sram[0:2]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:2]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size7
mux_right_track_8
(
.in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_9_[0], chanx_left_in[6], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size7_4_sram[0:2]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:2]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size7
mux_right_track_16
(
.in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_11_[0], chanx_left_in[8], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size7_5_sram[0:2]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:2]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size7
mux_left_track_3
(
.in({ chany_top_in[6], chany_top_in[13], chanx_right_in[4], chanx_right_in[13], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size7_6_sram[0:2]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:2]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size7
mux_left_track_9
(
.in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], chanx_right_in[6], chanx_right_in[16], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size7_7_sram[0:2]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:2]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size7
mux_left_track_17
(
.in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size7_8_sram[0:2]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:2]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size7_mem
mem_top_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_top_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_4_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_5_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_6_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_7_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_8_sram[0:2])
);
mux_tree_tapbuf_size4
mux_top_track_8
(
.in({ top_left_grid_pin_42_[0], chanx_right_in[8], chanx_right_in[15], chanx_left_in[8] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:2]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size4
mux_top_track_10
(
.in({ top_left_grid_pin_43_[0], chanx_right_in[9], chanx_right_in[19], chanx_left_in[9] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_top_track_10_undriven_sram_inv[0:2]),
.out(chany_top_out[5])
);
mux_tree_tapbuf_size4_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_top_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
mux_tree_tapbuf_size3
mux_top_track_12
(
.in({ top_left_grid_pin_44_[0], chanx_right_in[10], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_top_track_12_undriven_sram_inv[0:1]),
.out(chany_top_out[6])
);
mux_tree_tapbuf_size3
mux_top_track_14
(
.in({ top_left_grid_pin_45_[0], chanx_right_in[12], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_top_track_14_undriven_sram_inv[0:1]),
.out(chany_top_out[7])
);
mux_tree_tapbuf_size3
mux_top_track_16
(
.in({ top_left_grid_pin_46_[0], chanx_right_in[13], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:1]),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size3
mux_top_track_18
(
.in({ top_left_grid_pin_47_[0], chanx_right_in[14], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_top_track_18_undriven_sram_inv[0:1]),
.out(chany_top_out[9])
);
mux_tree_tapbuf_size3
mux_top_track_20
(
.in({ top_left_grid_pin_48_[0], chanx_right_in[16], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_top_track_20_undriven_sram_inv[0:1]),
.out(chany_top_out[10])
);
mux_tree_tapbuf_size3
mux_top_track_22
(
.in({ top_left_grid_pin_49_[0], chanx_right_in[17], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
.sram_inv(mux_top_track_22_undriven_sram_inv[0:1]),
.out(chany_top_out[11])
);
mux_tree_tapbuf_size3
mux_top_track_24
(
.in({ top_left_grid_pin_42_[0], chanx_right_in[18], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size3_6_sram[0:1]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:1]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size3_mem
mem_top_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_20
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_22
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_6_sram[0:1])
);
mux_tree_tapbuf_size2
mux_top_track_38
(
.in({ chanx_right_in[0], chanx_left_in[1] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_top_track_38_undriven_sram_inv[0:1]),
.out(chany_top_out[19])
);
mux_tree_tapbuf_size2_mem
mem_top_track_38
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size11
mux_right_track_4
(
.in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_11_[0], chanx_left_in[5], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size11_0_sram[0:3]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:3]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size11
mux_left_track_5
(
.in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], chanx_right_in[5], chanx_right_in[14], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size11_1_sram[0:3]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:3]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size11_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size11_0_sram[0:3])
);
mux_tree_tapbuf_size11_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size11_1_sram[0:3])
);
mux_tree_tapbuf_size6
mux_right_track_24
(
.in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], right_bottom_grid_pin_5_[0], chanx_left_in[9], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:2]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size6
mux_left_track_25
(
.in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], chanx_right_in[9], chanx_right_in[18], left_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:2]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size6_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size5
mux_right_track_32
(
.in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_7_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:2]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size5
mux_left_track_33
(
.in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], chanx_right_in[10], left_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:2]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size5_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
endmodule

746
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v
View File

@ -1,746 +0,0 @@
module sb_1__1_
( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, chanx_right_in, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_top_out, chanx_right_out, chany_bottom_out, chanx_left_out, ccff_tail );
input [0:0] prog_clk;
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_42_;
input [0:0] top_left_grid_pin_43_;
input [0:0] top_left_grid_pin_44_;
input [0:0] top_left_grid_pin_45_;
input [0:0] top_left_grid_pin_46_;
input [0:0] top_left_grid_pin_47_;
input [0:0] top_left_grid_pin_48_;
input [0:0] top_left_grid_pin_49_;
input [0:19] chanx_right_in;
input [0:0] right_bottom_grid_pin_34_;
input [0:0] right_bottom_grid_pin_35_;
input [0:0] right_bottom_grid_pin_36_;
input [0:0] right_bottom_grid_pin_37_;
input [0:0] right_bottom_grid_pin_38_;
input [0:0] right_bottom_grid_pin_39_;
input [0:0] right_bottom_grid_pin_40_;
input [0:0] right_bottom_grid_pin_41_;
input [0:19] chany_bottom_in;
input [0:0] bottom_left_grid_pin_42_;
input [0:0] bottom_left_grid_pin_43_;
input [0:0] bottom_left_grid_pin_44_;
input [0:0] bottom_left_grid_pin_45_;
input [0:0] bottom_left_grid_pin_46_;
input [0:0] bottom_left_grid_pin_47_;
input [0:0] bottom_left_grid_pin_48_;
input [0:0] bottom_left_grid_pin_49_;
input [0:19] chanx_left_in;
input [0:0] left_bottom_grid_pin_34_;
input [0:0] left_bottom_grid_pin_35_;
input [0:0] left_bottom_grid_pin_36_;
input [0:0] left_bottom_grid_pin_37_;
input [0:0] left_bottom_grid_pin_38_;
input [0:0] left_bottom_grid_pin_39_;
input [0:0] left_bottom_grid_pin_40_;
input [0:0] left_bottom_grid_pin_41_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_right_out;
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
wire [0:3] mux_bottom_track_17_undriven_sram_inv;
wire [0:3] mux_bottom_track_1_undriven_sram_inv;
wire [0:3] mux_bottom_track_25_undriven_sram_inv;
wire [0:2] mux_bottom_track_33_undriven_sram_inv;
wire [0:3] mux_bottom_track_3_undriven_sram_inv;
wire [0:4] mux_bottom_track_5_undriven_sram_inv;
wire [0:3] mux_bottom_track_9_undriven_sram_inv;
wire [0:3] mux_left_track_17_undriven_sram_inv;
wire [0:3] mux_left_track_1_undriven_sram_inv;
wire [0:3] mux_left_track_25_undriven_sram_inv;
wire [0:2] mux_left_track_33_undriven_sram_inv;
wire [0:3] mux_left_track_3_undriven_sram_inv;
wire [0:4] mux_left_track_5_undriven_sram_inv;
wire [0:3] mux_left_track_9_undriven_sram_inv;
wire [0:3] mux_right_track_0_undriven_sram_inv;
wire [0:3] mux_right_track_16_undriven_sram_inv;
wire [0:3] mux_right_track_24_undriven_sram_inv;
wire [0:3] mux_right_track_2_undriven_sram_inv;
wire [0:2] mux_right_track_32_undriven_sram_inv;
wire [0:4] mux_right_track_4_undriven_sram_inv;
wire [0:3] mux_right_track_8_undriven_sram_inv;
wire [0:3] mux_top_track_0_undriven_sram_inv;
wire [0:3] mux_top_track_16_undriven_sram_inv;
wire [0:3] mux_top_track_24_undriven_sram_inv;
wire [0:3] mux_top_track_2_undriven_sram_inv;
wire [0:2] mux_top_track_32_undriven_sram_inv;
wire [0:4] mux_top_track_4_undriven_sram_inv;
wire [0:3] mux_top_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_10_sram;
wire [0:3] mux_tree_tapbuf_size10_11_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:3] mux_tree_tapbuf_size10_9_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail;
wire [0:3] mux_tree_tapbuf_size12_0_sram;
wire [0:3] mux_tree_tapbuf_size12_1_sram;
wire [0:3] mux_tree_tapbuf_size12_2_sram;
wire [0:3] mux_tree_tapbuf_size12_3_sram;
wire [0:3] mux_tree_tapbuf_size12_4_sram;
wire [0:3] mux_tree_tapbuf_size12_5_sram;
wire [0:3] mux_tree_tapbuf_size12_6_sram;
wire [0:3] mux_tree_tapbuf_size12_7_sram;
wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail;
wire [0:4] mux_tree_tapbuf_size16_0_sram;
wire [0:4] mux_tree_tapbuf_size16_1_sram;
wire [0:4] mux_tree_tapbuf_size16_2_sram;
wire [0:4] mux_tree_tapbuf_size16_3_sram;
wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_3_sram;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
assign chany_bottom_out[3] = chany_top_in[2];
assign chany_bottom_out[5] = chany_top_in[4];
assign chany_bottom_out[6] = chany_top_in[5];
assign chany_bottom_out[7] = chany_top_in[6];
assign chany_bottom_out[9] = chany_top_in[8];
assign chany_bottom_out[10] = chany_top_in[9];
assign chany_bottom_out[11] = chany_top_in[10];
assign chany_bottom_out[13] = chany_top_in[12];
assign chany_bottom_out[14] = chany_top_in[13];
assign chany_bottom_out[15] = chany_top_in[14];
assign chany_bottom_out[17] = chany_top_in[16];
assign chany_bottom_out[18] = chany_top_in[17];
assign chany_bottom_out[19] = chany_top_in[18];
assign chanx_left_out[3] = chanx_right_in[2];
assign chanx_left_out[5] = chanx_right_in[4];
assign chanx_left_out[6] = chanx_right_in[5];
assign chanx_left_out[7] = chanx_right_in[6];
assign chanx_left_out[9] = chanx_right_in[8];
assign chanx_left_out[10] = chanx_right_in[9];
assign chanx_left_out[11] = chanx_right_in[10];
assign chanx_left_out[13] = chanx_right_in[12];
assign chanx_left_out[14] = chanx_right_in[13];
assign chanx_left_out[15] = chanx_right_in[14];
assign chanx_left_out[17] = chanx_right_in[16];
assign chanx_left_out[18] = chanx_right_in[17];
assign chanx_left_out[19] = chanx_right_in[18];
assign chany_top_out[3] = chany_bottom_in[2];
assign chany_top_out[5] = chany_bottom_in[4];
assign chany_top_out[6] = chany_bottom_in[5];
assign chany_top_out[7] = chany_bottom_in[6];
assign chany_top_out[9] = chany_bottom_in[8];
assign chany_top_out[10] = chany_bottom_in[9];
assign chany_top_out[11] = chany_bottom_in[10];
assign chany_top_out[13] = chany_bottom_in[12];
assign chany_top_out[14] = chany_bottom_in[13];
assign chany_top_out[15] = chany_bottom_in[14];
assign chany_top_out[17] = chany_bottom_in[16];
assign chany_top_out[18] = chany_bottom_in[17];
assign chany_top_out[19] = chany_bottom_in[18];
assign chanx_right_out[3] = chanx_left_in[2];
assign chanx_right_out[5] = chanx_left_in[4];
assign chanx_right_out[6] = chanx_left_in[5];
assign chanx_right_out[7] = chanx_left_in[6];
assign chanx_right_out[9] = chanx_left_in[8];
assign chanx_right_out[10] = chanx_left_in[9];
assign chanx_right_out[11] = chanx_left_in[10];
assign chanx_right_out[13] = chanx_left_in[12];
assign chanx_right_out[14] = chanx_left_in[13];
assign chanx_right_out[15] = chanx_left_in[14];
assign chanx_right_out[17] = chanx_left_in[16];
assign chanx_right_out[18] = chanx_left_in[17];
assign chanx_right_out[19] = chanx_left_in[18];
mux_tree_tapbuf_size12
mux_top_track_0
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[1:2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size12_0_sram[0:3]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:3]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size12
mux_top_track_2
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[3:4], chanx_right_in[13], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size12_1_sram[0:3]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:3]),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size12
mux_right_track_0
(
.in({ chany_top_in[2], chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[15], chanx_left_in[2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size12_2_sram[0:3]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:3]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size12
mux_right_track_2
(
.in({ chany_top_in[0], chany_top_in[4], chany_top_in[13], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size12_3_sram[0:3]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:3]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size12
mux_bottom_track_1
(
.in({ chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chanx_right_in[15], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[1:2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size12_4_sram[0:3]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:3]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size12
mux_bottom_track_3
(
.in({ chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[13], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3:4], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size12_5_sram[0:3]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:3]),
.out(chany_bottom_out[1])
);
mux_tree_tapbuf_size12
mux_left_track_1
(
.in({ chany_top_in[0], chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size12_6_sram[0:3]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:3]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size12
mux_left_track_3
(
.in({ chany_top_in[4], chany_top_in[13], chany_top_in[19], chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[13], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size12_7_sram[0:3]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:3]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size12_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_0_sram[0:3])
);
mux_tree_tapbuf_size12_mem
mem_top_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_1_sram[0:3])
);
mux_tree_tapbuf_size12_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_2_sram[0:3])
);
mux_tree_tapbuf_size12_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_3_sram[0:3])
);
mux_tree_tapbuf_size12_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_4_sram[0:3])
);
mux_tree_tapbuf_size12_mem
mem_bottom_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_5_sram[0:3])
);
mux_tree_tapbuf_size12_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_6_sram[0:3])
);
mux_tree_tapbuf_size12_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_7_sram[0:3])
);
mux_tree_tapbuf_size16
mux_top_track_4
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_43_[0], top_left_grid_pin_44_[0], top_left_grid_pin_45_[0], top_left_grid_pin_46_[0], top_left_grid_pin_47_[0], top_left_grid_pin_48_[0], top_left_grid_pin_49_[0], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14:15] }),
.sram(mux_tree_tapbuf_size16_0_sram[0:4]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:4]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size16
mux_right_track_4
(
.in({ chany_top_in[1], chany_top_in[5], chany_top_in[14], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[5], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size16_1_sram[0:4]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:4]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size16
mux_bottom_track_5
(
.in({ chany_top_in[5], chany_top_in[14], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_48_[0], bottom_left_grid_pin_49_[0], chanx_left_in[5], chanx_left_in[7], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size16_2_sram[0:4]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:4]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size16
mux_left_track_5
(
.in({ chany_top_in[5], chany_top_in[14:15], chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[5], chany_bottom_in[14], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_40_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size16_3_sram[0:4]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:4]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size16_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size16_0_sram[0:4])
);
mux_tree_tapbuf_size16_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size16_1_sram[0:4])
);
mux_tree_tapbuf_size16_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size16_2_sram[0:4])
);
mux_tree_tapbuf_size16_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size16_3_sram[0:4])
);
mux_tree_tapbuf_size10
mux_top_track_8
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_46_[0], chanx_right_in[6], chanx_right_in[11], chanx_right_in[16], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:3]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size10
mux_top_track_16
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_47_[0], chanx_right_in[8], chanx_right_in[15], chanx_right_in[17], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[7:8], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:3]),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size10
mux_top_track_24
(
.in({ top_left_grid_pin_44_[0], top_left_grid_pin_48_[0], chanx_right_in[9], chanx_right_in[18:19], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[3], chanx_left_in[9], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:3]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size10
mux_right_track_8
(
.in({ chany_top_in[3], chany_top_in[6], chany_top_in[16], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_38_[0], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:3]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size10
mux_right_track_16
(
.in({ chany_top_in[7:8], chany_top_in[17], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_39_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[8], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:3]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size10
mux_right_track_24
(
.in({ chany_top_in[9], chany_top_in[11], chany_top_in[18], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[9], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:3]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size10
mux_bottom_track_9
(
.in({ chany_top_in[6], chany_top_in[16], chanx_right_in[3], chanx_right_in[6], chanx_right_in[16], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_46_[0], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:3]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size10
mux_bottom_track_17
(
.in({ chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[17], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_47_[0], chanx_left_in[8], chanx_left_in[15], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:3]),
.out(chany_bottom_out[8])
);
mux_tree_tapbuf_size10
mux_bottom_track_25
(
.in({ chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[9], chanx_right_in[18], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_48_[0], chanx_left_in[9], chanx_left_in[18:19] }),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:3]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size10
mux_left_track_9
(
.in({ chany_top_in[6], chany_top_in[11], chany_top_in[16], chanx_right_in[6], chanx_right_in[16], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size10_9_sram[0:3]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:3]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size10
mux_left_track_17
(
.in({ chany_top_in[7:8], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], chany_bottom_in[7:8], chany_bottom_in[17], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size10_10_sram[0:3]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:3]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size10
mux_left_track_25
(
.in({ chany_top_in[3], chany_top_in[9], chany_top_in[18], chanx_right_in[9], chanx_right_in[18], chany_bottom_in[9], chany_bottom_in[11], chany_bottom_in[18], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size10_11_sram[0:3]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:3]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size10_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_bottom_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_9_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_10_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_11_sram[0:3])
);
mux_tree_tapbuf_size7
mux_top_track_32
(
.in({ top_left_grid_pin_45_[0], top_left_grid_pin_49_[0], chanx_right_in[0], chanx_right_in[10], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_top_track_32_undriven_sram_inv[0:2]),
.out(chany_top_out[16])
);
mux_tree_tapbuf_size7
mux_right_track_32
(
.in({ chany_top_in[10], chany_top_in[15], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[10], chany_bottom_in[19], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:2]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size7
mux_bottom_track_33
(
.in({ chany_top_in[10], chanx_right_in[10], chanx_right_in[19], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_49_[0], chanx_left_in[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_bottom_track_33_undriven_sram_inv[0:2]),
.out(chany_bottom_out[16])
);
mux_tree_tapbuf_size7
mux_left_track_33
(
.in({ chany_top_in[1], chany_top_in[10], chanx_right_in[10], chany_bottom_in[10], chany_bottom_in[15], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size7_3_sram[0:2]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:2]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size7_mem
mem_top_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2])
);
endmodule

724
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v
View File

@ -1,724 +0,0 @@
module sb_1__2_
( prog_clk, chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chanx_right_out, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:19] chanx_right_in;
input [0:0] right_top_grid_pin_1_;
input [0:0] right_bottom_grid_pin_34_;
input [0:0] right_bottom_grid_pin_35_;
input [0:0] right_bottom_grid_pin_36_;
input [0:0] right_bottom_grid_pin_37_;
input [0:0] right_bottom_grid_pin_38_;
input [0:0] right_bottom_grid_pin_39_;
input [0:0] right_bottom_grid_pin_40_;
input [0:0] right_bottom_grid_pin_41_;
input [0:19] chany_bottom_in;
input [0:0] bottom_left_grid_pin_42_;
input [0:0] bottom_left_grid_pin_43_;
input [0:0] bottom_left_grid_pin_44_;
input [0:0] bottom_left_grid_pin_45_;
input [0:0] bottom_left_grid_pin_46_;
input [0:0] bottom_left_grid_pin_47_;
input [0:0] bottom_left_grid_pin_48_;
input [0:0] bottom_left_grid_pin_49_;
input [0:19] chanx_left_in;
input [0:0] left_top_grid_pin_1_;
input [0:0] left_bottom_grid_pin_34_;
input [0:0] left_bottom_grid_pin_35_;
input [0:0] left_bottom_grid_pin_36_;
input [0:0] left_bottom_grid_pin_37_;
input [0:0] left_bottom_grid_pin_38_;
input [0:0] left_bottom_grid_pin_39_;
input [0:0] left_bottom_grid_pin_40_;
input [0:0] left_bottom_grid_pin_41_;
input [0:0] ccff_head;
output [0:19] chanx_right_out;
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:2] mux_bottom_track_11_undriven_sram_inv;
wire [0:1] mux_bottom_track_13_undriven_sram_inv;
wire [0:1] mux_bottom_track_15_undriven_sram_inv;
wire [0:1] mux_bottom_track_17_undriven_sram_inv;
wire [0:1] mux_bottom_track_19_undriven_sram_inv;
wire [0:2] mux_bottom_track_1_undriven_sram_inv;
wire [0:1] mux_bottom_track_21_undriven_sram_inv;
wire [0:1] mux_bottom_track_23_undriven_sram_inv;
wire [0:2] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_27_undriven_sram_inv;
wire [0:2] mux_bottom_track_3_undriven_sram_inv;
wire [0:2] mux_bottom_track_5_undriven_sram_inv;
wire [0:2] mux_bottom_track_7_undriven_sram_inv;
wire [0:2] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_left_track_17_undriven_sram_inv;
wire [0:3] mux_left_track_1_undriven_sram_inv;
wire [0:2] mux_left_track_25_undriven_sram_inv;
wire [0:2] mux_left_track_33_undriven_sram_inv;
wire [0:3] mux_left_track_3_undriven_sram_inv;
wire [0:3] mux_left_track_5_undriven_sram_inv;
wire [0:3] mux_left_track_9_undriven_sram_inv;
wire [0:3] mux_right_track_0_undriven_sram_inv;
wire [0:2] mux_right_track_16_undriven_sram_inv;
wire [0:2] mux_right_track_24_undriven_sram_inv;
wire [0:3] mux_right_track_2_undriven_sram_inv;
wire [0:2] mux_right_track_32_undriven_sram_inv;
wire [0:3] mux_right_track_4_undriven_sram_inv;
wire [0:3] mux_right_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:3] mux_tree_tapbuf_size14_0_sram;
wire [0:3] mux_tree_tapbuf_size14_1_sram;
wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_5_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_3_sram;
wire [0:2] mux_tree_tapbuf_size7_4_sram;
wire [0:2] mux_tree_tapbuf_size7_5_sram;
wire [0:2] mux_tree_tapbuf_size7_6_sram;
wire [0:2] mux_tree_tapbuf_size7_7_sram;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:3] mux_tree_tapbuf_size9_0_sram;
wire [0:3] mux_tree_tapbuf_size9_1_sram;
wire [0:3] mux_tree_tapbuf_size9_2_sram;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
assign chany_bottom_out[18] = chanx_right_in[0];
assign chany_bottom_out[17] = chanx_right_in[1];
assign chanx_left_out[3] = chanx_right_in[2];
assign chany_bottom_out[16] = chanx_right_in[3];
assign chanx_left_out[5] = chanx_right_in[4];
assign chanx_left_out[6] = chanx_right_in[5];
assign chanx_left_out[7] = chanx_right_in[6];
assign chany_bottom_out[15] = chanx_right_in[7];
assign chanx_left_out[9] = chanx_right_in[8];
assign chanx_left_out[10] = chanx_right_in[9];
assign chanx_left_out[11] = chanx_right_in[10];
assign chany_bottom_out[14] = chanx_right_in[11];
assign chanx_left_out[13] = chanx_right_in[12];
assign chanx_left_out[14] = chanx_right_in[13];
assign chanx_left_out[15] = chanx_right_in[14];
assign chanx_left_out[17] = chanx_right_in[16];
assign chanx_left_out[18] = chanx_right_in[17];
assign chanx_left_out[19] = chanx_right_in[18];
assign chany_bottom_out[19] = chanx_left_in[0];
assign chanx_right_out[3] = chanx_left_in[2];
assign chanx_right_out[5] = chanx_left_in[4];
assign chanx_right_out[6] = chanx_left_in[5];
assign chanx_right_out[7] = chanx_left_in[6];
assign chanx_right_out[9] = chanx_left_in[8];
assign chanx_right_out[10] = chanx_left_in[9];
assign chanx_right_out[11] = chanx_left_in[10];
assign chanx_right_out[13] = chanx_left_in[12];
assign chanx_right_out[14] = chanx_left_in[13];
assign chanx_right_out[15] = chanx_left_in[14];
assign chanx_right_out[17] = chanx_left_in[16];
assign chanx_right_out[18] = chanx_left_in[17];
assign chanx_right_out[19] = chanx_left_in[18];
assign SC_IN_TOP = SC_IN_BOT;
assign SC_OUT_TOP = SC_OUT_BOT;
mux_tree_tapbuf_size10
mux_right_track_0
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], chanx_left_in[2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:3]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size10_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size9
mux_right_track_2
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], chanx_left_in[4], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size9_0_sram[0:3]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:3]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size9
mux_left_track_1
(
.in({ chanx_right_in[2], chanx_right_in[12], chany_bottom_in[6], chany_bottom_in[13], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size9_1_sram[0:3]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:3]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size9
mux_left_track_3
(
.in({ chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size9_2_sram[0:3]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:3]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size9_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3])
);
mux_tree_tapbuf_size9_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_1_sram[0:3])
);
mux_tree_tapbuf_size9_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_2_sram[0:3])
);
mux_tree_tapbuf_size14
mux_right_track_4
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], chanx_left_in[5], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size14_0_sram[0:3]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:3]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size14
mux_left_track_5
(
.in({ chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], left_top_grid_pin_1_[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_40_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size14_1_sram[0:3]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:3]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size14_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_0_sram[0:3])
);
mux_tree_tapbuf_size14_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_1_sram[0:3])
);
mux_tree_tapbuf_size8
mux_right_track_8
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:3]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size8
mux_left_track_9
(
.in({ chanx_right_in[6], chanx_right_in[16], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], left_top_grid_pin_1_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:3]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size8_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size7
mux_right_track_16
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_38_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], chanx_left_in[8], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:2]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size7
mux_right_track_24
(
.in({ right_bottom_grid_pin_35_[0], right_bottom_grid_pin_39_[0], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[9], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:2]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size7
mux_bottom_track_1
(
.in({ chanx_right_in[2], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[1:2] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size7
mux_bottom_track_3
(
.in({ chanx_right_in[4], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3:4] }),
.sram(mux_tree_tapbuf_size7_3_sram[0:2]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]),
.out(chany_bottom_out[1])
);
mux_tree_tapbuf_size7
mux_bottom_track_5
(
.in({ chanx_right_in[5], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[5], chanx_left_in[7] }),
.sram(mux_tree_tapbuf_size7_4_sram[0:2]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size7
mux_bottom_track_7
(
.in({ chanx_right_in[6], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[6], chanx_left_in[11] }),
.sram(mux_tree_tapbuf_size7_5_sram[0:2]),
.sram_inv(mux_bottom_track_7_undriven_sram_inv[0:2]),
.out(chany_bottom_out[3])
);
mux_tree_tapbuf_size7
mux_left_track_17
(
.in({ chanx_right_in[8], chanx_right_in[17], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size7_6_sram[0:2]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:2]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size7
mux_left_track_25
(
.in({ chanx_right_in[9], chanx_right_in[18], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size7_7_sram[0:2]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:2]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size7_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_4_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_5_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_6_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_7_sram[0:2])
);
mux_tree_tapbuf_size5
mux_right_track_32
(
.in({ right_bottom_grid_pin_36_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[6], chany_bottom_in[13], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:2]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size5_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size4
mux_bottom_track_9
(
.in({ chanx_right_in[8], bottom_left_grid_pin_42_[0], chanx_left_in[8], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:2]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size4
mux_bottom_track_11
(
.in({ chanx_right_in[9], bottom_left_grid_pin_43_[0], chanx_left_in[9], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_bottom_track_11_undriven_sram_inv[0:2]),
.out(chany_bottom_out[5])
);
mux_tree_tapbuf_size4
mux_bottom_track_25
(
.in({ chanx_right_in[18:19], bottom_left_grid_pin_42_[0], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size4_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_bottom_track_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
mux_tree_tapbuf_size3
mux_bottom_track_13
(
.in({ chanx_right_in[10], bottom_left_grid_pin_44_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]),
.out(chany_bottom_out[6])
);
mux_tree_tapbuf_size3
mux_bottom_track_15
(
.in({ chanx_right_in[12], bottom_left_grid_pin_45_[0], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]),
.out(chany_bottom_out[7])
);
mux_tree_tapbuf_size3
mux_bottom_track_17
(
.in({ chanx_right_in[13], bottom_left_grid_pin_46_[0], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]),
.out(chany_bottom_out[8])
);
mux_tree_tapbuf_size3
mux_bottom_track_19
(
.in({ chanx_right_in[14], bottom_left_grid_pin_47_[0], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]),
.out(chany_bottom_out[9])
);
mux_tree_tapbuf_size3
mux_bottom_track_21
(
.in({ chanx_right_in[16], bottom_left_grid_pin_48_[0], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]),
.out(chany_bottom_out[10])
);
mux_tree_tapbuf_size3
mux_bottom_track_23
(
.in({ chanx_right_in[17], bottom_left_grid_pin_49_[0], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
.sram_inv(mux_bottom_track_23_undriven_sram_inv[0:1]),
.out(chany_bottom_out[11])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_19
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_21
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_23
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1])
);
mux_tree_tapbuf_size2
mux_bottom_track_27
(
.in({ chanx_right_in[15], bottom_left_grid_pin_43_[0] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_bottom_track_27_undriven_sram_inv[0:1]),
.out(chany_bottom_out[13])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_27
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size6
mux_left_track_33
(
.in({ chanx_right_in[10], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:2]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size6_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
endmodule

729
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v
View File

@ -1,729 +0,0 @@
module sb_2__0_
( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, top_right_grid_pin_1_, chanx_left_in, left_bottom_grid_pin_1_, left_bottom_grid_pin_3_, left_bottom_grid_pin_5_, left_bottom_grid_pin_7_, left_bottom_grid_pin_9_, left_bottom_grid_pin_11_, ccff_head, chany_top_out, chanx_left_out, ccff_tail );
input [0:0] prog_clk;
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_42_;
input [0:0] top_left_grid_pin_43_;
input [0:0] top_left_grid_pin_44_;
input [0:0] top_left_grid_pin_45_;
input [0:0] top_left_grid_pin_46_;
input [0:0] top_left_grid_pin_47_;
input [0:0] top_left_grid_pin_48_;
input [0:0] top_left_grid_pin_49_;
input [0:0] top_right_grid_pin_1_;
input [0:19] chanx_left_in;
input [0:0] left_bottom_grid_pin_1_;
input [0:0] left_bottom_grid_pin_3_;
input [0:0] left_bottom_grid_pin_5_;
input [0:0] left_bottom_grid_pin_7_;
input [0:0] left_bottom_grid_pin_9_;
input [0:0] left_bottom_grid_pin_11_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
wire [0:1] mux_left_track_11_undriven_sram_inv;
wire [0:1] mux_left_track_13_undriven_sram_inv;
wire [0:1] mux_left_track_15_undriven_sram_inv;
wire [0:1] mux_left_track_17_undriven_sram_inv;
wire [0:1] mux_left_track_19_undriven_sram_inv;
wire [0:2] mux_left_track_1_undriven_sram_inv;
wire [0:1] mux_left_track_25_undriven_sram_inv;
wire [0:1] mux_left_track_27_undriven_sram_inv;
wire [0:1] mux_left_track_29_undriven_sram_inv;
wire [0:1] mux_left_track_31_undriven_sram_inv;
wire [0:1] mux_left_track_33_undriven_sram_inv;
wire [0:1] mux_left_track_35_undriven_sram_inv;
wire [0:2] mux_left_track_3_undriven_sram_inv;
wire [0:2] mux_left_track_5_undriven_sram_inv;
wire [0:2] mux_left_track_7_undriven_sram_inv;
wire [0:1] mux_left_track_9_undriven_sram_inv;
wire [0:2] mux_top_track_0_undriven_sram_inv;
wire [0:1] mux_top_track_10_undriven_sram_inv;
wire [0:1] mux_top_track_12_undriven_sram_inv;
wire [0:1] mux_top_track_14_undriven_sram_inv;
wire [0:1] mux_top_track_16_undriven_sram_inv;
wire [0:1] mux_top_track_18_undriven_sram_inv;
wire [0:1] mux_top_track_20_undriven_sram_inv;
wire [0:1] mux_top_track_22_undriven_sram_inv;
wire [0:1] mux_top_track_24_undriven_sram_inv;
wire [0:1] mux_top_track_26_undriven_sram_inv;
wire [0:2] mux_top_track_2_undriven_sram_inv;
wire [0:2] mux_top_track_4_undriven_sram_inv;
wire [0:2] mux_top_track_6_undriven_sram_inv;
wire [0:1] mux_top_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_18_sram;
wire [0:1] mux_tree_tapbuf_size2_19_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
assign chanx_left_out[19] = chany_top_in[1];
assign chanx_left_out[18] = chany_top_in[2];
assign chanx_left_out[11] = chany_top_in[9];
assign chanx_left_out[10] = chany_top_in[10];
assign chany_top_out[19] = chanx_left_in[1];
assign chany_top_out[18] = chanx_left_in[2];
assign chany_top_out[17] = chanx_left_in[3];
assign chany_top_out[16] = chanx_left_in[4];
assign chany_top_out[15] = chanx_left_in[5];
assign chany_top_out[14] = chanx_left_in[6];
mux_tree_tapbuf_size6
mux_top_track_0
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[0] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:2]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size6
mux_top_track_4
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:2]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size6_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size5
mux_top_track_2
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:2]),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size5
mux_top_track_6
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_top_track_6_undriven_sram_inv[0:2]),
.out(chany_top_out[3])
);
mux_tree_tapbuf_size5_mem
mem_top_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_top_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
mux_tree_tapbuf_size3
mux_top_track_8
(
.in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:1]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size3
mux_top_track_24
(
.in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[8] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:1]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size3_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size2
mux_top_track_10
(
.in({ top_left_grid_pin_43_[0], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_top_track_10_undriven_sram_inv[0:1]),
.out(chany_top_out[5])
);
mux_tree_tapbuf_size2
mux_top_track_12
(
.in({ top_left_grid_pin_44_[0], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_top_track_12_undriven_sram_inv[0:1]),
.out(chany_top_out[6])
);
mux_tree_tapbuf_size2
mux_top_track_14
(
.in({ top_left_grid_pin_45_[0], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_top_track_14_undriven_sram_inv[0:1]),
.out(chany_top_out[7])
);
mux_tree_tapbuf_size2
mux_top_track_16
(
.in({ top_left_grid_pin_46_[0], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:1]),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size2
mux_top_track_18
(
.in({ top_left_grid_pin_47_[0], chanx_left_in[11] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_top_track_18_undriven_sram_inv[0:1]),
.out(chany_top_out[9])
);
mux_tree_tapbuf_size2
mux_top_track_20
(
.in({ top_left_grid_pin_48_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_top_track_20_undriven_sram_inv[0:1]),
.out(chany_top_out[10])
);
mux_tree_tapbuf_size2
mux_top_track_22
(
.in({ top_left_grid_pin_49_[0], chanx_left_in[9] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_top_track_22_undriven_sram_inv[0:1]),
.out(chany_top_out[11])
);
mux_tree_tapbuf_size2
mux_top_track_26
(
.in({ top_left_grid_pin_43_[0], chanx_left_in[7] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_top_track_26_undriven_sram_inv[0:1]),
.out(chany_top_out[13])
);
mux_tree_tapbuf_size2
mux_left_track_9
(
.in({ chany_top_in[16], left_bottom_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:1]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size2
mux_left_track_11
(
.in({ chany_top_in[15], left_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_left_track_11_undriven_sram_inv[0:1]),
.out(chanx_left_out[5])
);
mux_tree_tapbuf_size2
mux_left_track_13
(
.in({ chany_top_in[14], left_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_left_track_13_undriven_sram_inv[0:1]),
.out(chanx_left_out[6])
);
mux_tree_tapbuf_size2
mux_left_track_15
(
.in({ chany_top_in[13], left_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_left_track_15_undriven_sram_inv[0:1]),
.out(chanx_left_out[7])
);
mux_tree_tapbuf_size2
mux_left_track_17
(
.in({ chany_top_in[12], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:1]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size2
mux_left_track_19
(
.in({ chany_top_in[11], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_left_track_19_undriven_sram_inv[0:1]),
.out(chanx_left_out[9])
);
mux_tree_tapbuf_size2
mux_left_track_25
(
.in({ chany_top_in[8], left_bottom_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:1]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size2
mux_left_track_27
(
.in({ chany_top_in[7], left_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_left_track_27_undriven_sram_inv[0:1]),
.out(chanx_left_out[13])
);
mux_tree_tapbuf_size2
mux_left_track_29
(
.in({ chany_top_in[6], left_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_left_track_29_undriven_sram_inv[0:1]),
.out(chanx_left_out[14])
);
mux_tree_tapbuf_size2
mux_left_track_31
(
.in({ chany_top_in[5], left_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_left_track_31_undriven_sram_inv[0:1]),
.out(chanx_left_out[15])
);
mux_tree_tapbuf_size2
mux_left_track_33
(
.in({ chany_top_in[4], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_18_sram[0:1]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:1]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size2
mux_left_track_35
(
.in({ chany_top_in[3], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_19_sram[0:1]),
.sram_inv(mux_left_track_35_undriven_sram_inv[0:1]),
.out(chanx_left_out[17])
);
mux_tree_tapbuf_size2_mem
mem_top_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_20
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_22
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_26
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_19
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_27
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_29
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_31
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_18_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_35
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_19_sram[0:1])
);
mux_tree_tapbuf_size4
mux_left_track_1
(
.in({ chany_top_in[0], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:2]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size4
mux_left_track_3
(
.in({ chany_top_in[19], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:2]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size4
mux_left_track_5
(
.in({ chany_top_in[18], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:2]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size4
mux_left_track_7
(
.in({ chany_top_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_left_track_7_undriven_sram_inv[0:2]),
.out(chanx_left_out[3])
);
mux_tree_tapbuf_size4_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_left_track_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2])
);
endmodule

828
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v
View File

@ -1,828 +0,0 @@
module sb_2__1_
( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, top_right_grid_pin_1_, chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_top_out, chany_bottom_out, chanx_left_out, ccff_tail );
input [0:0] prog_clk;
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_42_;
input [0:0] top_left_grid_pin_43_;
input [0:0] top_left_grid_pin_44_;
input [0:0] top_left_grid_pin_45_;
input [0:0] top_left_grid_pin_46_;
input [0:0] top_left_grid_pin_47_;
input [0:0] top_left_grid_pin_48_;
input [0:0] top_left_grid_pin_49_;
input [0:0] top_right_grid_pin_1_;
input [0:19] chany_bottom_in;
input [0:0] bottom_right_grid_pin_1_;
input [0:0] bottom_left_grid_pin_42_;
input [0:0] bottom_left_grid_pin_43_;
input [0:0] bottom_left_grid_pin_44_;
input [0:0] bottom_left_grid_pin_45_;
input [0:0] bottom_left_grid_pin_46_;
input [0:0] bottom_left_grid_pin_47_;
input [0:0] bottom_left_grid_pin_48_;
input [0:0] bottom_left_grid_pin_49_;
input [0:19] chanx_left_in;
input [0:0] left_bottom_grid_pin_34_;
input [0:0] left_bottom_grid_pin_35_;
input [0:0] left_bottom_grid_pin_36_;
input [0:0] left_bottom_grid_pin_37_;
input [0:0] left_bottom_grid_pin_38_;
input [0:0] left_bottom_grid_pin_39_;
input [0:0] left_bottom_grid_pin_40_;
input [0:0] left_bottom_grid_pin_41_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
wire [0:2] mux_bottom_track_17_undriven_sram_inv;
wire [0:3] mux_bottom_track_1_undriven_sram_inv;
wire [0:2] mux_bottom_track_25_undriven_sram_inv;
wire [0:2] mux_bottom_track_33_undriven_sram_inv;
wire [0:3] mux_bottom_track_3_undriven_sram_inv;
wire [0:3] mux_bottom_track_5_undriven_sram_inv;
wire [0:3] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_left_track_11_undriven_sram_inv;
wire [0:2] mux_left_track_13_undriven_sram_inv;
wire [0:2] mux_left_track_15_undriven_sram_inv;
wire [0:1] mux_left_track_17_undriven_sram_inv;
wire [0:1] mux_left_track_19_undriven_sram_inv;
wire [0:2] mux_left_track_1_undriven_sram_inv;
wire [0:1] mux_left_track_21_undriven_sram_inv;
wire [0:1] mux_left_track_23_undriven_sram_inv;
wire [0:1] mux_left_track_25_undriven_sram_inv;
wire [0:1] mux_left_track_29_undriven_sram_inv;
wire [0:1] mux_left_track_31_undriven_sram_inv;
wire [0:1] mux_left_track_33_undriven_sram_inv;
wire [0:1] mux_left_track_35_undriven_sram_inv;
wire [0:1] mux_left_track_37_undriven_sram_inv;
wire [0:1] mux_left_track_39_undriven_sram_inv;
wire [0:2] mux_left_track_3_undriven_sram_inv;
wire [0:2] mux_left_track_5_undriven_sram_inv;
wire [0:2] mux_left_track_7_undriven_sram_inv;
wire [0:2] mux_left_track_9_undriven_sram_inv;
wire [0:3] mux_top_track_0_undriven_sram_inv;
wire [0:2] mux_top_track_16_undriven_sram_inv;
wire [0:2] mux_top_track_24_undriven_sram_inv;
wire [0:3] mux_top_track_2_undriven_sram_inv;
wire [0:2] mux_top_track_32_undriven_sram_inv;
wire [0:3] mux_top_track_4_undriven_sram_inv;
wire [0:3] mux_top_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:3] mux_tree_tapbuf_size14_0_sram;
wire [0:3] mux_tree_tapbuf_size14_1_sram;
wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_3_sram;
wire [0:2] mux_tree_tapbuf_size7_4_sram;
wire [0:2] mux_tree_tapbuf_size7_5_sram;
wire [0:2] mux_tree_tapbuf_size7_6_sram;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:3] mux_tree_tapbuf_size9_0_sram;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail;
assign chany_bottom_out[3] = chany_top_in[2];
assign chany_bottom_out[5] = chany_top_in[4];
assign chany_bottom_out[6] = chany_top_in[5];
assign chany_bottom_out[7] = chany_top_in[6];
assign chany_bottom_out[9] = chany_top_in[8];
assign chany_bottom_out[10] = chany_top_in[9];
assign chany_bottom_out[11] = chany_top_in[10];
assign chany_bottom_out[13] = chany_top_in[12];
assign chany_bottom_out[14] = chany_top_in[13];
assign chany_bottom_out[15] = chany_top_in[14];
assign chany_bottom_out[17] = chany_top_in[16];
assign chany_bottom_out[18] = chany_top_in[17];
assign chany_bottom_out[19] = chany_top_in[18];
assign chany_top_out[3] = chany_bottom_in[2];
assign chany_top_out[5] = chany_bottom_in[4];
assign chany_top_out[6] = chany_bottom_in[5];
assign chany_top_out[7] = chany_bottom_in[6];
assign chany_top_out[9] = chany_bottom_in[8];
assign chany_top_out[10] = chany_bottom_in[9];
assign chany_top_out[11] = chany_bottom_in[10];
assign chany_top_out[13] = chany_bottom_in[12];
assign chany_top_out[14] = chany_bottom_in[13];
assign chany_top_out[15] = chany_bottom_in[14];
assign chany_top_out[17] = chany_bottom_in[16];
assign chany_top_out[18] = chany_bottom_in[17];
assign chany_top_out[19] = chany_bottom_in[18];
assign chanx_left_out[13] = left_bottom_grid_pin_35_[0];
mux_tree_tapbuf_size10
mux_top_track_0
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:3]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size10
mux_bottom_track_1
(
.in({ chany_top_in[2], chany_top_in[12], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:3]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size10_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size8
mux_top_track_2
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[6], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:3]),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size8
mux_top_track_8
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_46_[0], top_right_grid_pin_1_[0], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:3]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size8
mux_bottom_track_9
(
.in({ chany_top_in[6], chany_top_in[16], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_49_[0], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:3]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size8_mem
mem_top_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size14
mux_top_track_4
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_43_[0], top_left_grid_pin_44_[0], top_left_grid_pin_45_[0], top_left_grid_pin_46_[0], top_left_grid_pin_47_[0], top_left_grid_pin_48_[0], top_left_grid_pin_49_[0], top_right_grid_pin_1_[0], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size14_0_sram[0:3]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:3]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size14
mux_bottom_track_5
(
.in({ chany_top_in[5], chany_top_in[14], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_48_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size14_1_sram[0:3]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:3]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size14_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_0_sram[0:3])
);
mux_tree_tapbuf_size14_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_1_sram[0:3])
);
mux_tree_tapbuf_size7
mux_top_track_16
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_47_[0], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:2]),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size7
mux_top_track_24
(
.in({ top_left_grid_pin_44_[0], top_left_grid_pin_48_[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:2]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size7
mux_bottom_track_17
(
.in({ chany_top_in[8], chany_top_in[17], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_46_[0], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:2]),
.out(chany_bottom_out[8])
);
mux_tree_tapbuf_size7
mux_left_track_1
(
.in({ chany_top_in[0], chany_top_in[2], chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size7_3_sram[0:2]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:2]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size7
mux_left_track_3
(
.in({ chany_top_in[4], chany_bottom_in[0], chany_bottom_in[4], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size7_4_sram[0:2]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:2]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size7
mux_left_track_5
(
.in({ chany_top_in[5], chany_bottom_in[1], chany_bottom_in[5], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size7_5_sram[0:2]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:2]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size7
mux_left_track_7
(
.in({ chany_top_in[6], chany_bottom_in[3], chany_bottom_in[6], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size7_6_sram[0:2]),
.sram_inv(mux_left_track_7_undriven_sram_inv[0:2]),
.out(chanx_left_out[3])
);
mux_tree_tapbuf_size7_mem
mem_top_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_4_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_5_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_6_sram[0:2])
);
mux_tree_tapbuf_size6
mux_top_track_32
(
.in({ top_left_grid_pin_45_[0], top_left_grid_pin_49_[0], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_top_track_32_undriven_sram_inv[0:2]),
.out(chany_top_out[16])
);
mux_tree_tapbuf_size6
mux_bottom_track_25
(
.in({ chany_top_in[9], chany_top_in[18], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_47_[0], chanx_left_in[6], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size6
mux_bottom_track_33
(
.in({ chany_top_in[10], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_48_[0], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_bottom_track_33_undriven_sram_inv[0:2]),
.out(chany_bottom_out[16])
);
mux_tree_tapbuf_size6_mem
mem_top_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2])
);
mux_tree_tapbuf_size9
mux_bottom_track_3
(
.in({ chany_top_in[4], chany_top_in[13], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size9_0_sram[0:3]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:3]),
.out(chany_bottom_out[1])
);
mux_tree_tapbuf_size9_mem
mem_bottom_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3])
);
mux_tree_tapbuf_size4
mux_left_track_9
(
.in({ chany_top_in[8], chany_bottom_in[7:8], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:2]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size4
mux_left_track_11
(
.in({ chany_top_in[9], chany_bottom_in[9], chany_bottom_in[11], left_bottom_grid_pin_35_[0] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_left_track_11_undriven_sram_inv[0:2]),
.out(chanx_left_out[5])
);
mux_tree_tapbuf_size4
mux_left_track_13
(
.in({ chany_top_in[10], chany_bottom_in[10], chany_bottom_in[15], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_left_track_13_undriven_sram_inv[0:2]),
.out(chanx_left_out[6])
);
mux_tree_tapbuf_size4
mux_left_track_15
(
.in({ chany_top_in[12], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_left_track_15_undriven_sram_inv[0:2]),
.out(chanx_left_out[7])
);
mux_tree_tapbuf_size4_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_left_track_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_left_track_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_left_track_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2])
);
mux_tree_tapbuf_size3
mux_left_track_17
(
.in({ chany_top_in[13], chany_bottom_in[13], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:1]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size3
mux_left_track_19
(
.in({ chany_top_in[14], chany_bottom_in[14], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_left_track_19_undriven_sram_inv[0:1]),
.out(chanx_left_out[9])
);
mux_tree_tapbuf_size3
mux_left_track_21
(
.in({ chany_top_in[16], chany_bottom_in[16], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_left_track_21_undriven_sram_inv[0:1]),
.out(chanx_left_out[10])
);
mux_tree_tapbuf_size3
mux_left_track_23
(
.in({ chany_top_in[17], chany_bottom_in[17], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_left_track_23_undriven_sram_inv[0:1]),
.out(chanx_left_out[11])
);
mux_tree_tapbuf_size3
mux_left_track_25
(
.in({ chany_top_in[18], chany_bottom_in[18], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:1]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size3_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_19
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_21
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_23
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
mux_tree_tapbuf_size2
mux_left_track_29
(
.in({ chany_top_in[19], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_left_track_29_undriven_sram_inv[0:1]),
.out(chanx_left_out[14])
);
mux_tree_tapbuf_size2
mux_left_track_31
(
.in({ chany_top_in[15], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_left_track_31_undriven_sram_inv[0:1]),
.out(chanx_left_out[15])
);
mux_tree_tapbuf_size2
mux_left_track_33
(
.in({ chany_top_in[11], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:1]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size2
mux_left_track_35
(
.in({ chany_top_in[7], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_left_track_35_undriven_sram_inv[0:1]),
.out(chanx_left_out[17])
);
mux_tree_tapbuf_size2
mux_left_track_37
(
.in({ chany_top_in[3], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_left_track_37_undriven_sram_inv[0:1]),
.out(chanx_left_out[18])
);
mux_tree_tapbuf_size2
mux_left_track_39
(
.in({ chany_top_in[1], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_left_track_39_undriven_sram_inv[0:1]),
.out(chanx_left_out[19])
);
mux_tree_tapbuf_size2_mem
mem_left_track_29
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_31
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_35
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_37
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_39
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
endmodule

848
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v
View File

@ -1,848 +0,0 @@
module sb_2__2_
( prog_clk, chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:19] chany_bottom_in;
input [0:0] bottom_right_grid_pin_1_;
input [0:0] bottom_left_grid_pin_42_;
input [0:0] bottom_left_grid_pin_43_;
input [0:0] bottom_left_grid_pin_44_;
input [0:0] bottom_left_grid_pin_45_;
input [0:0] bottom_left_grid_pin_46_;
input [0:0] bottom_left_grid_pin_47_;
input [0:0] bottom_left_grid_pin_48_;
input [0:0] bottom_left_grid_pin_49_;
input [0:19] chanx_left_in;
input [0:0] left_top_grid_pin_1_;
input [0:0] left_bottom_grid_pin_34_;
input [0:0] left_bottom_grid_pin_35_;
input [0:0] left_bottom_grid_pin_36_;
input [0:0] left_bottom_grid_pin_37_;
input [0:0] left_bottom_grid_pin_38_;
input [0:0] left_bottom_grid_pin_39_;
input [0:0] left_bottom_grid_pin_40_;
input [0:0] left_bottom_grid_pin_41_;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:1] mux_bottom_track_11_undriven_sram_inv;
wire [0:1] mux_bottom_track_13_undriven_sram_inv;
wire [0:1] mux_bottom_track_15_undriven_sram_inv;
wire [0:1] mux_bottom_track_17_undriven_sram_inv;
wire [0:1] mux_bottom_track_19_undriven_sram_inv;
wire [0:2] mux_bottom_track_1_undriven_sram_inv;
wire [0:1] mux_bottom_track_21_undriven_sram_inv;
wire [0:1] mux_bottom_track_23_undriven_sram_inv;
wire [0:1] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_27_undriven_sram_inv;
wire [0:1] mux_bottom_track_29_undriven_sram_inv;
wire [0:2] mux_bottom_track_3_undriven_sram_inv;
wire [0:2] mux_bottom_track_5_undriven_sram_inv;
wire [0:2] mux_bottom_track_7_undriven_sram_inv;
wire [0:1] mux_bottom_track_9_undriven_sram_inv;
wire [0:1] mux_left_track_11_undriven_sram_inv;
wire [0:1] mux_left_track_13_undriven_sram_inv;
wire [0:1] mux_left_track_15_undriven_sram_inv;
wire [0:1] mux_left_track_17_undriven_sram_inv;
wire [0:1] mux_left_track_19_undriven_sram_inv;
wire [0:2] mux_left_track_1_undriven_sram_inv;
wire [0:1] mux_left_track_21_undriven_sram_inv;
wire [0:1] mux_left_track_23_undriven_sram_inv;
wire [0:1] mux_left_track_25_undriven_sram_inv;
wire [0:1] mux_left_track_27_undriven_sram_inv;
wire [0:1] mux_left_track_29_undriven_sram_inv;
wire [0:1] mux_left_track_31_undriven_sram_inv;
wire [0:1] mux_left_track_33_undriven_sram_inv;
wire [0:1] mux_left_track_35_undriven_sram_inv;
wire [0:1] mux_left_track_37_undriven_sram_inv;
wire [0:1] mux_left_track_39_undriven_sram_inv;
wire [0:2] mux_left_track_3_undriven_sram_inv;
wire [0:2] mux_left_track_5_undriven_sram_inv;
wire [0:2] mux_left_track_7_undriven_sram_inv;
wire [0:1] mux_left_track_9_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_18_sram;
wire [0:1] mux_tree_tapbuf_size2_19_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_20_sram;
wire [0:1] mux_tree_tapbuf_size2_21_sram;
wire [0:1] mux_tree_tapbuf_size2_22_sram;
wire [0:1] mux_tree_tapbuf_size2_23_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:2] mux_tree_tapbuf_size5_2_sram;
wire [0:2] mux_tree_tapbuf_size5_3_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
assign chany_bottom_out[19] = chanx_left_in[0];
assign chany_bottom_out[15] = chanx_left_in[16];
assign chany_bottom_out[16] = chanx_left_in[17];
assign chany_bottom_out[17] = chanx_left_in[18];
assign chany_bottom_out[18] = chanx_left_in[19];
assign SC_IN_TOP = SC_IN_BOT;
assign SC_OUT_TOP = SC_OUT_BOT;
mux_tree_tapbuf_size6
mux_bottom_track_1
(
.in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size6
mux_bottom_track_5
(
.in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size6
mux_left_track_1
(
.in({ chany_bottom_in[19], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:2]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size6
mux_left_track_5
(
.in({ chany_bottom_in[1], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:2]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2])
);
mux_tree_tapbuf_size5
mux_bottom_track_3
(
.in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]),
.out(chany_bottom_out[1])
);
mux_tree_tapbuf_size5
mux_bottom_track_7
(
.in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[4] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_bottom_track_7_undriven_sram_inv[0:2]),
.out(chany_bottom_out[3])
);
mux_tree_tapbuf_size5
mux_left_track_3
(
.in({ chany_bottom_in[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size5_2_sram[0:2]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:2]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size5
mux_left_track_7
(
.in({ chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size5_3_sram[0:2]),
.sram_inv(mux_left_track_7_undriven_sram_inv[0:2]),
.out(chanx_left_out[3])
);
mux_tree_tapbuf_size5_mem
mem_bottom_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_bottom_track_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_2_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_left_track_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_3_sram[0:2])
);
mux_tree_tapbuf_size2
mux_bottom_track_9
(
.in({ bottom_right_grid_pin_1_[0], chanx_left_in[5] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:1]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size2
mux_bottom_track_11
(
.in({ bottom_left_grid_pin_42_[0], chanx_left_in[6] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_bottom_track_11_undriven_sram_inv[0:1]),
.out(chany_bottom_out[5])
);
mux_tree_tapbuf_size2
mux_bottom_track_13
(
.in({ bottom_left_grid_pin_43_[0], chanx_left_in[7] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]),
.out(chany_bottom_out[6])
);
mux_tree_tapbuf_size2
mux_bottom_track_15
(
.in({ bottom_left_grid_pin_44_[0], chanx_left_in[8] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]),
.out(chany_bottom_out[7])
);
mux_tree_tapbuf_size2
mux_bottom_track_17
(
.in({ bottom_left_grid_pin_45_[0], chanx_left_in[9] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]),
.out(chany_bottom_out[8])
);
mux_tree_tapbuf_size2
mux_bottom_track_19
(
.in({ bottom_left_grid_pin_46_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]),
.out(chany_bottom_out[9])
);
mux_tree_tapbuf_size2
mux_bottom_track_21
(
.in({ bottom_left_grid_pin_47_[0], chanx_left_in[11] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]),
.out(chany_bottom_out[10])
);
mux_tree_tapbuf_size2
mux_bottom_track_23
(
.in({ bottom_left_grid_pin_48_[0], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_bottom_track_23_undriven_sram_inv[0:1]),
.out(chany_bottom_out[11])
);
mux_tree_tapbuf_size2
mux_bottom_track_27
(
.in({ bottom_left_grid_pin_42_[0], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_bottom_track_27_undriven_sram_inv[0:1]),
.out(chany_bottom_out[13])
);
mux_tree_tapbuf_size2
mux_bottom_track_29
(
.in({ bottom_left_grid_pin_43_[0], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_bottom_track_29_undriven_sram_inv[0:1]),
.out(chany_bottom_out[14])
);
mux_tree_tapbuf_size2
mux_left_track_11
(
.in({ chany_bottom_in[4], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_left_track_11_undriven_sram_inv[0:1]),
.out(chanx_left_out[5])
);
mux_tree_tapbuf_size2
mux_left_track_13
(
.in({ chany_bottom_in[5], left_bottom_grid_pin_35_[0] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_left_track_13_undriven_sram_inv[0:1]),
.out(chanx_left_out[6])
);
mux_tree_tapbuf_size2
mux_left_track_15
(
.in({ chany_bottom_in[6], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_left_track_15_undriven_sram_inv[0:1]),
.out(chanx_left_out[7])
);
mux_tree_tapbuf_size2
mux_left_track_17
(
.in({ chany_bottom_in[7], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:1]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size2
mux_left_track_19
(
.in({ chany_bottom_in[8], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_left_track_19_undriven_sram_inv[0:1]),
.out(chanx_left_out[9])
);
mux_tree_tapbuf_size2
mux_left_track_21
(
.in({ chany_bottom_in[9], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_left_track_21_undriven_sram_inv[0:1]),
.out(chanx_left_out[10])
);
mux_tree_tapbuf_size2
mux_left_track_23
(
.in({ chany_bottom_in[10], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_left_track_23_undriven_sram_inv[0:1]),
.out(chanx_left_out[11])
);
mux_tree_tapbuf_size2
mux_left_track_27
(
.in({ chany_bottom_in[12], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_left_track_27_undriven_sram_inv[0:1]),
.out(chanx_left_out[13])
);
mux_tree_tapbuf_size2
mux_left_track_29
(
.in({ chany_bottom_in[13], left_bottom_grid_pin_35_[0] }),
.sram(mux_tree_tapbuf_size2_18_sram[0:1]),
.sram_inv(mux_left_track_29_undriven_sram_inv[0:1]),
.out(chanx_left_out[14])
);
mux_tree_tapbuf_size2
mux_left_track_31
(
.in({ chany_bottom_in[14], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size2_19_sram[0:1]),
.sram_inv(mux_left_track_31_undriven_sram_inv[0:1]),
.out(chanx_left_out[15])
);
mux_tree_tapbuf_size2
mux_left_track_33
(
.in({ chany_bottom_in[15], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size2_20_sram[0:1]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:1]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size2
mux_left_track_35
(
.in({ chany_bottom_in[16], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size2_21_sram[0:1]),
.sram_inv(mux_left_track_35_undriven_sram_inv[0:1]),
.out(chanx_left_out[17])
);
mux_tree_tapbuf_size2
mux_left_track_37
(
.in({ chany_bottom_in[17], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size2_22_sram[0:1]),
.sram_inv(mux_left_track_37_undriven_sram_inv[0:1]),
.out(chanx_left_out[18])
);
mux_tree_tapbuf_size2
mux_left_track_39
(
.in({ chany_bottom_in[18], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size2_23_sram[0:1]),
.sram_inv(mux_left_track_39_undriven_sram_inv[0:1]),
.out(chanx_left_out[19])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_19
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_21
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_23
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_27
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_29
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_19
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_21
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_23
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_27
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_29
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_18_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_31
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_19_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_20_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_35
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_21_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_37
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_22_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_39
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_23_sram[0:1])
);
mux_tree_tapbuf_size3
mux_bottom_track_25
(
.in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_49_[0], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:1]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size3
mux_left_track_9
(
.in({ chany_bottom_in[3], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:1]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size3
mux_left_track_25
(
.in({ chany_bottom_in[11], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:1]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
endmodule

10
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/arch_encoder.v
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@ -1,10 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps

63
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/digital_io_hd.v
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@ -1,63 +0,0 @@
`timescale 1ns/1ps
module GPIO (A, IE, OE, Y, in, out, mem_out);
output A;
output IE;
output OE;
output Y;
input in;
output out;
input mem_out;
assign A = in;
assign out = Y;
assign IE = mem_out;
sky130_fd_sc_hd__inv_1 ie_oe_inv (
.A (mem_out),
.Y (OE) );
endmodule
//
//
//
//
module EMBEDDED_IO (
input SOC_IN, //
output SOC_OUT, //
output SOC_DIR, //
output FPGA_IN, //
input FPGA_OUT, //
input FPGA_DIR //
);
assign FPGA_IN = SOC_IN;
assign SOC_OUT = FPGA_OUT;
assign SOC_DIR = FPGA_DIR;
endmodule
//
//
//
module GPIN (
inout A, //
output Y //
);
//
sky130_fd_sc_hd__buf_4 in_buf (
.A (A),
.X (Y) );
endmodule
//
//
//
module GPOUT (
inout Y, //
input A //
);
//
sky130_fd_sc_hd__buf_4 in_buf (
.A (A),
.X (Y) );
endmodule

42
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/inv_buf_passgate.v
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@ -1,42 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module const0(const0);
//
output [0:0] const0;
//
//
//
//
assign const0[0] = 1'b0;
endmodule
//
//
module const1(const1);
//
output [0:0] const1;
//
//
//
//
assign const1[0] = 1'b1;
endmodule
//

10
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/local_encoder.v
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@ -1,10 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps

107
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/luts.v
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@ -1,107 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module frac_lut4(in,
sram,
sram_inv,
mode,
mode_inv,
lut3_out,
lut4_out);
//
input [0:3] in;
//
input [0:15] sram;
//
input [0:15] sram_inv;
//
input [0:0] mode;
//
input [0:0] mode_inv;
//
output [0:1] lut3_out;
//
output [0:0] lut4_out;
//
wire [0:3] in;
wire [0:1] lut3_out;
wire [0:0] lut4_out;
//
//
//
wire [0:0] sky130_fd_sc_hd__buf_2_0_X;
wire [0:0] sky130_fd_sc_hd__buf_2_1_X;
wire [0:0] sky130_fd_sc_hd__buf_2_2_X;
wire [0:0] sky130_fd_sc_hd__buf_2_3_X;
wire [0:0] sky130_fd_sc_hd__inv_1_0_Y;
wire [0:0] sky130_fd_sc_hd__inv_1_1_Y;
wire [0:0] sky130_fd_sc_hd__inv_1_2_Y;
wire [0:0] sky130_fd_sc_hd__inv_1_3_Y;
wire [0:0] sky130_fd_sc_hd__or2_1_0_X;
//
//
//
//
sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_ (
.A(mode[0]),
.B(in[3]),
.X(sky130_fd_sc_hd__or2_1_0_X[0]));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
.A(in[0]),
.Y(sky130_fd_sc_hd__inv_1_0_Y[0]));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ (
.A(in[1]),
.Y(sky130_fd_sc_hd__inv_1_1_Y[0]));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ (
.A(in[2]),
.Y(sky130_fd_sc_hd__inv_1_2_Y[0]));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
.A(sky130_fd_sc_hd__or2_1_0_X[0]),
.Y(sky130_fd_sc_hd__inv_1_3_Y[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ (
.A(in[0]),
.X(sky130_fd_sc_hd__buf_2_0_X[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ (
.A(in[1]),
.X(sky130_fd_sc_hd__buf_2_1_X[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ (
.A(in[2]),
.X(sky130_fd_sc_hd__buf_2_2_X[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ (
.A(sky130_fd_sc_hd__or2_1_0_X[0]),
.X(sky130_fd_sc_hd__buf_2_3_X[0]));
frac_lut4_mux frac_lut4_mux_0_ (
.in(sram[0:15]),
.sram({sky130_fd_sc_hd__buf_2_0_X[0], sky130_fd_sc_hd__buf_2_1_X[0], sky130_fd_sc_hd__buf_2_2_X[0], sky130_fd_sc_hd__buf_2_3_X[0]}),
.sram_inv({sky130_fd_sc_hd__inv_1_0_Y[0], sky130_fd_sc_hd__inv_1_1_Y[0], sky130_fd_sc_hd__inv_1_2_Y[0], sky130_fd_sc_hd__inv_1_3_Y[0]}),
.lut3_out(lut3_out[0:1]),
.lut4_out(lut4_out[0]));
endmodule
//

879
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v
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@ -1,879 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module mux_tree_tapbuf_size10_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
endmodule
//
//
module mux_tree_tapbuf_size8_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
endmodule
//
//
module mux_tree_tapbuf_size4_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
endmodule
//
//
module mux_tree_tapbuf_size7_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
endmodule
//
//
module mux_tree_tapbuf_size11_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
endmodule
//
//
module mux_tree_tapbuf_size2_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:1] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[1];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
endmodule
//
//
module mux_tree_tapbuf_size6_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
endmodule
//
//
module mux_tree_tapbuf_size5_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
endmodule
//
//
module mux_tree_tapbuf_size12_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
endmodule
//
//
module mux_tree_tapbuf_size16_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:4] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[4];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ (
.CLK(prog_clk[0]),
.D(mem_out[3]),
.Q(mem_out[4]));
endmodule
//
//
module mux_tree_tapbuf_size3_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:1] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[1];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
endmodule
//
//
module mux_tree_tapbuf_size9_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
endmodule
//
//
module mux_tree_tapbuf_size14_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
endmodule
//
//
module mux_tree_size2_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:1] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[1];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
endmodule
//
//
module frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:16] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[16];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ (
.CLK(prog_clk[0]),
.D(mem_out[3]),
.Q(mem_out[4]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ (
.CLK(prog_clk[0]),
.D(mem_out[4]),
.Q(mem_out[5]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ (
.CLK(prog_clk[0]),
.D(mem_out[5]),
.Q(mem_out[6]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ (
.CLK(prog_clk[0]),
.D(mem_out[6]),
.Q(mem_out[7]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ (
.CLK(prog_clk[0]),
.D(mem_out[7]),
.Q(mem_out[8]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ (
.CLK(prog_clk[0]),
.D(mem_out[8]),
.Q(mem_out[9]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ (
.CLK(prog_clk[0]),
.D(mem_out[9]),
.Q(mem_out[10]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ (
.CLK(prog_clk[0]),
.D(mem_out[10]),
.Q(mem_out[11]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ (
.CLK(prog_clk[0]),
.D(mem_out[11]),
.Q(mem_out[12]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ (
.CLK(prog_clk[0]),
.D(mem_out[12]),
.Q(mem_out[13]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ (
.CLK(prog_clk[0]),
.D(mem_out[13]),
.Q(mem_out[14]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ (
.CLK(prog_clk[0]),
.D(mem_out[14]),
.Q(mem_out[15]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ (
.CLK(prog_clk[0]),
.D(mem_out[15]),
.Q(mem_out[16]));
endmodule
//
//
module EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:0] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[0];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
endmodule
//

1515
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v
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34
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/wires.v
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@ -1,34 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module direct_interc(in,
out);
//
input [0:0] in;
//
output [0:0] out;
//
//
//
//
wire [0:0] in;
wire [0:0] out;
assign out[0] = in[0];
endmodule
//
//

31
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_include_netlists.v
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@ -1,31 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
`include "./SRC/define_simulation.v"
//
`include "./SRC/fabric_netlists.v"
`ifdef AUTOCHECKED_SIMULATION
`include "top_output_verilog.v"
`endif
`ifdef ENABLE_FORMAL_VERIFICATION
`include "./SRC/top_top_formal_verification.v"
`ifdef FORMAL_SIMULATION
`include "./SRC/top_formal_random_top_tb.v"
`endif
`endif
`ifdef AUTOCHECKED_SIMULATION
`include "./SRC/top_autocheck_top_tb.v"
`endif

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FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v
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FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit
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000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000001100000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000001000001000000000000000000000000000000000000000000000000001111000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111100100000000000000000000000011000000000000000000000000000000000000000000000000000000000000000000000000110111111000001100001000000000001100000000000000000000

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FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml
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FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml
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FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log
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/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga/openfpga -f top_run.openfpga
Reading script file top_run.openfpga...
___ _____ ____ ____ _
/ _ \ _ __ ___ _ __ | ___| _ \ / ___| / \
| | | | '_ \ / _ \ '_ \| |_ | |_) | | _ / _ \
| |_| | |_) | __/ | | | _| | __/| |_| |/ ___ \
\___/| .__/ \___|_| |_|_| |_| \____/_/ \_\
|_|
OpenFPGA: An Open-source FPGA IP Generator
Versatile Place and Route (VPR)
FPGA-Verilog
FPGA-SPICE
FPGA-SDC
FPGA-Bitstream
This is a free software under the MIT License
Copyright (c) 2018 LNIS - The University of Utah
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
Command line to execute: vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 2x2 --route_chan_width 40 --absorb_buffer_luts off
VPR FPGA Placement and Routing.
Version: 0.0.0+520e54d7
Revision: 520e54d7
Compiled: 2020-11-09T18:01:05
Compiler: GNU 8.4.0 on Linux-3.10.0-1062.9.1.el7.x86_64 x86_64
Build Info: release VTR_ASSERT_LEVEL=2
University of Toronto
verilogtorouting.org
vtr-users@googlegroups.com
This is free open source code under MIT license.
VPR was run with the following command-line:
vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 2x2 --route_chan_width 40 --absorb_buffer_luts off
Architecture file: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml
Circuit name: top
# Loading Architecture Description
Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 3: Model 'frac_lut4' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
# Loading Architecture Description took 0.01 seconds (max_rss 9.0 MiB, delta_rss +0.6 MiB)
# Building complex block graph
Warning 6: [LINE 586] false logically-equivalent pin clb[0].I0[1].
Warning 7: [LINE 586] false logically-equivalent pin clb[0].I0[2].
Warning 8: [LINE 592] false logically-equivalent pin clb[0].I1[1].
Warning 9: [LINE 592] false logically-equivalent pin clb[0].I1[2].
Warning 10: [LINE 598] false logically-equivalent pin clb[0].I2[1].
Warning 11: [LINE 598] false logically-equivalent pin clb[0].I2[2].
Warning 12: [LINE 604] false logically-equivalent pin clb[0].I3[1].
Warning 13: [LINE 604] false logically-equivalent pin clb[0].I3[2].
Warning 14: [LINE 610] false logically-equivalent pin clb[0].I4[1].
Warning 15: [LINE 610] false logically-equivalent pin clb[0].I4[2].
Warning 16: [LINE 616] false logically-equivalent pin clb[0].I5[1].
Warning 17: [LINE 616] false logically-equivalent pin clb[0].I5[2].
Warning 18: [LINE 622] false logically-equivalent pin clb[0].I6[1].
Warning 19: [LINE 622] false logically-equivalent pin clb[0].I6[2].
Warning 20: [LINE 628] false logically-equivalent pin clb[0].I7[1].
Warning 21: [LINE 628] false logically-equivalent pin clb[0].I7[2].
# Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB)
# Load circuit
# Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.4 MiB)
# Clean circuit
Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs
Inferred 0 additional primitive pins as constant generators due to constant inputs
Swept input(s) : 0
Swept output(s) : 0 (0 dangling, 0 constant)
Swept net(s) : 0
Swept block(s) : 0
Constant Pins Marked: 0
# Clean circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB)
# Compress circuit
# Compress circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB)
# Verify circuit
# Verify circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB)
Circuit Statistics:
Blocks: 4
.input : 2
.output: 1
4-LUT : 1
Nets : 3
Avg Fanout: 1.0
Max Fanout: 1.0
Min Fanout: 1.0
Netlist Clocks: 0
# Build Timing Graph
Timing Graph Nodes: 6
Timing Graph Edges: 5
Timing Graph Levels: 4
# Build Timing Graph took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB)
Netlist contains 0 clocks
# Load Timing Constraints
SDC file 'top.sdc' not found
Setting default timing constraints:
* constrain all primay inputs and primary outputs on a virtual external clock 'virtual_io_clock'
* optimize virtual clock to run as fast as possible
Timing constraints created 1 clocks
Constrained Clock 'virtual_io_clock' (Virtual Clock)
# Load Timing Constraints took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB)
Timing analysis: ON
Circuit netlist file: top.net
Circuit placement file: top.place
Circuit routing file: top.route
Circuit SDC file: top.sdc
Packer: ENABLED
Placer: ENABLED
Router: ENABLED
Analysis: ENABLED
NetlistOpts.abosrb_buffer_luts : false
NetlistOpts.sweep_dangling_primary_ios : true
NetlistOpts.sweep_dangling_nets : true
NetlistOpts.sweep_dangling_blocks : true
NetlistOpts.sweep_constant_primary_outputs: false
PackerOpts.allow_unrelated_clustering: auto
PackerOpts.alpha_clustering: 0.750000
PackerOpts.beta_clustering: 0.900000
PackerOpts.cluster_seed_type: BLEND2
PackerOpts.connection_driven: true
PackerOpts.global_clocks: true
PackerOpts.hill_climbing_flag: false
PackerOpts.inter_cluster_net_delay: 1.000000
PackerOpts.timing_driven: true
PackerOpts.target_external_pin_util: auto
PlacerOpts.place_freq: PLACE_ONCE
PlacerOpts.place_algorithm: PATH_TIMING_DRIVEN_PLACE
PlacerOpts.pad_loc_type: FREE
PlacerOpts.place_cost_exp: 1.000000
PlacerOpts.place_chan_width: 40
PlacerOpts.inner_loop_recompute_divider: 0
PlacerOpts.recompute_crit_iter: 1
PlacerOpts.timing_tradeoff: 0.500000
PlacerOpts.td_place_exp_first: 1.000000
PlacerOpts.td_place_exp_last: 8.000000
PlaceOpts.seed: 1
AnnealSched.type: AUTO_SCHED
AnnealSched.inner_num: 1.000000
RouterOpts.route_type: DETAILED
RouterOpts.router_algorithm: TIMING_DRIVEN
RouterOpts.base_cost_type: DELAY_NORMALIZED_LENGTH
RouterOpts.fixed_channel_width: 40
RouterOpts.trim_empty_chan: false
RouterOpts.trim_obs_chan: false
RouterOpts.acc_fac: 1.000000
RouterOpts.bb_factor: 3
RouterOpts.bend_cost: 0.000000
RouterOpts.first_iter_pres_fac: 0.000000
RouterOpts.initial_pres_fac: 0.500000
RouterOpts.pres_fac_mult: 1.300000
RouterOpts.max_router_iterations: 50
RouterOpts.min_incremental_reroute_fanout: 16
RouterOpts.astar_fac: 1.200000
RouterOpts.criticality_exp: 1.000000
RouterOpts.max_criticality: 0.990000
RouterOpts.routing_failure_predictor = SAFE
RouterOpts.routing_budgets_algorithm = DISABLE
AnalysisOpts.gen_post_synthesis_netlist: false
RoutingArch.directionality: UNI_DIRECTIONAL
RoutingArch.switch_block_type: WILTON
RoutingArch.Fs: 3
# Packing
Warning 22: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 23: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 24: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 25: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Begin packing 'top.blif'.
After removing unused inputs...
total blocks: 4, total nets: 3, total inputs: 2, total outputs: 1
Begin prepacking.
Finish prepacking.
Using inter-cluster delay: 1.33777e-09
Packing with pin utilization targets: io_top:1,1 io_right:1,1 io_bottom:1,1 io_left:1,1 clb:0.8,1
Packing with high fanout thresholds: io_top:128 io_right:128 io_bottom:128 io_left:128 clb:32
Warning 26: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 27: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 28: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 29: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Not enough resources expand FPGA size to (4 x 4)
Complex block 0: 'c' (clb) .
Complex block 1: 'out:c' (io) .
Complex block 2: 'a' (io) .
Complex block 3: 'b' (io) .
Pb types usage...
inpad : 2
outpad : 1
fle : 1
clb : 1
lut3inter : 1
ble3 : 1
io : 3
lut3 : 1
lut : 1
Logic Element (fle) detailed count:
Total number of Logic Elements used : 1
LEs used for logic and registers : 0
LEs used for logic only : 1
LEs used for registers only : 0
EMPTY: # blocks: 0, average # input + clock pins used: 0, average # output pins used: 0
io: # blocks: 3, average # input + clock pins used: 0.333333, average # output pins used: 0.666667
clb: # blocks: 1, average # input + clock pins used: 2, average # output pins used: 1
Absorbed logical nets 0 out of 3 nets, 3 nets not absorbed.
Warning 30: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 31: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 32: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 33: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
FPGA sized to 4 x 4 (2x2)
Device Utilization: 0.25 (target 1.00)
Block Utilization: 0.17 Type: io
Block Utilization: 0.25 Type: clb
Netlist conversion complete.
# Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB)
# Load Packing
Begin loading packed FPGA netlist file.
Netlist generated from file 'top.net'.
Detected 0 constant generators (to see names run with higher pack verbosity)
Finished loading packed FPGA netlist file (took 0.01 seconds).
Warning 34: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity).
# Load Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB)
Warning 35: Netlist contains 0 global net to non-global architecture pin connections
Netlist num_nets: 3
Netlist num_blocks: 4
Netlist EMPTY blocks: 0.
Netlist io blocks: 3.
Netlist clb blocks: 1.
Netlist inputs pins: 2
Netlist output pins: 1
# Create Device
## Build Device Grid
Warning 36: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 37: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 38: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 39: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
FPGA sized to 4 x 4: 16 grid tiles (2x2)
Resource usage...
Netlist
3 blocks of type: io
Architecture
2 blocks of type: io_top
2 blocks of type: io_right
12 blocks of type: io_bottom
2 blocks of type: io_left
Netlist
1 blocks of type: clb
Architecture
4 blocks of type: clb
Device Utilization: 0.25 (target 1.00)
Physical Tile io_top:
Block Utilization: 1.50 Logical Block: io
Physical Tile io_right:
Block Utilization: 1.50 Logical Block: io
Physical Tile io_bottom:
Block Utilization: 0.25 Logical Block: io
Physical Tile io_left:
Block Utilization: 1.50 Logical Block: io
Physical Tile clb:
Block Utilization: 0.25 Logical Block: clb
## Build Device Grid took 0.00 seconds (max_rss 10.7 MiB, delta_rss +0.0 MiB)
## Build tileable routing resource graph
X-direction routing channel width is 40
Y-direction routing channel width is 40
Warning 40: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 41: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 42: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 43: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
## Build tileable routing resource graph took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB)
RR Graph Nodes: 756
RR Graph Edges: 2930
# Create Device took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB)
# Placement
## Computing placement delta delay look-up
### Build routing resource graph
Warning 44: in check_rr_node: RR node: 119 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 45: in check_rr_node: RR node: 120 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 46: in check_rr_node: RR node: 327 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 47: in check_rr_node: RR node: 328 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
### Build routing resource graph took 0.00 seconds (max_rss 11.2 MiB, delta_rss +0.0 MiB)
RR Graph Nodes: 756
RR Graph Edges: 2428
### Computing delta delays
### Computing delta delays took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.0 MiB)
## Computing placement delta delay look-up took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.3 MiB)
There are 3 point to point connections in this circuit.
BB estimate of min-dist (placement) wire length: 10
Completed placement consistency check successfully.
Initial placement cost: 1 bb_cost: 0.25 td_cost: 6.04709e-10
Initial placement estimated Critical Path Delay (CPD): 0.80931 ns
Initial placement estimated setup Total Negative Slack (sTNS): -0.80931 ns
Initial placement estimated setup Worst Negative Slack (sWNS): -0.80931 ns
Initial placement estimated setup slack histogram:
[ -8.1e-10: -8.1e-10) 1 (100.0%) |**************************************************
[ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
[ -8.1e-10: -8.1e-10) 0 ( 0.0%) |
Placement contains 0 placement macros involving 0 blocks (average macro size -nan)
------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------
T Av Cost Av BB Cost Av TD Cost CPD sTNS sWNS Ac Rate Std Dev R lim Crit Exp Tot Moves Alpha
------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------
9.2e-01 0.857 0.21 4.9164e-10 0.693 -0.693 -0.693 0.667 0.0425 3.0 1.00 6 0.950
8.8e-01 1.031 0.22 5.2788e-10 0.693 -0.693 -0.693 1.000 0.1248 3.0 1.00 12 0.500
4.4e-01 0.977 0.20 4.5978e-10 0.693 -0.693 -0.693 1.000 0.0478 3.0 1.00 18 0.500
2.2e-01 1.296 0.24 6.1181e-10 0.577 -0.577 -0.577 0.833 0.1114 3.0 1.00 24 0.900
2.0e-01 0.807 0.21 5.1793e-10 0.809 -0.809 -0.809 0.833 0.1585 3.0 1.00 30 0.900
1.8e-01 1.284 0.23 4.5908e-10 0.577 -0.577 -0.577 1.000 0.1344 3.0 1.00 36 0.500
8.9e-02 0.981 0.23 4.8318e-10 0.635 -0.635 -0.635 1.000 0.0703 3.0 1.00 42 0.500
4.4e-02 0.906 0.23 4.617e-10 0.693 -0.693 -0.693 0.833 0.0159 3.0 1.00 48 0.900
4.0e-02 0.915 0.20 4.3008e-10 0.693 -0.693 -0.693 1.000 0.0692 3.0 1.00 54 0.500
2.0e-02 1.000 0.18 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 3.0 1.00 60 0.950
1.9e-02 1.000 0.18 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 2.7 2.12 66 0.950
1.8e-02 0.982 0.17 3.9141e-10 0.577 -0.577 -0.577 0.667 0.0357 1.9 4.68 72 0.950
1.7e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 2.4 3.14 78 0.950
1.6e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.7 5.42 84 0.950
1.5e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.3 7.08 90 0.950
1.5e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.3 6.82 96 0.950
1.4e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.4 6.54 102 0.950
1.3e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.3 7.07 108 0.950
1.3e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.1 7.54 114 0.950
1.2e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.2 7.30 120 0.950
1.1e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.0 8.00 126 0.800
9.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 132 0.950
8.6e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.1 7.79 138 0.950
8.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.1 7.57 144 0.950
7.8e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 7.99 150 0.950
7.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 156 0.950
7.0e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.667 0.0000 1.1 7.79 162 0.950
6.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.833 0.0000 1.3 6.95 168 0.900
6.0e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.8 5.16 174 0.950
5.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 7.95 180 0.950
5.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.0 8.00 186 0.950
5.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 192 0.950
4.9e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.1 7.79 198 0.950
4.6e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 204 0.950
4.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 210 0.950
4.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.1 7.79 216 0.950
4.0e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.1 7.57 222 0.950
3.8e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.0 7.99 228 0.950
3.6e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 234 0.950
3.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 240 0.950
3.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 246 0.950
3.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.1 7.79 252 0.950
2.9e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.0 8.00 258 0.800
2.3e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 264 0.950
2.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 270 0.950
2.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.0 8.00 276 0.800
1.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 282 0.950
1.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 288 0.000
BB estimate of min-dist (placement) wire length: 6
Completed placement consistency check successfully.
Swaps called: 292
Placement estimated critical path delay: 0.57731 ns
Placement estimated setup Total Negative Slack (sTNS): -0.57731 ns
Placement estimated setup Worst Negative Slack (sWNS): -0.57731 ns
Placement estimated setup slack histogram:
[ -5.8e-10: -5.8e-10) 1 (100.0%) |**************************************************
[ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
[ -5.8e-10: -5.8e-10) 0 ( 0.0%) |
Placement cost: 1, bb_cost: 0.15, td_cost: 3.9141e-10,
Placement resource usage:
io implemented as io_bottom: 2
io implemented as io_left : 1
clb implemented as clb : 1
Placement number of temperatures: 48
Placement total # of swap attempts: 292
Swaps accepted: 125 (42.8 %)
Swaps rejected: 167 (57.2 %)
Swaps aborted : 0 ( 0.0 %)
Aborted Move Reasons:
# Placement took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.5 MiB)
# Routing
## Build tileable routing resource graph
X-direction routing channel width is 40
Y-direction routing channel width is 40
Warning 48: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 49: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 50: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 51: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
## Build tileable routing resource graph took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.0 MiB)
RR Graph Nodes: 756
RR Graph Edges: 2930
Confirming router algorithm: TIMING_DRIVEN.
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
Iter Time pres BBs Heap Re-Rtd Re-Rtd Overused RR Nodes Wirelength CPD sTNS sWNS hTNS hWNS Est Succ
(sec) fac Updt push Nets Conns (ns) (ns) (ns) (ns) (ns) Iter
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
1 0.0 0.0 0 203 3 3 1 ( 0.132%) 12 ( 2.5%) 0.867 -0.8673 -0.867 0.000 0.000 N/A
2 0.0 0.5 0 86 1 1 0 ( 0.000%) 12 ( 2.5%) 0.867 -0.8673 -0.867 0.000 0.000 N/A
Restoring best routing
Critical path: 0.86731 ns
Successfully routed after 2 routing iterations.
Router Stats: total_nets_routed: 4 total_connections_routed: 4 total_heap_pushes: 289 total_heap_pops: 187
# Routing took 0.01 seconds (max_rss 11.9 MiB, delta_rss +0.2 MiB)
Checking to ensure routing is legal...
Completed routing consistency check successfully.
Serial number (magic cookie) for the routing is: -18854
Circuit successfully routed with a channel width factor of 40.
Average number of bends per net: 2.00000 Maximum # of bends: 3
Number of global nets: 0
Number of routed nets (nonglobal): 3
Wire length results (in units of 1 clb segments)...
Total wirelength: 12, average net length: 4.00000
Maximum net length: 6
Wire length results in terms of physical segments...
Total wiring segments used: 9, average wire segments per net: 3.00000
Maximum segments used by a net: 4
Total local nets with reserved CLB opins: 0
Routing channel utilization histogram:
[ 1: inf) 0 ( 0.0%) |
[ 0.9: 1) 0 ( 0.0%) |
[ 0.8: 0.9) 0 ( 0.0%) |
[ 0.7: 0.8) 0 ( 0.0%) |
[ 0.5: 0.6) 0 ( 0.0%) |
[ 0.4: 0.5) 0 ( 0.0%) |
[ 0.3: 0.4) 0 ( 0.0%) |
[ 0.2: 0.3) 0 ( 0.0%) |
[ 0.1: 0.2) 0 ( 0.0%) |
[ 0: 0.1) 18 (100.0%) |************************************************
Maximum routing channel utilization: 0.05 at (1,0)
X - Directed channels: j max occ ave occ capacity
---- ------- ------- --------
0 2 0.750 40
1 2 0.500 40
2 0 0.000 40
Y - Directed channels: i max occ ave occ capacity
---- ------- ------- --------
0 2 0.750 40
1 3 1.000 40
2 0 0.000 40
Total tracks in x-direction: 120, in y-direction: 120
Logic area (in minimum width transistor areas, excludes I/Os and empty grid tiles)...
Total logic block area (Warning, need to add pitch of routing to blocks with height > 3): 215576
Total used logic block area: 53894
Routing area (in minimum width transistor areas)...
Total routing area: 23072.6, per logic tile: 1442.04
Segment usage by type (index): type utilization
---- -----------
0 0.0833
1 0
2 0.0208
Segment usage by length: length utilization
------ -----------
1 0.0833
2 0
4 0.0208
Hold Worst Negative Slack (hWNS): 0 ns
Hold Total Negative Slack (hTNS): 0 ns
Hold slack histogram:
[ 7.3e-10: 7.3e-10) 1 (100.0%) |**************************************************
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
Final critical path: 0.86731 ns, Fmax: 1152.99 MHz
Setup Worst Negative Slack (sWNS): -0.86731 ns
Setup Total Negative Slack (sTNS): -0.86731 ns
Setup slack histogram:
[ -8.7e-10: -8.7e-10) 1 (100.0%) |**************************************************
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
Timing analysis took 0.000405567 seconds (0.000363868 STA, 4.1699e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined).
VPR suceeded
The entire flow of VPR took 0.09 seconds (max_rss 11.9 MiB)
Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
Confirm selected options when call command 'read_openfpga_arch':
--file, -f: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
Reading XML architecture '/research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml'...
Read OpenFPGA architecture
Warning 52: Automatically set circuit model 'frac_lut4' to be default in its type.
Warning 53: Automatically set circuit model 'sky130_fd_sc_hd__sdfxtp_1' to be default in its type.
Warning 54: Automatically set circuit model 'sky130_fd_sc_hd__dfxtp_1' to be default in its type.
Use the default configurable memory model 'sky130_fd_sc_hd__dfxtp_1' for circuit model 'mux_tree' port 'sram')
Use the default configurable memory model 'sky130_fd_sc_hd__dfxtp_1' for circuit model 'mux_tree_tapbuf' port 'sram')
Use the default configurable memory model 'sky130_fd_sc_hd__dfxtp_1' for circuit model 'frac_lut4' port 'sram')
Read OpenFPGA architecture took 0.00 seconds (max_rss 12.0 MiB, delta_rss +0.1 MiB)
Check circuit library
Checking circuit library passed.
Check circuit library took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
Found 0 errors when checking configurable memory circuit models!
Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
Confirm selected options when call command 'read_openfpga_simulation_setting':
--file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'...
Read OpenFPGA simulation settings
Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
Command line to execute: link_openfpga_arch --activity_file top_ace_out.act --sort_gsb_chan_node_in_edges
Confirm selected options when call command 'link_openfpga_arch':
--activity_file: top_ace_out.act
--sort_gsb_chan_node_in_edges: on
--verbose: off
Link OpenFPGA architecture to VPR architecture
Building annotation for physical modes in pb_type...Done
Check physical mode annotation for pb_types passed.
Building annotation about physical types for pb_type interconnection...Done
Building annotation between operating and physical pb_types...Done
Check physical pb_type annotation for pb_types passed.
Building annotation between physical pb_types and circuit models...Done
Check physical pb_type annotation for circuit model passed.
Building annotation between physical pb_types and mode selection bits...Done
Check pb_type annotation for mode selection bits passed.
Assigning unique indices for primitive pb_graph nodes...Done
Binding operating pb_graph nodes/pins to physical pb_graph nodes/pins...Done
Check pb_graph annotation for physical nodes and pins passed.
Binded 4 routing resource graph switches to circuit models
Binded 3 routing segments to circuit models
Binded 2 direct connections to circuit models
Annotating rr_node with routed nets...Done with 15 nodes mapping
Annotating previous nodes for rr_node...Warning 55: Override the previous node '139' by previous node '137' for node '84' with in routing context annotation!
Done with 18 nodes mapping
# Build General Switch Block(GSB) annotation on top of routing resource graph
[11%] Backannotated GSB[0][0]
[22%] Backannotated GSB[0][1]
[33%] Backannotated GSB[0][2]
[44%] Backannotated GSB[1][0]
[55%] Backannotated GSB[1][1]
[66%] Backannotated GSB[1][2]
[77%] Backannotated GSB[2][0]
[88%] Backannotated GSB[2][1]
[100%] Backannotated GSB[2][2]
Backannotated 9 General Switch Blocks (GSBs).
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
# Sort incoming edges for each routing track output node of General Switch Block(GSB)
[11%] Sorted edges for GSB[0][0]
[22%] Sorted edges for GSB[0][1]
[33%] Sorted edges for GSB[0][2]
[44%] Sorted edges for GSB[1][0]
[55%] Sorted edges for GSB[1][1]
[66%] Sorted edges for GSB[1][2]
[77%] Sorted edges for GSB[2][0]
[88%] Sorted edges for GSB[2][1]
[100%] Sorted edges for GSB[2][2]
Sorted edges for 9 General Switch Blocks (GSBs).
# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
# Build a library of physical multiplexers
Built a multiplexer library of 15 physical multiplexers.
Maximum multiplexer size is 17.
# Build a library of physical multiplexers took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.3 MiB)
# Build the annotation about direct connection between tiles
Built 6 tile-to-tile direct connections
# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.0 MiB)
Building annotation for mapped blocks on grid locations...Done
User specified the operating clock frequency to use VPR results
Use VPR critical path delay 1.04077e-18 [ns] with a 20 [%] slack in OpenFPGA.
Will apply operating clock frequency 960.825 [MHz] to simulations
User specified the number of operating clock cycles to be inferred from signal activities
Average net density: 0.42
Median net density: 0.00
Average net density after weighting: 0.42
Will apply 2 operating clock cycles to simulations
Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.3 MiB)
Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_task/arch/fabric_key.xml
Confirm selected options when call command 'build_fabric':
--frame_view: off
--compress_routing: on
--duplicate_grid_pin: on
--load_fabric_key: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_task/arch/fabric_key.xml
--write_fabric_key: off
--generate_random_fabric_key: off
--verbose: off
Identify unique General Switch Blocks (GSBs)
Detected 9 unique general switch blocks from a total of 9 (compression rate=0.00%)
Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB)
Read Fabric Key
Read Fabric Key took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
Build fabric module graph
# Build constant generator modules
# Build constant generator modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Build user-defined modules
# Build user-defined modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Build essential (inverter/buffer/logic gate) modules
# Build essential (inverter/buffer/logic gate) modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Build local encoder (for multiplexers) modules
# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Building multiplexer modules
# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.3 MiB)
# Build Look-Up Table (LUT) modules
# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.3 MiB)
# Build wire modules
# Build wire modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.0 MiB)
# Build memory modules
# Build memory modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.0 MiB)
# Build grid modules
Building logical tiles...Done
Building physical tiles...Done
# Build grid modules took 0.00 seconds (max_rss 13.7 MiB, delta_rss +0.5 MiB)
# Build unique routing modules...
# Build unique routing modules... took 0.02 seconds (max_rss 15.8 MiB, delta_rss +2.1 MiB)
# Build FPGA fabric module
## Add grid instances to top module
## Add grid instances to top module took 0.00 seconds (max_rss 15.8 MiB, delta_rss +0.0 MiB)
## Add switch block instances to top module
## Add switch block instances to top module took 0.00 seconds (max_rss 15.8 MiB, delta_rss +0.0 MiB)
## Add connection block instances to top module
## Add connection block instances to top module took 0.00 seconds (max_rss 15.8 MiB, delta_rss +0.0 MiB)
## Add connection block instances to top module
## Add connection block instances to top module took 0.00 seconds (max_rss 16.0 MiB, delta_rss +0.3 MiB)
## Add module nets between grids and GSBs
## Add module nets between grids and GSBs took 0.01 seconds (max_rss 16.5 MiB, delta_rss +0.5 MiB)
## Add module nets for inter-tile connections
## Add module nets for inter-tile connections took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB)
## Add module nets for configuration buses
## Add module nets for configuration buses took 0.00 seconds (max_rss 16.8 MiB, delta_rss +0.3 MiB)
# Build FPGA fabric module took 0.01 seconds (max_rss 16.8 MiB, delta_rss +1.0 MiB)
Build fabric module graph took 0.03 seconds (max_rss 16.8 MiB, delta_rss +4.1 MiB)
Create I/O location mapping for top module
Create I/O location mapping for top module took 0.00 seconds (max_rss 16.8 MiB, delta_rss +0.0 MiB)
Command line to execute: repack
Confirm selected options when call command 'repack':
--verbose: off
Build routing resource graph for the physical implementation of logical tile
Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.3 MiB)
Repack clustered blocks to physical implementation of logical tile
Repack clustered block 'c'...Done
Repack clustered block 'out:c'...Done
Repack clustered block 'a'...Done
Repack clustered block 'b'...Done
Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB)
Build truth tables for physical LUTs
Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB)
Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml
Confirm selected options when call command 'build_architecture_bitstream':
--write_file: fabric_indepenent_bitstream.xml
--read_file: off
--verbose: off
Build fabric-independent bitstream for implementation 'top'
Generating bitstream for Switch blocks...Done
Generating bitstream for X-direction Connection blocks ...Done
Generating bitstream for Y-direction Connection blocks ...Done
Build fabric-independent bitstream for implementation 'top'
took 0.01 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB)
Warning 56: Directory path is empty and nothing will be created.
Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.03 seconds (max_rss 17.3 MiB, delta_rss +0.3 MiB)
Command line to execute: build_fabric_bitstream
Confirm selected options when call command 'build_fabric_bitstream':
--verbose: off
Build fabric dependent bitstream
Build fabric dependent bitstream
took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
Confirm selected options when call command 'write_fabric_bitstream':
--file, -f: fabric_bitstream.bit
--format: plain_text
--verbose: off
Warning 57: Directory path is empty and nothing will be created.
Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit'
Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml
Confirm selected options when call command 'write_fabric_bitstream':
--file, -f: fabric_bitstream.xml
--format: xml
--verbose: off
Warning 58: Directory path is empty and nothing will be created.
Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml'
Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose
Confirm selected options when call command 'write_fabric_verilog':
--file, -f: ./SRC
--explicit_port_mapping: on
--include_timing: on
--include_signal_init: on
--support_icarus_simulator: on
--print_user_defined_template: off
--verbose: on
Write Verilog netlists for FPGA fabric
Succeed to create directory './SRC'
Succeed to create directory './SRC/sub_module'
Succeed to create directory './SRC/lb'
Succeed to create directory './SRC/routing'
Generating Verilog netlist './SRC/sub_module/inv_buf_passgate.v' for essential gates...Done
Writing Verilog netlist for configuration decoders './SRC/sub_module/arch_encoder.v'...Done
Writing Verilog netlist for local decoders for multiplexers './SRC/sub_module/local_encoder.v'...Done
Writing Verilog netlist for Multiplexers './SRC/sub_module/muxes.v' ...Done
Writing Verilog netlist for LUTs './SRC/sub_module/luts.v'...Done
Writing Verilog netlist for wires './SRC/sub_module/wires.v'...Done
Writing Verilog netlist for memories './SRC/sub_module/memories.v' ...Done
Writing logical tiles...
Writing Verilog netlists for logic tile 'io' ...
Writing Verilog netlist './SRC/lb/logical_tile_io_mode_physical__iopad.v' for primitive pb_type 'iopad' ...
Writing Verilog codes of logical tile primitive block 'logical_tile_io_mode_physical__iopad'...Done
Writing Verilog netlist './SRC/lb/logical_tile_io_mode_io_.v' for pb_type 'io' ...
Writing Verilog codes of pb_type 'logical_tile_io_mode_io_'...Done
Done
Writing Verilog netlists for logic tile 'clb' ...
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v' for primitive pb_type 'frac_lut4' ...
Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4'...Done
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v' for pb_type 'frac_logic' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic'...Done
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v' for primitive pb_type 'ff' ...
Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff'...Done
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v' for pb_type 'fabric' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric'...Done
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle.v' for pb_type 'fle' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle'...Done
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_clb_.v' for pb_type 'clb' ...
Writing Verilog codes of pb_type 'logical_tile_clb_mode_clb_'...Done
Done
Writing logical tiles...Done
Building physical tiles...
Writing Verilog Netlist './SRC/lb/grid_io_top_top.v' for physical tile 'io_top' at top side ...Done
Writing Verilog Netlist './SRC/lb/grid_io_right_right.v' for physical tile 'io_right' at right side ...Done
Writing Verilog Netlist './SRC/lb/grid_io_bottom_bottom.v' for physical tile 'io_bottom' at bottom side ...Done
Writing Verilog Netlist './SRC/lb/grid_io_left_left.v' for physical tile 'io_left' at left side ...Done
Writing Verilog Netlist './SRC/lb/grid_clb.v' for physical_tile 'clb'...Done
Building physical tiles...Done
Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done
Written 73 Verilog modules in total
Write Verilog netlists for FPGA fabric
took 0.19 seconds (max_rss 17.7 MiB, delta_rss +0.4 MiB)
Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
Confirm selected options when call command 'write_verilog_testbench':
--file, -f: ./SRC
--fabric_netlist_file_path: off
--reference_benchmark_file_path: top_output_verilog.v
--print_top_testbench: on
--fast_configuration: off
--print_formal_verification_top_netlist: off
--print_preconfig_top_testbench: on
--print_simulation_ini: ./SimulationDeck/simulation_deck.ini
--explicit_port_mapping: on
--verbose: off
Warning 59: Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled
Write Verilog testbenches for FPGA fabric
Warning 60: Directory './SRC' already exists. Will overwrite contents
# Write pre-configured FPGA top-level Verilog netlist for design 'top'
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 17.7 MiB, delta_rss +0.0 MiB)
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top'
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 17.7 MiB, delta_rss +0.0 MiB)
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top'
Will use 2107 configuration clock cycles to top testbench
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.01 seconds (max_rss 17.8 MiB, delta_rss +0.1 MiB)
Succeed to create directory './SimulationDeck'
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini'
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB)
Write Verilog testbenches for FPGA fabric
took 0.03 seconds (max_rss 17.8 MiB, delta_rss +0.1 MiB)
Command line to execute: exit
Confirm selected options when call command 'exit':
Finish execution with 0 errors
The entire OpenFPGA flow took 0.25 seconds
Thank you for using OpenFPGA!

13
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/proj_const.tcl
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@ -1,13 +0,0 @@
set DIE_HEIGHT 700
set DIE_WIDTH 700
set DESIGN_NAME fpga_core
set TASK_NAME FPGA22_HIER_SKY_task
set VERILOG_PROJ_DIR FPGA22_HIER_SKY_Verilog
set FPGA_ROW 2
set FPGA_COL 2
set INIT_DESIGN_INPUT DP_RM_NDM
set TECHNOLOGY skywater
set DP_BLOCK_REFS [list sb_0__0_ sb_0__1_ sb_0__2_ sb_1__0_ sb_1__1_ sb_1__2_ sb_2__0_ sb_2__1_ sb_2__2_ cbx_1__0_ cbx_1__1_ cbx_1__2_ cby_0__1_ cby_1__1_ cby_2__1_ grid_clb];
set DP_FLOW "hier";
set DESIGN_STYLE "hier";
set STANDARD_CELLS sc_hd;

38
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml
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@ -1,38 +0,0 @@
<?xml version="1.0" ?>
<fabric_key>
<region id="0">
<key id="0" alias="sb_2__2_"/>
<key id="1" alias="cbx_2__2_"/>
<key id="2" alias="grid_io_top_top_2__3_"/>
<key id="3" alias="sb_1__2_"/>
<key id="4" alias="cbx_1__2_"/>
<key id="5" alias="grid_io_top_top_1__3_"/>
<key id="6" alias="sb_0__2_"/>
<key id="7" alias="cby_0__2_"/>
<key id="8" alias="grid_io_left_left_0__2_"/>
<key id="9" alias="grid_clb_1__2_"/>
<key id="10" alias="cby_1__2_"/>
<key id="11" alias="grid_clb_2__2_"/>
<key id="12" alias="cby_2__2_"/>
<key id="13" alias="grid_io_right_right_3__2_"/>
<key id="14" alias="sb_2__1_"/>
<key id="15" alias="cbx_2__1_"/>
<key id="16" alias="sb_1__1_"/>
<key id="17" alias="cbx_1__1_"/>
<key id="18" alias="sb_0__1_"/>
<key id="19" alias="cby_0__1_"/>
<key id="20" alias="grid_io_left_left_0__1_"/>
<key id="21" alias="grid_clb_1__1_"/>
<key id="22" alias="cby_1__1_"/>
<key id="23" alias="grid_clb_2__1_"/>
<key id="24" alias="cby_2__1_"/>
<key id="25" alias="grid_io_right_right_3__1_"/>
<key id="26" alias="sb_2__0_"/>
<key id="27" alias="cbx_2__0_"/>
<key id="28" alias="grid_io_bottom_bottom_2__0_"/>
<key id="29" alias="sb_1__0_"/>
<key id="30" alias="cbx_1__0_"/>
<key id="31" alias="grid_io_bottom_bottom_1__0_"/>
<key id="32" alias="sb_0__0_"/>
</region>
</fabric_key>

248
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml
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@ -1,248 +0,0 @@
<!-- Architecture annotation for OpenFPGA framework
This annotation supports the k4_frac_cc_sky130nm.xml
- General purpose logic block
- K = 6, N = 10, I = 40
- Single mode
- Routing architecture
- L = 4, fc_in = 0.15, fc_out = 0.1
- Skywater 130nm PDK
- circuit models are binded to the opensource skywater
foundry middle-speed (ms) standard cell library
-->
<openfpga_architecture>
<technology_library>
<device_library>
<device_model name="logic" type="transistor">
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="0.9" pn_ratio="2"/>
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
</device_model>
<device_model name="io" type="transistor">
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="2.5" pn_ratio="3"/>
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
</device_model>
</device_library>
<variation_library>
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
</variation_library>
</technology_library>
<circuit_library>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v">
<design_technology type="cmos" topology="inverter" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="Y" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v">
<design_technology type="cmos" topology="buffer" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="Y" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v">
<design_technology type="cmos" topology="OR"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
</circuit_model>
<!-- Define a circuit model for the standard cell MUX2
OpenFPGA requires the following truth table for the MUX2
When the select signal sel is enabled, the first input, i.e., in0
will be propagated to the output, i.e., out
If your standard cell provider does not offer the exact truth table,
you can simply swap the inputs as shown in the example below
-->
<circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v">
<design_technology type="cmos" topology="MUX2"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in0" lib_name="A1" size="1"/>
<port type="input" prefix="in1" lib_name="A0" size="1"/>
<port type="input" prefix="sel" lib_name="S" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="sky130_fd_sc_hd__sdfxtp_1" prefix="sky130_fd_sc_hd__sdfxtp_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="DI" lib_name="SCD" size="1"/>
<port type="input" prefix="Test_en" lib_name="SCE" size="1" is_global="true" default_val="0"/>
<!-- <port type="input" prefix="reset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_reset="true"/> -->
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
<lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
<lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/>
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="16"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxtp_1" default_val="1"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="sky130_fd_sc_hd__dfxtp_1" prefix="sky130_fd_sc_hd__dfxtp_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="EMBEDDED_IO" prefix="EMBEDDED_IO" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
<port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxtp_1" default_val="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfxtp_1" num_regions="1"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
</connection_block>
<switch_block>
<switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
<switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
<switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
</switch_block>
<routing_segment>
<segment name="L1" circuit_model_name="chan_segment"/>
<segment name="L2" circuit_model_name="chan_segment"/>
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<direct_connection>
<direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
</direct_connection>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO" mode_bits="1"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfxtp_1"/>
<!-- Binding operating pb_type to physical pb_type -->
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
<port name="in" physical_mode_port="in[0:2]"/>
<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
</pb_type>
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<!-- Binding operating pb_types in mode 'ble4' -->
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
<port name="in" physical_mode_port="in[0:3]"/>
<port name="out" physical_mode_port="lut4_out"/>
</pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<!-- Binding operating pb_types in mode 'shift_register' -->
<pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<!-- End physical pb_type binding in complex block IO -->
</pb_type_annotations>
</openfpga_architecture>

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FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml
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@ -1,670 +0,0 @@
<!--
Low-cost homogeneous FPGA Architecture.
- Skywater 130 nm technology
- General purpose logic block:
K = 4, N = 8, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared)
with optionally registered outputs
- Routing architecture:
- 10% L = 1, fc_in = 0.15, Fc_out = 0.10
- 10% L = 2, fc_in = 0.15, Fc_out = 0.10
- 80% L = 4, fc_in = 0.15, Fc_out = 0.10
- 100 routing tracks per channel
Authors: Xifan Tang
-->
<architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports.
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch)
that describe them.
-->
<models>
<!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io">
<input_ports>
<port name="outpad"/>
</input_ports>
<output_ports>
<port name="inpad"/>
</output_ports>
</model>
<model name="frac_lut4">
<input_ports>
<port name="in"/>
</input_ports>
<output_ports>
<port name="lut3_out"/>
<port name="lut4_out"/>
</output_ports>
</model>
<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
<model name="scff">
<input_ports>
<port name="D" clock="clk"/>
<port name="DI" clock="clk"/>
<port name="clk" is_clock="1"/>
</input_ports>
<output_ports>
<port name="Q" clock="clk"/>
</output_ports>
</model>
</models>
<tiles>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="1" area="0">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</tile>
<!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="1" area="0">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</tile>
<!-- Bottom-side has 6 I/O per tile -->
<tile name="io_bottom" capacity="6" area="0">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</tile>
<!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="1" area="0">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</tile>
<!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
<input name="I0" num_pins="3" equivalent="full"/>
<input name="I0i" num_pins="1" equivalent="none"/>
<input name="I1" num_pins="3" equivalent="full"/>
<input name="I1i" num_pins="1" equivalent="none"/>
<input name="I2" num_pins="3" equivalent="full"/>
<input name="I2i" num_pins="1" equivalent="none"/>
<input name="I3" num_pins="3" equivalent="full"/>
<input name="I3i" num_pins="1" equivalent="none"/>
<input name="I4" num_pins="3" equivalent="full"/>
<input name="I4i" num_pins="1" equivalent="none"/>
<input name="I5" num_pins="3" equivalent="full"/>
<input name="I5i" num_pins="1" equivalent="none"/>
<input name="I6" num_pins="3" equivalent="full"/>
<input name="I6i" num_pins="1" equivalent="none"/>
<input name="I7" num_pins="3" equivalent="full"/>
<input name="I7i" num_pins="1" equivalent="none"/>
<input name="regin" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="O" num_pins="16" equivalent="none"/>
<output name="regout" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="regin" fc_type="frac" fc_val="0"/>
<fc_override port_name="regout" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc>
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="left">clb.clk</loc>
<loc side="top">clb.regin clb.sc_in clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i </loc>
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.regout clb.sc_out</loc>
</pinlocations>
</tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout tileable="true">
<auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<row type="io_top" starty="H-1" priority="100"/>
<row type="io_bottom" starty="0" priority="100"/>
<col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</auto_layout>
<fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<row type="io_top" starty="H-1" priority="100"/>
<row type="io_bottom" starty="0" priority="100"/>
<col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</fixed_layout>
<fixed_layout name="12x12" width="14" height="14">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<row type="io_top" starty="H-1" priority="100"/>
<row type="io_bottom" starty="0" priority="100"/>
<col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</fixed_layout>
</layout>
<device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
lined up with Stratix IV.
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
by 2.5x when looking up in Jeff's tables.
The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-->
<area grid_logic_tile_area="0"/>
<chan_width_distr>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
<connection_block input_switch_name="ipin_cblock"/>
</device>
<switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist>
<segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="L1_mux"/>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="L2_mux"/>
<sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1</cb>
</segment>
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="L4_mux"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
</segmentlist>
<directlist>
<direct name="shift_register" from_pin="clb.regout" to_pin="clb.regin" x_offset="0" y_offset="-1" z_offset="0"/>
<direct name="scan_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0"/>
</directlist>
<complexblocklist>
<!-- Define input pads begin -->
<pb_type name="io">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation
-->
<mode name="physical" disabled_in_pack="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them.
-->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin -->
<!-- -Due to the absence of local routing,
the 4 inputs of fracturable LUT4 are no longer equivalent,
because the 4th input can not be switched when the dual-LUT3 modes are used.
So pin equivalence should be applied to the first 3 inputs only
-->
<pb_type name="clb">
<input name="I0" num_pins="3" equivalent="full"/>
<input name="I0i" num_pins="1" equivalent="none"/>
<input name="I1" num_pins="3" equivalent="full"/>
<input name="I1i" num_pins="1" equivalent="none"/>
<input name="I2" num_pins="3" equivalent="full"/>
<input name="I2i" num_pins="1" equivalent="none"/>
<input name="I3" num_pins="3" equivalent="full"/>
<input name="I3i" num_pins="1" equivalent="none"/>
<input name="I4" num_pins="3" equivalent="full"/>
<input name="I4i" num_pins="1" equivalent="none"/>
<input name="I5" num_pins="3" equivalent="full"/>
<input name="I5i" num_pins="1" equivalent="none"/>
<input name="I6" num_pins="3" equivalent="full"/>
<input name="I6i" num_pins="1" equivalent="none"/>
<input name="I7" num_pins="3" equivalent="full"/>
<input name="I7i" num_pins="1" equivalent="none"/>
<input name="regin" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="O" num_pins="16" equivalent="none"/>
<output name="regout" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered
-->
<pb_type name="fle" num_pb="8">
<input name="in" num_pins="4"/>
<input name="regin" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="out" num_pins="2"/>
<output name="regout" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true">
<pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/>
<input name="regin" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="out" num_pins="2"/>
<output name="regout" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<pb_type name="frac_logic" num_pb="1">
<input name="in" num_pins="4"/>
<output name="out" num_pins="2"/>
<!-- Define LUT -->
<pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
<input name="in" num_pins="4"/>
<output name="lut3_out" num_pins="2"/>
<output name="lut4_out" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
<direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
<mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
</interconnect>
</pb_type>
<!-- Define flip-flop with scan-chain capability, DI is the scan-chain data input -->
<pb_type name="ff" blif_model=".subckt scff" num_pb="2">
<input name="D" num_pins="1"/>
<input name="DI" num_pins="1"/>
<output name="Q" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_setup value="66e-12" port="ff.DI" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="fabric.sc_in" output="ff[0].DI"/>
<direct name="direct3" input="ff[0].Q" output="ff[1].DI"/>
<direct name="direct4" input="ff[1].Q" output="fabric.sc_out"/>
<direct name="direct5" input="ff[1].Q" output="fabric.regout"/>
<direct name="direct6" input="frac_logic.out[1:1]" output="ff[1:1].D"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="frac_logic.out[0:0] fabric.regin" output="ff[0:0].D">
<delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="45e-12" in_port="fabric.regin" out_port="ff[0:0].D"/>
</mux>
<mux name="mux2" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux>
<mux name="mux3" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in" output="fabric.in"/>
<direct name="direct3" input="fle.regin" output="fabric.regin"/>
<direct name="direct4" input="fle.sc_in" output="fabric.sc_in"/>
<direct name="direct5" input="fabric.out" output="fle.out"/>
<direct name="direct7" input="fabric.regout" output="fle.regout"/>
<direct name="direct8" input="fabric.sc_out" output="fle.sc_out"/>
<direct name="direct9" input="fle.clk" output="fabric.clk"/>
</interconnect>
</mode>
<!-- Physical mode definition end (physical implementation of the fle) -->
<!-- Dual 3-LUT mode definition begin -->
<mode name="n2_lut3">
<pb_type name="lut3inter" num_pb="1">
<input name="in" num_pins="3"/>
<output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/>
<pb_type name="ble3" num_pb="2">
<input name="in" num_pins="3"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define the LUT -->
<pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
-->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
235e-12
235e-12
235e-12
</delay_matrix>
</pb_type>
<!-- Define the flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
</direct>
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
<direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
<direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
<complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
<direct name="direct2" input="lut3inter.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
</interconnect>
</mode>
<!-- Dual 3-LUT mode definition end -->
<!-- 4-LUT mode definition begin -->
<mode name="n1_lut4">
<!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
397e-12
-->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12
261e-12
261e-12
261e-12
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect>
</mode>
<!-- 4-LUT mode definition end -->
<!-- Define shift register begin -->
<mode name="shift_register">
<pb_type name="shift_reg" num_pb="1">
<input name="regin" num_pins="1"/>
<output name="regout" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="shift_reg.regin" output="ff[0].D"/>
<direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
<direct name="direct3" input="ff[1].Q" output="shift_reg.regout"/>
<complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.regin" output="shift_reg.regin"/>
<direct name="direct2" input="shift_reg.regout" output="fle.regout"/>
<direct name="direct3" input="fle.clk" output="shift_reg.clk"/>
</interconnect>
</mode>
<!-- Define shift register end -->
</pb_type>
<interconnect>
<!-- We use direct connections to reduce the area to the most
The global local routing is going to compensate the loss in routability
-->
<!-- FIXME: The implicit port definition results in I0[0] connected to
in[2]. Such twisted connection is not expected.
I[0] should be connected to in[0]
-->
<direct name="direct_fle0" input="clb.I0[0:2]" output="fle[0:0].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle1" input="clb.I1[0:2]" output="fle[1:1].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle2" input="clb.I2[0:2]" output="fle[2:2].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle3" input="clb.I3[0:2]" output="fle[3:3].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle4" input="clb.I4[0:2]" output="fle[4:4].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle5" input="clb.I5[0:2]" output="fle[5:5].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle6" input="clb.I6[0:2]" output="fle[6:6].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle7" input="clb.I7[0:2]" output="fle[7:7].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<complete name="clks" input="clb.clk" output="fle[7:0].clk">
</complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification).
-->
<direct name="clbouts1" input="fle[3:0].out[0:1]" output="clb.O[7:0]"/>
<direct name="clbouts2" input="fle[7:4].out[0:1]" output="clb.O[15:8]"/>
<!-- Shift register chain links -->
<direct name="shift_register_in" input="clb.regin" output="fle[0:0].regin">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
<!--pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/-->
</direct>
<direct name="shift_register_out" input="fle[7:7].regout" output="clb.regout">
<!--pack_pattern name="chain" in_port="fle[7:7].regout" out_port="clb.regout"/-->
</direct>
<direct name="shift_register_link" input="fle[6:0].regout" output="fle[7:1].regin">
<!--pack_pattern name="chain" in_port="fle[6:0].regout" out_port="fle[7:1].regin"/-->
</direct>
<!-- Scan chain links -->
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
</direct>
<direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
</direct>
<direct name="scan_chain_link" input="fle[6:0].sc_out" output="fle[7:1].sc_in">
</direct>
</interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column -->
</pb_type>
<!-- Define general purpose logic block (CLB) ends -->
</complexblocklist>
</architecture>

37
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task.conf
View File

@ -1,37 +0,0 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=40
[ARCHITECTURES]
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS]
bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
[SYNTHESIS_PARAM]
bench0_top = top
bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
vpr_fpga_verilog_formal_verification_top_netlist=

37
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task_generation.conf
View File

@ -1,37 +0,0 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=40
[ARCHITECTURES]
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS]
bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
[SYNTHESIS_PARAM]
bench0_top = top
bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
vpr_fpga_verilog_formal_verification_top_netlist=

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