mirror of https://github.com/lnis-uofu/SOFA.git
Merge pull request #118 from lnis-uofu/gg_demo
[Flow] Updated CHD design
This commit is contained in:
ganeshgore
GitHub
commit
c6b6bd7536
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@ -0,0 +1 @@
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../../BENCHMARK
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@ -288,10 +288,10 @@
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</direct_connection>
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<tile_annotations>
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<global_port name="clk" is_clock="true" default_val="0">
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<tile name=="clb" port="clk" x="-1" y="-1"/>
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<tile name="clb" port="clk" x="-1" y="-1"/>
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</global_port>
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<global_port name="Reset" is_reset="true" default_val="1">
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<tile name=="clb" port="reset" x="-1" y="-1"/>
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<tile name="clb" port="reset" x="-1" y="-1"/>
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</global_port>
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</tile_annotations>
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<pb_type_annotations>
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@ -1,5 +1,5 @@
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<!--
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Low-cost homogeneous FPGA Architecture.
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Low-cost homogeneous FPGA Architecture for SOFA_CHD.
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- Skywater 130 nm technology
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- General purpose logic block:
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@ -202,23 +202,18 @@
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</fixed_layout>
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<fixed_layout name="16x16" width="18" height="18">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<row type="io_top" starty="H-1" priority="100"/>
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<row type="io_bottom" starty="0" priority="100"/>
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<col type="io_left" startx="0" priority="100"/>
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<col type="io_right" startx="W-1" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</fixed_layout>
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</layout>
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<device>
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<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
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models. We are modifying the delay values however, to include metal C and R, which allows more architecture
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experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
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(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
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45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
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RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
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lined up with Stratix IV.
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We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
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Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
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The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
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by 2.5x when looking up in Jeff's tables.
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The delay values are lined up with Stratix IV, which has an architecture similar to this
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proposed FPGA, and which is also 40 nm
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C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
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4x minimum drive strength buffer. -->
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<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
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<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
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area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
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@ -232,41 +227,25 @@
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<connection_block input_switch_name="ipin_cblock"/>
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</device>
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<switchlist>
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<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
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book area formula. This means the mux transistors are about 5x minimum drive strength.
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We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
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mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
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the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
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by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
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buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
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I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
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(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
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The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
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2.5x when looking up in Jeff's tables.
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Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
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This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
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<switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<switch type="mux" name="L1_mux" R="0" Cin="0" Cout="0" Tdel="${L1_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
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<switch type="mux" name="L2_mux" R="0" Cin="0" Cout="0" Tdel="${L2_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
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<switch type="mux" name="L4_mux" R="0" Cin="0" Cout="0" Tdel="${L4_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
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<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
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<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
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<switch type="mux" name="ipin_cblock" R="0" Cout="0" Cin="0" Tdel="${CB_MUX_DELAY}" mux_trans_size="1.222260" buf_size="auto"/>
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</switchlist>
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<segmentlist>
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<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
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With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
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reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
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<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
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<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
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<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="${L1_WIRE_R}" Cmetal="${L1_WIRE_C}">
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<mux name="L1_mux"/>
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<sb type="pattern">1 1</sb>
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<cb type="pattern">1</cb>
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</segment>
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<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15">
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<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="${L2_WIRE_R}" Cmetal="${L2_WIRE_C}">
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<mux name="L2_mux"/>
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<sb type="pattern">1 1 1</sb>
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<cb type="pattern">1 1</cb>
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</segment>
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<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
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<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="${L4_WIRE_R}" Cmetal="${L4_WIRE_C}">
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<mux name="L4_mux"/>
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<sb type="pattern">1 1 1 1 1</sb>
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<cb type="pattern">1 1 1 1</cb>
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@ -296,10 +275,10 @@
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="iopad.outpad">
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
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<delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="iopad.outpad"/>
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</direct>
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<direct name="inpad" input="iopad.inpad" output="io.inpad">
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<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
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<delay_constant max="${INPAD_DELAY}" in_port="iopad.inpad" out_port="io.inpad"/>
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</direct>
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</interconnect>
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</mode>
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@ -315,7 +294,7 @@
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</pb_type>
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<interconnect>
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<direct name="inpad" input="inpad.inpad" output="io.inpad">
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<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
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<delay_constant max="${INPAD_DELAY}" in_port="inpad.inpad" out_port="io.inpad"/>
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</direct>
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</interconnect>
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</mode>
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@ -325,7 +304,7 @@
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="outpad.outpad">
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
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<delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="outpad.outpad"/>
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</direct>
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</interconnect>
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</mode>
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@ -430,10 +409,10 @@
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<input name="reset" num_pins="1"/>
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<output name="Q" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_setup value="66e-12" port="ff.DI" clock="clk"/>
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<T_setup value="66e-12" port="ff.reset" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
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<T_setup value="${FF_T_SETUP}" port="ff.DI" clock="clk"/>
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<T_setup value="${FF_T_SETUP}" port="ff.reset" clock="clk"/>
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<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
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@ -446,22 +425,22 @@
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<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
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<complete name="complete2" input="fabric.reset" output="ff[1:0].reset"/>
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<mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
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<delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
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<delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
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<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
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<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
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</mux>
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<mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
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<delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
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<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
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<delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
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<delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
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</mux>
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<mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
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<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
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<delay_constant max="${LUT_OUT0_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
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<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="fabric.out[0]"/>
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</mux>
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<mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
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<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
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<delay_constant max="${LUT_OUT1_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
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<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="fabric.out[1]"/>
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</mux>
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</interconnect>
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</pb_type>
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@ -494,18 +473,10 @@
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<input name="in" num_pins="3" port_class="lut_in"/>
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<output name="out" num_pins="1" port_class="lut_out"/>
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<!-- LUT timing using delay matrix -->
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<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
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we instead take the average of these numbers to get more stable results
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82e-12
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173e-12
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261e-12
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263e-12
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398e-12
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-->
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<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
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235e-12
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235e-12
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235e-12
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${LUT3_DELAY}
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${LUT3_DELAY}
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${LUT3_DELAY}
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</delay_matrix>
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</pb_type>
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<!-- Define the flip-flop -->
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@ -513,8 +484,8 @@
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
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@ -525,8 +496,8 @@
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<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
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<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
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<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
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<delay_constant max="${LUT3_OUT_TO_FLE_OUT_DELAY}" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
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<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
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</mux>
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</interconnect>
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</pb_type>
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@ -556,20 +527,11 @@
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<input name="in" num_pins="4" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
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<!-- LUT timing using delay matrix -->
|
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<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||
we instead take the average of these numbers to get more stable results
|
||||
82e-12
|
||||
173e-12
|
||||
261e-12
|
||||
263e-12
|
||||
398e-12
|
||||
397e-12
|
||||
-->
|
||||
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
${LUT4_DELAY}
|
||||
${LUT4_DELAY}
|
||||
${LUT4_DELAY}
|
||||
${LUT4_DELAY}
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<!-- Define flip-flop -->
|
||||
|
|
@ -577,20 +539,21 @@
|
|||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
|
||||
<direct name="direct2" input="lut4.out" output="ff.D">
|
||||
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
|
||||
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut4.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
|
||||
<delay_constant max="${LUT4_OUT_TO_FLE_OUT_DELAY}" in_port="lut4.out" out_port="ble4.out"/>
|
||||
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff.Q" out_port="ble4.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
|
|
@ -612,15 +575,23 @@
|
|||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D"/>
|
||||
<direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
|
||||
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D">
|
||||
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="shift_reg.reg_in" out_port="ff[0].D"/>
|
||||
</direct>
|
||||
<direct name="direct2" input="ff[0].Q" output="ff[1].D">
|
||||
<delay_constant max="${FF0_TO_FF1_DELAY}" in_port="ff[0].Q" out_port="ff[1].D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
|
||||
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]"/>
|
||||
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]"/>
|
||||
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]">
|
||||
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="shift_reg.ff_out[0:0]"/>
|
||||
</direct>
|
||||
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]">
|
||||
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="shift_reg.ff_out[1:1]"/>
|
||||
</direct>
|
||||
<complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
|
|
@ -642,52 +613,36 @@
|
|||
I[0] should be connected to in[0]
|
||||
-->
|
||||
<direct name="direct_fle0" input="clb.I0[0:1]" output="fle[0:0].in[0:1]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<direct name="direct_fle0i" input="clb.I0i[0:1]" output="fle[0:0].in[2:3]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<direct name="direct_fle1" input="clb.I1[0:1]" output="fle[1:1].in[0:1]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<direct name="direct_fle1i" input="clb.I1i[0:1]" output="fle[1:1].in[2:3]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<direct name="direct_fle2" input="clb.I2[0:1]" output="fle[2:2].in[0:1]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<direct name="direct_fle2i" input="clb.I2i[0:1]" output="fle[2:2].in[2:3]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<direct name="direct_fle3" input="clb.I3[0:1]" output="fle[3:3].in[0:1]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<direct name="direct_fle3i" input="clb.I3i[0:1]" output="fle[3:3].in[2:3]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<direct name="direct_fle4" input="clb.I4[0:1]" output="fle[4:4].in[0:1]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<direct name="direct_fle4i" input="clb.I4i[0:1]" output="fle[4:4].in[2:3]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<direct name="direct_fle5" input="clb.I5[0:1]" output="fle[5:5].in[0:1]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<direct name="direct_fle5i" input="clb.I5i[0:1]" output="fle[5:5].in[2:3]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<direct name="direct_fle6" input="clb.I6[0:1]" output="fle[6:6].in[0:1]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<direct name="direct_fle6i" input="clb.I6i[0:1]" output="fle[6:6].in[2:3]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<direct name="direct_fle7" input="clb.I7[0:1]" output="fle[7:7].in[0:1]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<direct name="direct_fle7i" input="clb.I7i[0:1]" output="fle[7:7].in[2:3]">
|
||||
<!-- TODO: Timing should be backannotated from post-PnR results -->
|
||||
</direct>
|
||||
<complete name="clks" input="clb.clk" output="fle[7:0].clk">
|
||||
</complete>
|
||||
|
|
@ -703,7 +658,7 @@
|
|||
<!-- Shift register chain links -->
|
||||
<direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
|
||||
<!-- Put all inter-block carry chain delay on this one edge -->
|
||||
<delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
|
||||
<delay_constant max="0" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
|
||||
<!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
|
||||
</direct>
|
||||
<direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
|
||||
|
|
@ -715,7 +670,7 @@
|
|||
<!-- Scan chain links -->
|
||||
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
|
||||
<!-- Put all inter-block carry chain delay on this one edge -->
|
||||
<delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
|
||||
<delay_constant max="0" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
|
||||
</direct>
|
||||
<direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
|
||||
</direct>
|
||||
|
|
@ -724,7 +679,7 @@
|
|||
<!-- Carry chain links -->
|
||||
<direct name="carry_chain_in" input="clb.cin" output="fle[0:0].cin">
|
||||
<!-- Put all inter-block carry chain delay on this one edge -->
|
||||
<delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
|
||||
<delay_constant max="0" in_port="clb.cin" out_port="fle[0:0].cin"/>
|
||||
</direct>
|
||||
<direct name="carry_chain_out" input="fle[7:7].cout" output="clb.cout">
|
||||
</direct>
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
|
|
@ -8,16 +8,17 @@
|
|||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_analysis = false
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
fpga_flow=vpr_blif
|
||||
timeout_each_job = 1*60
|
||||
fpga_flow=yosys_vpr
|
||||
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
|
||||
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
|
||||
openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
|
||||
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
|
||||
|
|
@ -28,12 +29,26 @@ openfpga_vpr_route_chan_width=60
|
|||
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
|
||||
bench0=${PATH:TASK_DIR}/BENCHMARK/and2/and2.v
|
||||
bench1=${PATH:TASK_DIR}/BENCHMARK/and2_latch/and2_latch.v
|
||||
bench2=${PATH:TASK_DIR}/BENCHMARK/bin2bcd/bin2bcd.v
|
||||
bench3=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
|
||||
bench4=${PATH:TASK_DIR}/BENCHMARK/routing_test/routing_test.v
|
||||
# RS decoder needs 1.5k LUT4, exceeding device capacity
|
||||
#bench5=${PATH:TASK_DIR}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
|
||||
bench6=${PATH:TASK_DIR}/BENCHMARK/simon_bit_serial/rtl/*.v
|
||||
bench7=${PATH:TASK_DIR}/BENCHMARK/and2_or2/and2_or2.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = top
|
||||
bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
|
||||
bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
|
||||
bench0_top = and2
|
||||
bench1_top = and2_latch
|
||||
bench2_top = bin2bcd
|
||||
bench3_top = counter
|
||||
bench4_top = routing_test
|
||||
# RS decoder needs 1.5k LUT4, exceeding device capacity
|
||||
#bench5_top = rs_decoder_top
|
||||
bench6_top = top_module
|
||||
bench7_top = and2_or2
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
vpr_fpga_verilog_formal_verification_top_netlist=
|
||||
#end_flow_with_test=
|
||||
|
|
|
|||
|
|
@ -1 +1,26 @@
|
|||
DELAY_VALUE: 12
|
||||
L1_SB_MUX_DELAY: 0.81e-9
|
||||
L2_SB_MUX_DELAY: 0.81e-9
|
||||
L4_SB_MUX_DELAY: 0.81e-9
|
||||
CB_MUX_DELAY: 0.57e-9
|
||||
L1_WIRE_R: 100
|
||||
L1_WIRE_C: 1e-12
|
||||
L2_WIRE_R: 100
|
||||
L2_WIRE_C: 1e-12
|
||||
L4_WIRE_R: 100
|
||||
L4_WIRE_C: 1e-12
|
||||
INPAD_DELAY: 0.11e-9
|
||||
OUTPAD_DELAY: 0.11e-9
|
||||
FF_T_SETUP: 0.39e-9
|
||||
FF_T_CLK2Q: 0.43e-9
|
||||
LUT_OUT0_TO_FF_D_DELAY: 0.32e-9
|
||||
LUT_OUT1_TO_FF_D_DELAY: 0.16e-9
|
||||
LUT_OUT0_TO_FLE_OUT_DELAY: 0.65e-9
|
||||
FF0_Q_TO_FLE_OUT_DELAY: 0.48e-9
|
||||
LUT_OUT1_TO_FLE_OUT_DELAY: 0.47e-9
|
||||
FF1_Q_TO_FLE_OUT_DELAY: 0.37e-9
|
||||
LUT3_DELAY: 0.86e-9
|
||||
LUT3_OUT_TO_FLE_OUT_DELAY: 0.65e-9
|
||||
LUT4_DELAY: 1.20e-9
|
||||
LUT4_OUT_TO_FLE_OUT_DELAY: 0.66e-9
|
||||
REGIN_TO_FF0_DELAY: 0.15e-9
|
||||
FF0_TO_FF1_DELAY: 0.16e-9
|
||||
|
|
|
|||
|
|
@ -36,9 +36,19 @@ write_fabric_bitstream --format xml --file fabric_bitstream.xml
|
|||
|
||||
# Write the Verilog netlist for FPGA fabric
|
||||
# - Enable the use of explicit port mapping in Verilog netlist
|
||||
write_fabric_verilog --file ./SRC --explicit_port_mapping --verbose
|
||||
write_fabric_verilog \
|
||||
--file ./SRC \
|
||||
--explicit_port_mapping \
|
||||
--include_timing \
|
||||
--verbose
|
||||
|
||||
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
|
||||
write_verilog_testbench \
|
||||
--file ./SRC \
|
||||
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
|
||||
--print_top_testbench \
|
||||
--print_preconfig_top_testbench \
|
||||
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
|
||||
--explicit_port_mapping
|
||||
|
||||
# Write the SDC files for PnR backend
|
||||
# - Turn on every options here
|
||||
|
|
|
|||
|
|
@ -1,6 +1,12 @@
|
|||
# Run VPR for the 'and' design
|
||||
# This script is designed to generate Verilog testbenches
|
||||
# with a fixed device layout
|
||||
# It will only output netlists to be used by verification tools
|
||||
# including
|
||||
# - Verilog testbenches, used by ModelSim
|
||||
# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
|
||||
#
|
||||
#--write_rr_graph example_rr_graph.xml
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --route_chan_width 200
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
|
||||
|
||||
# Read OpenFPGA architecture definition
|
||||
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
||||
|
|
@ -24,11 +30,7 @@ lut_truth_table_fixup
|
|||
# Build the module graph
|
||||
# - Enabled compression on routing architecture modules
|
||||
# - Enable pin duplication on grid modules
|
||||
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE}
|
||||
|
||||
# Write the fabric hierarchy of module graph to a file
|
||||
# This is used by hierarchical PnR flows
|
||||
write_fabric_hierarchy --file ./fabric_hierarchy.txt
|
||||
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
|
||||
|
||||
# Repack the netlist to physical pbs
|
||||
# This must be done before bitstream generator and testbench generation
|
||||
|
|
@ -37,28 +39,29 @@ repack #--verbose
|
|||
|
||||
# Build the bitstream
|
||||
# - Output the fabric-independent bitstream to a file
|
||||
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
|
||||
|
||||
build_fabric_bitstream
|
||||
build_architecture_bitstream --verbose --write_file arch_bitstream.xml
|
||||
|
||||
# Build fabric-dependent bitstream
|
||||
build_fabric_bitstream
|
||||
write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
|
||||
write_fabric_bitstream --format xml --file fabric_bitstream.xml
|
||||
build_fabric_bitstream --verbose
|
||||
|
||||
# Write fabric-dependent bitstream
|
||||
write_fabric_bitstream --file fabric_bitstream.xml --format xml
|
||||
|
||||
# Write the Verilog testbench for FPGA fabric
|
||||
# - We suggest the use of same output directory as fabric Verilog netlists
|
||||
# - Must specify the reference benchmark file if you want to output any testbenches
|
||||
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
|
||||
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
|
||||
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
|
||||
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
|
||||
|
||||
# Write the SDC files for PnR backend
|
||||
# - Turn on every options here
|
||||
write_pnr_sdc --file ./SDC
|
||||
|
||||
# Write SDC to disable timing for configure ports
|
||||
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
|
||||
write_verilog_testbench --file ./SRC \
|
||||
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
|
||||
--print_top_testbench \
|
||||
--print_preconfig_top_testbench \
|
||||
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
|
||||
--explicit_port_mapping
|
||||
# Exclude signal initialization since it does not help simulator converge
|
||||
# due to the lack of reset pins for flip-flops
|
||||
#--include_signal_init
|
||||
|
||||
# Write the SDC to run timing analysis for a mapped FPGA fabric
|
||||
write_analysis_sdc --file ./SDC_analysis
|
||||
|
|
@ -67,4 +70,4 @@ write_analysis_sdc --file ./SDC_analysis
|
|||
exit
|
||||
|
||||
# Note :
|
||||
# To run verification at the end of the flow maintain source in ./SRC directory
|
||||
# To run verification at the end of the flow maintain source in ./SRC directory
|
||||
|
|
|
|||
Loading…
Reference in New Issue