mirror of https://github.com/lnis-uofu/SOFA.git
Merge pull request #106 from lnis-uofu/xt_dev
Add bitstream generation flow-run
This commit is contained in:
tangxifan
GitHub
commit
2c0e779758
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# This script is designed to generate bitstream
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# with a fixed device layout, which can be used for bitstream loaders
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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# Apply fix-up to clustering nets based on routing results
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pb_pin_fixup #--verbose
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# Apply fix-up to Look-Up Table truth tables based on packing results
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lut_truth_table_fixup
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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# - Enabled frame view creation to save runtime and memory
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# Note that this is turned on when bitstream generation
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# is the ONLY purpose of the flow!!!
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build_fabric --compress_routing --duplicate_grid_pin --frame_view --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
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# Repack the netlist to physical pbs
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# This must be done before bitstream generator and testbench generation
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# Strongly recommend it is done after all the fix-up have been applied
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repack #--verbose
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# Build the bitstream
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# - Output the fabric-independent bitstream to a file
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build_architecture_bitstream --verbose --write_file arch_bitstream.xml
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# Build fabric-dependent bitstream
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build_fabric_bitstream --verbose
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# Write fabric-dependent bitstream
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write_fabric_bitstream --file fabric_bitstream.txt --format plain_text
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write_fabric_bitstream --file fabric_bitstream.xml --format xml
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# Finish and exit OpenFPGA
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exit
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 1*60
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fpga_flow=yosys_vpr
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arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
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[OpenFPGA_SHELL]
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openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
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openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
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openfpga_vpr_device_layout=12x12
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openfpga_vpr_route_chan_width=40
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external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
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[ARCHITECTURES]
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arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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[BENCHMARKS]
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bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
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bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
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bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
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bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
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bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
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# RS decoder needs 1.5k LUT4, exceeding device capacity
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#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
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bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
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bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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bench1_top = and2_latch
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bench2_top = bin2bcd
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bench3_top = counter
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bench4_top = routing_test
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# RS decoder needs 1.5k LUT4, exceeding device capacity
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#bench5_top = rs_decoder_top
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bench6_top = top_module
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bench7_top = and2_or2
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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#end_flow_with_test=
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 1*60
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fpga_flow=yosys_vpr
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arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
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[OpenFPGA_SHELL]
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openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
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openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
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openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
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openfpga_vpr_device_layout=12x12
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openfpga_vpr_route_chan_width=60
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external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
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[ARCHITECTURES]
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arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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[BENCHMARKS]
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bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
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bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
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bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
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bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
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bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
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# RS decoder needs 1.5k LUT4, exceeding device capacity
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#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
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bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
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bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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bench1_top = and2_latch
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bench2_top = bin2bcd
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bench3_top = counter
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bench4_top = routing_test
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# RS decoder needs 1.5k LUT4, exceeding device capacity
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#bench5_top = rs_decoder_top
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bench6_top = top_module
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bench7_top = and2_or2
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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#end_flow_with_test=
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@ -0,0 +1,53 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 1*60
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fpga_flow=yosys_vpr
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arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
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[OpenFPGA_SHELL]
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openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
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openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
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openfpga_vpr_device_layout=12x12
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openfpga_vpr_route_chan_width=60
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external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
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[ARCHITECTURES]
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arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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[BENCHMARKS]
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bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
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bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
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bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
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bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
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bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
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# RS decoder needs 1.5k LUT4, exceeding device capacity
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#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
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bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
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bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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bench1_top = and2_latch
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bench2_top = bin2bcd
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bench3_top = counter
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bench4_top = routing_test
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# RS decoder needs 1.5k LUT4, exceeding device capacity
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#bench5_top = rs_decoder_top
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bench6_top = top_module
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bench7_top = and2_or2
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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#end_flow_with_test=
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