diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
new file mode 100644
index 0000000..295c863
--- /dev/null
+++ b/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
@@ -0,0 +1,49 @@
+# This script is designed to generate bitstream
+# with a fixed device layout, which can be used for bitstream loaders
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup #--verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+#  - Enabled frame view creation to save runtime and memory
+#    Note that this is turned on when bitstream generation 
+#    is the ONLY purpose of the flow!!!
+build_fabric --compress_routing --duplicate_grid_pin --frame_view --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file arch_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.txt --format plain_text
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
+
+# Finish and exit OpenFPGA
+exit
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_bitstream/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_bitstream/config/task_template.conf
new file mode 100644
index 0000000..da59633
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_bitstream/config/task_template.conf
@@ -0,0 +1,53 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
+openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=40
+external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
+
+[ARCHITECTURES]
+arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
+bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
+bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
+bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
+bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
+bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
+bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench1_top = and2_latch
+bench2_top = bin2bcd
+bench3_top = counter
+bench4_top = routing_test
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5_top = rs_decoder_top
+bench6_top = top_module
+bench7_top = and2_or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_bitstream/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_bitstream/config/task_template.conf
new file mode 100644
index 0000000..770d490
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_bitstream/config/task_template.conf
@@ -0,0 +1,53 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
+openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
+openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=60
+external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
+
+[ARCHITECTURES]
+arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
+bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
+bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
+bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
+bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
+bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
+bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench1_top = and2_latch
+bench2_top = bin2bcd
+bench3_top = counter
+bench4_top = routing_test
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5_top = rs_decoder_top
+bench6_top = top_module
+bench7_top = and2_or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_bitstream/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_bitstream/config/task_template.conf
new file mode 100644
index 0000000..9a4a1a0
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_bitstream/config/task_template.conf
@@ -0,0 +1,53 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
+openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=60
+external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
+
+[ARCHITECTURES]
+arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
+bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
+bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
+bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
+bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
+bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
+bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench1_top = and2_latch
+bench2_top = bin2bcd
+bench3_top = counter
+bench4_top = routing_test
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5_top = rs_decoder_top
+bench6_top = top_module
+bench7_top = and2_or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=