Added global signal feedthrough

SOFA_A/CommonFiles/restructure_fabric_sofa_a.py

@@ -251,6 +251,7 @@ def main():
         instance_map[int(x)][int(y)] = inst.name
     create_global_feedthrough(fpga, "reset", instance_map)
     create_global_feedthrough(fpga, "prog_reset", instance_map)
+    create_global_feedthrough(fpga, "test_enable", instance_map)
 
     save_netlist(fpga)
     filename = SVG_DIR + f"{PROJ_NAME}_floorplan.svg"

SOFA_A/FPGA88_SOFA_A/.spydrnet

@@ -1 +1 @@
-spydrnet_physical
+spydrnet_physical

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/arch/openfpga_arch.xml

@@ -154,7 +154,7 @@
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <port type="input" prefix="D" size="1"/>
       <port type="input" prefix="DI" lib_name="SCD" size="1"/>
-      <port type="input" prefix="scan_enable" lib_name="SCE" size="1" is_global="true" default_val="0"/>
+      <port type="input" prefix="test_enable" lib_name="SCE" size="1" is_global="true" default_val="0"/>
       <port type="input" prefix="reset" lib_name="RESET_B" size="1" default_val="1"/>
       <port type="output" prefix="Q" size="1"/>
       <port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="false" default_val="0" />

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_clb.v

@@ -23,7 +23,7 @@ module grid_clb
     right_width_0_height_0_subtile_0__pin_I7_1_,
     right_width_0_height_0_subtile_0__pin_I7i_0_,
     right_width_0_height_0_subtile_0__pin_I7i_1_,
-    scan_enable,
+    test_enable,
     top_width_0_height_0_subtile_0__pin_I0_0_,
     top_width_0_height_0_subtile_0__pin_I0_1_,
     top_width_0_height_0_subtile_0__pin_I0i_0_,
@@ -86,7 +86,7 @@ module grid_clb
     input right_width_0_height_0_subtile_0__pin_I7_1_;
     input right_width_0_height_0_subtile_0__pin_I7i_0_;
     input right_width_0_height_0_subtile_0__pin_I7i_1_;
-    input scan_enable;
+    input test_enable;
     input top_width_0_height_0_subtile_0__pin_I0_0_;
     input top_width_0_height_0_subtile_0__pin_I0_1_;
     input top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -160,7 +160,7 @@ module grid_clb
     wire right_width_0_height_0_subtile_0__pin_O_15_;
     wire right_width_0_height_0_subtile_0__pin_O_8_;
     wire right_width_0_height_0_subtile_0__pin_O_9_;
-    wire scan_enable;
+    wire test_enable;
     wire top_width_0_height_0_subtile_0__pin_I0_0_;
     wire top_width_0_height_0_subtile_0__pin_I0_1_;
     wire top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -215,7 +215,7 @@ module grid_clb
         .clb_sc_in(top_width_0_height_0_subtile_0__pin_sc_in_0_),
         .prog_clk(prog_clk),
         .prog_reset(prog_reset),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ccff_tail(ccff_tail),
         .clb_O({top_width_0_height_0_subtile_0__pin_O_0_, top_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, top_width_0_height_0_subtile_0__pin_O_3_, top_width_0_height_0_subtile_0__pin_O_4_, top_width_0_height_0_subtile_0__pin_O_5_, top_width_0_height_0_subtile_0__pin_O_6_, top_width_0_height_0_subtile_0__pin_O_7_, right_width_0_height_0_subtile_0__pin_O_8_, right_width_0_height_0_subtile_0__pin_O_9_, right_width_0_height_0_subtile_0__pin_O_10_, right_width_0_height_0_subtile_0__pin_O_11_, right_width_0_height_0_subtile_0__pin_O_12_, right_width_0_height_0_subtile_0__pin_O_13_, right_width_0_height_0_subtile_0__pin_O_14_, right_width_0_height_0_subtile_0__pin_O_15_}),
         .clb_cout(bottom_width_0_height_0_subtile_0__pin_cout_0_),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_clb_.v

@@ -26,7 +26,7 @@ module logical_tile_clb_mode_clb_
     clb_sc_in,
     prog_clk,
     prog_reset,
-    scan_enable,
+    test_enable,
     ccff_tail,
     clb_O,
     clb_cout,
@@ -58,7 +58,7 @@ module logical_tile_clb_mode_clb_
     input clb_sc_in;
     input prog_clk;
     input prog_reset;
-    input scan_enable;
+    input test_enable;
     output ccff_tail;
     output [0:15]clb_O;
     output clb_cout;
@@ -205,7 +205,7 @@ module logical_tile_clb_mode_clb_
     wire logical_tile_clb_mode_default__fle_7_fle_sc_out;
     wire prog_clk;
     wire prog_reset;
-    wire scan_enable;
+    wire test_enable;
 
     direct_interc direct_interc_0_
     (
@@ -673,7 +673,7 @@ module logical_tile_clb_mode_clb_
         .fle_sc_in(direct_interc_24_out),
         .prog_clk(prog_clk),
         .prog_reset(prog_reset),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_0_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_0_fle_out),
@@ -691,7 +691,7 @@ module logical_tile_clb_mode_clb_
         .fle_sc_in(direct_interc_33_out),
         .prog_clk(prog_clk),
         .prog_reset(prog_reset),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_1_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_1_fle_out),
@@ -709,7 +709,7 @@ module logical_tile_clb_mode_clb_
         .fle_sc_in(direct_interc_42_out),
         .prog_clk(prog_clk),
         .prog_reset(prog_reset),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_2_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_2_fle_out),
@@ -727,7 +727,7 @@ module logical_tile_clb_mode_clb_
         .fle_sc_in(direct_interc_51_out),
         .prog_clk(prog_clk),
         .prog_reset(prog_reset),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_3_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_3_fle_out),
@@ -745,7 +745,7 @@ module logical_tile_clb_mode_clb_
         .fle_sc_in(direct_interc_60_out),
         .prog_clk(prog_clk),
         .prog_reset(prog_reset),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_4_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_4_fle_out),
@@ -763,7 +763,7 @@ module logical_tile_clb_mode_clb_
         .fle_sc_in(direct_interc_69_out),
         .prog_clk(prog_clk),
         .prog_reset(prog_reset),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_5_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_5_fle_out),
@@ -781,7 +781,7 @@ module logical_tile_clb_mode_clb_
         .fle_sc_in(direct_interc_78_out),
         .prog_clk(prog_clk),
         .prog_reset(prog_reset),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_6_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_6_fle_out),
@@ -799,7 +799,7 @@ module logical_tile_clb_mode_clb_
         .fle_sc_in(direct_interc_87_out),
         .prog_clk(prog_clk),
         .prog_reset(prog_reset),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ccff_tail(ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_7_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_7_fle_out),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle.v

@@ -11,7 +11,7 @@ module logical_tile_clb_mode_default__fle
     fle_sc_in,
     prog_clk,
     prog_reset,
-    scan_enable,
+    test_enable,
     ccff_tail,
     fle_cout,
     fle_out,
@@ -28,7 +28,7 @@ module logical_tile_clb_mode_default__fle
     input fle_sc_in;
     input prog_clk;
     input prog_reset;
-    input scan_enable;
+    input test_enable;
     output ccff_tail;
     output fle_cout;
     output [0:1]fle_out;
@@ -62,7 +62,7 @@ module logical_tile_clb_mode_default__fle
     wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out;
     wire prog_clk;
     wire prog_reset;
-    wire scan_enable;
+    wire test_enable;
 
     direct_interc direct_interc_0_
     (
@@ -145,7 +145,7 @@ module logical_tile_clb_mode_default__fle
         .fabric_sc_in(direct_interc_10_out),
         .prog_clk(prog_clk),
         .prog_reset(prog_reset),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ccff_tail(ccff_tail),
         .fabric_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout),
         .fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric.v

@@ -11,7 +11,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     fabric_sc_in,
     prog_clk,
     prog_reset,
-    scan_enable,
+    test_enable,
     ccff_tail,
     fabric_cout,
     fabric_out,
@@ -28,7 +28,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     input fabric_sc_in;
     input prog_clk;
     input prog_reset;
-    input scan_enable;
+    input test_enable;
     output ccff_tail;
     output fabric_cout;
     output [0:1]fabric_out;
@@ -78,7 +78,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     wire mux_tree_size2_mem_2_ccff_tail;
     wire prog_clk;
     wire prog_reset;
-    wire scan_enable;
+    wire test_enable;
 
     direct_interc direct_interc_0_
     (
@@ -156,7 +156,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
         .ff_DI(direct_interc_8_out),
         .ff_clk(direct_interc_10_out),
         .ff_reset(direct_interc_9_out),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q)
     );
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1
@@ -165,7 +165,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
         .ff_DI(direct_interc_11_out),
         .ff_clk(direct_interc_13_out),
         .ff_reset(direct_interc_12_out),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q)
     );
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v

@@ -6,7 +6,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
     ff_DI,
     ff_clk,
     ff_reset,
-    scan_enable,
+    test_enable,
     ff_Q
 );
 
@@ -14,7 +14,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
     input ff_DI;
     input ff_clk;
     input ff_reset;
-    input scan_enable;
+    input test_enable;
     output ff_Q;
 
     wire ff_D;
@@ -22,7 +22,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
     wire ff_Q;
     wire ff_clk;
     wire ff_reset;
-    wire scan_enable;
+    wire test_enable;
 
     sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_
     (
@@ -30,7 +30,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
         .D(ff_D),
         .RESET_B(ff_reset),
         .SCD(ff_DI),
-        .SCE(scan_enable),
+        .SCE(test_enable),
         .Q(ff_Q)
     );
 endmodule

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_left_tile.v

@@ -12,6 +12,7 @@ module bottom_left_tile
     right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
     right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
     right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
+    test_enable_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
     top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
     top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
@@ -31,6 +32,7 @@ module bottom_left_tile
     input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
+    input test_enable_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
     input top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
     input top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
@@ -53,6 +55,7 @@ module bottom_left_tile
     wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
+    wire test_enable_top_in;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
     wire top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
     wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_tile.v

@@ -16,6 +16,7 @@ module bottom_tile
     right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
     right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
     right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
+    test_enable_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
@@ -51,6 +52,7 @@ module bottom_tile
     input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
+    input test_enable_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@@ -96,6 +98,7 @@ module bottom_tile
     wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
+    wire test_enable_top_in;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/left_tile.v

@@ -24,6 +24,9 @@ module left_tile
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
+    test_enable_bottom_in,
+    test_enable_right_in,
+    test_enable_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
     top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
     top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
@@ -43,7 +46,9 @@ module left_tile
     right_width_0_height_0_subtile_0__pin_inpad_0_,
     right_width_0_height_0_subtile_1__pin_inpad_0_,
     right_width_0_height_0_subtile_2__pin_inpad_0_,
-    right_width_0_height_0_subtile_3__pin_inpad_0_
+    right_width_0_height_0_subtile_3__pin_inpad_0_,
+    test_enable_bottom_out,
+    test_enable_top_out
 );
 
     input ccff_head;
@@ -68,6 +73,9 @@ module left_tile
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
+    input test_enable_bottom_in;
+    input test_enable_right_in;
+    input test_enable_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
     input top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
     input top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
@@ -88,6 +96,8 @@ module left_tile
     output right_width_0_height_0_subtile_1__pin_inpad_0_;
     output right_width_0_height_0_subtile_2__pin_inpad_0_;
     output right_width_0_height_0_subtile_3__pin_inpad_0_;
+    output test_enable_bottom_out;
+    output test_enable_top_out;
 
     wire ccff_head;
     wire ccff_head_0;
@@ -130,6 +140,11 @@ module left_tile
     wire right_width_0_height_0_subtile_1__pin_inpad_0_;
     wire right_width_0_height_0_subtile_2__pin_inpad_0_;
     wire right_width_0_height_0_subtile_3__pin_inpad_0_;
+    wire test_enable_bottom_in;
+    wire test_enable_bottom_out;
+    wire test_enable_right_in;
+    wire test_enable_top_in;
+    wire test_enable_top_out;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
     wire top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
     wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
@@ -145,6 +160,10 @@ assign reset_top_out = reset_bottom_in;
 assign reset_top_in = reset_right_in;
 assign reset_bottom_in = reset_top_in;
 assign reset_bottom_out = reset_top_out;
+assign test_enable_top_out = test_enable_bottom_in;
+assign test_enable_top_in = test_enable_right_in;
+assign test_enable_bottom_in = test_enable_top_in;
+assign test_enable_bottom_out = test_enable_top_out;
     cby_0__1_ cby_0__1_
     (
         .ccff_head_0(ccff_head_0),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/right_tile.v

@@ -14,7 +14,7 @@ module right_tile
     prog_clk,
     prog_reset,
     reset,
-    scan_enable,
+    test_enable,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
@@ -75,7 +75,7 @@ module right_tile
     input prog_clk;
     input prog_reset;
     input reset;
-    input scan_enable;
+    input test_enable;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@@ -196,7 +196,7 @@ module right_tile
     wire right_width_0_height_0_subtile_0__pin_O_15_;
     wire right_width_0_height_0_subtile_0__pin_O_8_;
     wire right_width_0_height_0_subtile_0__pin_O_9_;
-    wire scan_enable;
+    wire test_enable;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@@ -308,7 +308,7 @@ module right_tile
         .right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/tile.v

@@ -24,7 +24,9 @@ module tile
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
-    scan_enable,
+    test_enable_bottom_in,
+    test_enable_right_in,
+    test_enable_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
@@ -59,6 +61,9 @@ module tile
     right_width_0_height_0_subtile_0__pin_O_15_,
     right_width_0_height_0_subtile_0__pin_O_8_,
     right_width_0_height_0_subtile_0__pin_O_9_,
+    test_enable_bottom_out,
+    test_enable_left_out,
+    test_enable_top_out,
     top_width_0_height_0_subtile_0__pin_O_0_,
     top_width_0_height_0_subtile_0__pin_O_1_,
     top_width_0_height_0_subtile_0__pin_O_2_,
@@ -91,7 +96,9 @@ module tile
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
-    input scan_enable;
+    input test_enable_bottom_in;
+    input test_enable_right_in;
+    input test_enable_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@@ -126,6 +133,9 @@ module tile
     output right_width_0_height_0_subtile_0__pin_O_15_;
     output right_width_0_height_0_subtile_0__pin_O_8_;
     output right_width_0_height_0_subtile_0__pin_O_9_;
+    output test_enable_bottom_out;
+    output test_enable_left_out;
+    output test_enable_top_out;
     output top_width_0_height_0_subtile_0__pin_O_0_;
     output top_width_0_height_0_subtile_0__pin_O_1_;
     output top_width_0_height_0_subtile_0__pin_O_2_;
@@ -220,7 +230,13 @@ module tile
     wire right_width_0_height_0_subtile_0__pin_O_15_;
     wire right_width_0_height_0_subtile_0__pin_O_8_;
     wire right_width_0_height_0_subtile_0__pin_O_9_;
-    wire scan_enable;
+    wire test_enable;
+    wire test_enable_bottom_in;
+    wire test_enable_bottom_out;
+    wire test_enable_left_out;
+    wire test_enable_right_in;
+    wire test_enable_top_in;
+    wire test_enable_top_out;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@@ -253,6 +269,12 @@ assign reset_left_out = reset;
 assign reset_top_in = reset_right_in;
 assign reset_bottom_in = reset_top_in;
 assign reset_bottom_out = reset_top_out;
+assign test_enable = test_enable_bottom_in;
+assign test_enable_top_out = test_enable_left_out;
+assign test_enable_top_in = test_enable_right_in;
+assign test_enable_left_out = test_enable;
+assign test_enable_bottom_in = test_enable_top_in;
+assign test_enable_bottom_out = test_enable_top_out;
     cbx_1__1_ cbx_1__1_
     (
         .ccff_head(ccff_tail_2),
@@ -330,7 +352,7 @@ assign reset_bottom_out = reset_top_out;
         .right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_right_tile.v

@@ -13,7 +13,7 @@ module top_right_tile
     prog_clk,
     prog_reset,
     reset,
-    scan_enable,
+    test_enable,
     top_width_0_height_0_subtile_0__pin_cin_0_,
     top_width_0_height_0_subtile_0__pin_reg_in_0_,
     top_width_0_height_0_subtile_0__pin_sc_in_0_,
@@ -65,7 +65,7 @@ module top_right_tile
     input prog_clk;
     input prog_reset;
     input reset;
-    input scan_enable;
+    input test_enable;
     input top_width_0_height_0_subtile_0__pin_cin_0_;
     input top_width_0_height_0_subtile_0__pin_reg_in_0_;
     input top_width_0_height_0_subtile_0__pin_sc_in_0_;
@@ -182,7 +182,7 @@ module top_right_tile
     wire right_width_0_height_0_subtile_0__pin_O_15_;
     wire right_width_0_height_0_subtile_0__pin_O_8_;
     wire right_width_0_height_0_subtile_0__pin_O_9_;
-    wire scan_enable;
+    wire test_enable;
     wire top_width_0_height_0_subtile_0__pin_O_0_;
     wire top_width_0_height_0_subtile_0__pin_O_1_;
     wire top_width_0_height_0_subtile_0__pin_O_2_;
@@ -290,7 +290,7 @@ module top_right_tile
         .right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v

@@ -25,7 +25,7 @@ module top_tile
     right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
     right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
     right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
-    scan_enable,
+    test_enable,
     top_width_0_height_0_subtile_0__pin_cin_0_,
     top_width_0_height_0_subtile_0__pin_reg_in_0_,
     top_width_0_height_0_subtile_0__pin_sc_in_0_,
@@ -84,7 +84,7 @@ module top_tile
     input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
     input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
     input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
-    input scan_enable;
+    input test_enable;
     input top_width_0_height_0_subtile_0__pin_cin_0_;
     input top_width_0_height_0_subtile_0__pin_reg_in_0_;
     input top_width_0_height_0_subtile_0__pin_sc_in_0_;
@@ -202,7 +202,7 @@ module top_tile
     wire right_width_0_height_0_subtile_0__pin_O_15_;
     wire right_width_0_height_0_subtile_0__pin_O_8_;
     wire right_width_0_height_0_subtile_0__pin_O_9_;
-    wire scan_enable;
+    wire test_enable;
     wire top_width_0_height_0_subtile_0__pin_O_0_;
     wire top_width_0_height_0_subtile_0__pin_O_1_;
     wire top_width_0_height_0_subtile_0__pin_O_2_;
@@ -300,7 +300,7 @@ module top_tile
         .right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/fpga_top.v

@@ -7,7 +7,7 @@ module fpga_top
     isol_n,
     prog_reset,
     prog_clk,
-    scan_enable,
+    test_enable,
     gfpga_pad_io_soc_in,
     gfpga_pad_io_soc_out,
     gfpga_pad_io_soc_dir,
@@ -20,7 +20,7 @@ module fpga_top
     input isol_n;
     input prog_reset;
     input prog_clk;
-    input scan_enable;
+    input test_enable;
     input [0:127]gfpga_pad_io_soc_in;
     output [0:127]gfpga_pad_io_soc_out;
     output [0:127]gfpga_pad_io_soc_dir;
@@ -32,7 +32,7 @@ module fpga_top
     wire isol_n;
     wire prog_reset;
     wire prog_clk;
-    wire scan_enable;
+    wire test_enable;
     wire [0:127]gfpga_pad_io_soc_in;
     wire [0:127]gfpga_pad_io_soc_out;
     wire [0:127]gfpga_pad_io_soc_dir;
@@ -5259,7 +5259,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5323,7 +5323,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5387,7 +5387,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5451,7 +5451,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5515,7 +5515,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5579,7 +5579,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5643,7 +5643,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5707,7 +5707,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5771,7 +5771,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5835,7 +5835,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5899,7 +5899,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5963,7 +5963,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6027,7 +6027,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6091,7 +6091,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6155,7 +6155,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6219,7 +6219,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6283,7 +6283,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6347,7 +6347,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6411,7 +6411,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6475,7 +6475,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6539,7 +6539,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6603,7 +6603,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6667,7 +6667,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6731,7 +6731,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6795,7 +6795,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6859,7 +6859,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6923,7 +6923,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6987,7 +6987,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7051,7 +7051,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7115,7 +7115,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7179,7 +7179,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7243,7 +7243,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7307,7 +7307,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7371,7 +7371,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7435,7 +7435,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7499,7 +7499,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7563,7 +7563,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7627,7 +7627,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7691,7 +7691,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7755,7 +7755,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7819,7 +7819,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7883,7 +7883,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7947,7 +7947,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8011,7 +8011,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8075,7 +8075,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8139,7 +8139,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8203,7 +8203,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8267,7 +8267,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8331,7 +8331,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8395,7 +8395,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8459,7 +8459,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8523,7 +8523,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8587,7 +8587,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8651,7 +8651,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8715,7 +8715,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8779,7 +8779,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8843,7 +8843,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8907,7 +8907,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8971,7 +8971,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9035,7 +9035,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9099,7 +9099,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9163,7 +9163,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9227,7 +9227,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9291,7 +9291,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_clb.v

@@ -4,7 +4,7 @@ module grid_clb
 (
     prog_reset,
     prog_clk,
-    scan_enable,
+    test_enable,
     top_width_0_height_0_subtile_0__pin_I0_0_,
     top_width_0_height_0_subtile_0__pin_I0_1_,
     top_width_0_height_0_subtile_0__pin_I0i_0_,
@@ -67,7 +67,7 @@ module grid_clb
 
     input prog_reset;
     input prog_clk;
-    input scan_enable;
+    input test_enable;
     input top_width_0_height_0_subtile_0__pin_I0_0_;
     input top_width_0_height_0_subtile_0__pin_I0_1_;
     input top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -129,7 +129,7 @@ module grid_clb
 
     wire prog_reset;
     wire prog_clk;
-    wire scan_enable;
+    wire test_enable;
     wire top_width_0_height_0_subtile_0__pin_I0_0_;
     wire top_width_0_height_0_subtile_0__pin_I0_1_;
     wire top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -193,7 +193,7 @@ module grid_clb
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}),
         .clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}),
         .clb_I1({top_width_0_height_0_subtile_0__pin_I1_0_, top_width_0_height_0_subtile_0__pin_I1_1_}),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_clb_.v

@@ -4,7 +4,7 @@ module logical_tile_clb_mode_clb_
 (
     prog_reset,
     prog_clk,
-    scan_enable,
+    test_enable,
     clb_I0,
     clb_I0i,
     clb_I1,
@@ -36,7 +36,7 @@ module logical_tile_clb_mode_clb_
 
     input prog_reset;
     input prog_clk;
-    input scan_enable;
+    input test_enable;
     input [0:1]clb_I0;
     input [0:1]clb_I0i;
     input [0:1]clb_I1;
@@ -67,7 +67,7 @@ module logical_tile_clb_mode_clb_
 
     wire prog_reset;
     wire prog_clk;
-    wire scan_enable;
+    wire test_enable;
     wire [0:1]clb_I0;
     wire [0:1]clb_I0i;
     wire [0:1]clb_I1;
@@ -211,7 +211,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_19_out, direct_interc_20_out, direct_interc_21_out, direct_interc_22_out}),
         .fle_reg_in(direct_interc_23_out),
         .fle_sc_in(direct_interc_24_out),
@@ -229,7 +229,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_28_out, direct_interc_29_out, direct_interc_30_out, direct_interc_31_out}),
         .fle_reg_in(direct_interc_32_out),
         .fle_sc_in(direct_interc_33_out),
@@ -247,7 +247,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_37_out, direct_interc_38_out, direct_interc_39_out, direct_interc_40_out}),
         .fle_reg_in(direct_interc_41_out),
         .fle_sc_in(direct_interc_42_out),
@@ -265,7 +265,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_46_out, direct_interc_47_out, direct_interc_48_out, direct_interc_49_out}),
         .fle_reg_in(direct_interc_50_out),
         .fle_sc_in(direct_interc_51_out),
@@ -283,7 +283,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_55_out, direct_interc_56_out, direct_interc_57_out, direct_interc_58_out}),
         .fle_reg_in(direct_interc_59_out),
         .fle_sc_in(direct_interc_60_out),
@@ -301,7 +301,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_64_out, direct_interc_65_out, direct_interc_66_out, direct_interc_67_out}),
         .fle_reg_in(direct_interc_68_out),
         .fle_sc_in(direct_interc_69_out),
@@ -319,7 +319,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_73_out, direct_interc_74_out, direct_interc_75_out, direct_interc_76_out}),
         .fle_reg_in(direct_interc_77_out),
         .fle_sc_in(direct_interc_78_out),
@@ -337,7 +337,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_82_out, direct_interc_83_out, direct_interc_84_out, direct_interc_85_out}),
         .fle_reg_in(direct_interc_86_out),
         .fle_sc_in(direct_interc_87_out),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle.v

@@ -4,7 +4,7 @@ module logical_tile_clb_mode_default__fle
 (
     prog_reset,
     prog_clk,
-    scan_enable,
+    test_enable,
     fle_in,
     fle_reg_in,
     fle_sc_in,
@@ -21,7 +21,7 @@ module logical_tile_clb_mode_default__fle
 
     input prog_reset;
     input prog_clk;
-    input scan_enable;
+    input test_enable;
     input [0:3]fle_in;
     input fle_reg_in;
     input fle_sc_in;
@@ -37,7 +37,7 @@ module logical_tile_clb_mode_default__fle
 
     wire prog_reset;
     wire prog_clk;
-    wire scan_enable;
+    wire test_enable;
     wire [0:3]fle_in;
     wire fle_reg_in;
     wire fle_sc_in;
@@ -68,7 +68,7 @@ module logical_tile_clb_mode_default__fle
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fabric_in({direct_interc_5_out, direct_interc_6_out, direct_interc_7_out, direct_interc_8_out}),
         .fabric_reg_in(direct_interc_9_out),
         .fabric_sc_in(direct_interc_10_out),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v

@@ -4,7 +4,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
 (
     prog_reset,
     prog_clk,
-    scan_enable,
+    test_enable,
     fabric_in,
     fabric_reg_in,
     fabric_sc_in,
@@ -21,7 +21,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
 
     input prog_reset;
     input prog_clk;
-    input scan_enable;
+    input test_enable;
     input [0:3]fabric_in;
     input fabric_reg_in;
     input fabric_sc_in;
@@ -37,7 +37,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
 
     wire prog_reset;
     wire prog_clk;
-    wire scan_enable;
+    wire test_enable;
     wire [0:3]fabric_in;
     wire fabric_reg_in;
     wire fabric_sc_in;
@@ -93,7 +93,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0
     (
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ff_D(mux_tree_size2_2_out),
         .ff_DI(direct_interc_8_out),
         .ff_reset(direct_interc_9_out),
@@ -102,7 +102,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1
     (
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ff_D(mux_tree_size2_3_out),
         .ff_DI(direct_interc_11_out),
         .ff_reset(direct_interc_12_out),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v

@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
 (
-    scan_enable,
+    test_enable,
     ff_D,
     ff_DI,
     ff_reset,
@@ -10,14 +10,14 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
     ff_clk
 );
 
-    input scan_enable;
+    input test_enable;
     input ff_D;
     input ff_DI;
     input ff_reset;
     output ff_Q;
     input ff_clk;
 
-    wire scan_enable;
+    wire test_enable;
     wire ff_D;
     wire ff_DI;
     wire ff_reset;
@@ -26,7 +26,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
 
     sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_
     (
-        .SCE(scan_enable),
+        .SCE(test_enable),
         .D(ff_D),
         .SCD(ff_DI),
         .RESET_B(ff_reset),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/fpga_top.v

@@ -16,7 +16,7 @@ module fpga_top(clk,
                 isol_n,
                 prog_reset,
                 prog_clk,
-                scan_enable,
+                test_enable,
                 gfpga_pad_io_soc_in,
                 gfpga_pad_io_soc_out,
                 gfpga_pad_io_soc_dir,
@@ -33,7 +33,7 @@ input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GLOBAL PORTS -----
-input [0:0] scan_enable;
+input [0:0] test_enable;
 //----- GPIN PORTS -----
 input [0:127] gfpga_pad_io_soc_in;
 //----- GPOUT PORTS -----
@@ -5246,7 +5246,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_1__1_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5309,7 +5309,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_1__2_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5372,7 +5372,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_1__3_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5435,7 +5435,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_1__4_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5498,7 +5498,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_1__5_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5561,7 +5561,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_1__6_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5624,7 +5624,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_1__7_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5687,7 +5687,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_1__8_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5750,7 +5750,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_2__1_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5813,7 +5813,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_2__2_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5876,7 +5876,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_2__3_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5939,7 +5939,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_2__4_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6002,7 +6002,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_2__5_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6065,7 +6065,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_2__6_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6128,7 +6128,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_2__7_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6191,7 +6191,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_2__8_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6254,7 +6254,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_3__1_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6317,7 +6317,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_3__2_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6380,7 +6380,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_3__3_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6443,7 +6443,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_3__4_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6506,7 +6506,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_3__5_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6569,7 +6569,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_3__6_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6632,7 +6632,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_3__7_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6695,7 +6695,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_3__8_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6758,7 +6758,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_4__1_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6821,7 +6821,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_4__2_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6884,7 +6884,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_4__3_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6947,7 +6947,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_4__4_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7010,7 +7010,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_4__5_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7073,7 +7073,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_4__6_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7136,7 +7136,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_4__7_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7199,7 +7199,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_4__8_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7262,7 +7262,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_5__1_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7325,7 +7325,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_5__2_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7388,7 +7388,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_5__3_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7451,7 +7451,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_5__4_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7514,7 +7514,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_5__5_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7577,7 +7577,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_5__6_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7640,7 +7640,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_5__7_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7703,7 +7703,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_5__8_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7766,7 +7766,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_6__1_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7829,7 +7829,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_6__2_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7892,7 +7892,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_6__3_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7955,7 +7955,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_6__4_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8018,7 +8018,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_6__5_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8081,7 +8081,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_6__6_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8144,7 +8144,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_6__7_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8207,7 +8207,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_6__8_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8270,7 +8270,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_7__1_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8333,7 +8333,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_7__2_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8396,7 +8396,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_7__3_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8459,7 +8459,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_7__4_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8522,7 +8522,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_7__5_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8585,7 +8585,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_7__6_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8648,7 +8648,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_7__7_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8711,7 +8711,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_7__8_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8774,7 +8774,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_8__1_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8837,7 +8837,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_8__2_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8900,7 +8900,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_8__3_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8963,7 +8963,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_8__4_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9026,7 +9026,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_8__5_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9089,7 +9089,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_8__6_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9152,7 +9152,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_8__7_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9215,7 +9215,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 	grid_clb grid_clb_8__8_ (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_clb.v

@@ -14,7 +14,7 @@
 // ----- Verilog module for grid_clb -----
 module grid_clb(prog_reset,
                 prog_clk,
-                scan_enable,
+                test_enable,
                 top_width_0_height_0_subtile_0__pin_I0_0_,
                 top_width_0_height_0_subtile_0__pin_I0_1_,
                 top_width_0_height_0_subtile_0__pin_I0i_0_,
@@ -78,7 +78,7 @@ input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GLOBAL PORTS -----
-input [0:0] scan_enable;
+input [0:0] test_enable;
 //----- INPUT PORTS -----
 input [0:0] top_width_0_height_0_subtile_0__pin_I0_0_;
 //----- INPUT PORTS -----
@@ -213,7 +213,7 @@ output [0:0] ccff_tail;
 	logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}),
 		.clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}),
 		.clb_I1({top_width_0_height_0_subtile_0__pin_I1_0_, top_width_0_height_0_subtile_0__pin_I1_1_}),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_clb_.v

@@ -14,7 +14,7 @@
 // ----- Verilog module for logical_tile_clb_mode_clb_ -----
 module logical_tile_clb_mode_clb_(prog_reset,
                                   prog_clk,
-                                  scan_enable,
+                                  test_enable,
                                   clb_I0,
                                   clb_I0i,
                                   clb_I1,
@@ -47,7 +47,7 @@ input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GLOBAL PORTS -----
-input [0:0] scan_enable;
+input [0:0] test_enable;
 //----- INPUT PORTS -----
 input [0:1] clb_I0;
 //----- INPUT PORTS -----
@@ -256,7 +256,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.fle_in({direct_interc_19_out, direct_interc_20_out, direct_interc_21_out, direct_interc_22_out}),
 		.fle_reg_in(direct_interc_23_out),
 		.fle_sc_in(direct_interc_24_out),
@@ -273,7 +273,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.fle_in({direct_interc_28_out, direct_interc_29_out, direct_interc_30_out, direct_interc_31_out}),
 		.fle_reg_in(direct_interc_32_out),
 		.fle_sc_in(direct_interc_33_out),
@@ -290,7 +290,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.fle_in({direct_interc_37_out, direct_interc_38_out, direct_interc_39_out, direct_interc_40_out}),
 		.fle_reg_in(direct_interc_41_out),
 		.fle_sc_in(direct_interc_42_out),
@@ -307,7 +307,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.fle_in({direct_interc_46_out, direct_interc_47_out, direct_interc_48_out, direct_interc_49_out}),
 		.fle_reg_in(direct_interc_50_out),
 		.fle_sc_in(direct_interc_51_out),
@@ -324,7 +324,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.fle_in({direct_interc_55_out, direct_interc_56_out, direct_interc_57_out, direct_interc_58_out}),
 		.fle_reg_in(direct_interc_59_out),
 		.fle_sc_in(direct_interc_60_out),
@@ -341,7 +341,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.fle_in({direct_interc_64_out, direct_interc_65_out, direct_interc_66_out, direct_interc_67_out}),
 		.fle_reg_in(direct_interc_68_out),
 		.fle_sc_in(direct_interc_69_out),
@@ -358,7 +358,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.fle_in({direct_interc_73_out, direct_interc_74_out, direct_interc_75_out, direct_interc_76_out}),
 		.fle_reg_in(direct_interc_77_out),
 		.fle_sc_in(direct_interc_78_out),
@@ -375,7 +375,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.fle_in({direct_interc_82_out, direct_interc_83_out, direct_interc_84_out, direct_interc_85_out}),
 		.fle_reg_in(direct_interc_86_out),
 		.fle_sc_in(direct_interc_87_out),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle.v

@@ -14,7 +14,7 @@
 // ----- Verilog module for logical_tile_clb_mode_default__fle -----
 module logical_tile_clb_mode_default__fle(prog_reset,
                                           prog_clk,
-                                          scan_enable,
+                                          test_enable,
                                           fle_in,
                                           fle_reg_in,
                                           fle_sc_in,
@@ -32,7 +32,7 @@ input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GLOBAL PORTS -----
-input [0:0] scan_enable;
+input [0:0] test_enable;
 //----- INPUT PORTS -----
 input [0:3] fle_in;
 //----- INPUT PORTS -----
@@ -98,7 +98,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_
 	logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
 		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.fabric_in({direct_interc_5_out, direct_interc_6_out, direct_interc_7_out, direct_interc_8_out}),
 		.fabric_reg_in(direct_interc_9_out),
 		.fabric_sc_in(direct_interc_10_out),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v

@@ -14,7 +14,7 @@
 // ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric -----
 module logical_tile_clb_mode_default__fle_mode_physical__fabric(prog_reset,
                                                                 prog_clk,
-                                                                scan_enable,
+                                                                test_enable,
                                                                 fabric_in,
                                                                 fabric_reg_in,
                                                                 fabric_sc_in,
@@ -32,7 +32,7 @@ input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GLOBAL PORTS -----
-input [0:0] scan_enable;
+input [0:0] test_enable;
 //----- INPUT PORTS -----
 input [0:3] fabric_in;
 //----- INPUT PORTS -----
@@ -122,7 +122,7 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail;
 		.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail));
 
 	logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.ff_D(mux_tree_size2_2_out),
 		.ff_DI(direct_interc_8_out),
 		.ff_reset(direct_interc_9_out),
@@ -130,7 +130,7 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail;
 		.ff_clk(direct_interc_10_out));
 
 	logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
-		.scan_enable(scan_enable),
+		.test_enable(test_enable),
 		.ff_D(mux_tree_size2_3_out),
 		.ff_DI(direct_interc_11_out),
 		.ff_reset(direct_interc_12_out),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v

@@ -11,14 +11,14 @@
 `default_nettype none
 
 // ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff -----
-module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff(scan_enable,
+module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff(test_enable,
                                                                                  ff_D,
                                                                                  ff_DI,
                                                                                  ff_reset,
                                                                                  ff_Q,
                                                                                  ff_clk);
 //----- GLOBAL PORTS -----
-input [0:0] scan_enable;
+input [0:0] test_enable;
 //----- INPUT PORTS -----
 input [0:0] ff_D;
 //----- INPUT PORTS -----
@@ -50,7 +50,7 @@ wire [0:0] ff_clk;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ (
-		.SCE(scan_enable),
+		.SCE(test_enable),
 		.D(ff_D),
 		.SCD(ff_DI),
 		.RESET_B(ff_reset),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/fpga_top.v

@@ -7,7 +7,7 @@ module fpga_top
     isol_n,
     prog_reset,
     prog_clk,
-    scan_enable,
+    test_enable,
     gfpga_pad_io_soc_in,
     gfpga_pad_io_soc_out,
     gfpga_pad_io_soc_dir,
@@ -20,7 +20,7 @@ module fpga_top
     input isol_n;
     input prog_reset;
     input prog_clk;
-    input scan_enable;
+    input test_enable;
     input [0:127]gfpga_pad_io_soc_in;
     output [0:127]gfpga_pad_io_soc_out;
     output [0:127]gfpga_pad_io_soc_dir;
@@ -32,7 +32,7 @@ module fpga_top
     wire isol_n;
     wire prog_reset;
     wire prog_clk;
-    wire scan_enable;
+    wire test_enable;
     wire [0:127]gfpga_pad_io_soc_in;
     wire [0:127]gfpga_pad_io_soc_out;
     wire [0:127]gfpga_pad_io_soc_dir;
@@ -5259,7 +5259,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5323,7 +5323,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5387,7 +5387,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5451,7 +5451,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5515,7 +5515,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5579,7 +5579,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5643,7 +5643,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5707,7 +5707,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5771,7 +5771,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5835,7 +5835,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5899,7 +5899,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5963,7 +5963,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6027,7 +6027,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6091,7 +6091,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6155,7 +6155,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6219,7 +6219,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6283,7 +6283,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6347,7 +6347,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6411,7 +6411,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6475,7 +6475,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6539,7 +6539,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6603,7 +6603,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6667,7 +6667,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6731,7 +6731,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6795,7 +6795,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6859,7 +6859,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6923,7 +6923,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6987,7 +6987,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7051,7 +7051,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7115,7 +7115,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7179,7 +7179,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7243,7 +7243,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7307,7 +7307,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7371,7 +7371,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7435,7 +7435,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7499,7 +7499,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7563,7 +7563,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7627,7 +7627,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7691,7 +7691,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7755,7 +7755,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7819,7 +7819,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7883,7 +7883,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7947,7 +7947,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8011,7 +8011,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8075,7 +8075,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8139,7 +8139,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8203,7 +8203,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8267,7 +8267,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8331,7 +8331,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8395,7 +8395,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8459,7 +8459,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8523,7 +8523,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8587,7 +8587,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8651,7 +8651,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8715,7 +8715,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8779,7 +8779,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8843,7 +8843,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8907,7 +8907,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8971,7 +8971,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9035,7 +9035,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9099,7 +9099,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9163,7 +9163,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9227,7 +9227,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9291,7 +9291,7 @@ module fpga_top
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_clb.v

@@ -4,7 +4,7 @@ module grid_clb
 (
     prog_reset,
     prog_clk,
-    scan_enable,
+    test_enable,
     top_width_0_height_0_subtile_0__pin_I0_0_,
     top_width_0_height_0_subtile_0__pin_I0_1_,
     top_width_0_height_0_subtile_0__pin_I0i_0_,
@@ -67,7 +67,7 @@ module grid_clb
 
     input prog_reset;
     input prog_clk;
-    input scan_enable;
+    input test_enable;
     input top_width_0_height_0_subtile_0__pin_I0_0_;
     input top_width_0_height_0_subtile_0__pin_I0_1_;
     input top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -129,7 +129,7 @@ module grid_clb
 
     wire prog_reset;
     wire prog_clk;
-    wire scan_enable;
+    wire test_enable;
     wire top_width_0_height_0_subtile_0__pin_I0_0_;
     wire top_width_0_height_0_subtile_0__pin_I0_1_;
     wire top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -193,7 +193,7 @@ module grid_clb
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}),
         .clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}),
         .clb_I1({top_width_0_height_0_subtile_0__pin_I1_0_, top_width_0_height_0_subtile_0__pin_I1_1_}),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_clb_.v

@@ -4,7 +4,7 @@ module logical_tile_clb_mode_clb_
 (
     prog_reset,
     prog_clk,
-    scan_enable,
+    test_enable,
     clb_I0,
     clb_I0i,
     clb_I1,
@@ -36,7 +36,7 @@ module logical_tile_clb_mode_clb_
 
     input prog_reset;
     input prog_clk;
-    input scan_enable;
+    input test_enable;
     input [0:1]clb_I0;
     input [0:1]clb_I0i;
     input [0:1]clb_I1;
@@ -67,7 +67,7 @@ module logical_tile_clb_mode_clb_
 
     wire prog_reset;
     wire prog_clk;
-    wire scan_enable;
+    wire test_enable;
     wire [0:1]clb_I0;
     wire [0:1]clb_I0i;
     wire [0:1]clb_I1;
@@ -211,7 +211,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_19_out, direct_interc_20_out, direct_interc_21_out, direct_interc_22_out}),
         .fle_reg_in(direct_interc_23_out),
         .fle_sc_in(direct_interc_24_out),
@@ -229,7 +229,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_28_out, direct_interc_29_out, direct_interc_30_out, direct_interc_31_out}),
         .fle_reg_in(direct_interc_32_out),
         .fle_sc_in(direct_interc_33_out),
@@ -247,7 +247,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_37_out, direct_interc_38_out, direct_interc_39_out, direct_interc_40_out}),
         .fle_reg_in(direct_interc_41_out),
         .fle_sc_in(direct_interc_42_out),
@@ -265,7 +265,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_46_out, direct_interc_47_out, direct_interc_48_out, direct_interc_49_out}),
         .fle_reg_in(direct_interc_50_out),
         .fle_sc_in(direct_interc_51_out),
@@ -283,7 +283,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_55_out, direct_interc_56_out, direct_interc_57_out, direct_interc_58_out}),
         .fle_reg_in(direct_interc_59_out),
         .fle_sc_in(direct_interc_60_out),
@@ -301,7 +301,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_64_out, direct_interc_65_out, direct_interc_66_out, direct_interc_67_out}),
         .fle_reg_in(direct_interc_68_out),
         .fle_sc_in(direct_interc_69_out),
@@ -319,7 +319,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_73_out, direct_interc_74_out, direct_interc_75_out, direct_interc_76_out}),
         .fle_reg_in(direct_interc_77_out),
         .fle_sc_in(direct_interc_78_out),
@@ -337,7 +337,7 @@ module logical_tile_clb_mode_clb_
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fle_in({direct_interc_82_out, direct_interc_83_out, direct_interc_84_out, direct_interc_85_out}),
         .fle_reg_in(direct_interc_86_out),
         .fle_sc_in(direct_interc_87_out),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle.v

@@ -4,7 +4,7 @@ module logical_tile_clb_mode_default__fle
 (
     prog_reset,
     prog_clk,
-    scan_enable,
+    test_enable,
     fle_in,
     fle_reg_in,
     fle_sc_in,
@@ -21,7 +21,7 @@ module logical_tile_clb_mode_default__fle
 
     input prog_reset;
     input prog_clk;
-    input scan_enable;
+    input test_enable;
     input [0:3]fle_in;
     input fle_reg_in;
     input fle_sc_in;
@@ -37,7 +37,7 @@ module logical_tile_clb_mode_default__fle
 
     wire prog_reset;
     wire prog_clk;
-    wire scan_enable;
+    wire test_enable;
     wire [0:3]fle_in;
     wire fle_reg_in;
     wire fle_sc_in;
@@ -68,7 +68,7 @@ module logical_tile_clb_mode_default__fle
     (
         .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .fabric_in({direct_interc_5_out, direct_interc_6_out, direct_interc_7_out, direct_interc_8_out}),
         .fabric_reg_in(direct_interc_9_out),
         .fabric_sc_in(direct_interc_10_out),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v

@@ -4,7 +4,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
 (
     prog_reset,
     prog_clk,
-    scan_enable,
+    test_enable,
     fabric_in,
     fabric_reg_in,
     fabric_sc_in,
@@ -21,7 +21,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
 
     input prog_reset;
     input prog_clk;
-    input scan_enable;
+    input test_enable;
     input [0:3]fabric_in;
     input fabric_reg_in;
     input fabric_sc_in;
@@ -37,7 +37,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
 
     wire prog_reset;
     wire prog_clk;
-    wire scan_enable;
+    wire test_enable;
     wire [0:3]fabric_in;
     wire fabric_reg_in;
     wire fabric_sc_in;
@@ -93,7 +93,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0
     (
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ff_D(mux_tree_size2_2_out),
         .ff_DI(direct_interc_8_out),
         .ff_reset(direct_interc_9_out),
@@ -102,7 +102,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1
     (
-        .scan_enable(scan_enable),
+        .test_enable(test_enable),
         .ff_D(mux_tree_size2_3_out),
         .ff_DI(direct_interc_11_out),
         .ff_reset(direct_interc_12_out),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v

@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
 (
-    scan_enable,
+    test_enable,
     ff_D,
     ff_DI,
     ff_reset,
@@ -10,14 +10,14 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
     ff_clk
 );
 
-    input scan_enable;
+    input test_enable;
     input ff_D;
     input ff_DI;
     input ff_reset;
     output ff_Q;
     input ff_clk;
 
-    wire scan_enable;
+    wire test_enable;
     wire ff_D;
     wire ff_DI;
     wire ff_reset;
@@ -26,7 +26,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
 
     sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_
     (
-        .SCE(scan_enable),
+        .SCE(test_enable),
         .D(ff_D),
         .SCD(ff_DI),
         .RESET_B(ff_reset),

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/openfpgashell.log

@@ -268,11 +268,11 @@ Logic Element (fle) detailed count:
   LEs used for logic only             : 1
   LEs used for registers only         : 0
 
-Incr Slack updates 1 in 2.584e-06 sec
+Incr Slack updates 1 in 2.224e-06 sec
-Full Max Req/Worst Slack updates 1 in 1.735e-06 sec
+Full Max Req/Worst Slack updates 1 in 2.152e-06 sec
 Incr Max Req/Worst Slack updates 0 in 0 sec
 Incr Criticality updates 0 in 0 sec
-Full Criticality updates 1 in 1.882e-06 sec
+Full Criticality updates 1 in 1.857e-06 sec
 Warning 27: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
 Warning 28: Ambiguous block type specification at grid location (0,9). Existing block type 'io_top' at (0,9) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
 Warning 29: Ambiguous block type specification at grid location (9,0). Existing block type 'io_bottom' at (9,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
@@ -507,11 +507,11 @@ Iter   Time    pres  BBs    Heap  Re-Rtd  Re-Rtd Overused RR Nodes      Wireleng
       (sec)     fac Updt    push    Nets   Conns                                       (ns)       (ns)       (ns)       (ns)       (ns)     Iter
 ---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
    1    0.0     0.0    0     226       3       3       0 ( 0.000%)      27 ( 0.3%)   13.980     -13.98    -13.980      0.000      0.000      N/A
-Incr Slack updates 4 in 1.2947e-05 sec
+Incr Slack updates 4 in 1.9664e-05 sec
-Full Max Req/Worst Slack updates 1 in 3.948e-06 sec
+Full Max Req/Worst Slack updates 1 in 2.711e-06 sec
-Incr Max Req/Worst Slack updates 3 in 6.005e-06 sec
+Incr Max Req/Worst Slack updates 3 in 1.4906e-05 sec
-Incr Criticality updates 3 in 6.601e-06 sec
+Incr Criticality updates 3 in 1.5953e-05 sec
-Full Criticality updates 1 in 2.382e-06 sec
+Full Criticality updates 1 in 2.375e-06 sec
 Restoring best routing
 Critical path: 13.98 ns
 Successfully routed after 1 routing iterations.
@@ -658,11 +658,11 @@ Final setup slack histogram:
 Final geomean non-virtual intra-domain period: nan ns (nan MHz)
 Final fanout-weighted geomean non-virtual intra-domain period: nan ns (nan MHz)
 
-Incr Slack updates 1 in 6.046e-06 sec
+Incr Slack updates 1 in 7.13e-06 sec
-Full Max Req/Worst Slack updates 1 in 4.007e-06 sec
+Full Max Req/Worst Slack updates 1 in 5.927e-06 sec
 Incr Max Req/Worst Slack updates 0 in 0 sec
 Incr Criticality updates 0 in 0 sec
-Full Criticality updates 1 in 3.533e-06 sec
+Full Criticality updates 1 in 5.366e-06 sec
 --line removed--
 VPR suceeded
 --line removed--
@@ -992,11 +992,11 @@ Building annotation for post-routing and clustering synchornization results...Do
 Building annotation for mapped blocks on grid locations...Done
 User specified the operating clock frequency to use VPR results
 Use VPR critical path delay 1.6776e-17 [ns] with a 20 [%] slack in OpenFPGA.
-Incr Slack updates 1 in 6.177e-06 sec
+Incr Slack updates 1 in 5.809e-06 sec
-Full Max Req/Worst Slack updates 1 in 5.086e-06 sec
+Full Max Req/Worst Slack updates 1 in 3.941e-06 sec
 Incr Max Req/Worst Slack updates 0 in 0 sec
 Incr Criticality updates 0 in 0 sec
-Full Criticality updates 1 in 5.057e-06 sec
+Full Criticality updates 1 in 3.894e-06 sec
 Will apply operating clock frequency 59.609 [MHz] to simulations
 User specified the number of operating clock cycles to be inferred from signal activities
 Average net density: 0.42
@@ -1314,9 +1314,9 @@ Finish execution with 0 errors
 --line removed--
 
 Thank you for using OpenFPGA!
-Incr Slack updates 2 in 2.3068e-05 sec
+Incr Slack updates 2 in 1.3494e-05 sec
-Full Max Req/Worst Slack updates 1 in 4.469e-06 sec
+Full Max Req/Worst Slack updates 1 in 5.371e-06 sec
-Incr Max Req/Worst Slack updates 1 in 5.627e-06 sec
+Incr Max Req/Worst Slack updates 1 in 6.386e-06 sec
 Incr Criticality updates 0 in 0 sec
-Full Criticality updates 2 in 1.1276e-05 sec
+Full Criticality updates 2 in 1.2969e-05 sec
 0

SOFA_A/FPGA88_SOFA_A/release/post_synth/top_instances_ports.txt

@@ -387,7 +387,7 @@
         "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I7_1_",
         "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I7i_0_",
         "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I7i_1_",
-        "0001_Direction.IN,scan_enable",
+        "0001_Direction.IN,test_enable",
         "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I0_0_",
         "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I0_1_",
         "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I0i_0_",

SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/test_enable_ports.txt

@@ -0,0 +1,8 @@
+= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+Module                    |       In        |       Out      
+Module                    |   L   R   T   B |   L   R   T   B
+= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+bottom_left_tile          |   -   -   1   - |   -   -   -   -
+bottom_tile               |   -   -   7   - |   -   -   -   -
+left_tile                 |   -   1   3   3 |   -   -   3   4
+tile                      |   -   7  21  21 |   7   -  21  28