[Documentation] Format README

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tangxifan 2020-10-09 22:37:39 -06:00
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FPGA tape-outs using the open-source Skywater 130nm PDK and OpenFPGA FPGA tape-outs using the open-source Skywater 130nm PDK and OpenFPGA
* Keep this folder clean and organized as follows * Keep this folder clean and organized as follows
- DOC: documentation of the project - **DOC**: documentation of the project
- ARCH: Architecture XML and other input files which OpenFPGA requires to generate Verilog netlists - **ARCH**: Architecture XML and other input files which OpenFPGA requires to generate Verilog netlists
- BENCHMARK: Benchmarks to be tested on the FPGA fabric - **BENCHMARK**: Benchmarks to be tested on the FPGA fabric
- HDL: Hardware description netlists for the FPGA fabrics - **HDL**: Hardware description netlists for the FPGA fabrics
- SDC: design constraints - **SDC**: design constraints
- SCRIPT: Scripts to setup, run OpenFPGA etc. - **SCRIPT**: Scripts to setup, run OpenFPGA etc.
- TESTBENCH: Verilog testbenches generated by OpenFPGA - **TESTBENCH**: Verilog testbenches generated by OpenFPGA
- PDK: Technology files linked from skywater opensource pdk - **PDK**: Technology files linked from skywater opensource pdk
- SNPS\_ICC2: scripts and workspace of Synopsys IC Compiler 2 - **SNPS\_ICC2**: scripts and workspace of Synopsys IC Compiler 2
Keep a README inside the folder about the ICC2 version and how-to-use. Keep a README inside the folder about the ICC2 version and how-to-use.
- MSIM: scripts and workspace of verification using Mentor ModelSim - **MSIM**: scripts and workspace of verification using Mentor ModelSim
* Note: * Note:
- Please **ONLY** place folders under this directory - Please **ONLY** place folders under this directory