mirror of https://github.com/lnis-uofu/SOFA.git
[Doc] Reorganize documentation for SOFA HD device family
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<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="black" x="0" y="13">regin</tspan>
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|
|
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<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="black" x="0" y="13">LUT4_out</tspan>
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|
|
||||||
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#797979" x="0" y="13">LUT3_out[0]</tspan>
|
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</text>
|
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</g>
|
|
||||||
<g id="Graphic_194">
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|
|
||||||
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#797979" x="0" y="13">LUT3_out[1]</tspan>
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</g>
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<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#797979" x="0" y="13">scin</tspan>
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</text>
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</g>
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<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#797979" x="0" y="13">scout</tspan>
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</g>
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<g id="Graphic_207">
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<ellipse cx="515.47594" cy="347.1108" rx="2.58243758861826" ry="2.7500043942302" fill="black"/>
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<ellipse cx="515.47594" cy="347.1108" rx="2.58243758861826" ry="2.7500043942302" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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</g>
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<g id="Graphic_208">
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<ellipse cx="516.05846" cy="393.8696" rx="2.58243758861826" ry="2.75000439423017" fill="black"/>
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||||||
<ellipse cx="516.05846" cy="393.8696" rx="2.58243758861826" ry="2.75000439423017" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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</g>
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<g id="Graphic_209">
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<ellipse cx="514.0598" cy="277.86368" rx="2.58243758861826" ry="2.7500043942302" fill="black"/>
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||||||
<ellipse cx="514.0598" cy="277.86368" rx="2.58243758861826" ry="2.7500043942302" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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</g>
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<g id="Graphic_210">
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|
|
||||||
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#797979" x="0" y="13">regin</tspan>
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</text>
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</g>
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|
||||||
<g id="Graphic_224">
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|
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<path d="M 434.01406 253.81365 L 434.01885 302.853 C 434.01885 302.853 449.32593 295.48294 449.04247 295.19947 C 448.759 294.916 448.7542 259.19948 448.7542 259.19948 Z" fill="#417fff"/>
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<path d="M 434.01406 253.81365 L 434.01885 302.853 C 434.01885 302.853 449.32593 295.48294 449.04247 295.19947 C 448.759 294.916 448.7542 259.19948 448.7542 259.19948 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
|
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||||||
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
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||||||
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
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</text>
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</g>
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<path d="M 421.91773 206.7161 L 421.90706 266.99222 L 434.01406 266.66667" stroke="#797979" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
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<path d="M 405.67654 250.73817 L 405.66667 292.68104 L 433.12215 292.66667" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
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<g id="Graphic_228">
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<ellipse cx="405.64233" cy="250.738" rx="2.58243758861832" ry="2.75000439423021" fill="black"/>
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<ellipse cx="405.64233" cy="250.738" rx="2.58243758861832" ry="2.75000439423021" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#797979" x="0" y="13">regout</tspan>
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<g id="Graphic_232">
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<text transform="translate(130.62533 378.8501)" fill="black">
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<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="black" x="0" y="11">CLK</tspan>
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</text>
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</g>
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<g id="Line_233">
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<path d="M 161.41582 386 L 460.1427 385.33333 L 460.0294 358.36674" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
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<g id="Graphic_235">
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<ellipse cx="460.0305" cy="357.6732" rx="2.58243758861832" ry="2.75000439423023" fill="black"/>
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<ellipse cx="460.0305" cy="357.6732" rx="2.58243758861832" ry="2.75000439423023" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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</g>
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<g id="Graphic_236">
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<path d="M 470.1986 286.21817 L 478.9792 289.51437 L 470.1986 292.81057 Z" fill="#ccc"/>
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<path d="M 470.1986 286.21817 L 478.9792 289.51437 L 470.1986 292.81057 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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</g>
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<g id="Graphic_237">
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<path d="M 470.64405 354.9232 L 479.42464 358.2194 L 470.64405 361.5156 Z" fill="#ccc"/>
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<path d="M 470.64405 354.9232 L 479.42464 358.2194 L 470.64405 361.5156 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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</g>
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<g id="Graphic_238">
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<path d="M 523.83856 240.093 L 523.84334 289.13237 C 523.84334 289.13237 539.1504 281.7623 538.86696 281.47883 C 538.5835 281.19536 538.5787 245.47883 538.5787 245.47883 Z" fill="#417fff"/>
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<path d="M 523.83856 240.093 L 523.84334 289.13237 C 523.84334 289.13237 539.1504 281.7623 538.86696 281.47883 C 538.5835 281.19536 538.5787 245.47883 538.5787 245.47883 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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<text transform="translate(525.46094 242.0072)" fill="white">
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||||||
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
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||||||
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
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|
||||||
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
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</text>
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</g>
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||||||
<g id="Graphic_240">
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|
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<path d="M 525.6516 311.8801 L 525.6564 360.9195 C 525.6564 360.9195 540.9635 353.5494 540.68 353.26594 C 540.39654 352.98248 540.39176 317.26594 540.39176 317.26594 Z" fill="#417fff"/>
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<path d="M 525.6516 311.8801 L 525.6564 360.9195 C 525.6564 360.9195 540.9635 353.5494 540.68 353.26594 C 540.39654 352.98248 540.39176 317.26594 540.39176 317.26594 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
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<g id="Graphic_239">
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<text transform="translate(527.274 313.7943)" fill="white">
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||||||
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
|
|
||||||
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
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||||||
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
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|
||||||
</text>
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</g>
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|
||||||
<g id="Graphic_242">
|
|
||||||
<path d="M 429.816 326.56605 L 429.8208 375.6054 C 429.8208 375.6054 445.12786 368.23534 444.8444 367.95188 C 444.56093 367.6684 444.55615 331.95188 444.55615 331.95188 Z" fill="#417fff"/>
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<path d="M 429.816 326.56605 L 429.8208 375.6054 C 429.8208 375.6054 445.12786 368.23534 444.8444 367.95188 C 444.56093 367.6684 444.55615 331.95188 444.55615 331.95188 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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<g id="Graphic_241">
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<text transform="translate(430.4519 328.96835)" fill="white">
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||||||
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
|
|
||||||
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
|
|
||||||
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
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</text>
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</g>
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<path d="M 429.21986 340.20005 L 429.816 341 L 416 341.3335 L 416 312.86334 L 484.9886 312.79427" stroke="#797979" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
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<g id="Graphic_244">
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<ellipse cx="484.99324" cy="313.3301" rx="2.58243758861832" ry="2.7500043942302" fill="black"/>
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<ellipse cx="484.99324" cy="313.3301" rx="2.58243758861832" ry="2.7500043942302" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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</g>
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<g id="Line_245">
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<path d="M 187.85625 206.7161 L 187.33333 287.3643 L 207.34185 287.33333" stroke="#797979" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
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<g id="Graphic_246">
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<text transform="translate(178.33572 188.64967)" fill="#797979">
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<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#797979" x="0" y="13">cin</tspan>
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</text>
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</g>
|
|
||||||
<g id="Graphic_248">
|
|
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<path d="M 206.7669 278.2587 L 206.7717 327.29805 C 206.7717 327.29805 222.07878 319.92797 221.79531 319.6445 C 221.51185 319.36105 221.50707 283.6445 221.50707 283.6445 Z" fill="#999"/>
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<path d="M 206.7669 278.2587 L 206.7717 327.29805 C 206.7717 327.29805 222.07878 319.92797 221.79531 319.6445 C 221.51185 319.36105 221.50707 283.6445 221.50707 283.6445 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
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<g id="Graphic_247">
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<text transform="translate(208.61997 279.72197)" fill="white">
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<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
|
|
||||||
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
|
|
||||||
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
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<g id="Graphic_250">
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<text transform="translate(293.65994 325.3254)" fill="#797979">
|
|
||||||
<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#797979" x="0" y="13">LUT2_out[1]</tspan>
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</text>
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</g>
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<g id="Graphic_251">
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<path d="M 378.5414 394.57625 L 329.502 394.58103 C 329.502 394.58103 336.8721 409.8881 337.15556 409.60465 C 337.43902 409.3212 373.15556 409.3164 373.15556 409.3164 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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<g id="Graphic_254">
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<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#797979" x="0" y="13">LUT2_out[0]</tspan>
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</text>
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<ellipse cx="188.10011" cy="287.80266" rx="2.58243758861827" ry="2.75000439423021" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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<tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="black" x="0" y="13">Reset</tspan>
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</svg>
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|
Before Width: | Height: | Size: 26 KiB |
|
|
@ -1,11 +0,0 @@
|
||||||
.. _arch:
|
|
||||||
Architecture
|
|
||||||
|
|
||||||
.. toctree::
|
|
||||||
:maxdepth: 2
|
|
||||||
|
|
||||||
fpga_arch
|
|
||||||
|
|
||||||
io_resource
|
|
||||||
|
|
||||||
clb_arch
|
|
||||||
|
|
@ -1,107 +0,0 @@
|
||||||
.. _io_resource:
|
|
||||||
|
|
||||||
I/O Resources
|
|
||||||
-------------
|
|
||||||
|
|
||||||
.. _io_resource_overview:
|
|
||||||
|
|
||||||
Overview
|
|
||||||
~~~~~~~~
|
|
||||||
|
|
||||||
The *High-Density* (HD) FPGA IP has 144 I/O pins as shown in :numref:`fig_fpga_io_switch`.
|
|
||||||
|
|
||||||
Among the 144 I/Os,
|
|
||||||
|
|
||||||
- **29 external I/Os** are accessible through the Caravel SoC's *General-Purpose I/Os* (GPIOs).
|
|
||||||
|
|
||||||
- **115 internal I/Os** are accessible through the Caravel SOC's logic analyzer and wishbone interfaces, which are controlled by the RISC-V processor. See :ref:`io_resource_debug` and :ref:`io_resource_accelerator` for details.
|
|
||||||
|
|
||||||
.. warning:: For all the unused GPIOs, please set them to **input** mode, so that the FPGA will not output any noise signals to damage other SoC components.
|
|
||||||
|
|
||||||
.. note:: The connectivity of the 115 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes.
|
|
||||||
|
|
||||||
.. warning:: The internal I/O pins will drive either Wishbone or the logic analyzer, following the same truth table as mode-switch bit in :numref:`fig_fpga_io_switch`.
|
|
||||||
|
|
||||||
.. _fig_fpga_io_switch:
|
|
||||||
|
|
||||||
.. figure:: ./figures/fpga_io_switch.svg
|
|
||||||
:scale: 20%
|
|
||||||
:alt: I/O arrangement of FPGA IP
|
|
||||||
|
|
||||||
I/O arrangement of *High-Density* (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface
|
|
||||||
|
|
||||||
|
|
||||||
.. _io_resource_accelerator:
|
|
||||||
|
|
||||||
Accelerator Mode
|
|
||||||
~~~~~~~~~~~~~~~~
|
|
||||||
|
|
||||||
When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor.
|
|
||||||
:numref:`fig_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations.
|
|
||||||
|
|
||||||
.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:29] are not connected.
|
|
||||||
|
|
||||||
.. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator.
|
|
||||||
|
|
||||||
.. _fig_fpga_io_map_wishbone_mode:
|
|
||||||
|
|
||||||
.. figure:: ./figures/fpga_io_map_wishbone_mode.svg
|
|
||||||
:scale: 20%
|
|
||||||
:alt: I/O arrangement of FPGA IP when interfacing wishbone bus
|
|
||||||
|
|
||||||
I/O arrangement of *High-Density* (HD) FPGA IP when interfacing wishbone bus
|
|
||||||
|
|
||||||
.. _io_resource_debug:
|
|
||||||
|
|
||||||
Debug Mode
|
|
||||||
~~~~~~~~~~
|
|
||||||
|
|
||||||
When the logic analyzer interface is enabled, the FPGA can operate in debug mode, whose internal signals can be readback through the registers of the RISC-V processor.
|
|
||||||
:numref:`fig_fpga_io_map_logic_analyzer_mode` illustrates the detailed I/O arrangement for the FPGA, where the logic analyzer signals are connected to fixed FPGA I/O locations.
|
|
||||||
|
|
||||||
.. note:: The logic analyzer is 128-bit, while 115 bits can drive or be driven by the FPGA I/O. The other 14 bits are connected to internal spots of the FPGA fabric, monitoring critical signal activities of the FPGA in debugging purpose.
|
|
||||||
|
|
||||||
.. warning:: If the logic analyzer is not used, please configure both the management SoC and the FPGA as follows:
|
|
||||||
|
|
||||||
- all the I/O directionality is set to **input mode**.
|
|
||||||
- all the output ports is pulled down to **logic ``0``**.
|
|
||||||
|
|
||||||
.. _fig_fpga_io_map_logic_analyzer_mode:
|
|
||||||
|
|
||||||
.. figure:: ./figures/fpga_io_map_logic_analyzer_mode.svg
|
|
||||||
:scale: 20%
|
|
||||||
:alt: I/O arrangement of FPGA IP when interfacing logic analyzer
|
|
||||||
|
|
||||||
I/O arrangement of *High-Density* (HD) FPGA IP when interfacing logic analyzer
|
|
||||||
|
|
||||||
.. _io_resource_circuit:
|
|
||||||
|
|
||||||
FPGA I/O Circuit
|
|
||||||
~~~~~~~~~~~~~~~~
|
|
||||||
|
|
||||||
As shown in :numref:`fig_embedded_io_schematic`, the I/O circuit used in the I/O tiles of the FPGA fabric (see :numref:`fig_fpga_arch`) is an digital I/O cell with
|
|
||||||
|
|
||||||
- An **active-low** I/O isolation signal ``IO_ISOL_N`` to set the I/O in input mode. This is to avoid any unexpected output signals to damage circuits outside the FPGA due to configurable memories are not properly initialized.
|
|
||||||
|
|
||||||
.. warning:: This feature may not be needed if the configurable memory cell has a built-in set/reset functionality!
|
|
||||||
|
|
||||||
- An internal protection circuitry to ensure clean signals at all the SOC I/O ports. This is to avoid
|
|
||||||
|
|
||||||
- ``SOC_OUT`` port outputs any random signal when the I/O is in input mode
|
|
||||||
- ``FPGA_IN`` port is driven by any random signal when the I/O is output mode
|
|
||||||
|
|
||||||
- An internal configurable memory element to control the direction of I/O cell
|
|
||||||
|
|
||||||
The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where
|
|
||||||
|
|
||||||
- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode
|
|
||||||
|
|
||||||
- When configuration bit (FF output) is logic ``0``, the I/O cell is in output mode
|
|
||||||
|
|
||||||
.. _fig_embedded_io_schematic:
|
|
||||||
|
|
||||||
.. figure:: ./figures/embedded_io_schematic.svg
|
|
||||||
:scale: 30%
|
|
||||||
:alt: Schematic of embedded I/O cell used in FPGA
|
|
||||||
|
|
||||||
Schematic of embedded I/O cell used in FPGA
|
|
||||||
|
|
@ -0,0 +1,9 @@
|
||||||
|
.. _datasheet:
|
||||||
|
Datasheets
|
||||||
|
|
||||||
|
.. toctree::
|
||||||
|
:maxdepth: 2
|
||||||
|
|
||||||
|
sofa_hd/index
|
||||||
|
|
||||||
|
qlsofa_hd/index
|
||||||
|
|
@ -0,0 +1,16 @@
|
||||||
|
.. _datasheet_sofa_hd:
|
||||||
|
QLSOFA HD
|
||||||
|
|
||||||
|
QLSOFA HD
|
||||||
|
---------
|
||||||
|
|
||||||
|
.. toctree::
|
||||||
|
:maxdepth: 2
|
||||||
|
|
||||||
|
qlsofa_hd_fpga_arch
|
||||||
|
|
||||||
|
qlsofa_hd_io_resource
|
||||||
|
|
||||||
|
qlsofa_hd_clb_arch
|
||||||
|
|
||||||
|
qlsofa_hd_circuit_design
|
||||||
|
|
@ -0,0 +1,36 @@
|
||||||
|
.. _qlsofa_hd_circuit_design:
|
||||||
|
|
||||||
|
Circuit Designs
|
||||||
|
---------------
|
||||||
|
|
||||||
|
.. _qlsofa_hd_circuit_design_io:
|
||||||
|
|
||||||
|
I/O Circuit
|
||||||
|
^^^^^^^^^^^
|
||||||
|
|
||||||
|
As shown in :numref:`fig_qlsofa_hd_embedded_io_schematic`, the I/O circuit used in the I/O tiles of the FPGA fabric (see :numref:`fig_qlsofa_hd_fpga_arch`) is an digital I/O cell with
|
||||||
|
|
||||||
|
- An **active-low** I/O isolation signal ``IO_ISOL_N`` to set the I/O in input mode. This is to avoid any unexpected output signals to damage circuits outside the FPGA due to configurable memories are not properly initialized.
|
||||||
|
|
||||||
|
.. warning:: This feature may not be needed if the configurable memory cell has a built-in set/reset functionality!
|
||||||
|
|
||||||
|
- An internal protection circuitry to ensure clean signals at all the SOC I/O ports. This is to avoid
|
||||||
|
|
||||||
|
- ``SOC_OUT`` port outputs any random signal when the I/O is in input mode
|
||||||
|
- ``FPGA_IN`` port is driven by any random signal when the I/O is output mode
|
||||||
|
|
||||||
|
- An internal configurable memory element to control the direction of I/O cell
|
||||||
|
|
||||||
|
The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where
|
||||||
|
|
||||||
|
- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode
|
||||||
|
|
||||||
|
- When configuration bit (FF output) is logic ``0``, the I/O cell is in output mode
|
||||||
|
|
||||||
|
.. _fig_qlsofa_hd_embedded_io_schematic:
|
||||||
|
|
||||||
|
.. figure:: ./figures/qlsofa_hd_embedded_io_schematic.svg
|
||||||
|
:scale: 30%
|
||||||
|
:alt: Schematic of embedded I/O cell used in FPGA
|
||||||
|
|
||||||
|
Schematic of embedded I/O cell used in FPGA
|
||||||
|
|
@ -0,0 +1,131 @@
|
||||||
|
.. _qlsofa_hd_clb_arch:
|
||||||
|
|
||||||
|
Configurable Logic Block
|
||||||
|
------------------------
|
||||||
|
|
||||||
|
.. _qlsofa_hd_clb_arch_generality:
|
||||||
|
|
||||||
|
Generality
|
||||||
|
~~~~~~~~~~
|
||||||
|
|
||||||
|
Each Logic Block (CLB) consists of 8 Logic Elements (LEs) as shown in :numref:`fig_qlsofa_hd_clb_arch`.
|
||||||
|
All the pins of the LEs are directly wired to CLB pins without a local routing architecture.
|
||||||
|
Feedback connections between LEs are implemented by the global routing architecture outside the CLBs.
|
||||||
|
|
||||||
|
.. _fig_qlsofa_hd_clb_arch:
|
||||||
|
|
||||||
|
.. figure:: ./figures/qlsofa_hd_clb_arch.svg
|
||||||
|
:scale: 20%
|
||||||
|
:alt: Configurable Logic Block schematic
|
||||||
|
|
||||||
|
Configurable logic block schematic
|
||||||
|
|
||||||
|
.. _qlsofa_hd_clb_arch_le:
|
||||||
|
|
||||||
|
Multi-mode Logic Element
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
Physical Implementation
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
As shown in :numref:`fig_qlsofa_hd_fle_arch_schematic`, each Logic Element (LE) consists of
|
||||||
|
|
||||||
|
- a fracturable 4-input Look-Up Table (LUT)
|
||||||
|
- two D-type Flip-Flops (FF)
|
||||||
|
|
||||||
|
.. _fig_qlsofa_hd_fle_arch_schematic:
|
||||||
|
|
||||||
|
.. figure:: ./figures/qlsofa_hd_fle_arch_schematic.svg
|
||||||
|
:scale: 30%
|
||||||
|
:alt: Logic element schematic
|
||||||
|
|
||||||
|
Detailed schematic of a logic element
|
||||||
|
|
||||||
|
The LE can operate in different modes to map logic function efficiently
|
||||||
|
|
||||||
|
- 4-input LUT and single FF (see details in :ref:`qlsofa_hd_clb_arch_le_single_lut4_mode`).
|
||||||
|
- Dual 3-input LUTs and 2 FFs (see details in :ref:`qlsofa_hd_clb_arch_le_dual_lut3_mode`).
|
||||||
|
- 2-bit shift registers (see details in :ref:`qlsofa_hd_clb_arch_le_shift_reg_mode`).
|
||||||
|
|
||||||
|
|
||||||
|
.. _qlsofa_hd_clb_arch_le_single_lut4_mode:
|
||||||
|
|
||||||
|
Operating mode: LUT4 + FF
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
The logic element can operate in the Look-Up Table (LUT) + Flip-flop (FF) mode as many classical FPGA logic elements.
|
||||||
|
As depicted in :numref:`fig_qlsofa_hd_fle_arch_single_lut4_mode`, the fracturable LUT will operate as a single-output 4-input LUT and the upper FF is used to implemented sequential logic.
|
||||||
|
|
||||||
|
The operating mode is designed to efficiently implement 4-input functions.
|
||||||
|
|
||||||
|
.. _fig_qlsofa_hd_fle_arch_single_lut4_mode:
|
||||||
|
|
||||||
|
.. figure:: ./figures/qlsofa_hd_fle_arch_single_lut4_mode.svg
|
||||||
|
:scale: 30%
|
||||||
|
:alt: Logic element schematic
|
||||||
|
|
||||||
|
Resource usage of the logic element operating in LUT4 + FF mode (Grey blocks and lines are unused resources).
|
||||||
|
|
||||||
|
.. _qlsofa_hd_clb_arch_le_dual_lut3_mode:
|
||||||
|
|
||||||
|
Operating mode: Dual-LUT3
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
The logic element can operate in the dual Look-Up Tables (LUTs) and Flip-flops (FFs) mode as many modern FPGA logic elements.
|
||||||
|
As depicted in :numref:`fig_qlsofa_hd_fle_arch_dual_lut3_mode`, the fracturable LUT will operate as two 3-input LUTs with shared inputs.
|
||||||
|
|
||||||
|
The operating mode is designed to efficiently implement two 3-input functions with shared input variables. A popular example is the adder function, where the carry logic can be mapped to the upper LUT3 and the sum logic can be mapped to the lower LUT3.
|
||||||
|
|
||||||
|
.. _fig_qlsofa_hd_fle_arch_dual_lut3_mode:
|
||||||
|
|
||||||
|
.. figure:: ./figures/qlsofa_hd_fle_arch_dual_lut3_mode.svg
|
||||||
|
:scale: 30%
|
||||||
|
:alt: Logic element schematic
|
||||||
|
|
||||||
|
Resource usage of the logic element operating in dual LUT3 + FFs mode (Grey blocks and lines are unused resources).
|
||||||
|
|
||||||
|
.. _qlsofa_hd_clb_arch_le_shift_reg_mode:
|
||||||
|
|
||||||
|
Operating mode: Shift-Register
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
As depicted in :numref:`fig_qlsofa_hd_fle_arch_shift_register_mode`, the Flip-flops (FFs) can be connected in dedicated routing wires to implement high-performance shift registers.
|
||||||
|
|
||||||
|
The operating mode is designed to efficiently implement shift registers which are widely used in buffer logic, e.g., FIFOs.
|
||||||
|
|
||||||
|
.. _fig_qlsofa_hd_fle_arch_shift_register_mode:
|
||||||
|
|
||||||
|
.. figure:: ./figures/qlsofa_hd_fle_arch_shift_register_mode.svg
|
||||||
|
:scale: 30%
|
||||||
|
:alt: Logic element schematic
|
||||||
|
|
||||||
|
Resource usage of the logic element operating in shift register mode (Grey blocks and lines are unused resources).
|
||||||
|
|
||||||
|
.. _qlsofa_hd_clb_arch_le_soft_adder_mode:
|
||||||
|
|
||||||
|
Operating mode: Soft Adder
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
As depicted in :numref:`fig_qlsofa_hd_fle_arch_soft_adder_mode`, the 4-input LUT can implement an 1-bit adder logic, where carry inputs and outputs are connected through dedicated carry chain wires ``cin`` and ``cout`` across logic elements. This is more delay efficient than implementing adders through the dual LUT3 mode (see details in :ref:`qlsofa_hd_clb_arch_le_dual_lut3_mode`).
|
||||||
|
|
||||||
|
The operating mode is designed to efficiently implement multi-bit adders.
|
||||||
|
|
||||||
|
.. _fig_qlsofa_hd_fle_arch_soft_adder_mode:
|
||||||
|
|
||||||
|
.. figure:: ./figures/qlsofa_hd_fle_arch_soft_adder_mode.svg
|
||||||
|
:scale: 30%
|
||||||
|
:alt: Logic element schematic
|
||||||
|
|
||||||
|
Resource usage of the logic element operating in soft adder mode (Grey blocks and lines are unused resources).
|
||||||
|
|
||||||
|
.. _qlsofa_hd_clb_arch_scan_chain:
|
||||||
|
|
||||||
|
|
||||||
|
Scan Chain
|
||||||
|
~~~~~~~~~~
|
||||||
|
|
||||||
|
There is a built-in scan-chain in the CLB where all the `sc_in` and `sc_out` ports of LEs are connected in a chain, as illustrated in :numref:`fig_qlsofa_hd_clb_arch`.
|
||||||
|
When `Test_en` signal is active, users can readback the contents of all the D-type flip-flops of the LEs thanks to the scan-chain.
|
||||||
|
When `Test_en` signal is disabled, D-type flip-flops of the LEs operate in regular mode to propagate datapath signal from LUT outputs.
|
||||||
|
|
||||||
|
.. note:: The scan-chain of CLBs are connected in a chain at the top-level. See details in :ref:`qlsofa_hd_fpga_arch_scan_chain`.
|
||||||
|
|
@ -0,0 +1,76 @@
|
||||||
|
.. _qlsofa_hd_fpga_arch:
|
||||||
|
|
||||||
|
Architecture
|
||||||
|
-------------
|
||||||
|
|
||||||
|
:numref:`fig_qlsofa_hd_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric.
|
||||||
|
The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric.
|
||||||
|
I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`qlsofa_hd_io_resource`).
|
||||||
|
|
||||||
|
.. _fig_qlsofa_hd_fpga_arch:
|
||||||
|
|
||||||
|
.. figure:: ./figures/qlsofa_hd_fpga_arch.svg
|
||||||
|
:scale: 25%
|
||||||
|
:alt: Tile-based FPGA architecture
|
||||||
|
|
||||||
|
Tile-based FPGA architecture
|
||||||
|
|
||||||
|
|
||||||
|
.. _qlsofa_hd_fpga_arch_tiles:
|
||||||
|
|
||||||
|
Tiles
|
||||||
|
-----
|
||||||
|
|
||||||
|
The FPGA architecture follows a tile-based organization, to exploit the fine-grainularity in physical design, where three types of tiles are built:
|
||||||
|
|
||||||
|
.. table:: FPGA tile type and functionalities
|
||||||
|
|
||||||
|
+------+----------+----------------------------------------------+
|
||||||
|
| Type | Capacity | Description |
|
||||||
|
+======+==========+==============================================+
|
||||||
|
| CLB | 144 || Each CLB tile consists of |
|
||||||
|
| | || - a Configurable Logic Block (CLB) |
|
||||||
|
| | || - a X-direction Connection Block (CBx) |
|
||||||
|
| | || - a Y-direction Connection Block (CBy) |
|
||||||
|
| | || - a Switch Block (SB). |
|
||||||
|
| | | |
|
||||||
|
| | || This is the majority tile across the fabric |
|
||||||
|
| | | to implement logics and registers. |
|
||||||
|
+------+----------+----------------------------------------------+
|
||||||
|
| IO-A | 36 || The type-A I/O is a low-density I/O tile |
|
||||||
|
| | | which is designed to mainly interface |
|
||||||
|
| | || the GPIOs of the SoC. |
|
||||||
|
| | | |
|
||||||
|
| | || Each I/O-A tile consists of 1 digitial I/O |
|
||||||
|
| | | cell. |
|
||||||
|
+------+----------+----------------------------------------------+
|
||||||
|
| IO-B | 12 || The type-B I/O is a high-density I/O tile |
|
||||||
|
| | | which is designed to mainly interface |
|
||||||
|
| | || the wishbone interface and logic analyzer |
|
||||||
|
| | | of the SoC. |
|
||||||
|
| | | |
|
||||||
|
| | || Each I/O-B tile consists of 9 digitial I/O |
|
||||||
|
| | | cells. |
|
||||||
|
+------+----------+----------------------------------------------+
|
||||||
|
|
||||||
|
.. _qlsofa_hd_fpga_arch_scan_chain:
|
||||||
|
|
||||||
|
Scan-chain
|
||||||
|
----------
|
||||||
|
|
||||||
|
There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`qlsofa_hd_clb_arch_scan_chain`), as illustrated in :numref:`fig_qlsofa_hd_fabric_scan_chain`.
|
||||||
|
|
||||||
|
When `Test_en` signal is active, users can
|
||||||
|
|
||||||
|
- overwrite the contents of all the D-type flip-flops in the FPGA by feeding signals to the `SC_HEAD` port
|
||||||
|
- readback the contents of all the D-type flip-flops in the FPGA through the `SC_TAIL` port.
|
||||||
|
|
||||||
|
.. _fig_qlsofa_hd_fabric_scan_chain:
|
||||||
|
|
||||||
|
.. figure:: ./figures/qlsofa_hd_fabric_scan_chain.svg
|
||||||
|
:scale: 25%
|
||||||
|
:alt: Built-in scan-chain across FPGA
|
||||||
|
|
||||||
|
Built-in scan-chain across FPGA
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,109 @@
|
||||||
|
.. _qlsofa_hd_io_resource:
|
||||||
|
|
||||||
|
I/O Resources
|
||||||
|
-------------
|
||||||
|
|
||||||
|
DATA I/Os
|
||||||
|
^^^^^^^^^
|
||||||
|
|
||||||
|
The *High-Density* (HD) FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`.
|
||||||
|
|
||||||
|
Among the 144 I/Os,
|
||||||
|
|
||||||
|
- **29 external I/Os** are accessible through the Caravel SoC's *General-Purpose I/Os* (GPIOs).
|
||||||
|
|
||||||
|
- **115 internal I/Os** are accessible through the Caravel SOC's logic analyzer and wishbone interfaces, which are controlled by the RISC-V processor. See :ref:`qlsofa_hd_io_resource_debug` and :ref:`qlsofa_hd_io_resource_accelerator` for details.
|
||||||
|
|
||||||
|
.. warning:: For all the unused GPIOs, please set them to **input** mode, so that the FPGA will not output any noise signals to damage other SoC components.
|
||||||
|
|
||||||
|
.. note:: The connectivity of the 115 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes.
|
||||||
|
|
||||||
|
.. warning:: The internal I/O pins will drive either Wishbone or the logic analyzer, following the same truth table as mode-switch bit in :numref:`fig_qlsofa_hd_fpga_io_switch`.
|
||||||
|
|
||||||
|
.. _fig_qlsofa_hd_fpga_io_switch:
|
||||||
|
|
||||||
|
.. figure:: ./figures/qlsofa_hd_fpga_io_switch.svg
|
||||||
|
:scale: 20%
|
||||||
|
:alt: I/O arrangement of FPGA IP
|
||||||
|
|
||||||
|
I/O arrangement of *High-Density* (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface
|
||||||
|
|
||||||
|
.. _io_resource_qlsofa_hd_external_io:
|
||||||
|
|
||||||
|
External I/Os
|
||||||
|
~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
A SOFA HD FPGA IP contains 37 external I/O pins, including 29 data I/Os and 8 control I/Os.
|
||||||
|
|
||||||
|
Full details are summarized in the following table.
|
||||||
|
|
||||||
|
.. table:: SOFA HD FPGA I/O usage and sizes
|
||||||
|
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| I/O Type | Description | No. of Pins |
|
||||||
|
+===========+========================================================================+=============+
|
||||||
|
| Data I/O | Datapath I/Os of FPGA fabric | 29 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| Clk | Operating clock of FPGA core | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| ProgClk | Clock used by configuration protocol to program FPGA fabric | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| CCin | Input of configuation protocol to load bitstream | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| CCout | Output of configuration protocol to read back bitstream | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| TestEn | Activate the test mode of FPGA fabric | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| SCin | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| SCout | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| IO_ISLO_N | Active-low signal to enable I/O datapath isolation from external ports | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| Total | | 37 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
|
||||||
|
.. _qlsofa_hd_io_resource_accelerator:
|
||||||
|
|
||||||
|
Accelerator Mode
|
||||||
|
~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor.
|
||||||
|
:numref:`fig_qlsofa_hd_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations.
|
||||||
|
|
||||||
|
.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:29] are not connected.
|
||||||
|
|
||||||
|
.. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator.
|
||||||
|
|
||||||
|
.. _fig_qlsofa_hd_fpga_io_map_wishbone_mode:
|
||||||
|
|
||||||
|
.. figure:: ./figures/qlsofa_hd_fpga_io_map_wishbone_mode.svg
|
||||||
|
:scale: 20%
|
||||||
|
:alt: I/O arrangement of FPGA IP when interfacing wishbone bus
|
||||||
|
|
||||||
|
I/O arrangement of *High-Density* (HD) FPGA IP when interfacing wishbone bus
|
||||||
|
|
||||||
|
.. _qlsofa_hd_io_resource_debug:
|
||||||
|
|
||||||
|
Debug Mode
|
||||||
|
~~~~~~~~~~
|
||||||
|
|
||||||
|
When the logic analyzer interface is enabled, the FPGA can operate in debug mode, whose internal signals can be readback through the registers of the RISC-V processor.
|
||||||
|
:numref:`fig_qlsofa_hd_fpga_io_map_logic_analyzer_mode` illustrates the detailed I/O arrangement for the FPGA, where the logic analyzer signals are connected to fixed FPGA I/O locations.
|
||||||
|
|
||||||
|
.. note:: The logic analyzer is 128-bit, while 115 bits can drive or be driven by the FPGA I/O. The other 14 bits are connected to internal spots of the FPGA fabric, monitoring critical signal activities of the FPGA in debugging purpose.
|
||||||
|
|
||||||
|
.. warning:: If the logic analyzer is not used, please configure both the management SoC and the FPGA as follows:
|
||||||
|
|
||||||
|
- all the I/O directionality is set to **input mode**.
|
||||||
|
- all the output ports is pulled down to **logic ``0``**.
|
||||||
|
|
||||||
|
.. _fig_qlsofa_hd_fpga_io_map_logic_analyzer_mode:
|
||||||
|
|
||||||
|
.. figure:: ./figures/qlsofa_hd_fpga_io_map_logic_analyzer_mode.svg
|
||||||
|
:scale: 20%
|
||||||
|
:alt: I/O arrangement of FPGA IP when interfacing logic analyzer
|
||||||
|
|
||||||
|
I/O arrangement of *High-Density* (HD) FPGA IP when interfacing logic analyzer
|
||||||
|
|
||||||
|
|
||||||
|
Before Width: | Height: | Size: 38 KiB After Width: | Height: | Size: 38 KiB |
|
Before Width: | Height: | Size: 18 KiB After Width: | Height: | Size: 18 KiB |
|
Before Width: | Height: | Size: 22 KiB After Width: | Height: | Size: 22 KiB |
|
Before Width: | Height: | Size: 21 KiB After Width: | Height: | Size: 21 KiB |
|
Before Width: | Height: | Size: 21 KiB After Width: | Height: | Size: 21 KiB |
|
Before Width: | Height: | Size: 21 KiB After Width: | Height: | Size: 21 KiB |
|
Before Width: | Height: | Size: 21 KiB After Width: | Height: | Size: 21 KiB |
|
Before Width: | Height: | Size: 72 KiB After Width: | Height: | Size: 72 KiB |
|
Before Width: | Height: | Size: 16 KiB After Width: | Height: | Size: 16 KiB |
|
Before Width: | Height: | Size: 17 KiB After Width: | Height: | Size: 17 KiB |
|
Before Width: | Height: | Size: 25 KiB After Width: | Height: | Size: 25 KiB |
|
|
@ -0,0 +1,16 @@
|
||||||
|
.. _datasheet_sofa_hd:
|
||||||
|
SOFA HD
|
||||||
|
|
||||||
|
SOFA HD
|
||||||
|
-------
|
||||||
|
|
||||||
|
.. toctree::
|
||||||
|
:maxdepth: 2
|
||||||
|
|
||||||
|
sofa_hd_fpga_arch
|
||||||
|
|
||||||
|
sofa_hd_io_resource
|
||||||
|
|
||||||
|
sofa_hd_clb_arch
|
||||||
|
|
||||||
|
sofa_hd_circuit_design
|
||||||
|
|
@ -0,0 +1,36 @@
|
||||||
|
.. _sofa_hd_circuit_design:
|
||||||
|
|
||||||
|
Circuit Designs
|
||||||
|
---------------
|
||||||
|
|
||||||
|
.. _sofa_hd_circuit_design_io:
|
||||||
|
|
||||||
|
I/O Circuit
|
||||||
|
^^^^^^^^^^^
|
||||||
|
|
||||||
|
As shown in :numref:`fig_sofa_hd_embedded_io_schematic`, the I/O circuit used in the I/O tiles of the FPGA fabric (see :numref:`fig_sofa_hd_fpga_arch`) is an digital I/O cell with
|
||||||
|
|
||||||
|
- An **active-low** I/O isolation signal ``IO_ISOL_N`` to set the I/O in input mode. This is to avoid any unexpected output signals to damage circuits outside the FPGA due to configurable memories are not properly initialized.
|
||||||
|
|
||||||
|
.. warning:: This feature may not be needed if the configurable memory cell has a built-in set/reset functionality!
|
||||||
|
|
||||||
|
- An internal protection circuitry to ensure clean signals at all the SOC I/O ports. This is to avoid
|
||||||
|
|
||||||
|
- ``SOC_OUT`` port outputs any random signal when the I/O is in input mode
|
||||||
|
- ``FPGA_IN`` port is driven by any random signal when the I/O is output mode
|
||||||
|
|
||||||
|
- An internal configurable memory element to control the direction of I/O cell
|
||||||
|
|
||||||
|
The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where
|
||||||
|
|
||||||
|
- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode
|
||||||
|
|
||||||
|
- When configuration bit (FF output) is logic ``0``, the I/O cell is in output mode
|
||||||
|
|
||||||
|
.. _fig_sofa_hd_embedded_io_schematic:
|
||||||
|
|
||||||
|
.. figure:: ./figures/sofa_hd_embedded_io_schematic.svg
|
||||||
|
:scale: 30%
|
||||||
|
:alt: Schematic of embedded I/O cell used in FPGA
|
||||||
|
|
||||||
|
Schematic of embedded I/O cell used in FPGA
|
||||||
|
|
@ -1,26 +1,26 @@
|
||||||
.. _clb_arch:
|
.. _sofa_hd_clb_arch:
|
||||||
|
|
||||||
Configurable Logic Block
|
Configurable Logic Block
|
||||||
------------------------
|
------------------------
|
||||||
|
|
||||||
.. _clb_arch_generality:
|
.. _sofa_hd_clb_arch_generality:
|
||||||
|
|
||||||
Generality
|
Generality
|
||||||
~~~~~~~~~~
|
~~~~~~~~~~
|
||||||
|
|
||||||
Each Logic Block (CLB) consists of 8 Logic Elements (LEs) as shown in :numref:`fig_clb_arch`.
|
Each Logic Block (CLB) consists of 8 Logic Elements (LEs) as shown in :numref:`fig_sofa_hd_clb_arch`.
|
||||||
All the pins of the LEs are directly wired to CLB pins without a local routing architecture.
|
All the pins of the LEs are directly wired to CLB pins without a local routing architecture.
|
||||||
Feedback connections between LEs are implemented by the global routing architecture outside the CLBs.
|
Feedback connections between LEs are implemented by the global routing architecture outside the CLBs.
|
||||||
|
|
||||||
.. _fig_clb_arch:
|
.. _fig_sofa_hd_clb_arch:
|
||||||
|
|
||||||
.. figure:: ./figures/clb_arch.svg
|
.. figure:: ./figures/sofa_hd_clb_arch.svg
|
||||||
:scale: 20%
|
:scale: 20%
|
||||||
:alt: Configurable Logic Block schematic
|
:alt: Configurable Logic Block schematic
|
||||||
|
|
||||||
Configurable logic block schematic
|
Configurable logic block schematic
|
||||||
|
|
||||||
.. _clb_arch_le:
|
.. _sofa_hd_clb_arch_le:
|
||||||
|
|
||||||
Multi-mode Logic Element
|
Multi-mode Logic Element
|
||||||
~~~~~~~~~~~~~~~~~~~~~~~~
|
~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
@ -28,14 +28,14 @@ Multi-mode Logic Element
|
||||||
Physical Implementation
|
Physical Implementation
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^
|
^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
As shown in :numref:`fig_fle_arch`, each Logic Element (LE) consists of
|
As shown in :numref:`fig_sofa_hd_fle_arch`, each Logic Element (LE) consists of
|
||||||
|
|
||||||
- a fracturable 4-input Look-Up Table (LUT)
|
- a fracturable 4-input Look-Up Table (LUT)
|
||||||
- two D-type Flip-Flops (FF)
|
- two D-type Flip-Flops (FF)
|
||||||
|
|
||||||
.. _fig_fle_arch:
|
.. _fig_sofa_hd_fle_arch:
|
||||||
|
|
||||||
.. figure:: ./figures/fle_arch.svg
|
.. figure:: ./figures/sofa_hd_fle_arch.svg
|
||||||
:scale: 30%
|
:scale: 30%
|
||||||
:alt: Logic element schematic
|
:alt: Logic element schematic
|
||||||
|
|
||||||
|
|
@ -43,71 +43,71 @@ As shown in :numref:`fig_fle_arch`, each Logic Element (LE) consists of
|
||||||
|
|
||||||
The LE can operate in different modes to map logic function efficiently
|
The LE can operate in different modes to map logic function efficiently
|
||||||
|
|
||||||
- 4-input LUT and single FF (see details in :ref:`clb_arch_le_single_lut4_mode`).
|
- 4-input LUT and single FF (see details in :ref:`sofa_hd_clb_arch_le_single_lut4_mode`).
|
||||||
- Dual 3-input LUTs and 2 FFs (see details in :ref:`clb_arch_le_dual_lut3_mode`).
|
- Dual 3-input LUTs and 2 FFs (see details in :ref:`sofa_hd_clb_arch_le_dual_lut3_mode`).
|
||||||
- 2-bit shift registers (see details in :ref:`clb_arch_le_shift_reg_mode`).
|
- 2-bit shift registers (see details in :ref:`sofa_hd_clb_arch_le_shift_reg_mode`).
|
||||||
|
|
||||||
|
|
||||||
.. _clb_arch_le_single_lut4_mode:
|
.. _sofa_hd_clb_arch_le_single_lut4_mode:
|
||||||
|
|
||||||
Operating mode: LUT4 + FF
|
Operating mode: LUT4 + FF
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
The logic element can operate in the Look-Up Table (LUT) + Flip-flop (FF) mode as many classical FPGA logic elements.
|
The logic element can operate in the Look-Up Table (LUT) + Flip-flop (FF) mode as many classical FPGA logic elements.
|
||||||
As depicted in :numref:`fig_fle_arch_single_lut4_mode`, the fracturable LUT will operate as a single-output 4-input LUT and the upper FF is used to implemented sequential logic.
|
As depicted in :numref:`fig_sofa_hd_fle_arch_single_lut4_mode`, the fracturable LUT will operate as a single-output 4-input LUT and the upper FF is used to implemented sequential logic.
|
||||||
|
|
||||||
The operating mode is designed to efficiently implement 4-input functions.
|
The operating mode is designed to efficiently implement 4-input functions.
|
||||||
|
|
||||||
.. _fig_fle_arch_single_lut4_mode:
|
.. _fig_sofa_hd_fle_arch_single_lut4_mode:
|
||||||
|
|
||||||
.. figure:: ./figures/fle_arch_single_lut4_mode.svg
|
.. figure:: ./figures/sofa_hd_fle_arch_single_lut4_mode.svg
|
||||||
:scale: 30%
|
:scale: 30%
|
||||||
:alt: Logic element schematic
|
:alt: Logic element schematic
|
||||||
|
|
||||||
Resource usage of the logic element operating in LUT4 + FF mode (Grey blocks and lines are unused resources).
|
Resource usage of the logic element operating in LUT4 + FF mode (Grey blocks and lines are unused resources).
|
||||||
|
|
||||||
.. _clb_arch_le_dual_lut3_mode:
|
.. _sofa_hd_clb_arch_le_dual_lut3_mode:
|
||||||
|
|
||||||
Operating mode: Dual-LUT3
|
Operating mode: Dual-LUT3
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
The logic element can operate in the dual Look-Up Tables (LUTs) and Flip-flops (FFs) mode as many modern FPGA logic elements.
|
The logic element can operate in the dual Look-Up Tables (LUTs) and Flip-flops (FFs) mode as many modern FPGA logic elements.
|
||||||
As depicted in :numref:`fig_fle_arch_dual_lut3_mode`, the fracturable LUT will operate as two 3-input LUTs with shared inputs.
|
As depicted in :numref:`fig_sofa_hd_fle_arch_dual_lut3_mode`, the fracturable LUT will operate as two 3-input LUTs with shared inputs.
|
||||||
|
|
||||||
The operating mode is designed to efficiently implement two 3-input functions with shared input variables. A popular example is the adder function, where the carry logic can be mapped to the upper LUT3 and the sum logic can be mapped to the lower LUT3.
|
The operating mode is designed to efficiently implement two 3-input functions with shared input variables. A popular example is the adder function, where the carry logic can be mapped to the upper LUT3 and the sum logic can be mapped to the lower LUT3.
|
||||||
|
|
||||||
.. _fig_fle_arch_dual_lut3_mode:
|
.. _fig_sofa_hd_fle_arch_dual_lut3_mode:
|
||||||
|
|
||||||
.. figure:: ./figures/fle_arch_dual_lut3_mode.svg
|
.. figure:: ./figures/sofa_hd_fle_arch_dual_lut3_mode.svg
|
||||||
:scale: 30%
|
:scale: 30%
|
||||||
:alt: Logic element schematic
|
:alt: Logic element schematic
|
||||||
|
|
||||||
Resource usage of the logic element operating in dual LUT3 + FFs mode (Grey blocks and lines are unused resources).
|
Resource usage of the logic element operating in dual LUT3 + FFs mode (Grey blocks and lines are unused resources).
|
||||||
|
|
||||||
.. _clb_arch_le_shift_reg_mode:
|
.. _sofa_hd_clb_arch_le_shift_reg_mode:
|
||||||
|
|
||||||
Operating mode: Shift-Register
|
Operating mode: Shift-Register
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
As depicted in :numref:`fig_fle_arch_shift_reg_mode`, the Flip-flops (FFs) can be connected in dedicated routing wires to implement high-performance shift registers.
|
As depicted in :numref:`fig_sofa_hd_fle_arch_shift_reg_mode`, the Flip-flops (FFs) can be connected in dedicated routing wires to implement high-performance shift registers.
|
||||||
|
|
||||||
The operating mode is designed to efficiently implement shift registers which are widely used in buffer logic, e.g., FIFOs.
|
The operating mode is designed to efficiently implement shift registers which are widely used in buffer logic, e.g., FIFOs.
|
||||||
|
|
||||||
.. _fig_fle_arch_shift_reg_mode:
|
.. _fig_sofa_hd_fle_arch_shift_reg_mode:
|
||||||
|
|
||||||
.. figure:: ./figures/fle_arch_shift_reg_mode.svg
|
.. figure:: ./figures/sofa_hd_fle_arch_shift_reg_mode.svg
|
||||||
:scale: 30%
|
:scale: 30%
|
||||||
:alt: Logic element schematic
|
:alt: Logic element schematic
|
||||||
|
|
||||||
Resource usage of the logic element operating in shift register mode (Grey blocks and lines are unused resources).
|
Resource usage of the logic element operating in shift register mode (Grey blocks and lines are unused resources).
|
||||||
|
|
||||||
.. _clb_arch_scan_chain:
|
.. _sofa_hd_clb_arch_scan_chain:
|
||||||
|
|
||||||
Scan Chain
|
Scan Chain
|
||||||
~~~~~~~~~~
|
~~~~~~~~~~
|
||||||
|
|
||||||
There is a built-in scan-chain in the CLB where all the `sc_in` and `sc_out` ports of LEs are connected in a chain, as illustrated in :numref:`fig_clb_arch`.
|
There is a built-in scan-chain in the CLB where all the `sc_in` and `sc_out` ports of LEs are connected in a chain, as illustrated in :numref:`fig_sofa_hd_clb_arch`.
|
||||||
When `Test_en` signal is active, users can readback the contents of all the D-type flip-flops of the LEs thanks to the scan-chain.
|
When `Test_en` signal is active, users can readback the contents of all the D-type flip-flops of the LEs thanks to the scan-chain.
|
||||||
When `Test_en` signal is disabled, D-type flip-flops of the LEs operate in regular mode to propagate datapath signal from LUT outputs.
|
When `Test_en` signal is disabled, D-type flip-flops of the LEs operate in regular mode to propagate datapath signal from LUT outputs.
|
||||||
|
|
||||||
.. note:: The scan-chain of CLBs are connected in a chain at the top-level. See details in :ref:`fpga_arch_scan_chain`.
|
.. note:: The scan-chain of CLBs are connected in a chain at the top-level. See details in :ref:`sofa_hd_fpga_arch_scan_chain`.
|
||||||
|
|
@ -1,30 +1,25 @@
|
||||||
.. _fpga_arch:
|
.. _sofa_hd_fpga_arch:
|
||||||
|
|
||||||
FPGA Overview
|
Architecture
|
||||||
-------------
|
-------------
|
||||||
|
|
||||||
.. _fpga_arch_overview:
|
:numref:`fig_sofa_hd_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric.
|
||||||
|
|
||||||
Architecture Overview
|
|
||||||
~~~~~~~~~~~~~~~~~~~~~
|
|
||||||
|
|
||||||
:numref:`fig_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric.
|
|
||||||
The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric.
|
The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric.
|
||||||
I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`io_resource`).
|
I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`sofa_hd_io_resource`).
|
||||||
|
|
||||||
.. _fig_fpga_arch:
|
.. _fig_sofa_hd_fpga_arch:
|
||||||
|
|
||||||
.. figure:: ./figures/fpga_arch.svg
|
.. figure:: ./figures/sofa_hd_fpga_arch.svg
|
||||||
:scale: 25%
|
:scale: 25%
|
||||||
:alt: Tile-based FPGA architecture
|
:alt: Tile-based FPGA architecture
|
||||||
|
|
||||||
Tile-based FPGA architecture
|
Tile-based FPGA architecture
|
||||||
|
|
||||||
|
|
||||||
.. _fpga_arch_tiles:
|
.. _sofa_hd_fpga_arch_tiles:
|
||||||
|
|
||||||
Tiles
|
Tiles
|
||||||
~~~~~
|
-----
|
||||||
|
|
||||||
The FPGA architecture follows a tile-based organization, to exploit the fine-grainularity in physical design, where three types of tiles are built:
|
The FPGA architecture follows a tile-based organization, to exploit the fine-grainularity in physical design, where three types of tiles are built:
|
||||||
|
|
||||||
|
|
@ -58,21 +53,21 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra
|
||||||
| | | cells. |
|
| | | cells. |
|
||||||
+------+----------+----------------------------------------------+
|
+------+----------+----------------------------------------------+
|
||||||
|
|
||||||
.. _fpga_arch_scan_chain:
|
.. _sofa_hd_fpga_arch_scan_chain:
|
||||||
|
|
||||||
Scan-chain
|
Scan-chain
|
||||||
~~~~~~~~~~
|
----------
|
||||||
|
|
||||||
There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`clb_arch_scan_chain`), as illustrated in :numref:`fig_fabric_scan_chain`.
|
There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`sofa_hd_clb_arch_scan_chain`), as illustrated in :numref:`fig_sofa_hd_fabric_scan_chain`.
|
||||||
|
|
||||||
When `Test_en` signal is active, users can
|
When `Test_en` signal is active, users can
|
||||||
|
|
||||||
- overwrite the contents of all the D-type flip-flops in the FPGA by feeding signals to the `SC_HEAD` port
|
- overwrite the contents of all the D-type flip-flops in the FPGA by feeding signals to the `SC_HEAD` port
|
||||||
- readback the contents of all the D-type flip-flops in the FPGA through the `SC_TAIL` port.
|
- readback the contents of all the D-type flip-flops in the FPGA through the `SC_TAIL` port.
|
||||||
|
|
||||||
.. _fig_fabric_scan_chain:
|
.. _fig_sofa_hd_fabric_scan_chain:
|
||||||
|
|
||||||
.. figure:: ./figures/fabric_scan_chain.svg
|
.. figure:: ./figures/sofa_hd_fabric_scan_chain.svg
|
||||||
:scale: 25%
|
:scale: 25%
|
||||||
:alt: Built-in scan-chain across FPGA
|
:alt: Built-in scan-chain across FPGA
|
||||||
|
|
||||||
|
|
@ -0,0 +1,109 @@
|
||||||
|
.. _sofa_hd_io_resource:
|
||||||
|
|
||||||
|
I/O Resources
|
||||||
|
-------------
|
||||||
|
|
||||||
|
DATA I/Os
|
||||||
|
^^^^^^^^^
|
||||||
|
|
||||||
|
The *High-Density* (HD) FPGA IP has 144 data I/O pins as shown in :numref:`fig_sofa_hd_fpga_io_switch`.
|
||||||
|
|
||||||
|
Among the 144 I/Os,
|
||||||
|
|
||||||
|
- **29 external I/Os** are accessible through the Caravel SoC's *General-Purpose I/Os* (GPIOs).
|
||||||
|
|
||||||
|
- **115 internal I/Os** are accessible through the Caravel SOC's logic analyzer and wishbone interfaces, which are controlled by the RISC-V processor. See :ref:`sofa_hd_io_resource_debug` and :ref:`sofa_hd_io_resource_accelerator` for details.
|
||||||
|
|
||||||
|
.. warning:: For all the unused GPIOs, please set them to **input** mode, so that the FPGA will not output any noise signals to damage other SoC components.
|
||||||
|
|
||||||
|
.. note:: The connectivity of the 115 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes.
|
||||||
|
|
||||||
|
.. warning:: The internal I/O pins will drive either Wishbone or the logic analyzer, following the same truth table as mode-switch bit in :numref:`fig_sofa_hd_fpga_io_switch`.
|
||||||
|
|
||||||
|
.. _fig_sofa_hd_fpga_io_switch:
|
||||||
|
|
||||||
|
.. figure:: ./figures/sofa_hd_fpga_io_switch.svg
|
||||||
|
:scale: 20%
|
||||||
|
:alt: I/O arrangement of FPGA IP
|
||||||
|
|
||||||
|
I/O arrangement of *High-Density* (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface
|
||||||
|
|
||||||
|
.. _io_resource_sofa_hd_external_io:
|
||||||
|
|
||||||
|
External I/Os
|
||||||
|
~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
A SOFA HD FPGA IP contains 37 external I/O pins, including 29 data I/Os and 8 control I/Os.
|
||||||
|
|
||||||
|
Full details are summarized in the following table.
|
||||||
|
|
||||||
|
.. table:: SOFA HD FPGA I/O usage and sizes
|
||||||
|
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| I/O Type | Description | No. of Pins |
|
||||||
|
+===========+========================================================================+=============+
|
||||||
|
| Data I/O | Datapath I/Os of FPGA fabric | 29 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| Clk | Operating clock of FPGA core | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| ProgClk | Clock used by configuration protocol to program FPGA fabric | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| CCin | Input of configuation protocol to load bitstream | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| CCout | Output of configuration protocol to read back bitstream | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| TestEn | Activate the test mode of FPGA fabric | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| SCin | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| SCout | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| IO_ISLO_N | Active-low signal to enable I/O datapath isolation from external ports | 1 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
| Total | | 37 |
|
||||||
|
+-----------+------------------------------------------------------------------------+-------------+
|
||||||
|
|
||||||
|
.. _sofa_hd_io_resource_accelerator:
|
||||||
|
|
||||||
|
Accelerator Mode
|
||||||
|
~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor.
|
||||||
|
:numref:`fig_sofa_hd_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations.
|
||||||
|
|
||||||
|
.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:29] are not connected.
|
||||||
|
|
||||||
|
.. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator.
|
||||||
|
|
||||||
|
.. _fig_sofa_hd_fpga_io_map_wishbone_mode:
|
||||||
|
|
||||||
|
.. figure:: ./figures/sofa_hd_fpga_io_map_wishbone_mode.svg
|
||||||
|
:scale: 20%
|
||||||
|
:alt: I/O arrangement of FPGA IP when interfacing wishbone bus
|
||||||
|
|
||||||
|
I/O arrangement of *High-Density* (HD) FPGA IP when interfacing wishbone bus
|
||||||
|
|
||||||
|
.. _sofa_hd_io_resource_debug:
|
||||||
|
|
||||||
|
Debug Mode
|
||||||
|
~~~~~~~~~~
|
||||||
|
|
||||||
|
When the logic analyzer interface is enabled, the FPGA can operate in debug mode, whose internal signals can be readback through the registers of the RISC-V processor.
|
||||||
|
:numref:`fig_sofa_hd_fpga_io_map_logic_analyzer_mode` illustrates the detailed I/O arrangement for the FPGA, where the logic analyzer signals are connected to fixed FPGA I/O locations.
|
||||||
|
|
||||||
|
.. note:: The logic analyzer is 128-bit, while 115 bits can drive or be driven by the FPGA I/O. The other 14 bits are connected to internal spots of the FPGA fabric, monitoring critical signal activities of the FPGA in debugging purpose.
|
||||||
|
|
||||||
|
.. warning:: If the logic analyzer is not used, please configure both the management SoC and the FPGA as follows:
|
||||||
|
|
||||||
|
- all the I/O directionality is set to **input mode**.
|
||||||
|
- all the output ports is pulled down to **logic ``0``**.
|
||||||
|
|
||||||
|
.. _fig_sofa_hd_fpga_io_map_logic_analyzer_mode:
|
||||||
|
|
||||||
|
.. figure:: ./figures/sofa_hd_fpga_io_map_logic_analyzer_mode.svg
|
||||||
|
:scale: 20%
|
||||||
|
:alt: I/O arrangement of FPGA IP when interfacing logic analyzer
|
||||||
|
|
||||||
|
I/O arrangement of *High-Density* (HD) FPGA IP when interfacing logic analyzer
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -1,75 +0,0 @@
|
||||||
.. _dc_ac_character:
|
|
||||||
|
|
||||||
DC and AC Characteristics
|
|
||||||
-------------------------
|
|
||||||
|
|
||||||
Each FPGA device contains 37 external I/O pins, whose details are summarized in the following tables.
|
|
||||||
|
|
||||||
I/O usage and port information
|
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
||||||
|
|
||||||
.. table:: I/O usage and sizes
|
|
||||||
|
|
||||||
+-----------+------------------------------------------------------------------------+-------------+
|
|
||||||
| I/O Type | Description | No. of Pins |
|
|
||||||
+===========+========================================================================+=============+
|
|
||||||
| Data I/O | Datapath I/Os of FPGA fabric | 29 |
|
|
||||||
+-----------+------------------------------------------------------------------------+-------------+
|
|
||||||
| Clk | Operating clock of FPGA core | 1 |
|
|
||||||
+-----------+------------------------------------------------------------------------+-------------+
|
|
||||||
| ProgClk | Clock used by configuration protocol to program FPGA fabric | 1 |
|
|
||||||
+-----------+------------------------------------------------------------------------+-------------+
|
|
||||||
| CCin | Input of configuation protocol to load bitstream | 1 |
|
|
||||||
+-----------+------------------------------------------------------------------------+-------------+
|
|
||||||
| CCout | Output of configuration protocol to read back bitstream | 1 |
|
|
||||||
+-----------+------------------------------------------------------------------------+-------------+
|
|
||||||
| TestEn | Activate the test mode of FPGA fabric | 1 |
|
|
||||||
+-----------+------------------------------------------------------------------------+-------------+
|
|
||||||
| SCin | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 |
|
|
||||||
+-----------+------------------------------------------------------------------------+-------------+
|
|
||||||
| SCout | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 |
|
|
||||||
+-----------+------------------------------------------------------------------------+-------------+
|
|
||||||
| IO_ISLO_N | Active-low signal to enable I/O datapath isolation from external ports | 1 |
|
|
||||||
+-----------+------------------------------------------------------------------------+-------------+
|
|
||||||
| Total | | 37 |
|
|
||||||
+-----------+------------------------------------------------------------------------+-------------+
|
|
||||||
|
|
||||||
Recommended Operating Conditions
|
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
||||||
|
|
||||||
.. table:: Recommended Operating Conditions
|
|
||||||
|
|
||||||
+----------+------------------------------+------+---------+------+-------+
|
|
||||||
| Symbol | Description | Min | Typical | Max | Units |
|
|
||||||
+==========+==============================+======+=========+======+=======+
|
|
||||||
| VDD_io | Supply voltage for I/Os | 1.8 | 3.3 | 5.0 | V |
|
|
||||||
+----------+------------------------------+------+---------+------+-------+
|
|
||||||
| VDD_core | Supply voltage for FPGA core | 1.62 | 1.8 | 1.98 | V |
|
|
||||||
+----------+------------------------------+------+---------+------+-------+
|
|
||||||
| V_in | Input voltage for other I/Os | TBD | 3.3 | TBD | V |
|
|
||||||
+----------+------------------------------+------+---------+------+-------+
|
|
||||||
| I_in | Maximum current through pins | N/A | TBD | TBD | mA |
|
|
||||||
+----------+------------------------------+------+---------+------+-------+
|
|
||||||
| f_max | Maximum frequency of I/Os | N/A | TBD | TBD | MHz |
|
|
||||||
+----------+------------------------------+------+---------+------+-------+
|
|
||||||
|
|
||||||
.. note:: Threshold voltage of logic `1` for I/O (V_OH) is 0.8 * VDD_io. In other words, V_in should be at least 2.64V in order to be sensed as logic `1`
|
|
||||||
.. note:: Threshold voltage of logic `0` for I/O (V_OH) is 0.4. In other words, V_in should not exceed 0.4V in order to be sensed as logic `0`.
|
|
||||||
|
|
||||||
Typical AC Characteristics
|
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
||||||
|
|
||||||
.. table:: Typical AC characteristics for FPGA I/Os
|
|
||||||
|
|
||||||
+-----------------+-------------------------------------------+------+------+-------+
|
|
||||||
| Symbol | Description | Min | Max | Units |
|
|
||||||
+=================+===========================================+======+======+=======+
|
|
||||||
| V_in Overshoot | Maximum allowed overshoot voltage for Vin | TBD | TBD | V |
|
|
||||||
+-----------------+-------------------------------------------+------+------+-------+
|
|
||||||
| V_in Undershoot | Minimum allowed overshoot voltage for Vin | TBD | TBD | V |
|
|
||||||
+-----------------+-------------------------------------------+------+------+-------+
|
|
||||||
| I_VDD_core | Quiescent VDD_core supply current | TBD | TBD | mA |
|
|
||||||
+-----------------+-------------------------------------------+------+------+-------+
|
|
||||||
| I_VDD_io | Quiescent VDD_io supply current | TBD | TBD | mA |
|
|
||||||
+-----------------+-------------------------------------------+------+------+-------+
|
|
||||||
|
|
||||||
|
|
@ -1,38 +0,0 @@
|
||||||
.. _device_resource:
|
|
||||||
|
|
||||||
Device Resources
|
|
||||||
----------------
|
|
||||||
|
|
||||||
.. _device_resource_hd_fpga:
|
|
||||||
|
|
||||||
High-Density FPGA
|
|
||||||
~~~~~~~~~~~~~~~~~
|
|
||||||
|
|
||||||
The High Density (HD) FPGA is an embedded FPGA built with the Skywater 130nm High Density Standard Cell library (`Sky130_fd_SC_HD <https://cs.opensource.google/skywater-pdk/skywater-pdk/+/master:libraries/sky130_fd_sc_hd/>`_).
|
|
||||||
|
|
||||||
.. table:: Logic capacity of High Density (HD) FPGA IP
|
|
||||||
|
|
||||||
+-------------------------------+------------+
|
|
||||||
| Resource Type | Capacity |
|
|
||||||
+===============================+============+
|
|
||||||
| Look-Up Tables [1]_ | 1152 |
|
|
||||||
+-------------------------------+------------+
|
|
||||||
| Flip-flops | 2304 |
|
|
||||||
+-------------------------------+------------+
|
|
||||||
| Max. Configuration Speed [2]_ | 50MHz |
|
|
||||||
+-------------------------------+------------+
|
|
||||||
| Max. Operating Speed [2]_ | 50MHz |
|
|
||||||
+-------------------------------+------------+
|
|
||||||
| User I/O Pins [3]_ | 144 |
|
|
||||||
+-------------------------------+------------+
|
|
||||||
| Max. I/O Speed [2]_ | 33MHz |
|
|
||||||
+-------------------------------+------------+
|
|
||||||
| Core Voltage | 1.8V |
|
|
||||||
+-------------------------------+------------+
|
|
||||||
|
|
||||||
.. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT.
|
|
||||||
|
|
||||||
.. [2] bounded by the maximum speed of `GPIO cells of Skywater 130nm PDK <https://skywater-pdk.readthedocs.io/en/latest/contents/libraries/sky130_fd_io/docs/user_guide.html#design-metrics-1>`_. Higher speed may be expected when a high-speed GPIO cell is available.
|
|
||||||
|
|
||||||
.. [3] I/Os are divided into two groups: GPIO and embedded I/O. See details in :ref:`io_resource`.
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,37 @@
|
||||||
|
.. _hd_fpga_device_comparison:
|
||||||
|
|
||||||
|
Device Comparison
|
||||||
|
-----------------
|
||||||
|
|
||||||
|
The High Density (HD) FPGAs are embedded FPGAs built with the Skywater 130nm High Density Standard Cell library (`Sky130_fd_SC_HD <https://cs.opensource.google/skywater-pdk/skywater-pdk/+/master:libraries/sky130_fd_sc_hd/>`_).
|
||||||
|
|
||||||
|
.. table:: Logic capacity of High Density (HD) FPGA IPs
|
||||||
|
|
||||||
|
+-------------------------------+------------+-----------+
|
||||||
|
| Resource/Capacity | SOFA HD | QLSOFA HD |
|
||||||
|
+===============================+============+===========+
|
||||||
|
| Look-Up Tables [1]_ | 1152 | 1152 |
|
||||||
|
+-------------------------------+------------+-----------+
|
||||||
|
| Flip-flops | 2304 | 2304 |
|
||||||
|
+-------------------------------+------------+-----------+
|
||||||
|
| Soft Adders [2]_ | N/A | 1152 |
|
||||||
|
+-------------------------------+------------+-----------+
|
||||||
|
| Max. Configuration Speed [3]_ | 50MHz | 50MHz |
|
||||||
|
+-------------------------------+------------+-----------+
|
||||||
|
| Max. Operating Speed [3]_ | 50MHz | 50 MHz |
|
||||||
|
+-------------------------------+------------+-----------+
|
||||||
|
| User I/O Pins [4]_ | 144 | 144 |
|
||||||
|
+-------------------------------+------------+-----------+
|
||||||
|
| Max. I/O Speed [3]_ | 33MHz | 33 MHz |
|
||||||
|
+-------------------------------+------------+-----------+
|
||||||
|
| Core Voltage | 1.8V | 1.8V |
|
||||||
|
+-------------------------------+------------+-----------+
|
||||||
|
|
||||||
|
.. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT.
|
||||||
|
|
||||||
|
.. [2] counted by 3-input Look-Up Tables (LUTs) that are organized as a carry chain
|
||||||
|
|
||||||
|
.. [3] bounded by the maximum speed of `GPIO cells of Skywater 130nm PDK <https://skywater-pdk.readthedocs.io/en/latest/contents/libraries/sky130_fd_io/docs/user_guide.html#design-metrics-1>`_. Higher speed may be expected when a high-speed GPIO cell is available.
|
||||||
|
|
||||||
|
.. [4] I/Os are divided into two groups: GPIOs and embedded I/Os.
|
||||||
|
|
||||||
|
|
@ -0,0 +1,44 @@
|
||||||
|
.. _hd_fpga_dc_ac_character:
|
||||||
|
|
||||||
|
DC and AC Characteristics
|
||||||
|
-------------------------
|
||||||
|
|
||||||
|
Recommended Operating Conditions
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
.. table:: Recommended Operating Conditions
|
||||||
|
|
||||||
|
+----------+------------------------------+------+---------+------+-------+
|
||||||
|
| Symbol | Description | Min | Typical | Max | Units |
|
||||||
|
+==========+==============================+======+=========+======+=======+
|
||||||
|
| VDD_io | Supply voltage for I/Os | 1.8 | 3.3 | 5.0 | V |
|
||||||
|
+----------+------------------------------+------+---------+------+-------+
|
||||||
|
| VDD_core | Supply voltage for FPGA core | 1.62 | 1.8 | 1.98 | V |
|
||||||
|
+----------+------------------------------+------+---------+------+-------+
|
||||||
|
| V_in | Input voltage for other I/Os | TBD | 3.3 | TBD | V |
|
||||||
|
+----------+------------------------------+------+---------+------+-------+
|
||||||
|
| I_in | Maximum current through pins | N/A | TBD | TBD | mA |
|
||||||
|
+----------+------------------------------+------+---------+------+-------+
|
||||||
|
| f_max | Maximum frequency of I/Os | N/A | TBD | TBD | MHz |
|
||||||
|
+----------+------------------------------+------+---------+------+-------+
|
||||||
|
|
||||||
|
.. note:: Threshold voltage of logic `1` for I/O (V_OH) is 0.8 * VDD_io. In other words, V_in should be at least 2.64V in order to be sensed as logic `1`
|
||||||
|
.. note:: Threshold voltage of logic `0` for I/O (V_OH) is 0.4. In other words, V_in should not exceed 0.4V in order to be sensed as logic `0`.
|
||||||
|
|
||||||
|
Typical AC Characteristics
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
.. table:: Typical AC characteristics for FPGA I/Os
|
||||||
|
|
||||||
|
+-----------------+-------------------------------------------+------+------+-------+
|
||||||
|
| Symbol | Description | Min | Max | Units |
|
||||||
|
+=================+===========================================+======+======+=======+
|
||||||
|
| V_in Overshoot | Maximum allowed overshoot voltage for Vin | TBD | TBD | V |
|
||||||
|
+-----------------+-------------------------------------------+------+------+-------+
|
||||||
|
| V_in Undershoot | Minimum allowed overshoot voltage for Vin | TBD | TBD | V |
|
||||||
|
+-----------------+-------------------------------------------+------+------+-------+
|
||||||
|
| I_VDD_core | Quiescent VDD_core supply current | TBD | TBD | mA |
|
||||||
|
+-----------------+-------------------------------------------+------+------+-------+
|
||||||
|
| I_VDD_io | Quiescent VDD_io supply current | TBD | TBD | mA |
|
||||||
|
+-----------------+-------------------------------------------+------+------+-------+
|
||||||
|
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
HD FPGAs
|
||||||
|
--------
|
||||||
|
|
||||||
|
.. _device_family_hd_fpga:
|
||||||
|
HD FPGA Family
|
||||||
|
|
||||||
|
.. toctree::
|
||||||
|
:maxdepth: 2
|
||||||
|
|
||||||
|
hd_device_comp
|
||||||
|
|
||||||
|
hd_device_dcac
|
||||||
|
|
@ -1,11 +1,9 @@
|
||||||
.. _device:
|
.. _device_family:
|
||||||
Device Datasheet
|
Device Family
|
||||||
|
|
||||||
.. toctree::
|
.. toctree::
|
||||||
:maxdepth: 2
|
:maxdepth: 2
|
||||||
|
|
||||||
device_overview
|
introduction
|
||||||
|
|
||||||
device_resource
|
hd_fpga/index
|
||||||
|
|
||||||
dc_ac_character
|
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
.. _device_overview:
|
.. _device_family_introduction:
|
||||||
|
|
||||||
General Description
|
Introduction
|
||||||
-------------------
|
------------
|
||||||
|
|
||||||
All the FPGA devices in this project are fully open-source, from the architecture description to the physical design outputs, e.g., GDSII.
|
All the FPGA devices in this project are fully open-source, from the architecture description to the physical design outputs, e.g., GDSII.
|
||||||
All the devices are designed through the OpenFPGA framework and the Skywater 130nm PDK.
|
All the devices are designed through the OpenFPGA framework and the Skywater 130nm PDK.
|
||||||
|
|
@ -7,15 +7,15 @@ Welcome to SKywater-OpenFPGA documentation!
|
||||||
===========================================
|
===========================================
|
||||||
|
|
||||||
.. toctree::
|
.. toctree::
|
||||||
:caption: Device Datasheet
|
:caption: Device Family
|
||||||
|
|
||||||
device/index
|
device/index
|
||||||
|
|
||||||
.. toctree::
|
.. toctree::
|
||||||
:maxdepth: 2
|
:maxdepth: 2
|
||||||
:caption: FPGA Architecture
|
:caption: Datasheets
|
||||||
|
|
||||||
arch/index
|
datasheet/index
|
||||||
|
|
||||||
.. toctree::
|
.. toctree::
|
||||||
:maxdepth: 2
|
:maxdepth: 2
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue