mirror of https://github.com/lnis-uofu/SOFA.git
[Script] Update report timing script for SOFA CHD
This commit is contained in:
parent
004b5b7625
commit
17cb17cd5d
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@ -6,9 +6,9 @@
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##################################
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# Define environment variables
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#
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set DEVICE_NAME "SOFA_HD"
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#set DEVICE_NAME "SOFA_HD"
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#set DEVICE_NAME "QLSOFA_HD"
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#set DEVICE_NAME "SOFA_CHD"
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set DEVICE_NAME "SOFA_CHD"
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set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
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@ -30,9 +30,13 @@ set_app_var svr_enable_vpp true
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# Enable reporting ALL the timing paths even those are NOT constrained
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set_app_var timing_report_unconstrained_paths true
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
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if {"SOFA_CHD" == ${DEVICE_NAME}} {
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
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} else {
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
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}
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set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
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@ -49,6 +53,9 @@ foreach DESIGN_NAME ${DESIGN_NAMES} {
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##################################
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# Read timing libraries
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read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
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if {"SOFA_CHD" == ${DEVICE_NAME}} {
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read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
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}
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##################################
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# Read post-PnR netlists
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@ -6,9 +6,9 @@
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##################################
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# Define environment variables
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#
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set DEVICE_NAME "SOFA_HD"
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#set DEVICE_NAME "SOFA_HD"
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#set DEVICE_NAME "QLSOFA_HD"
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#set DEVICE_NAME "SOFA_CHD"
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set DEVICE_NAME "SOFA_CHD"
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set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
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@ -30,9 +30,13 @@ set_app_var svr_enable_vpp true
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# Enable reporting ALL the timing paths even those are NOT constrained
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set_app_var timing_report_unconstrained_paths tr
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
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if {"SOFA_CHD" == ${DEVICE_NAME}} {
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
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} else {
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
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}
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set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
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@ -44,6 +48,9 @@ remove_lib -all
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##################################
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# Read timing libraries
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read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
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if {"SOFA_CHD" == ${DEVICE_NAME}} {
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read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
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}
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##################################
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# Read post-PnR netlists
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@ -23,7 +23,6 @@ if {"SOFA_HD" == ${DEVICE_NAME}} {
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set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
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}
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set TIMING_REPORT_HOME "../TIMING_REPORTS/";
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# Enable preprocessing in Verilog parser
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@ -31,9 +30,13 @@ set_app_var svr_enable_vpp true
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# Enable reporting ALL the timing paths even those are NOT constrained
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set_app_var timing_report_unconstrained_paths tr
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
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if {"SOFA_CHD" == ${DEVICE_NAME}} {
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
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} else {
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
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}
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set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
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@ -45,6 +48,9 @@ remove_lib -all
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##################################
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# Read timing libraries
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read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
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if {"SOFA_CHD" == ${DEVICE_NAME}} {
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read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
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}
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##################################
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# Read post-PnR netlists
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@ -6,9 +6,9 @@
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##################################
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# Define environment variables
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set DEVICE_NAME "SOFA_HD"
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#set DEVICE_NAME "SOFA_HD"
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#set DEVICE_NAME "QLSOFA_HD"
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#set DEVICE_NAME "SOFA_CHD"
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set DEVICE_NAME "SOFA_CHD"
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set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
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@ -29,9 +29,13 @@ set_app_var svr_enable_vpp true
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# Enable reporting ALL the timing paths even those are NOT constrained
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set_app_var timing_report_unconstrained_paths tr
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
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if {"SOFA_CHD" == ${DEVICE_NAME}} {
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
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} else {
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
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}
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set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
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@ -49,6 +53,9 @@ foreach DESIGN_NAME ${DESIGN_NAMES} {
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##################################
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# Read timing libraries
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read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
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if {"SOFA_CHD" == ${DEVICE_NAME}} {
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read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
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}
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##################################
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# Read post-PnR netlists
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