From 17cb17cd5db44cf8719f896577a13555e661115f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 3 Apr 2021 17:15:09 -0600 Subject: [PATCH] [Script] Update report timing script for SOFA CHD --- SNPS_PT/SCRIPT/report_timing_cb.tcl | 17 ++++++++++++----- SNPS_PT/SCRIPT/report_timing_clb.tcl | 17 ++++++++++++----- SNPS_PT/SCRIPT/report_timing_io.tcl | 14 ++++++++++---- SNPS_PT/SCRIPT/report_timing_sb.tcl | 17 ++++++++++++----- 4 files changed, 46 insertions(+), 19 deletions(-) diff --git a/SNPS_PT/SCRIPT/report_timing_cb.tcl b/SNPS_PT/SCRIPT/report_timing_cb.tcl index ea32e88..df59639 100644 --- a/SNPS_PT/SCRIPT/report_timing_cb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_cb.tcl @@ -6,9 +6,9 @@ ################################## # Define environment variables # -set DEVICE_NAME "SOFA_HD" +#set DEVICE_NAME "SOFA_HD" #set DEVICE_NAME "QLSOFA_HD" -#set DEVICE_NAME "SOFA_CHD" +set DEVICE_NAME "SOFA_CHD" set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; @@ -30,9 +30,13 @@ set_app_var svr_enable_vpp true # Enable reporting ALL the timing paths even those are NOT constrained set_app_var timing_report_unconstrained_paths true -set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" - -set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" +if {"SOFA_CHD" == ${DEVICE_NAME}} { + set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB" + set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib" +} else { + set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" + set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" +} set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" @@ -49,6 +53,9 @@ foreach DESIGN_NAME ${DESIGN_NAMES} { ################################## # Read timing libraries read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" + if {"SOFA_CHD" == ${DEVICE_NAME}} { + read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib" + } ################################## # Read post-PnR netlists diff --git a/SNPS_PT/SCRIPT/report_timing_clb.tcl b/SNPS_PT/SCRIPT/report_timing_clb.tcl index f983c50..b106e70 100644 --- a/SNPS_PT/SCRIPT/report_timing_clb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_clb.tcl @@ -6,9 +6,9 @@ ################################## # Define environment variables # -set DEVICE_NAME "SOFA_HD" +#set DEVICE_NAME "SOFA_HD" #set DEVICE_NAME "QLSOFA_HD" -#set DEVICE_NAME "SOFA_CHD" +set DEVICE_NAME "SOFA_CHD" set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; @@ -30,9 +30,13 @@ set_app_var svr_enable_vpp true # Enable reporting ALL the timing paths even those are NOT constrained set_app_var timing_report_unconstrained_paths tr -set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" - -set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" +if {"SOFA_CHD" == ${DEVICE_NAME}} { + set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB" + set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib" +} else { + set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" + set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" +} set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" @@ -44,6 +48,9 @@ remove_lib -all ################################## # Read timing libraries read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" +if {"SOFA_CHD" == ${DEVICE_NAME}} { + read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib" +} ################################## # Read post-PnR netlists diff --git a/SNPS_PT/SCRIPT/report_timing_io.tcl b/SNPS_PT/SCRIPT/report_timing_io.tcl index 095a3a8..42100f4 100644 --- a/SNPS_PT/SCRIPT/report_timing_io.tcl +++ b/SNPS_PT/SCRIPT/report_timing_io.tcl @@ -23,7 +23,6 @@ if {"SOFA_HD" == ${DEVICE_NAME}} { set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; } - set TIMING_REPORT_HOME "../TIMING_REPORTS/"; # Enable preprocessing in Verilog parser @@ -31,9 +30,13 @@ set_app_var svr_enable_vpp true # Enable reporting ALL the timing paths even those are NOT constrained set_app_var timing_report_unconstrained_paths tr -set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" - -set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" +if {"SOFA_CHD" == ${DEVICE_NAME}} { + set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB" + set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib" +} else { + set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" + set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" +} set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" @@ -45,6 +48,9 @@ remove_lib -all ################################## # Read timing libraries read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" +if {"SOFA_CHD" == ${DEVICE_NAME}} { + read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib" +} ################################## # Read post-PnR netlists diff --git a/SNPS_PT/SCRIPT/report_timing_sb.tcl b/SNPS_PT/SCRIPT/report_timing_sb.tcl index 72a8c72..b8ae9ff 100644 --- a/SNPS_PT/SCRIPT/report_timing_sb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_sb.tcl @@ -6,9 +6,9 @@ ################################## # Define environment variables -set DEVICE_NAME "SOFA_HD" +#set DEVICE_NAME "SOFA_HD" #set DEVICE_NAME "QLSOFA_HD" -#set DEVICE_NAME "SOFA_CHD" +set DEVICE_NAME "SOFA_CHD" set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; @@ -29,9 +29,13 @@ set_app_var svr_enable_vpp true # Enable reporting ALL the timing paths even those are NOT constrained set_app_var timing_report_unconstrained_paths tr -set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" - -set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" +if {"SOFA_CHD" == ${DEVICE_NAME}} { + set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB" + set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib" +} else { + set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" + set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" +} set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" @@ -49,6 +53,9 @@ foreach DESIGN_NAME ${DESIGN_NAMES} { ################################## # Read timing libraries read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" + if {"SOFA_CHD" == ${DEVICE_NAME}} { + read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib" + } ################################## # Read post-PnR netlists