riscv
/
SOFA
mirror of https://github.com/lnis-uofu/SOFA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Doc] Typo fix

This commit is contained in:
tangxifan 2021-04-02 11:51:54 -06:00
parent aa845d506e
commit 1290bbdc90
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -7,7 +7,7 @@
SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework.
This repository provide the following support for the eFPGA IPs
- **Architecture description file** : Users can inspect architecture details and try architecture evalution using the [VTR project](https://github.com/verilog-to-routing/vtr-verilog-to-routing) and the [OpenFPGA project(https://github.com/lnis-uofu/OpenFPGA)].
- **Architecture description file** : Users can inspect architecture details and try architecture evalution using the [VTR project](https://github.com/verilog-to-routing/vtr-verilog-to-routing) and the [OpenFPGA project](https://github.com/lnis-uofu/OpenFPGA).
- **Post-layout Verilog Netlists**: Users can run HDL simulations on the eFPGA IPs to validate their applications
- **Benchmark suites**: An example benchmarking suite with which users can run quick examples on the eFPGA IPs
- **Documentation**: Datasheets for each eFPGA IPs downto circuit-level details