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 SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework.
 
 This repository provide the following support for the eFPGA IPs
-- **Architecture description file** : Users can inspect architecture details and try architecture evalution using the [VTR project](https://github.com/verilog-to-routing/vtr-verilog-to-routing) and the [OpenFPGA project(https://github.com/lnis-uofu/OpenFPGA)].
+- **Architecture description file** : Users can inspect architecture details and try architecture evalution using the [VTR project](https://github.com/verilog-to-routing/vtr-verilog-to-routing) and the [OpenFPGA project](https://github.com/lnis-uofu/OpenFPGA).
 - **Post-layout Verilog Netlists**: Users can run HDL simulations on the eFPGA IPs to validate their applications
 - **Benchmark suites**: An example benchmarking suite with which users can run quick examples on the eFPGA IPs
 - **Documentation**: Datasheets for each eFPGA IPs downto circuit-level details